Information processing method for information processing system, and information processing system

Abstract

The present disclosure relates to an information processing method for an information processing system, and to an information processing system, that make it possible to reduce deterioration in processing performance caused by latency in a system on chip (SoC). In a data transfer path for a target to read data or write data on the basis of an instruction from an initiator, when the maximum operating frequency related to communication between a first path that goes through a register that latches data, a second path that does not go through the register, and the initiator, which has been supplying the instructions, is larger than the desired operating frequency in an information processing system composed of the SoC, it is possible to operate at the desired operating frequency without having to go through the registers. Therefore, the second path that does not go through the registers is selected, and processing corresponding to the instruction is executed, so as to reduce latency. The present disclosure can be applied to an information processing system composed of an SoC.

Description

Information Processing Method of Information Processing System and Information Processing System

[0001] The present disclosure relates to an information processing method of an information processing system and an information processing system, and particularly to an information processing method of an information processing system for reducing degradation of processing performance caused by latency in a SoC (System on Chip) and an information processing system.

[0002] A SoC (System on Chip) is composed of a plurality of initiators (CPU instructions, CPU data, DMAC (Direct Memory Access Controller), etc.) including a CPU (Central Processing Unit) and targets (memory, etc.).

[0003] In recent years, due to the progress of semiconductor processes, the density of gates has increased, the physical gate area that can be implemented on a SoC has increased, the scale of logic circuits has increased accordingly, and the gates have become faster, enabling the implementation of complex logic circuits.

[0004] On the other hand, in the layout process of a SoC, due to the increase and complexity of these logic circuits, the timing convergence work to enable operation at the target operating frequency of the SoC product has become a difficult task and has consumed a great deal of time and effort.

[0005] Also, in the timing convergence work, even if the layout is repeatedly rearranged, it may be necessary to take measures such as reducing the operating frequency or increasing the chip size because the operation guarantee at the target operating frequency cannot be achieved.

[0006] Therefore, a technique has been proposed in which registers are inserted into a signal group between an initiator and a target that are critical paths, and the path is divided to reduce the delay amount and guarantee operation at the target operating frequency.

[0007] However, while this method allows timing constraints to be met, it increases the latency of access cycles, effectively degrading processing performance. In particular, CPU instruction fetching accesses the target every cycle, so its latency is increased compared to other initiators, and the impact on processing performance degradation is significant.

[0008] For this reason, a technique has been proposed in which a path with a register pre-inserted in the signal group between the initiator and the target, and a path without a register pre-inserted, are provided, and these paths are switched and used according to the operating frequency of the actual circuit after design (see Patent Document 1).

[0009] Japanese Patent Publication No. 2007-018264

[0010] By the way, even in the design and manufacturing of SoCs using the technology described in Patent Document 1, the operating frequency depends on the required performance of the product, the manufacturing process, and the physical implementation, so various trade-offs are considered and one of the paths is selected.

[0011] Here, for example, consider a bus connecting initiators A and B to targets C and D, where, in communication via this bus, operation at the target operating frequency can be guaranteed between initiator A and targets C and D at a predetermined operating frequency, but operation at the target operating frequency cannot be guaranteed between initiator B and targets C and D.

[0012] In this case, if the technology described in Patent Document 1 above is used, in order to satisfy the predetermined operating frequency, targets C and D cannot guarantee operation at the target operating frequency for initiator B, so the configuration is such that a path in which a register is inserted is selected in both cases.

[0013] However, in this case, targets C and D will select the path with the inserted register even though the timing constraints can be met with a path without the inserted register for initiator A. As a result, unnecessary latency will occur in communication with initiator A, leading to a degradation in processing performance.

[0014] This disclosure is made in light of these circumstances and aims to reduce the degradation of processing performance caused by unnecessary latency in SoCs (System on Chip).

[0015] An information processing method for an information processing system, which is one aspect of the present disclosure, is an information processing method for an information processing system, which includes a path for transferring data for a target to read or write data based on an instruction from an initiator in a System On Chip (SoC) consisting of at least one initiator and at least one target, the path comprising a first path that passes through a storage unit that stores the data and a second path that does not pass through the storage unit, and a selection process to select either the first path or the second path depending on the initiator that supplied the instruction.

[0016] An information processing system in one aspect of this disclosure is an information processing system comprising: a first path that passes through a storage unit that stores the data; a second path that does not pass through the storage unit; and a selection unit that selects the first path or the second path according to the initiator that supplied the instruction. The system is an information processing system in a System On Chip (SoC) consisting of at least one initiator and at least one target, and a path for a target to read or write data based on an instruction from the initiator.

[0017] In one aspect of this disclosure, a System On Chip (SoC) comprising at least one initiator and at least one target is provided with a path for transferring data for a target to read or write data based on an instruction from the initiator, the path being provided includes a first path that passes through a storage unit that stores the data and a second path that does not pass through the storage unit, and the first path or the second path is selected depending on the initiator that supplied the instruction.

[0018] This figure illustrates a typical bus configuration used in an information processing system to illustrate the outline of this disclosure. This figure illustrates an example of a state machine, a typical component used in the initiator and target in Figure 1. This figure illustrates an outline of an example configuration of the information processing system of this disclosure. This figure illustrates an outline of an example configuration of a target to which the proposed technology is applied to achieve operation at a target operating frequency. This figure illustrates an outline of an example configuration of a target to which the technology of this disclosure is applied. This figure illustrates an example configuration of a preferred embodiment of the information processing system of this disclosure. This figure illustrates an example configuration of a maximum operating frequency table (MAX Frequency Table Register). This figure illustrates an example configuration of additional information. This is a flowchart illustrating the processing of the system manager. This is a flowchart illustrating the processing of the initiator. This is a flowchart illustrating the processing of the target. This is a timing chart illustrating the processing when only the register latch path is used. This is a timing chart illustrating the processing of this disclosure. This figure illustrates a first modification of this disclosure. This figure illustrates a second modification of this disclosure.

[0019] Preferred embodiments of this disclosure will be described in detail below with reference to the attached drawings. In this specification and the drawings, components having substantially the same functional configuration are denoted by the same reference numerals, and redundant descriptions will be omitted.

[0020] The following describes the configurations for implementing this technology. The explanation will proceed in the following order.

[0021] 1. Outline of this Disclosure 2. Preferred Embodiments 3. First Modification 4. Second Modification

[0022] <<1. Overview of this Disclosure>> <Typical SoC Configuration Example> This disclosure is particularly aimed at reducing the degradation of processing performance caused by latency in SoCs (System on Chip). Therefore, we will first explain the overview of this disclosure.

[0023] Figure 1 shows an example configuration of an information processing system 11 consisting of a typical SoC bus, and is composed of an arbiter 20, initiators 21-1 to 21-3, multiplexers (selectors) 22-1 to 22-3, targets 23-1 to 23-4, and a decoder 24.

[0024] Initiators 21-1 to 21-3 and targets 23-1 to 23-4 are also referred to as initiators #1 to #3 and targets #1 to #4 in the diagram, and they correspond to each other. However, in the following explanation, they will be referred to as initiators 21-1 to 21-3 and targets 23-1 to 23-4.

[0025] Initiators 21-1 to 21-3 consist of, for example, CPU (Central Processing Unit) instructions, CPU data, and DMAC (Direct Memory Access Controller), and transmit predetermined operation instructions and requests to the target and acquire signals corresponding to the requests.

[0026] Targets 23-1 to 23-4 are, for example, memory, and they return signals according to instructions and requests from the initiator.

[0027] Arbiter 20 receives and mediates bus usage requests for the address bus and write data bus from initiators 21-1 to 21-3. Based on the mediation results, it connects multiplexers 22-1 and 22-2 to one of initiators 21-1 to 21-3, and connects the address bus and write data bus from the initiator 21-1 to 21-3 whose usage has been accepted to targets 23-1 to 23-4.

[0028] Initiators 21-1 to 21-3, in accordance with the arbitration result, supply addresses and write data to targets 23-1 to 23-4 via multiplexers 22-1 and 22-2, using the address bus and write data bus.

[0029] The decoder 24 decodes the instructions supplied by initiators 21-1 to 21-3, and based on the decoding result, controls the multiplexer 22-3 to mediate the use of the read data bus and supplies the read data supplied by any of targets 23-1 to 23-4 to initiators 21-1 to 21-3.

[0030] With this configuration, in the information processing system 11 of Figure 1, initiators 21-1 to 21-3 enable data writing and reading to targets 23-1 to 23-4.

[0031] Incidentally, these initiators 21-1 to 21-3 and targets 23-1 to 23-4 are composed of state machines such as the Moore machine 31 shown on the left side of Figure 2 and the Mealy machine 32 shown on the right side of Figure 2.

[0032] The Moore machine 31 is composed of a combinational circuit 41 and a state register 42 consisting of a flip-flop circuit. An input signal is processed by the combinational circuit 41 and supplied to the state register 42 as an input signal that serves as a transition condition. The state machine's transition result, based on the input signal that serves as the transition condition for the state register 42, is then output as a control signal.

[0033] Furthermore, in addition to the combinational circuit 41 and state register 42 found in the Moore machine, the Mealy machine 32 is configured to include a combinational circuit 43 located after the state register 42, which receives signals indicating the transition state in the state register 42 and input signals.

[0034] With this configuration, the Mealy machine 32 can output a control signal at the moment it receives an input signal, whereas the Moore machine 31, compared to the Mealy machine 32, delays the output of the control signal by one clock cycle after receiving the input signal.

[0035] Thus, the operating frequencies of the initiators 21-1 to 21-3 and targets 23-1 to 23-4 differ depending on whether they are composed of Moore machine 31 or Mealy machine 32.

[0036] In recent years, advances in semiconductor processes have led to increased gate density, resulting in a larger physical gate area that can be implemented on an SoC. Consequently, the scale of logic circuits has increased, and gate speeds have improved, making it possible to implement complex logic circuits. As a result, information processing systems 11 consisting of an SoC bus now include logic circuits that are more complex than the Moore machines 31 and Mealy machines 32 mentioned above, such as data error correction circuits.

[0037] As a result, as mentioned above, more complex circuits with different operating frequencies, such as Moore machine 31 and Mealy machine 32, will be used in larger quantities. Furthermore, differences in wiring distances depending on the layout make the adjustment work required to guarantee operation at the target operating frequency during the SoC layout process difficult.

[0038] Therefore, in recent years, techniques have been proposed to ensure operation at the target operating frequency by incorporating register circuits such as flip-flop circuits into the circuit path during adjustment work to guarantee operation at the target operating frequency.

[0039] Here, using an example configuration such as the information processing system 100 shown in Figure 3, we will explain the proposed technology that ensures operation at the target operating frequency.

[0040] The information processing system 100 in Figure 3 is configured such that initiators 111-1 and 111-2, which consist of instruction fetch circuits and load / store circuits generally provided in a CPU, and targets 112-1 and 112-2, which consist of memory controllers generally provided in SRAM (Static Random Access Memory), are connected by a bus 121.

[0041] In the information processing system 100 of FIG. 3, for example, in each of the paths P1 and P3 between the initiator 111-1 and the targets 112-1 and 112-2, operations at the target operating frequency are possible. However, in each of the paths P2 and P4 between the initiator 111-2 and the targets 112-1 and 112-2, delays occur and operations at the target operating frequency are not possible.

[0042] In such a case, the proposed technology is a technology that absorbs delays and realizes operations at the target operating frequency by providing a register composed of flip-flops or the like on the signal path constituting the target 112.

[0043] More specifically, for example, the memory controller serving as the target 112 is generally composed of a SRAM (Static Random Access Memory) macro 151, an ECC decode logic circuit 152, and a BUS target I / F 153, as shown in the left part of FIG. 4.

[0044] The SRAM macro 151 is composed of a memory cell array, an address decoder, a precharge circuit, a write circuit, a read circuit, an address decoder circuit, etc., and executes all processes of operations for writing and reading SRAM data.

[0045] The ECC (Error Correcting Code) decode logic circuit 152 detects and corrects data corruption read from the SRAM macro 151 and outputs it to the BUS target I / F 153.

[0046] The BUS target I / F 153 functions as an interface related to communication via the bus 121.

[0047] Here, the ECC (Error Correcting Code) decoding logic circuit 152 has a large number of logic stages and is prone to delays. Here, it is assumed that due to the delay in this ECC decoding logic circuit 152, the targets 112-1 and 112-2 cannot operate at the target operating frequency in communication with the initiator 111-2. However, the delay in the ECC decoding logic circuit 152 is only an example. In reality, for example, when using a plurality of SRAM macros, there are many other delay factors, such as the delay occurring in the selection circuit of the plurality of SRAM macros. However, here, the description will be limited to the delay in the decoding logic circuit 152.

[0048] The proposed technique is applied in such a case. By replacing the memory controllers 112-1 and 112-2, which are the targets in the left part of FIG. 4, with the memory controller 112' as shown in the right part of FIG. 4, a register 161 composed of a flip-flop circuit is sandwiched between the ECC decoding logic circuit 152 and the BUS target I / F 153, thereby eliminating the delay and enabling operation at the target operating frequency.

[0049] However, the targets 112-1 and 112-2 can also operate at the target operating frequency in the memory controller 112 in the left part of FIG. 4 that does not include the register 161 in the paths P1 and P3 with the initiator 111-1, respectively.

[0050] Despite such a configuration, in order for the targets 112-1 and 112-2 to achieve operation at the target operating frequency in the paths P2 and P4 with the initiator 111-2, by replacing them with the memory controller 112' with the register 161 sandwiched, unnecessary latency will occur in the communication in the paths P1 and P3 with the initiator 111-1 that can originally operate at the target operating frequency, resulting in a deterioration of the processing performance.

[0051] Therefore, in this disclosure, the memory controller 112' shown on the left side of Figure 5 (similar to the left side of Figure 4) is replaced with the memory controller 112'' shown on the right side of Figure 5. That is, in the memory controller 112'' shown on the right side of Figure 5, a selector 171 is provided between the ECC decode logic circuit 152 and the BUS target I / F 153, so that a path P11 that does not go through the register 161 and a path P12 that goes through the register 161 can be dynamically switched and used by the selector 171.

[0052] In other words, for example, in Figure 3, in paths P1 and P3 between initiator 111-1 and targets 112-1 and 112-2, respectively, the selector 171 is configured to select path P11, which does not go through register 161. On the other hand, in paths P2 and P4 between initiator 111-2 and targets 112-1 and 112-2, respectively, the selector 171 is configured to select path P12, which goes through register 161.

[0053] With this configuration, in the paths P1 and P3 between the initiator 111-1 and the targets 112-1 and 112-2, the path P11 that does not go through register 161 is selected, making it possible to suppress the occurrence of latency caused by register 161.

[0054] Furthermore, in paths P2 and P4 between initiator 111-2 and targets 112-1 and 112-2, respectively, the selector 171 selects path P12 via register 161. This results in a one-cycle delay in the clock, but enables operation at the target operating frequency.

[0055] As a result, it becomes possible to achieve operation at the target operating frequency without increasing the man-hours required in the layout process for timing convergence, and further reduce performance degradation by suppressing the occurrence of unnecessary latency.

[0056] Hereafter, a path like path P11 that does not pass through register (storage unit) 161 will be referred to as a register-through path, and a path like path P12 that passes through register (storage unit) 161 will be referred to as a register-latch path. In other words, in this disclosure, by switching between register-through paths and register-latch paths, the occurrence of unnecessary latency is suppressed, performance degradation is reduced, and operation at the target operating frequency is achieved.

[0057] <<2. Preferred Embodiments>> Next, with reference to Figure 6, a configuration example of a preferred embodiment of an information processing system consisting of the SoC (System On Chip) of this disclosure will be described.

[0058] The information processing system 201 in Figure 6 consists of a bus 210, a system manager 211, a CPU 212, a DMAC 213, and memory controllers (MEM controllers) 214-1 to 214-3. Hereafter, unless it is necessary to distinguish between them individually, the memory controllers 214-1 to 214-3 will simply be referred to as memory controller 214, and the other components will be referred to similarly.

[0059] The system manager 211, CPU 212, DMAC 213, and memory controllers 214-1 to 214-3 are connected via bus 210 and control the operation of the CPU 212, DMAC 213, and memory controllers 214-1 to 214-3. In this embodiment, the system manager 211 is described as being configured as hardware, but it may also be configured as software.

[0060] The CPU (Central Processing Unit) 212 supplies a bus request signal to memory controllers 214-1 to 214-3 via the bus 210, which consists of an address identifying the initiator and target, a read command or write command, information on the size of the data to be transferred, and additional information described later, instructing them to write or read data. In response to this bus request signal, the CPU 212 supplies the data to be written as a bus write data signal to memory controllers 214-1 to 214-3, or acquires the data read from memory controllers 214-1 to 214-3 as a bus read data signal.

[0061] The CPU 212 includes an instruction fetch circuit 231 and a load / store circuit 232 that function as initiators. The instruction fetch circuit 231 and the load / store circuit 232 supply bus request signals to the target memory controllers 214-1 to 214-3, instructing them to read data, and in response, acquire the data to be read as a bus read signal.

[0062] Furthermore, the load-store circuit 232 supplies bus request signals to the target memory controllers 214-1 to 214-3, instructing them to write data, and supplies the data to be written as bus slide data signals.

[0063] In this process, the instruction fetch circuit 231 and the load / store circuit 232, based on instructions from the system manager 211, supply the memory controller 214 with a bus request signal containing additional information, including whether or not to access the SRAM 244 via register 243 (via a register latch path) to read or write data, and their own initiator ID.

[0064] The DMAC (Direct Memory Access Controller) 213, according to the settings of the CPU 212, supplies a bus request signal via the bus 210 to one of the memory controllers 214-1 to 214-3, which consists of an address identifying the initiator and target, a read command or write command, information on the size of the data to be transferred, and additional information described later, to instruct the writing or reading of data. In addition, the DMAC 213 acquires data to be read from the memory controllers 214-1 to 214-3 as a bus read data signal, or supplies data to be written to the memory controllers 214-1 to 214-3 as a bus write data signal.

[0065] Since the DMAC 213 is basically configured to act as a proxy for the CPU 212 in writing and reading data to and from the memory controller 214, the processing performed on the memory controller 214 is basically the same as that of the CPU 212.

[0066] Furthermore, the DMAC (Direct Memory Access Controller) 213 includes a DMA control circuit 233 that functions as an initiator. Therefore, the DMA control circuit 233 also supplies the target memory controller 214 with information indicating whether or not to access the SRAM 244 via the register 243 (via a register latch path) to read or write data, along with additional information including its own initiator ID, based on instructions from the system manager 211.

[0067] The memory control circuits 241-1 to 241-3 correspond to the BUS target I / F 153 of the memory controller 112'' in Figure 5, and write or read data to the built-in SRAM (Static Random Access Memory) 244-1 to 244-3 based on commands from the instruction fetch circuit 231 and load / store circuit 232 of the CPU 212, which is the initiator, and the DMA control circuit 233 of the DMAC 213.

[0068] Each of the memory control circuits 241-1 to 241-3 comprises a memory control circuit 241-1 to 241-3, a write selector 242-1-1 to 242-1-3, a read selector 242-2-1 to 242-2-3, a write register (storage unit) 243-1-1 to 243-1-3, a read register (storage unit) 243-2-1 to 243-2-3, and SRAM 244-1 to 244-3, respectively.

[0069] Each of the memory control circuits 241-1 to 241-3 functions as a target and writes or reads data to or from the SRAMs 244-1 to 244-3 based on instructions (commands) contained in the bus request signals from the instruction fetch circuit 231 and load / store circuit 232 of the CPU 212, which is the initiator, and from the DMA control circuit 233 of the DMAC 213.

[0070] When writing data, the memory control circuits 241-1 to 241-3 control the write selectors 242-1-1 to 242-1-3 based on additional information contained in the bus request signals from the load / store circuit 232 of the CPU 212 and the DMA control circuit 233 of the DMAC 213, which are the initiators, and selection information from the system manager 211, and write either through the write registers 243-1-1 to 243-1-3 or without using the registers 243-1-1 to 243-1-3.

[0071] Furthermore, when reading data, the memory control circuits 241-1 to 241-3 control the read selectors 242-2-1 to 242-2-3 based on additional information contained in the bus request signals from the instruction fetch circuit 231 and load / store circuit 232 of the CPU 212, which are the initiators, and the DMA control circuit 233 of the DMAC 213, as well as selection information from the system manager 211, to read the data either through the read registers 243-2-1 to 243-2-3 or without using the registers 243-2-1 to 243-2-3.

[0072] In other words, when the write selectors 242-1-1 to 242-1-3 are controlled, writing via the write registers 243-1-1 to 243-1-3 is data writing via the register latch path, and writing without going through registers 243-1-1 to 243-1-3 is data writing via the register through path.

[0073] Similarly, when the read selectors 242-2-1 to 242-2-3 are controlled, reading data via the read registers 243-2-1 to 243-2-3 is considered reading data via the register latch path, while reading data without going through registers 243-2-1 to 243-2-3 is considered reading data via the register through path.

[0074] When writing or reading data, the memory control circuits 241-1 to 241-3 determine whether to execute the data via a register-through path or a register-latch path based on the additional information included in the bus request signal described above and the selection information set for each initiator supplied by the system manager 211.

[0075] Then, based on the determination result corresponding to this additional information and selection information, the memory control circuits 241-1 to 241-3 control selectors 242-1-1 to 242-1-3 and selectors 242-2-1 to 242-2-3 to write or read data via either a register through path or a register latch path.

[0076] The system manager 211 stores a maximum operating frequency table (MAX Frequency Table Register) for each initiator-target combination, which is a table of the maximum operating frequencies for communication using the bus 210. By comparing this with the target operating frequency, the system manager 211 identifies whether to use a register latch path or a register through path for each target initiator and supplies a list of selection information.

[0077] <Maximum Operating Frequency Table Register> The maximum operating frequency table (MAX Frequency Table Register) for each combination of initiator and target in communication using bus 210 is, for example, as shown in Figure 7.

[0078] In the table in Figure 7, the maximum operating frequencies for reading and writing for each initiator are listed, from top to bottom in the figure, and from left to right in the figure, in order from target to target.

[0079] More specifically, in the table in Figure 7, there are columns labeled Address Space A to Address Space C, which identify the target memory control circuits 241-1 to 241-3 from top to bottom in the figure. From left to right in the figure, the maximum operating frequencies for the initiator instruction fetch circuit 231 during read and write operations, the load-store circuit 232 during read and write operations, and the DMA control circuit 233 during read and write operations are listed.

[0080] In other words, according to the table in Figure 7, the maximum operating frequency for reading during communication with the memory control circuits 241-1 to 241-3 in the instruction fetch circuit 231 is 200 MHz. Also, since there are no write commands in the instruction fetch circuit 231, it is marked with "-".

[0081] Furthermore, in the load / store circuit 232, the maximum operating frequency during reading in communication with the memory control circuit 241-1 is 200 MHz, and the maximum operating frequency during reading in communication with the memory control circuits 241-2 and 241-3 is 150 MHz. In the load / store circuit 232, the maximum operating frequency during writing in communication with the memory control circuits 241-1 to 241-3 is 200 MHz.

[0082] Furthermore, the DMA control circuit 233 has a maximum operating frequency of 150 MHz when reading data in communication with memory control circuits 241-1 and 241-2, and a maximum operating frequency of 200 MHz when reading data in communication with memory control circuit 241-3. In addition, the load / store circuit 232 has a maximum operating frequency of 200 MHz when writing data in communication with memory control circuits 241-1 to 241-3.

[0083] With this configuration, for example, if the target operating frequency is 180MHz, the system manager 211 generates selection information to select a register through path for the target memory control circuit 241-1 (Address Space A) when reading to the instruction fetch circuit 231, when reading to the load-store circuit 232, when writing, and when writing to the DMA control circuit 233, because the target operating frequency is lower than the maximum operating frequency (200MHz > 180MHz), a latch is not required. On the other hand, when reading to the DMA control circuit 233, a latch is required because the target operating frequency is higher than the maximum operating frequency (150MHz < 180MHz), and the system manager 211 generates selection information to select a register latch path.

[0084] Furthermore, for the target memory control circuit 241-2 (Address Space B), the system manager 211 generates selection information to select the register through path when reading to the instruction fetch circuit 231, writing to the load-store circuit 232, and writing to the DMA control circuit 233, because the target operating frequency of 180MHz is lower than the maximum operating frequency of 200MHz, a latch is not required. On the other hand, when reading to the load-store circuit 232 and reading to the DMA control circuit 233, a latch is required because the target operating frequency of 180MHz is higher than the maximum operating frequency of 150MHz, and the system manager 211 generates selection information to select the register latch path.

[0085] Furthermore, for the target memory control circuit 241-3 (Address Space C), the system manager 211 generates selection information to select the register through path when reading to the instruction fetch circuit 231, writing to the load-store circuit 232, and reading and writing to the DMA control circuit 233, because the target operating frequency of 180MHz is lower than the maximum operating frequency of 200MHz, a latch is not required. On the other hand, when reading to the load-store circuit 232, a latch is required because the target operating frequency of 180MHz is higher than the maximum operating frequency of 150MHz, so the system manager 211 generates selection information to select the register latch path.

[0086] The system manager 211 updates the maximum operating frequency table (MAX Frequency Table Register) for each combination of the initiator and target at startup or at other times, based on the characteristics of the initiator and target.

[0087] The table of maximum operating frequencies is set based on the characteristics of the initiator and target. Therefore, if the characteristics of the initiator and target change depending on the operating environment, the table needs to be updated accordingly. When this table of maximum operating frequencies is updated, the selection information is also updated. Therefore, it is necessary to ensure operation at the target operating frequency until the update of the maximum operating frequency table is complete and the selection information corresponding to the updated table is delivered to the target.

[0088] Therefore, the system manager 211 uses the Configuration Activation Register to instruct all initiators to always read and write via the register latch path when sending bus request signals to the target, regardless of the selection information. More specifically, the system manager 211 sets the Configuration Activation Register to 0 (Setting Disable (initial value)) to instruct all initiators to always read and write via the register latch path when sending bus request signals to the target, regardless of the selection information.

[0089] When the Configuration Activation Register is 0, all initiators, when sending a bus request signal to a target, include their initiator ID and variable response information that always instructs the read or write operation to be performed via the register latch path.

[0090] Here, we will explain an example of the configuration of additional information. Additional information is, for example, the 3 bits of information shown as INFO in Figure 8.

[0091] The additional information INFO in Figure 8 is a 3-bit piece of information with bits 2, 1, and 0 set from left to right in the figure, and the initiator ID is represented by bits 2 and 1. In Figure 8, when (bit 2, bit 1) is (0, 0), the initiator ID of the instruction fetch circuit 231 is represented; when (bit 2, bit 1) is (0, 1), the initiator ID of the load / store circuit 232 is represented; and when (bit 2, bit 1) is (1, 0), the initiator ID of the DMA control circuit 233 is represented. Note that (bit 2, bit 1) being (1, 1) is a reserved code.

[0092] Furthermore, bit 0 represents response variable information; when it is 0, it represents response variable disabled, requiring the register latch path to always be selected, and when it is 1, it represents response variable enabled, requiring a decision to be made for each initiator identified by the initiator ID based on the selection information.

[0093] In other words, when the system manager 211 writes the maximum operating frequency table at startup, or when it updates it in response to changes in the operating environment, it sets the Configuration Activation Register to 0 and instructs all initiators (instruction fetch circuit 231, load / store circuit 232, and DMA control circuit 233) to send additional information that disables variable response when sending bus request signals.

[0094] In response to this instruction, all initiators (instruction fetch circuit 231, load / store circuit 232, and DMA control circuit 233) send additional information, including response variable information that disables response variable, along with their own initiator ID, when sending bus request signals to all targets (memory control circuits 241-1 to 241-3).

[0095] All targets (memory control circuits 241-1 to 241-3) always read and write data via the register latch path when the response variable information of the additional information included in the bus request signal from the initiator (instruction fetch circuit 231, load / store circuit 232, and DMA control circuit 233) is 0 and the response variable is disabled.

[0096] Meanwhile, once the system manager 211 has finished updating the maximum operating frequency table, it generates new selection information for each target, and after distributing the generated selection information, it sets the Configuration Activation Register to 1 (Setting Enable) and instructs all initiators (instruction fetch circuit 231, load store circuit 232, and DMA control circuit 233) to send additional information, including response variable information that enables response variable when sending bus request signals.

[0097] In response to this instruction, all initiators (instruction fetch circuit 231, load / store circuit 232, and DMA control circuit 233) transmit additional information, including their initiator ID and response-variable information that becomes response-variable enabled, when sending a bus request signal to all targets (memory control circuits 241-1 to 241-3).

[0098] All targets (memory control circuits 241-1 to 241-3) read and write data via either a register latch path or a register through path, specified by the selection information corresponding to the initiator identified by the initiator ID, if the response variable information included in the bus request signal from the initiator (instruction fetch circuit 231, load store circuit 232, and DMA control circuit 233) is set to response variable enabled.

[0099] <System Manager Processing> Next, the processing performed by the system manager 211 will be explained with reference to the flowchart in Figure 9.

[0100] In step S31, the system manager 211 performs a reset in various configurations and then executes a reset release process.

[0101] In step S32, the system manager 211 distributes the Configuration Activation Register, which has been written to 0, to all initiators (instruction fetch circuit 231, load store circuit 232, and DMA control circuit 233), and instructs them to send additional information, including response variable information that disables response variable, when sending the bus request signal.

[0102] In step S33, the system manager 211 writes a value to the maximum operating frequency table (MAX Frequency Table Register). At this time, the system manager 211 may write a value to the maximum operating frequency table (MAX Frequency Table Register) that has been set as a default value in advance based on the initiator and target, when the system starts up.

[0103] In step S34, the system manager 211 generates selection information for each target based on the values ​​in the maximum operating frequency table (MAX Frequency Table Register), and distributes the generated selection information to each target. At startup, the selection information may be generated using the method described with reference to Figure 7, or default values ​​may be stored in advance and read and written. Through this process, each target receives the selection information distributed by the system manager 211.

[0104] In step S35, the system manager 211 writes 1 to the Configuration Activation Register.

[0105] In step S36, the system manager 211 distributes the Configuration Activation Register with 1 written to it to all initiators (instruction fetch circuit 231, load store circuit 232, and DMA control circuit 233), and instructs them to send additional information including response variable information that enables response variable activation when sending the bus request signal.

[0106] In other words, through the processing in steps S33 to S35, selection information based on the appropriate value of the maximum operating frequency table (MAX Frequency Table Register) is distributed to each target. This makes it possible to appropriately switch between the register through path and the register latch path depending on the combination of initiator and target, thereby enabling the transmission of additional information that enables variable response.

[0107] In step S37, the system manager 211 determines whether or not it is necessary to update the maximum operating frequency table (MAX Frequency Table Register). For example, the system manager 211 determines whether or not an update is necessary based on whether or not the user has prepared new values ​​corresponding to the changes in the operating environment and the characteristics of the initiator and target and requested an update.

[0108] If it is determined in step S37 that an update is necessary, the process proceeds to step S38.

[0109] In step S38, the system manager 211 writes 0 to the Configuration Activation Register, and the process returns to step S32.

[0110] In other words, when sending a new bus request signal, additional information that disables the variable response is sent when the selection information is updated in conjunction with the update of the Maximum Operating Frequency Table Register and distributed to each target, in order to guarantee the operating frequency, read and write operations are performed on the register latch path for all targets.

[0111] Furthermore, in step S33, unlike during startup, new values ​​corresponding to the changes in the operating environment prepared by the user and the characteristics of the initiator and target are written to the Maximum Operating Frequency Table Register.

[0112] Furthermore, if it is determined in step S37 that an update is not necessary, the same process is repeated until it is determined that an update is necessary.

[0113] Through the above process, upon startup, a reset release process is performed, a value is written to and generated in the Maximum Operating Frequency Table Register (MAX Frequency Table Register), and until selection information is generated based on the generated Maximum Operating Frequency Table and distributed to each target, reading and writing operations are performed via the register latch path on all targets.

[0114] Then, once the selection information is generated and distributed to each target, all targets determine whether to use a register latch path or a register through path based on the selection information and initiator ID, and data reading and writing are performed along the determined path.

[0115] Furthermore, if the Maximum Operating Frequency Table Register is updated thereafter, read and write operations will be performed on all targets via the register latch path until the update is complete, selection information is generated from the updated Maximum Operating Frequency Table, and distributed to each target.

[0116] <Initiator Processing> Next, the initiator processing will be explained with reference to the flowchart in Figure 10.

[0117] In step S51, the initiator (instruction fetch circuit 231, load / store circuit 232, and DMA control circuit 233) performs resets in various configurations and then executes a reset release process.

[0118] In step S52, the initiator determines whether or not there was an instruction to enable additional information in a variable response manner, based on whether or not a Configuration Activation Register with 0 written to it was supplied by the system manager 211.

[0119] If it is determined in step S52 that there is an instruction to enable variable response for additional information, the process proceeds to step S53.

[0120] In step S53, when the initiator sends a bus request signal to the target, it includes its initiator ID and the response variable information (which has been enabled) as additional information, and the process returns to step S52.

[0121] On the other hand, if it is determined in step S52 that there is no instruction to enable variable response for additional information, the process proceeds to step S54.

[0122] In step S54, when the initiator sends a bus request signal to the target, it includes its initiator ID and the response variable information (with response variable disabled) as additional information, and the process returns to step S52.

[0123] As a result of the above process, the initiator (instruction fetch circuit 231, load / store circuit 232, and DMA control circuit 233) will be supplied with a Configuration Activation Register with a value written to it until a value is written to the Max Frequency Table Register, selection information is generated, and it is distributed to all targets, in response to instructions from the System Manager 211. For this reason, when sending a bus request signal, the initiator sends additional information that disables the variable response information. Then, once a value is written to the Max Frequency Table Register (updated), selection information is generated, and it is distributed to all targets, a Configuration Activation Register with a value written to it will be supplied, so the initiator sends a bus request signal that includes additional information that enables the variable response information.

[0124] This ensures operation at the target operating frequency, although the clock signal will be delayed by one cycle via a register latch path until the target writes a value to the Max Frequency Table Register based on the additional information contained in the bus request signal supplied by the initiator, the selection information is generated, and then distributed to all targets.

[0125] Furthermore, when values ​​are written to the Maximum Operating Frequency Table Register, and selection information is generated based on the Maximum Operating Frequency Table and distributed to all targets, the targets can appropriately switch between register latch paths and register crash-through paths based on the selection information. This eliminates unnecessary register latch paths, thereby reducing unnecessary latency and suppressing performance degradation.

[0126] Furthermore, if the initiator is the load-store circuit 232, the variable response information in the additional information, which consists of either variable response disabled or variable response enabled, may be specified by an operand in the load-store instruction.

[0127] <Target Processing> Next, the target processing will be explained with reference to the flowchart in Figure 11. This processing assumes that each target has obtained selection information distributed from the system manager 211 through the processing in step S35 of the flowchart in Figure 9.

[0128] In step S71, the targets (memory control circuits 241-1 to 241-3) perform resets in their respective configurations, and then execute a reset release process.

[0129] In step S72, when the target receives a bus request signal from the initiator, it obtains additional information contained in the bus request signal.

[0130] In step S73, the target determines whether the variable response information of the additional information is valid and whether the initiator identified by the initiator ID is instructed to communicate via the register-through path based on the selection information.

[0131] In step S73, if the variable response information of the additional information is enabled and the initiator identified by the initiator ID is instructed to communicate via the register through path based on the selection information, the process proceeds to step S74.

[0132] In step S74, the target responds to the command included in the bus request signal to the initiator via a register-through pass, and the process returns to step S72.

[0133] On the other hand, in step S73, if the variable response information of the additional information is disabled, or if the initiator identified by the initiator ID is not instructed to communicate via the register through path based on the selected information, the process proceeds to step S75.

[0134] In step S75, the target responds to the initiator via a register latch path to the command included in the bus request signal, with a delay of one cycle of the clock signal, and the process returns to step S72.

[0135] Through the above processing, the target (memory control circuits 241-1 to 241-3) responds to the commands included in the bus request signal via the register-through path to the initiator, based on the additional information in the bus request signal from the initiator and the selection information from the system manager 211, if the variable response information is enabled and, based on the selection information, the initiator identified by the initiator ID is instructed to communicate via the register-through path. This suppresses responses via unnecessary register-latch paths, thereby reducing latency and preventing performance degradation.

[0136] Furthermore, if the variable response information of the additional information is disabled, or if the initiator identified by the initiator ID is not instructed to communicate via the register-through path based on the selection information, the target will respond to the initiator via the register-latch path with a one-cycle delay to the commands included in the bus request signal. This results in a response that is delayed by one cycle due to being latched by the register, but it makes it possible to achieve operation at the target operating frequency.

[0137] <Specific Operation Example of the Information Processing System Disclosed> Here, with reference to the timing charts in Figures 12 and 13, a specific operation example of the information processing system 201 disclosed in this disclosure will be described when the maximum operating frequency table (MAX Frequency Table Register) is the table in Figure 7.

[0138] Figure 12 is a timing chart illustrating the processing when only the register latch path is used, and Figure 13 is a timing chart illustrating the processing when the information processing system 201 of this disclosure switches between the register latch path and the register through path.

[0139] Furthermore, the timing charts in Figures 12 and 13 illustrate the timing of when the initiator sequentially requests the target to perform the following read operations, consisting of the first to fifth processes, and when the target executes these read operations in response to the requests. Note that while this explanation focuses on the timing of the target's read operations, the timing for the target's write operations is similar. Therefore, the explanation of the target's write operations is omitted.

[0140] Furthermore, Figure 12 shows, from top to bottom, the clock, the initiator that is the main operator, the command (COMM), the address (ADDR), the state (STAT), and the target read data (RDAT). In Figure 13, the second row from the top is designated as additional information (INFO), and the rest is the same as in Figure 12.

[0141] Furthermore, the first process involves the initiator, the instruction fetch circuit 231, instructing the target, the memory control circuit (Address Space A) 241-1, to read data, and in response, the memory control circuit (Address Space A) 241-1 reads the data.

[0142] Furthermore, the second process involves the instruction fetch circuit 231 instructing the memory control circuit (Address Space B) 241-2 to read data, and the memory control circuit (Address Space B) 241-2 reading the data in response.

[0143] Furthermore, the third process involves the load-store circuit 232, which acts as the initiator, instructing the target memory control circuit (Address Space C) 241-3 to read data, and in response, the memory control circuit (Address Space C) 241-3 reads the data.

[0144] Furthermore, the fourth process involves the load / store circuit 232 instructing the memory control circuit (Address Space A) 241-1 to read data, and the memory control circuit (Address Space A) 241-1 reading the data in response.

[0145] Furthermore, the fifth process involves the initiator, the DMA control circuit 233, instructing the target, the memory control circuit (Address Space B) 241-2, to read the data, and in response, the memory control circuit (Address Space B) 241-2 reads the data.

[0146] <Example of processing when using only the register latch path> That is, when using only the register latch path, in the clock period from time T0 to T1 in Figure 12, during the period t0 to t1 starting from time t0, as the first processing described above, the instruction fetch circuit 231, which is the initiator, supplies a bus request signal that includes a data read instruction (COMM = READ) and an address (ADDR = Address Space A) that specifies the target to the memory control circuit (Address Space A) 241-1.

[0147] At this time, the target memory control circuit (Address Space A) 241-1 is in the READY state and therefore receives a bus request signal from the instruction fetch circuit 231.

[0148] Through this process, the memory control circuit (Address Space A) 241-1 recognizes a data read command from the initiator instruction fetch circuit 231, and controls the selector 242-2-1 to read data from the SRAM 244-1 via the register latch path (via register 243-2-1 and selector 242-2-1).

[0149] In other words, since the processing is done via a register latch path, the read data is latched in register 243-2-1 for a period t1 to t2, starting from time t1, within the clock period from time T1 to T2. Therefore, the memory control circuit (Address Space A) 241-1 enters a WAIT state for one cycle of the clock period.

[0150] Then, in the clock period from time T2 to T3, during the period t2 to t3 starting from time t2, the memory control circuit (Address Space A) 241-1 reads the data latched in register 243-2-1 as valid data A from SRAM 244-1.

[0151] At the same time, as the second process described above, the initiator, the instruction fetch circuit 231, supplies a bus request signal that includes a data read instruction (COMM = READ) and an address (ADDR = Address Space B) that specifies the target to the memory control circuit (Address Space B) 241-2.

[0152] At this time, the target memory control circuit (Address Space B) 241-2 is in the READY state and therefore receives a bus request signal from the instruction fetch circuit 231.

[0153] Through this process, the memory control circuit (Address Space B) 241-2 recognizes a data read command from the initiator instruction fetch circuit 231, and controls the selector 242-2-2 to read data from the SRAM 244-2 via the register latch path (through register 243-2-2 and selector 242-2-2).

[0154] Here too, since the processing is done via the register latch path, the read data is latched in register 243-2-2 for the period t3-t4, starting from time t3, within the clock period from time T3 to T4. Therefore, the memory control circuit (Address Space A) 241-2 enters a WAIT state for one cycle of the clock period.

[0155] Then, in the clock period from time T4 to T5, during the period t4 to t5 starting from time t4, the memory control circuit (Address Space A) 241-2 reads the data latched in register 243-2-2 as valid data B from SRAM 244-2.

[0156] At the same time, as the third process described above, the load-store circuit 232, which is the initiator, supplies a bus request signal that includes a data read command (COMM = READ) and an address (ADDR = Address Space C) that specifies the target to the memory control circuit (Address Space C) 241-3.

[0157] At this time, the target memory control circuit (Address Space C) 241-3 is in a READY state and therefore receives a bus request signal from the load / store circuit 232.

[0158] Through this process, the memory control circuit (Address Space C) 241-3 recognizes a data read command from the initiator load-store circuit 232, and controls the selector 242-2-3 to read data from the SRAM 244-3 via the register latch path (through registers 243-2-3 and selector 242-2-3).

[0159] In other words, since the processing is done via a register latch path, the read data is latched in register 243-2-3 for the period t5-t6, starting from time t5, within the clock period from time T5 to T6. Therefore, the memory control circuit (Address Space A) 241-3 enters a WAIT state for one cycle of the clock period.

[0160] Then, in the clock period from time T6 to T7, during the period t6 to t7 starting from time t6, the memory control circuit (Address Space C) 241-3 reads the data latched in register 243-2-3 as valid data C from SRAM 244-3.

[0161] At the same time, as the fourth process described above, the load-store circuit 232, which is the initiator, supplies a bus request signal that includes a data read command (COMM = READ) and an address (ADDR = Address Space A) that specifies the target to the memory control circuit (Address Space A) 241-1.

[0162] At this time, the target memory control circuit (Address Space A) 241-1 is in the READY state and therefore receives a bus request signal from the load / store circuit 232.

[0163] Through this process, the memory control circuit (Address Space A) 241-1 recognizes a data read command from the initiator load-store circuit 232, and controls the selector 242-1-2 to read data from the SRAM 244-1 via the register latch path (via register 243-2-1 and selector 242-2-1).

[0164] Here too, processing takes place via the register latch path, so the read data is latched in register 243-2-1 for the period t7-t8, starting from time t7, within the clock period from time T7 to T8. Therefore, the memory control circuit (Address Space A) 241-1 enters a WAIT state for one cycle of the clock period.

[0165] Then, in the clock period from time T8 to T9, during the period t8 to t9 starting from time t8, the memory control circuit (Address Space A) 241-1 reads the data latched in register 243-1-2 as valid data A from SRAM 244-1.

[0166] At the same time, as the fifth process described above, the DMA control circuit 233, which is the initiator, supplies a bus request signal that includes a data read command (COMM = READ) and an address (ADDR = Address Space B) that specifies the target to the memory control circuit (Address Space B) 241-2.

[0167] At this time, the target memory control circuit (Address Space B) 241-2 is in a READY state and therefore receives a bus request signal from the DMA control circuit 233.

[0168] Through this process, the memory control circuit (Address Space B) 241-2 recognizes the data read command from the initiator DMA control circuit 233, and controls the selector 242-2-2 to read the data from the SRAM 244-2 via the register latch path (via register 243-2-2 and selector 242-2-2).

[0169] Here too, since the processing is done via the register latch path, the read data is latched in register 243-2-2 for the period t9-t10, starting from time t9, within the clock period from time T9 to T10. Therefore, the memory control circuit (Address Space B) 241-2 enters a WAIT state for one cycle of the clock period.

[0170] Then, in the clock period from time T10 to T11, during the period t10 to t11 starting from time t10, the memory control circuit (Address Space B) 241-2 reads the data latched in register 243-2-2 as valid data B from SRAM 244-2.

[0171] <Example of processing by the information processing system of this disclosure> On the other hand, the information processing system 201 of this disclosure performs the following processing as shown in the timing chart of Figure 13.

[0172] In other words, in the clock period from time T0 to T1 in Figure 13, during the period t0 to t1 starting from time t0, as the first process described above, the initiator instruction fetch circuit 231 supplies a bus request signal containing 0b000 as additional information INFO, along with a data read instruction (COMM = READ) and an address (ADDR = Address Space A) that specifies the target to the memory control circuit (Address Space A) 241-1. Note that in the additional information INFO, only the lower three bits (bit2, bit1, bit0) contain information. Here, (bit2, bit1, bit0) is (0,0,0), so the initiator ID of the instruction fetch circuit 231 is represented from (bit2, bit1), and since bit0 is 0, it is represented that the response variable information is disabled.

[0173] At this time, the target memory control circuit (Address Space A) 241-1, being in the READY state, receives a bus request signal from the instruction fetch circuit 231 that includes a command and additional information.

[0174] Through this process, the memory control circuit (Address Space A) 241-1 recognizes a data read command from the initiator instruction fetch circuit 231, and, since the response variable is disabled, controls the selector 242-2-1 to read data from the SRAM 244-1 via the register latch path (via register 243-2-1 and selector 242-2-1).

[0175] In other words, since the processing is done via a register latch path, the read data is latched in register 243-2-1 for a period t1 to t2, starting from time t1, within the clock period from time T1 to T2. Therefore, the memory control circuit (Address Space A) 241-1 enters a WAIT state for one cycle of the clock period.

[0176] Then, in the clock period from time T2 to T3, during the period t2 to t3 starting from time t2, the memory control circuit (Address Space A) 241-1 reads the data latched in register 243-2-1 as valid data A from SRAM 244-1.

[0177] At the same time, as the second process described above, the initiator, the instruction fetch circuit 231, supplies a bus request signal containing 0b001 as additional information INFO, along with a data read instruction (COMM = READ) and an address (ADDR = Address Space B) that specifies the target to the memory control circuit (Address Space B) 241-2. Here, since the lower three bits (bit2, bit1, bit0) are (0,0,1), the initiator ID of the instruction fetch circuit 231 is represented from (bit2, bit1), and since bit0 is 1, it is expressed that the response variable information is enabled.

[0178] At this time, the target memory control circuit (Address Space B) 241-2 is in a READY state and therefore receives a bus request signal from the instruction fetch circuit 231 that includes a command and additional information.

[0179] Through this process, the memory control circuit (Address Space B) 241-2 recognizes a data read command from the initiator instruction fetch circuit 231, and, since it is responsive, it determines whether to use a register latch path or a register through path based on selection information supplied in advance by the system manager 211. According to the maximum operating frequency table (MAX Frequency Table Register) in Figure 7, the maximum operating frequency of the instruction fetch circuit 231 during read communication with the memory control circuit 241-1 is 200 MHz. Therefore, when the target operating frequency is 180 MHz, the selection information is set to select the register through path.

[0180] Therefore, the memory control circuit (Address Space B) 241-2 controls the selector 242-2-2 based on the selection information to read data from the SRAM 244-2 via a register-through path (a path that does not go through selector 242-2-2).

[0181] In this case, since processing is performed via a register through-path, the read data is not latched in register 243-2-2. Therefore, in the clock period from time t3 to t4, the memory control circuit (Address Space A) 241-2 reads the data valid data B from SRAM 244-2 without going through register 243-2-2. In other words, in this process, the data valid data B from SRAM 244-2 is read directly without going through register 243-2-2, so the state of the period from time t3 to t4 becomes READY, and the data is read immediately without any WAIT occurring. This prevents the selection of unnecessary register latch paths, thus suppressing latency.

[0182] Also, simultaneously, as the third process described above, the load-store circuit 232, which is the initiator, supplies a bus request signal containing 0b011 as additional information INFO, along with a data read command (COMM = READ) and an address (ADDR = Address Space C) that specifies the target to the memory control circuit (Address Space C) 241-3.

[0183] At this time, the target memory control circuit (Address Space C) 241-3, being in the READY state, receives a bus request signal from the load / store circuit 232 that includes a command and additional information.

[0184] Through this process, the memory control circuit (Address Space C) 241-3 recognizes a data read command from the initiator load-store circuit 232 and, since it is responsive, determines whether to use a register latch path or a register through path based on selection information supplied in advance by the system manager 211. According to the maximum operating frequency table (MAX Frequency Table Register) in Figure 7, the maximum operating frequency during reading in communication with the memory control circuit 241-3 of the load-store circuit 232 is 150 MHz. Therefore, when the target operating frequency is 180 MHz, the selection information is set to select the register latch path.

[0185] Therefore, the memory control circuit (Address Space C) 241-3 controls the selector 242-2-3 to read data from the SRAM 244-3 via the register latch path (register 243-2-3 and selector 242-2-3).

[0186] In other words, since the processing is done via a register latch path, the read data is latched in register 243-2-3 for the period t4-t5, starting from time t4, within the clock period from time T4 to T5. Therefore, the memory control circuit (Address Space A) 241-3 enters a WAIT state for one cycle of the clock period.

[0187] Then, in the clock period from time T5 to T6, during the period t5 to t6 starting from time t5, the memory control circuit (Address Space C) 241-3 reads the data latched in register 243-2-3 as valid data C from SRAM 244-3.

[0188] At the same time, as the fourth process described above, the load-store circuit 232, which is the initiator, supplies a bus request signal that includes a data read command (COMM = READ), an address (ADDR = Address Space A) that specifies the target to the memory control circuit (Address Space A) 241-1, and additional information INFO, which includes 0b011.

[0189] At this time, the target memory control circuit (Address Space A) 241-1, being in the READY state, receives a bus request signal from the load / store circuit 232 that includes a command and additional information.

[0190] Through this process, the memory control circuit (Address Space A) 241-1 recognizes the data read command from the initiator load-store circuit 232 and, since it is responsive, determines whether to use a register latch path or a register through path based on selection information supplied in advance by the system manager 211. According to the maximum operating frequency table (MAX Frequency Table Register) in Figure 7, the maximum operating frequency of the load-store circuit 232 during read communication with the memory control circuit 241-1 is 200 MHz. Therefore, when the target operating frequency is 180 MHz, the selection information is set to select the register through path.

[0191] Therefore, the memory control circuit (Address Space A) 241-1 controls the selector 242-2-1 to read data from the SRAM 244-1 via a register-through path (a path that does not go through register 243-2-1).

[0192] In this case, since processing is performed via a register through-path, the read data is not latched in register 243-2-1. Therefore, in the clock period from time t6 to t7, the memory control circuit (Address Space A) 241-1 reads the data valid data A from SRAM 244-1 without going through register 243-2-1. In other words, in this process, the data valid data A is read directly from SRAM 244-1 without going through register 243-2-1, so the state in the period from time t6 to t7 becomes READY, and the data is read immediately without any WAIT occurring. This prevents the selection of unnecessary register latch paths, thus suppressing latency.

[0193] At the same time, as the fifth process described above, the DMA control circuit 233, which is the initiator, supplies a bus request signal that includes a data read command (COMM = READ), an address (ADDR = Address Space B) specifying the target to the memory control circuit (Address Space B) 241-2, and additional information INFO, which includes 0b101.

[0194] At this time, the target memory control circuit (Address Space B) 241-2 is in a READY state and therefore receives a bus request signal from the DMA control circuit 233 that includes a command and additional information.

[0195] Through this process, the memory control circuit (Address Space B) 241-2 recognizes the data read command from the initiator DMA control circuit 233, and, since it is responsive, it determines whether to use a register latch path or a register through path based on selection information supplied in advance by the system manager 211. According to the maximum operating frequency table (MAX Frequency Table Register) in Figure 7, the maximum operating frequency of the DMA control circuit 233 during reading in communication with the memory control circuit 241-2 is 150 MHz. Therefore, when the target operating frequency is 180 MHz, the selection information is set to select the register latch path.

[0196] Therefore, the memory control circuit (Address Space B) 241-2 controls the selector 242-2-2 to read data from the SRAM 244-2 via the register latch path (register 243-2-2 and selector 242-2-2).

[0197] In other words, since the processing is done via a register latch path, the read data is latched in register 243-2-2 for the period t7-t8, starting from time t7, within the clock period from time T7 to T8. Therefore, the memory control circuit (Address Space B) 241-2 enters a WAIT state for one cycle of the clock period.

[0198] Then, in the clock period from time T8 to T9, during the period t8 to t9 starting from time t8, the memory control circuit (Address Space B) 241-2 reads the data latched in register 243-2-2 as valid data B from SRAM 244-2.

[0199] As described above, the processes explained with reference to the timing charts in Figures 12 and 13 are all the same processes that execute the first to fifth processes.

[0200] However, in the case of processing that is executed only by the register latch path as explained with reference to the timing chart in Figure 12, it is performed during the period from time t0 to t11, whereas in the information processing system 201 of this disclosure as explained with reference to the timing chart in Figure 13, it is performed during the period from time t0 to t9.

[0201] In other words, in this disclosure, based on the maximum operating frequency table (MAX Frequency Table Register) in Figure 7, the register latch path is used only for processing initiators and targets that cannot operate at the target operating frequency, while processing of initiators and targets that can operate at the target operating frequency is performed via the register through path.

[0202] As a result, by processing the interaction between the initiator and target, which can operate at the target operating frequency, using a register-through path, unnecessary latency can be suppressed, thereby preventing a decrease in processing performance.

[0203] Furthermore, by using a register latch path to handle the interaction between an initiator and target that cannot operate at the target operating frequency, it becomes possible to reliably achieve operation at the target operating frequency.

[0204] <<3. First Modification>> In the above, we have described examples in which the maximum operating frequency table (MAX Frequency Table Register) is either written to at startup or updated when the user prepares a new value and requests an update in response to some change in the operating environment.

[0205] However, the system manager 211 may acquire information related to the operating environment, such as the operating temperature, power supply voltage, and operating frequency of the initiator and target, and may also pre-store multiple maximum operating frequency tables (MAX Frequency Table Registers) corresponding to the operating environment, and autonomously update the maximum operating frequency tables (MAX Frequency Table Registers) in response to changes in the acquired operating environment.

[0206] Figure 14 shows a first modified example of an information processing system that autonomously updates the maximum operating frequency table (MAX Frequency Table Register) in response to changes in the operating environment.

[0207] In the information processing system 201' of Figure 14, components with the same functions as those in the information processing system 201 of Figure 6 are denoted by the same reference numerals, and their explanations are omitted as appropriate.

[0208] The difference between the information processing system 201' in Figure 14 and the information processing system 201 in Figure 6 is that a system manager 211' is provided instead of a system manager 211.

[0209] The system manager 211' acquires information on temperature, power supply voltage, and operating frequency related to the operating environment of the initiator and target from the temperature monitoring circuit 311, the electrode supply circuit 312, and the clock generator 313, respectively, and updates the maximum operating frequency table (MAX Frequency Table Register) according to the acquired operating environment information.

[0210] More specifically, the system manager 211' includes an operating environment-specific table storage unit 211a' which stores the values ​​of multiple maximum operating frequency tables (MAX Frequency Table Registers) for each operating environment.

[0211] Then, based on the acquired information on temperature, power supply voltage, and operating frequency related to the operating environment of the initiator and target, the system manager 211' reads the value corresponding to the current operating environment from the operating environment-specific table storage unit 211a' when there is a change greater than a predetermined magnitude in the current maximum operating frequency table and the corresponding operating environment, and autonomously updates the maximum operating frequency table.

[0212] Furthermore, the processing performed by the information processing system 201 in Figure 14 is basically the same as the processing described with reference to the flowcharts in Figures 9 to 11, so its explanation will be omitted. However, regarding the processing in step S37 of the flowchart in Figure 9, the system manager 211' determines whether an update is necessary based on whether the difference between the current operating environment and the operating environment corresponding to the currently set maximum operating frequency table (MAX Frequency Table Register) is greater than a predetermined value.

[0213] If it is determined that an update is necessary, the process returns to step S32, and after the response variable information of the additional information is updated to disable response variable, in step S33, the system manager 211' autonomously updates the maximum operating frequency table by reading the table values ​​corresponding to the current operating environment from the operating environment table storage unit 211a' and writing them to the maximum operating frequency table (MAX Frequency Table Register). At this time, the system manager 211' generates new selection information for each target based on the new maximum operating frequency table and distributes it to each target.

[0214] This configuration enables processing using an optimal maximum operating frequency table according to the operating state, allowing for more dynamic operation and more appropriate switching between the register through path and the register latch path. This makes it possible to achieve operation at the target operating frequency while suppressing latency caused by unnecessary register latch paths, thereby reducing performance degradation.

[0215] <<4. Second Modification>> In the above, we have described an example in which initiators and targets are connected to a single bus 210. However, by connecting multiple buses with a relay controller equipped with both target and initiator functions, a configuration that can accommodate a more complex bus topology is also possible.

[0216] Figure 15 shows an example of an information processing system configuration with a more complex bus topology, achieved by connecting multiple buses with relay controllers that have both target and initiator functions.

[0217] In the information processing system 201'' of Figure 15, components having the same functions as those in the information processing system 201 of Figure 6 are denoted by the same reference numerals, and their explanations are omitted as appropriate.

[0218] In the information processing system 201'' of Figure 15, the difference from the information processing system 201 of Figure 6 is that bus 210-1 is provided instead of bus 210, and a new bus 210-2 is also provided, and furthermore, the two buses 210-1 and 210-2 are connected by a relay controller 351 that has both target and initiator functions.

[0219] Furthermore, in bus 210-1, a relay controller 351 is connected in place of memory controllers 214-1 and 214-2.

[0220] Furthermore, the bus 210-2 is connected to memory controllers 214-1 and 214-2, and a relay controller 351.

[0221] Furthermore, a system manager 211'' is provided instead of system manager 211.

[0222] The relay controller 351 includes a relay control circuit 361 that functions as a target, a relay control circuit 362 that functions as an initiator, and further includes selectors 371-1 and 371-2, and registers 372-1 and 372-2 that connect the relay control circuits 361 and 362.

[0223] In other words, the relay control circuit 361, which functions as a target, exchanges bus read data signals and bus slide data signals based on bus request signals from the initiators (instruction fetch circuit 231, load / store circuit 232, and DMA control circuit 233) connected via bus 210-1.

[0224] In this case, the relay control circuit 361 controls the selector 371-1 based on the additional signal and selection information to choose whether the write data should be a register latch path (a path that goes through register 372-1) or a register through path (a path that does not go through register 372-1), and supplies the write data to the relay control circuit 362 which functions as an initiator on the bus 210-2 side.

[0225] Furthermore, based on the additional signal and selection information, the relay control circuit 361 controls the selector 371-2 to choose whether the read data should be a register latch path (a path via register 372-2) or a register through path (a path that does not go through register 372-2), and acquires the read data from the relay control circuit 362, which functions as an initiator on the bus 210-2 side.

[0226] The relay control circuit 362 functions as an initiator and operates similarly to the initiators, the instruction fetch circuit 231, the load-store circuit 232, and the DMA control circuit 233.

[0227] System manager 211'' is identical to system manager 211 in its basic functions, but supplies a Configuration Activation Register to the instruction fetch circuit 231, load / store circuit 232, and DMA control circuit 233, which function as initiators, and the relay control circuit 361, respectively, via buses 210-1 and 210-2.

[0228] Furthermore, the system manager 211'' writes and updates values ​​in the maximum operating frequency table (MAX Frequency Table Register), and generates and distributes selection information for each target (memory control circuits 241-1 to 241-3, and relay control circuit 362) based on the maximum operating frequency table.

[0229] Furthermore, the processing of the system manager 211'', the initiator, and the target are basically the same as those explained with reference to the flowcharts in Figures 9 to 11, so their explanation will be omitted.

[0230] This configuration makes it possible to achieve operation at the target operating frequency even in information processing systems with more complex bus topology structures, while suppressing latency caused by unnecessary register latch paths and reducing processing performance degradation.

[0231] Furthermore, in this specification, a system means a collection of multiple components (devices, modules (parts), etc.), regardless of whether all components are located in the same enclosure or not. Therefore, multiple devices housed in separate enclosures and connected via a network, and a single device in which multiple modules are housed in one enclosure, are both considered systems.

[0232] Furthermore, the embodiments of this disclosure are not limited to those described above, and various modifications are possible without departing from the gist of this disclosure.

[0233] For example, this disclosure can take the form of cloud computing, in which a single function is shared and processed collaboratively by multiple devices via a network.

[0234] Furthermore, each step described in the flowchart above can be performed by a single device, or it can be divided and performed by multiple devices.

[0235] Furthermore, if a single step includes multiple processes, those processes can be executed by a single device or shared among multiple devices.

[0236] Furthermore, among the processes described in the embodiments of this disclosure described above, all or part of the processes described as being performed automatically may be performed manually, or all or part of the processes described as being performed manually may be performed automatically by known methods. In addition, the processing procedures, specific names, and information including various data and parameters shown in the above document and drawings may be changed at will unless otherwise specified. For example, the various information shown in each figure is not limited to the information shown.

[0237] Furthermore, each component of the illustrated device is a functional concept and does not necessarily have to be physically configured as shown. In other words, the specific forms of distribution and integration of each device are not limited to those shown, and all or part of them can be functionally or physically distributed and integrated in any unit according to various loads and usage conditions.

[0238] Furthermore, the embodiments of this disclosure described above can be combined as appropriate in areas that do not contradict the processing content. Also, the steps shown in the sequence diagram or flowchart of this embodiment can be changed in order as appropriate. For example, each step may be processed chronologically, repeatedly, or partially in parallel.

[0239] Furthermore, this disclosure may also take the following configurations: <1> An information processing method for an information processing system comprising: a path for transferring data for a target to read or write data based on an instruction from an initiator in a System On Chip (SoC) consisting of at least one initiator and at least one target, the path comprising: a first path passing through a storage unit that stores the data; and a second path not passing through the storage unit, wherein the method includes a selection process to select either the first path or the second path depending on the initiator that supplied the instruction. <2> The information processing method for an information processing system according to <1>, wherein the selection process selects either the first path or the second path based on a combination of the initiator that supplied the instruction and the target. <3> The selection process selects either the first path or the second path based on the operating frequency at which the target operates in accordance with the instructions supplied by the initiator, which is determined by the combination of the initiator that supplied the instructions and the target, as described in <2>. <4> The selection process selects either the first path or the second path based on a comparison between the operating frequency at which the target operates and the operating frequency targeted by the information processing system, as described in <3>. <5> The selection process selects the first path if the operating frequency at which the target operates is lower than the operating frequency targeted by the information processing system, as described in <4>. <6> The selection process selects the second path if the operating frequency at which the target operates is higher than the operating frequency targeted by the information processing system, as described in <4>.<7> An information processing method for an information processing system according to <2>, further comprising: an acquisition process to acquire selection information for each initiator, the selection process to select the first path or the second path, the selection information indicating which path to select for the initiator that has supplied the instruction; <8> An information processing method for an information processing system according to <7>, wherein the selection information is generated for each target based on each value in a table consisting of the maximum operating frequencies on which the target can operate for each combination of the initiator and the target, and a target operating frequency in the information processing system; <9> An information processing method for an information processing system according to <8>, wherein the table is a table consisting of the maximum operating frequencies on which the target can operate for each combination of the initiator and the type of instruction supplied by the initiator and the target. <10> The selection information is information indicating which of the first or second path to select, based on a comparison between the maximum operating frequency on which the target can operate, as specified in the table for each target from the types of the initiator and the instruction, and the operating frequency targeted by the information processing system. The information processing method for the information processing system according to <9>. <11> The selection information is information indicating that the first path is selected when the maximum operating frequency on which the target can operate, as specified in the table for each target from the types of the initiator and the instruction, is smaller than the operating frequency targeted by the information processing system. The information processing method for the information processing system according to <10>. <12> The selection information is information indicating that the second path is selected when the maximum operating frequency on which the target can operate, as specified in the table for each target from the types of the initiator and the instruction, is larger than the operating frequency targeted by the information processing system. The information processing method for the information processing system according to <10>.<13> The table is different depending on the operating environment of the initiator and the target. <14> The operating environment is the operating temperature, power supply voltage, and operating frequency. <15> The table is updated according to the changes in the operating environment. <16> When the table is updated according to the changes in the operating environment, the selection information is also updated based on the updated table. <17> From the start to the completion of the update of the table in response to the changes in the operating environment, the selection process is information for selecting the first path. <18> When the initiator supplies the command to the target, it supplies additional information along with the command, consisting of an initiator ID that identifies itself and instruction information that either instructs to select the first route regardless of the selection information, or instructs to select either the first route or the second route based on the selection information, and at startup, until each value in the table is written, or when the table is updated in response to a change in the operating environment, from the start of the update until it is completed, the additional information includes instruction information that instructs to select the first route regardless of the selection information, and the selection process selects the first route based on the instruction information in the additional information. The information processing method for the information processing system described in <16>. <19> After each value in the table has been written, or after the update has been completed, the additional information includes instruction information that instructs to select either the first route or the second route based on the selection information, and the selection process selects either the first route or the second route based on the selection information based on the instruction information in the additional information. The information processing method for the information processing system according to <18>.<20> An information processing system comprising: a first path for transferring data to be read or written by a target based on an instruction from an initiator in a System On Chip (SoC) consisting of at least one initiator and at least one target, the first path passing through a storage unit that stores the data, a second path not passing through the storage unit, and a selection unit that selects the first path or the second path according to the initiator that supplied the instruction.

[0240] 201, 101', 201'' Information processing system, 210, 210-1, 210-2 Bus, 211, 211', 211'' System manager, 211a' Operating environment-specific table storage unit, 212 CPU, 213 DMAC, 214, 214-1 to 214-3 Memory controller, 231 Instruction fetch circuit, 232 Load / store circuit, 233 DMA control circuit, 241, 241-1 to 241-3 Memory control circuit, 242, 242-1-1 to 242-1-3, 242-2-1 to 242-2-3 Selector, 243, 243-1-1 to 243-1-3, 243-2-1 to 243-2-3 Register, 244-1 to 244-3 SRAM, 351 Relay controllers, 361, 362; Relay control circuits, 371-1, 371-2; Selectors, 372-1, 372-2; Registers

Claims

1. An information processing method for an information processing system comprising: a path for transferring data for a target to read or write data based on an instruction from an initiator in a System On Chip (SoC) consisting of at least one initiator and at least one target, the path comprising: a first path passing through a storage unit that stores the data; and a second path not passing through the storage unit, wherein the method includes a selection process to select either the first path or the second path depending on the initiator that supplied the instruction.

2. The information processing method for the information processing system according to claim 1, wherein the selection process selects the first path or the second path based on the combination of the initiator that supplied the instruction and the target.

3. The information processing method for an information processing system according to claim 2, wherein the selection process selects either the first path or the second path based on the operating frequency at which the target operates in accordance with the instruction supplied by the initiator, which is determined by the combination of the initiator that supplied the instruction and the target.

4. The information processing method for the information processing system according to claim 3, wherein the selection process selects the first path or the second path based on a comparison between the operating frequency when the target is operating and the target operating frequency in the information processing system.

5. The information processing method for the information processing system according to claim 4, wherein the selection process selects the first path when the operating frequency of the target is lower than the target operating frequency in the information processing system.

6. The information processing method for the information processing system according to claim 4, wherein the selection process selects the second path when the operating frequency of the target is higher than the target operating frequency in the information processing system.

7. An information processing method for an information processing system according to claim 2, further comprising an acquisition process to acquire selection information for each initiator, the selection process comprising selecting the first route or the second route, the selection information indicating that the selection is to be made for the initiator that supplied the command.

8. The information processing method for the information processing system according to claim 7, wherein the selection information is generated for each target based on the values ​​in a table consisting of the maximum operating frequencies at which the target can operate for each combination of the initiator and the target, and the target operating frequency in the information processing system.

9. The information processing method for the information processing system according to claim 8, wherein the table is a table consisting of the maximum operating frequency on which the target can operate for each combination of the initiator, the type of instruction supplied by the initiator, and the target.

10. The information processing method for the information processing system according to claim 9, wherein the selection information is information indicating which of the first path or the second path to select, based on a comparison between the maximum operating frequency on which the target can operate, which is identified in the table from the type of initiator and the instruction for each target, and the operating frequency targeted in the information processing system.

11. The information processing method for the information processing system according to claim 10, wherein the selection information is information indicating that, for each target in the table, the first path is selected if the maximum operating frequency on which the target can operate, which is determined from the type of initiator and the instruction, is smaller than the target operating frequency in the information processing system.

12. The information processing method for the information processing system according to claim 10, wherein the selection information is information indicating that, in the table, for each target, if the maximum operating frequency on which the target can operate, which is determined from the type of initiator and the instruction, is greater than the operating frequency targeted by the information processing system, the second path is selected.

13. The table is different depending on the operating environment of the initiator and the target.

14. The information processing method for the information processing system according to claim 13, wherein the operating environment is the operating temperature, power supply voltage, and operating frequency.

15. The information processing method for the information processing system according to claim 13, wherein the table is updated in accordance with changes in the operating environment.

16. The information processing method for the information processing system according to claim 15, wherein when the table is updated in accordance with a change in the operating environment, the selection information is also updated based on the updated table.

17. The information processing method for the information processing system according to claim 16, wherein the selection process is information for selecting the first path from the time the update of the table in response to the change in the operating environment is started until it is completed.

18. When the initiator supplies the command to the target, it supplies additional information along with the command, comprising an initiator ID that identifies itself, and instruction information that either instructs the target to select the first route independently of the selection information, or instructs the target to select either the first route or the second route based on the selection information; during startup, until each value in the table is written, or when the table is updated in response to a change in the operating environment, from the start of the update until it is completed, the additional information includes instruction information that instructs the target to select the first route independently of the selection information; and the selection process selects the first route based on the instruction information in the additional information; the information processing method for the information processing system according to claim 16.

19. An information processing method for an information processing system according to claim 18, wherein, after each value in the table has been written or after the update has been completed, the additional information includes instruction information that instructs to select either the first route or the second route based on the selection information, and the selection process selects either the first route or the second route based on the selection information based on the instruction information in the additional information.

20. An information processing system comprising: a path for transferring data for a target to read or write data based on an instruction from an initiator in a System On Chip (SoC) consisting of at least one initiator and at least one target, the path passing through a storage unit that stores the data; a second path that does not pass through the storage unit; and a selection unit that selects the first path or the second path according to the initiator that supplied the instruction.

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