Quantum bit element, method for manufacturing quantum bit element, and method for controlling quantum bit element

Abstract

The present invention reduces the probability of occurrence of an arithmetic error in a quantum bit element. A quantum bit element 11 comprises: a substrate 12 having a silicon crystal body 12a on the surface thereof; and a gate electrode 16 that is formed on the crystal body 12a, applies a voltage perpendicularly to the (111) plane of the crystal body 12a, and induces a potential in quantum dots in the crystal body 12a.

Description

Qubit element, method for manufacturing a qubit element, and method for controlling a qubit element

[0001] The present invention relates to a qubit element comprising a substrate having a silicon crystal and a gate electrode that induces an electric potential in quantum dots within the crystal, a method for manufacturing a qubit element, and a method for controlling a qubit element.

[0002] For example, Patent Document 1 describes a quantum device in which a controllably quantum mechanically coupled dangling bond extending from the surface of a semiconductor has an interval of at least one atom in the semiconductor, and at least one electrode selectively changes the electronic state of the dangling bond. Patent Document 2 describes a spin qubit type semiconductor element and its integrated circuit that can achieve both high-speed spin operation and high integration. Non-Patent Document 1 describes a technique that can achieve high yield in swap gate operation in a MOS type two-qubit element.

[0003] Japanese Patent Publication No. 2011-525050, Japanese Patent Publication No. 2023-81394

[0004] Hidehiro Asai et al., “Device structure and fabrication process for silicon spin qubit realizing "process-variation-robust SWAP gate operation", Japanese Journal of Applied Physics, 2023, 62, SC1088.

[0005] As disclosed in Non-Patent Document 1, CMOS (Complementary Metal-Oxide-Semiconductor) technology is generally applied to the manufacture of qubit elements. In CMOS technology, qubits are formed in the silicon layer below the gate silicon oxide layer, and electrodes are formed on top of the gate silicon oxide layer. The electrodes induce a potential perpendicular to the (100) plane of the silicon layer. At this time, spin-orbit interaction acts on electrons confined in the silicon crystal. Spin-orbit interaction effectively forms a magnetic field acting parallel to the (100) plane (in-plane direction), and charge noise causes fluctuations in the electron orbit. As a result, fluctuations occur in the direction of the electron spin, which is oriented by the external magnetic field. This shortens the coherence time and increases the probability of computation errors. Therefore, in qubit elements using CMOS technology, stabilizing the direction of the electron spin is a challenge in order to reduce the probability of computation errors. Other challenges and novel features will become clear from the description and accompanying drawings of this specification.

[0006] According to one embodiment of the present invention, a qubit element comprises a substrate having a silicon crystal on its surface, and a gate electrode formed on the crystal, which applies a voltage perpendicular to the (111) plane of the crystal, thereby inducing a potential for confining electrons in quantum dots within the crystal.

[0007] According to another embodiment of the present invention, the qubit element comprises a substrate having a silicon crystal on its surface, a first gate electrode formed on the crystal and extending linearly with a first width, which applies a voltage perpendicular to the (111) plane of the crystal and induces a potential for confining electrons in a first quantum dot within the crystal, a second gate electrode formed on the crystal in parallel with the first gate electrode and extending linearly with a second width, which applies a voltage perpendicular to the (111) plane of the crystal and induces a potential for confining electrons in a second quantum dot within the crystal, and on both sides of the combined first gate electrode and second gate electrode The device comprises two first barrier electrodes positioned and extending linearly with a third width in parallel with the first and second gate electrodes, applying a voltage perpendicular to the (111) plane of the crystal to induce a potential within the crystal and form a barrier to electrons; and a second barrier electrode positioned between the first and second gate electrodes and extending linearly with a fourth width in parallel with the first and second gate electrodes, applying a voltage perpendicular to the (111) plane of the crystal to induce a potential within the crystal and form a potential for controlling the interaction between two electrons beneath the first and second gate electrodes.

[0008] According to yet another embodiment of the present invention, a method for manufacturing a qubit element comprises the steps of: exposing a (111)-oriented silicon substrate to phosphorus gas; epitaxially growing a silicon crystal on the surface of the silicon substrate; depositing a material selectively deposited on a folded half on the surface of the crystal; depositing an electrode material on the crystal and the material selectively deposited on the folded half; and arranging a mask on the surface of the electrode material based on the material selectively deposited on the folded half, and aligning the shape of the electrode defined by the mask with the crystal.

[0009] According to an embodiment of the present invention, a method for controlling a qubit element is a method for controlling a qubit element comprising a substrate having a silicon crystal on its surface, wherein a voltage is applied perpendicular to the (111) plane of the crystal by a gate electrode formed on the crystal, thereby inducing a potential in quantum dots within the crystal and controlling the quantum dots.

[0010] According to an embodiment of the present invention, a method for controlling a qubit element is a method for controlling a qubit element comprising a substrate having a silicon crystal on its surface, wherein a voltage is applied perpendicular to the (111) plane of the crystal by a first gate electrode and a second gate electrode formed on the crystal, thereby inducing potentials in a first quantum dot and a second quantum dot within the crystal, and controlling the first quantum dot and the second quantum dot.

[0011] According to embodiments of the present invention, the probability of computation errors occurring in a qubit element can be reduced.

[0012] This is a conceptual diagram schematically showing the configuration of a qubit element according to the first embodiment of the present invention. This is a cross-sectional view along line 2-2 in Figure 1. This is a plan view of the qubit element. This is a conceptual diagram explaining the relationship between the orientation of the crystal and the spin-orbit interaction. This is a conceptual diagram showing a wafer used in the manufacture of the qubit element. This is a conceptual diagram showing fins sandwiched between oxide films on the wafer. This is a conceptual diagram showing a gate electrode and barrier electrode formed on the oxide film. This is a conceptual diagram schematically showing the configuration of a qubit element according to the second embodiment of the present invention. This is a cross-sectional view along line 9-9 in Figure 8. This is a conceptual diagram showing a wafer used in the manufacture of the qubit element. This is a conceptual diagram showing fins sandwiched between oxide films on the wafer. This is a conceptual diagram schematically showing the configuration of a qubit element according to the third embodiment of the present invention. This is a cross-sectional view along line 13-13 in Figure 12. This is a conceptual diagram showing a wafer used in the manufacture of the qubit element. This is a conceptual diagram showing fins sandwiched between oxide films on the wafer. This is a conceptual diagram schematically showing the configuration of a qubit element according to the fourth embodiment of the present invention. This is a cross-sectional view along line 17-17 in Figure 16. This is a plan view of the qubit element. This is a conceptual diagram schematically showing the configuration of a qubit element according to the fifth embodiment of the present invention. This is a cross-sectional view along line 20-20 in Figure 19. This is a conceptual diagram schematically showing the configuration of a qubit element according to the sixth embodiment of the present invention. This is a cross-sectional view along line 22-22 in Figure 21. This is a conceptual diagram schematically showing the configuration of a qubit element according to the seventh embodiment of the present invention. This is a conceptual diagram schematically showing the configuration of a qubit element according to the first modification of the seventh embodiment. This is a conceptual diagram schematically showing the configuration of a qubit element according to the second modification of the seventh embodiment. This is a conceptual diagram schematically showing the configuration of a qubit element according to the third modification of the seventh embodiment. This is a conceptual diagram schematically showing the configuration of a qubit element according to the fourth modification of the seventh embodiment. This is a conceptual diagram schematically showing the configuration of a qubit element according to the fifth modification of the seventh embodiment. This is a conceptual diagram schematically showing the configuration of a qubit element according to the sixth modification of the seventh embodiment. This is a conceptual diagram schematically showing the configuration of a qubit element according to the seventh modification of the seventh embodiment. This is a conceptual diagram schematically showing the configuration of a qubit element according to the eighth embodiment of the present invention. This is a conceptual diagram showing a wafer used in the manufacture of a qubit element.This is a conceptual diagram showing a crystalline structure and a silicon germanium layer that constitute a part of a fin formed on a wafer. This is a conceptual diagram showing a fin formed on a wafer. This is a conceptual diagram schematically showing the configuration of a qubit element according to one modification of the eighth embodiment. This is a conceptual diagram schematically showing the configuration of a qubit element according to the ninth embodiment of the present invention. This is a cross-sectional view along line 37-37 in Figure 36. This is a conceptual diagram showing a wafer used in the manufacture of a qubit element. This is an enlarged plan view schematically showing the 7x7 structure of a silicon substrate. This is a conceptual diagram showing phosphorus atoms adsorbed on the surface of a wafer. This is a conceptual diagram showing a crystalline structure epitaxially grown on the surface of a wafer. This is a conceptual diagram showing a band structure schematically representing the energy distribution of the conduction band and valence band of silicon. 43A is a conceptual diagram showing the position of point L in the Brillouin zone, and 43B is a conceptual diagram showing the position of point X0 in the Brillouin zone. This is a conceptual diagram showing the top perspective configuration of a qubit element according to the tenth embodiment. This is a conceptual diagram showing the top view configuration of the qubit element shown in Figure 44. This is a conceptual diagram schematically showing the relationship between the conduction band energy level of the first quantum dot and the Fermi level of the source region, and the relationship between the conduction band energy levels of the second quantum dot and the first quantum dot in the qubit element according to the 10th embodiment. 46A shows the state when electrons are injected into all levels below the L-point energy level of the first quantum dot, and 46B shows the state in which only the electrons in the L-point energy level of the first quantum dot move to the L-point energy level of the second quantum dot, and the electrons are confined to the L-point energy level of the crystalline band structure. This is a conceptual diagram showing the top perspective view configuration of the qubit element according to the 11th embodiment. 48A is Si. （１－ｘ） Ge ｘ Layer (where x < 0.8) and Si （１－ｘ） Ge ｘ This is a conceptual diagram showing the structure of a laminate including layers (where x is 0.8 ≤ x < 1), and Figure 48B shows Si （１－ｘ） Ge ｘFigure 29 shows a conceptual diagram of a qubit element according to a sixth modification of the seventh embodiment shown in Figure 29, and

[0013] The embodiments of the present invention will be described below with reference to the drawings. In all the drawings used to describe the embodiments, components having the same function will be denoted by the same or related reference numerals, and repeated descriptions will be omitted. In addition, if there are multiple similar components (parts), symbols may be added to the general reference numeral to indicate individual or specific parts. Furthermore, in the following embodiments, descriptions of the same or similar parts will not be repeated unless particularly necessary. Also, in the cross-sectional and plan views, the size of each part does not correspond to that of the actual device, and in order to make the drawings easier to understand, certain parts may be displayed relatively larger. Even when the cross-sectional and plan views correspond, certain parts may be displayed relatively larger in order to make the drawings easier to understand. Furthermore, in the following description, the X direction, Y direction, and Z direction will be used. The X direction and Y direction are orthogonal to each other and constitute the horizontal plane, and the Z direction is perpendicular to the horizontal plane. The direction parallel to the wafer surface (in-plane direction) is sometimes called the X-Y direction, the direction perpendicular to the wafer surface (perpendicular direction) is sometimes called the Z direction, and the plane in the X-Y direction is sometimes called the X-Y plane.

[0014] (First Embodiment) A qubit element according to the first embodiment of the present invention will be described with reference to Figures 1 to 7. First, the structure of the qubit element will be described. Figure 1 schematically shows the configuration of a qubit element 11 according to the first embodiment of the present invention. The qubit element 11 comprises a substrate 12 having a silicon crystal 12a on at least its surface. The substrate 12 is a silicon substrate with a (111) plane oriented perpendicular to the surface of the substrate 12. The crystal 12a is single-crystal silicon, with a (111) plane oriented perpendicular to the surface, and silicon with nuclear spin 0 (mass number 28) is used as the material. Fins 13 extending linearly with a predetermined width W1 protruding from the surface of the crystal 12a are formed on the surface of the crystal 12a by processing the crystal 12a. That is, the fins 13 are made of crystal 12a. Multiple rows of fins 13 may be arranged parallel to each other on a single substrate 12.

[0015] An oxide film 14 is formed on the surface of the crystal 12a. The oxide film 14 is made of, for example, silicon oxide. The oxide film 14 is formed to cover the sides of the fin 13. The surface of the oxide film 14 is planarized. The upper surface of the fin 13 is positioned flush with the planarized plane 15 of the oxide film 14.

[0016] A gate electrode 16 is positioned on the flattened plane 15. The gate electrode 16 extends linearly on the plane 15 with a predetermined width W2 and crosses the fin 13. Here, the gate electrode 16 extends in a straight line. Each edge of the gate electrode 16 extending in the linear direction forms a straight line.

[0017] An insulating layer 17 is formed between the gate electrode 16 and the plane 15, and between the gate electrode 16 and the fin 13. The insulating layer 17 is made of, for example, silicon oxide. The insulating layer 17 insulates the gate electrode 16 from the fin 13. As shown in Figure 2, quantum dots 23 are established within the fin 13 located below the gate electrode 16. The gate electrode 16 applies a voltage perpendicular to the (111) plane of the crystal 12a constituting the fin 13. The gate electrode 16 induces a potential in the quantum dots 23 within the crystal 12a constituting the fin 13.

[0018] On the flattened plane 15, two barrier electrodes 18 are arranged. The barrier electrodes 18 extend linearly on both sides of the gate electrode 16 in parallel with the gate electrode 16 with a width W3 determined on both sides of the gate electrode 16 and cross the fin 13. Here, each individual barrier electrode 18 extends linearly parallel to the gate electrode 16. In each individual barrier electrode 18, the ridge lines extending in its line direction each draw a straight line.

[0019] An insulating layer 19 is formed between the barrier electrode 18 and the plane 15 and between the barrier electrode 18 and the fin 13. The insulating layer 19 is formed of, for example, silicon oxide. The insulating layer 19 insulates the fin 13 from the barrier electrode 18. As shown in FIG. 2 described above, the barrier electrode 18 applies a voltage perpendicular to the (111) plane of the crystal 12a constituting the fin 13. The barrier electrode 18 induces a potential in the fin 13 and forms a barrier 21 for the electrons of the quantum dot 23.

[0020] As shown in FIG. 3, the intersection angles of the gate electrode 16, the two barrier electrodes 18, and the fin 13 in a top view are set to 90 degrees. It is desirable to set the width W2 of the gate electrode 16 and the width W1 of the fin 13 to the same value. In this case, the contour of the intersection region 22 in a top view is set to a square.

[0021] Next, the operation of the quantum bit element 11 will be described. In establishing the quantum dot, electrons are confined in the fin 13. When a voltage is applied perpendicularly to the (111) plane of the crystal 12a constituting the fin 13 from the gate electrode 16 and symmetrically in the X - Y plane within the X - Y plane, as shown in FIG. 4, in a crystal with a (111) orientation, a center of inversion is ensured as site symmetry, so the inversion symmetry becomes high. That is, in the quantum bit element 11 according to the first embodiment, since the inversion symmetry becomes high, the spin - orbit interaction acting on the electrons becomes extremely small. The direction of the electron spin aligns with the direction of the magnetic field when an external magnetic field is applied. Since the spin - orbit interaction acting on the electrons is extremely small, the direction of the electron spin is stabilized.

[0022] When a voltage is supplied to the barrier electrode 18, a potential is induced perpendicularly to the (111) plane of the crystal 12a constituting the fin 13 from the barrier electrode 18. As shown in FIG. 2 described above, the electric field forms a barrier 21 for electrons. The movement of electrons in the line direction of the fin 13 is restricted. Electrons are confined in the fin 13 under the gate electrode 16. Under the gate electrode 16, a potential is induced from the gate electrode 16 to the fin 13, and the quantum dot 23 is well controlled. When a voltage is applied perpendicularly to the (111) plane of the crystal 12a constituting the fin 13 from the barrier electrode 18 while maintaining inversion symmetry about the center of the quantum dot 23 in the X - Y plane, as shown in FIG. 4 described above, in a crystal with (111) orientation, an inversion center is ensured as site symmetry, so the inversion symmetry is increased. That is, in the quantum bit element 11 according to the first embodiment, since the inversion symmetry is increased, the spin - orbit interaction acting on the electrons confined in the fin 13 under the gate electrode 16 becomes extremely small, so the direction of the electron spin is stabilized.

[0023] According to the discovery of the present inventor, as shown in FIG. 4 described above, even when a voltage is applied perpendicularly to the (110) plane in the silicon crystal, no inversion center occurs as site symmetry. This is because along the (110) axis, there may be no other atom at the position where the atoms in the lattice are rotated 180 degrees around this axis. The Dresselhaus spin - orbit interaction and the Rashba spin - orbit interaction occur. Charge noise causes fluctuations in the orbit. As a result, fluctuations occur in the direction of the electron spin. Thereby, the coherence time is shortened.

[0024] Also, even when a voltage is applied perpendicularly to the (100) plane in the silicon crystal, no inversion center occurs as site symmetry. This is because along the (100) axis, there may be no other atom at the position where the atoms in the lattice are rotated 180 degrees around this axis. The Dresselhaus spin - orbit interaction and the Rashba spin - orbit interaction occur. Charge noise causes fluctuations in the orbit. As a result, fluctuations occur in the direction of the electron spin. Thereby, the coherence time is shortened.

[0025] In the qubit element 11 according to the first embodiment, a silicon substrate is used as the substrate 12, with the (111) plane oriented perpendicular to the surface of the substrate 12. The gate electrode 16 is composed of a conductor laminated on the surface of the substrate 12. When a voltage is supplied to the gate electrode 16, a potential is induced perpendicular to the (111) plane of the crystal body 12a constituting the fin 13 from the gate electrode 16. A potential perpendicular to the (111) plane is induced simply by controlling the orientation of the crystal body 12a.

[0026] The gate electrode 16 extends linearly on the crystal 12a with a predetermined width W2 and crosses a fin 13 that protrudes from the surface of the crystal 12a and extends linearly with a predetermined width W1. The intersection region 22 between the gate electrode 16 and the fin 13 is partitioned by the width W1 of the fin 13 in the linear direction of the gate electrode 16. Electrons are confined in the linear direction of the gate electrode 16 within the width W1 of the fin 13. In this way, a quantum dot is successfully established. Within the width W1 of the fin 13, a potential is induced from the gate electrode 16 to the fin 13, and the quantum dot 23 is well controlled.

[0027] The intersection angle between the gate electrode 16 and the fin 13 in a top view is set to 90 degrees. The contour of the intersection region 22 in a top view is set by the width W2 of the gate electrode 16 and the width W1 of the fin 13. It is desirable that the width W2 of the gate electrode 16 and the width W1 of the fin 13 be set to the same value, in which case the contour of the intersection region 22 in a top view is set to a square.

[0028] Next, the manufacturing method of the qubit element 11 will be described. As shown in Figure 5, a wafer 24 is prepared. In Figure 5, for convenience, a region corresponding to one quantum dot is cut out. The wafer 24 is made of a silicon crystal. The wafer 24 is cut out, for example, from a single crystal ingot. In the wafer 24, the (111) plane is oriented in the direction perpendicular to the surface of the wafer 24.

[0029] Fins 13 are formed on the surface of the wafer 24. An etching mask 25 is placed on the surface of the wafer 24 during the formation of the fins 13. The crystalline material other than the area protected by the mask 25 is etched to form the fins 13. As shown in Figure 6, once the fins 13 are formed, an oxide film 14 is deposited on the surface of the wafer 24. When the oxide film 14 is planarized, a plane 15 is formed. The oxide film 14 is formed to cover the sides of the fins 13. The upper surface of the fins 13 is positioned flush with the planarized plane 15 of the oxide film 14.

[0030] As shown in Figure 7, an insulating layer and an electrode film are sequentially deposited on the plane 15. The electrode film is made of a conductive material such as a metallic material or polycrystalline silicon. An etching mask is formed on the surface of the electrode film. The electrode film and insulating layer, except for the parts protected by the mask, are sequentially etched to form the insulating layer 17 and gate electrode 16, and the insulating layer 19 and barrier electrode 18, respectively. On the wafer 24, multiple quantum dots may be arranged in the linear direction of the fins 13, or multiple rows of fins 13 may be arranged in the linear direction of the gate electrode 16.

[0031] As described above, the control method for the qubit element 11 shown in Figure 1 involves applying a voltage to the gate electrode 16 formed on the crystal 12a, thereby creating an electric field perpendicular to the (111) plane of the crystal 12a. This control method for the qubit element 11 induces a potential in the quantum dots 23 within the fins 13, thereby controlling the electrons in the quantum dots 23. This reduces the probability of computation errors occurring in the qubit element 11.

[0032] (Second Embodiment) A qubit element according to a second embodiment of the present invention will be described with reference to Figures 8 to 11. Figures 8 and 9 schematically show the configuration of a qubit element 11a according to the second embodiment of the present invention. The qubit element 11a comprises a substrate 12 having at least a silicon crystal 12a on its surface, similar to the qubit element 11 described above. The substrate 12 is a silicon substrate oriented with a (111) plane perpendicular to the surface of the substrate 12. Fins 26 are formed on the surface of the crystal 12a, protruding from the surface of the crystal 12a and extending linearly with a predetermined width W1. Multiple rows of fins 26 may be arranged parallel to each other on a single substrate 12.

[0033] The fin 26 is formed by a laminate 27 that sandwiches a silicon crystal 27a at a heterojunction. In the crystal 27a, the (111) plane is oriented perpendicular to the plane of the substrate 12. The laminate 27 comprises a first silicon-germanium layer 27b having a surface that extends flush with the plane 15, and a second silicon-germanium layer 27c that sandwiches the crystal 27a between the first silicon-germanium layer 27b and the laminate 27. The gate electrode 16 extends linearly on the plane 15 with a predetermined width W2 and crosses the fin 26, as described above (in the first embodiment). The barrier electrode 18 extends linearly on both sides of the gate electrode 16 with a predetermined width W3 and crosses the fin 26, as described above (in the first embodiment).

[0034] In the fin 26, electrons are confined within the crystal 27a according to the heterojunction perpendicular to the plane of the substrate 12. When a voltage is applied from the gate electrode 16 perpendicular to the (111) plane of the crystal 27a and symmetrically in the X-Y plane, as shown in Figure 4 above, an inversion center is secured as site symmetry in the (111) oriented crystal, thus increasing the inversion symmetry. That is, in the qubit element 11a according to the second embodiment, the inversion symmetry is increased, so the spin-orbit interaction acting on the electrons confined in the crystal 27a under the gate electrode 16 becomes extremely small, and the direction of electron spin is stabilized.

[0035] In manufacturing the qubit element 11a, a wafer 28 is prepared as shown in Figure 10. The wafer 28 is made of a silicon crystal. On the wafer 28, the (111) plane is oriented perpendicular to the surface of the wafer 28. On the surface of the wafer 28, a silicon germanium layer 29a, a silicon crystal layer 29b, and a silicon germanium layer 29c are stacked in order. On the surface of the wafer 28, a fin 26 is formed based on the silicon germanium layer 29a, the silicon crystal layer 29b, and the silicon germanium layer 29c. In forming the fin 26, as described above (in the first embodiment), an etching mask 25 is placed on the surface of the silicon germanium layer 29c. Here, since both the wafer 28 and the silicon crystal layer 29b are (111) oriented, the silicon germanium lattice is aligned with the silicon lattice. The silicon germanium layer 29a, the silicon crystal layer 29b, and the silicon germanium layer 29c are successfully grown continuously epitaxially from the silicon (wafer 28).

[0036] As shown in Figure 11, once the fins 26 are formed, an oxide film 14 is deposited on the surface of the wafer 28. When the oxide film 14 is planarized, a plane 15 is formed. The oxide film 14 is formed to cover the sides of the fins 26. The upper surface of the fins 26 is positioned flush with the planarized plane 15 of the oxide film 14. Subsequently, as described above (in the first embodiment), the gate electrode 16 and the barrier electrode 18 are established on the plane 15.

[0037] (Third Embodiment) A qubit element according to the third embodiment of the present invention will be described with reference to Figures 12 to 15. Figures 12 and 13 schematically show the configuration of the qubit element 11b according to the third embodiment of the present invention. The qubit element 11b comprises a substrate 12 having at least a silicon crystal 12a on its surface, similar to the qubit element 11 of the first embodiment described above. The substrate 12 is a silicon substrate oriented with a (111) plane perpendicular to the surface of the substrate 12. Fins 31 are formed on the surface of the crystal 12a, protruding from the surface of the crystal 12a and extending linearly with a predetermined width W1. Multiple rows of fins 31 may be arranged parallel to each other on a single substrate 12.

[0038] The fin 31 is formed by a laminate 32 sandwiching a silicon crystal 32a. In the crystal 32a, the (111) plane is oriented perpendicular to the plane of the substrate 12. The laminate 32 comprises a first insulating layer 32b having a surface that extends flush with the plane 15, and a second insulating layer 32c that sandwiches the crystal 32a between the first insulating layer 32b and the second insulating layer 32c. The first insulating layer 32b and the second insulating layer 32c are formed from an oxide film such as silicon oxide. The gate electrode 16 extends linearly on the plane 15 with a predetermined width W2 and crosses the fin 31, as described above (in the first embodiment). The barrier electrode 18 extends linearly on both sides of the gate electrode 16 with a predetermined width W3 and crosses the fin 31, as described above (in the first embodiment).

[0039] In the fin 31, electrons are confined within the crystal 32a. When a voltage is applied from the gate electrode 16 perpendicular to the (111) plane of the crystal 32a and symmetrically in the X-Y plane, as shown in Figure 4 above, an inversion center is secured as site symmetry in the (111) oriented crystal, thus increasing the inversion symmetry. That is, in the qubit element 11b according to the third embodiment, the inversion symmetry is increased, so the spin-orbit interaction acting on the electrons confined in the crystal 32a under the gate electrode 16 becomes extremely small, and the direction of electron spin is stabilized.

[0040] In manufacturing the qubit element 11a, a wafer 33 is prepared as shown in Figure 14. The wafer 33 is made of a silicon crystal. On the wafer 33, the (111) plane is oriented perpendicular to the surface of the wafer 33. On the surface of the wafer 33, an insulating layer 34a, a silicon crystal layer 34b, and an insulating layer 34c are stacked in order. The insulating layers 34a and 34c are formed, for example, of silicon oxide. On the surface of the wafer 33, a fin 31 is formed based on the insulating layer 34a, the silicon crystal layer 34b, and the insulating layer 34c. In forming the fin 31, as described above (in the first embodiment), an etching mask 25 is placed on the surface of the insulating layer 34c.

[0041] As shown in Figure 15, once the fin 31 is formed, an oxide film 14 is deposited on the surface of the wafer 33. When the oxide film 14 is planarized, a plane 15 is formed. The oxide film 14 is formed to cover the sides of the fin 31. The upper surface of the fin 31 is positioned flush with the planarized plane 15 of the oxide film 14. Subsequently, as described above (in the first embodiment), the gate electrode 16 and barrier electrode 18 are established on the plane 15.

[0042] (Fourth Embodiment) A qubit element according to the fourth embodiment of the present invention will be described with reference to Figures 16 to 18. Figures 16 and 17 schematically show the configuration of a qubit element 41 according to the fourth embodiment of the present invention. The qubit element 41 comprises a substrate 12 having a silicon crystal 12a on at least its surface. The substrate 12 is a silicon substrate with a (111) plane oriented perpendicular to the surface of the substrate 12. The crystal 12a is single-crystal silicon, with a (111) plane oriented perpendicular to the surface, and silicon with nuclear spin 0 (mass number 28) is used as the material. Fins 13 extending linearly with a predetermined width W1 protruding from the surface of the crystal 12a are formed on the surface of the crystal 12a by processing the crystal 12a. Multiple rows of fins 13 may be arranged parallel to each other on a single substrate 12.

[0043] An oxide film 14 is formed on the surface of the crystal 12a. The oxide film 14 is made of, for example, silicon oxide. The oxide film 14 is formed to cover the sides of the fin 13. The surface of the oxide film 14 is planarized. The upper surface of the fin 13 is positioned flush with the planarized plane 15 of the oxide film 14.

[0044] A first gate electrode 42a and a second gate electrode 42b are arranged on the flattened plane 15. The first gate electrode 42a extends linearly on the plane 15 with a predetermined width W2 and crosses the fin 13. The second gate electrode 42b extends linearly on the plane 15 with a predetermined width W2, parallel to the first gate electrode 42a, and crosses the fin 13. Here, the first gate electrode 42a and the second gate electrode 42b extend in a straight line. The edges extending in the linear direction of the first gate electrode 42a and the second gate electrode 42b each form a straight line.

[0045] An insulating layer 43a is formed between the first gate electrode 42a and the plane 15, and between the first gate electrode 42a and the fin 13. An insulating layer 43b is formed between the second gate electrode 42b and the plane 15, and between the second gate electrode 42b and the fin 13. The insulating layers 43a and 43b are made of, for example, silicon oxide. The insulating layers 43a and 43b insulate the first gate electrode 42a and the second gate electrode 42b from the fin 13. As shown in Figure 17, quantum dots 52 are established within the fin 13 located beneath the first gate electrode 42a and the second gate electrode 42b. The first gate electrode 42a and the second gate electrode 42b apply a voltage perpendicular to the (111) plane of the crystal 12a constituting the fin 13. The first gate electrode 42a and the second gate electrode 42b induce a potential in the quantum dots 52 within the crystal 12a constituting the fin 13.

[0046] Two first barrier electrodes 44a and 44b are arranged on the flattened plane 15. The first barrier electrodes 44a and 44b extend linearly on both sides of the combined first gate electrode 42a and second gate electrode 42b with a predetermined width W3, crossing the fin 13. Here, each individual first barrier electrode 44a and 44b extends linearly parallel to the first gate electrode 42a and the second gate electrode 42b. In each individual first barrier electrode 44a and 44b, the edges extending in the linear direction form a straight line.

[0047] Insulating layers 45a and 45b are formed between the first barrier electrodes 44a and 44b and the plane 15, and between the first barrier electrodes 44a and 44b and the fin 13. The insulating layers 45a and 45b are made of, for example, silicon oxide. The insulating layers 45a and 45b insulate the first barrier electrodes 44a and 44b from the fin 13. As shown in Figure 17 above, the first barrier electrodes 44a and 44b apply a voltage perpendicular to the (111) plane of the crystal 12a constituting the fin 13. The first barrier electrodes 44a and 44b induce a potential within the fin 13, forming a barrier 46 for the electrons of the quantum dot 52.

[0048] A second barrier electrode 47 is positioned on the flattened plane 15. The second barrier electrode 47 extends linearly between the first gate electrode 42a and the second gate electrode 42b with a width W4 determined to be parallel to them, and crosses the fin 13. Here, the second barrier electrode 47 extends linearly parallel to the first gate electrode 42a and the second gate electrode 42b. In the second barrier electrode 47, the edges extending in the linear direction each form a straight line.

[0049] An insulating layer 48 is formed between the second barrier electrode 47 and the plane 15, and between the second barrier electrode 47 and the fin 13. The insulating layer 48 is made of, for example, silicon oxide. The insulating layer 48 insulates the second barrier electrode 47 from the fin 13. As shown in Figure 17 above, the second barrier electrode 47 applies a voltage perpendicular to the (111) plane of the crystal 12a constituting the fin 13. The second barrier electrode 47 induces a potential within the fin 13, forming a barrier 49 to control the interaction between the two electrons of the two quantum dots 52.

[0050] As shown in Figure 18, the intersection angles between the first gate electrode 42a, the second gate electrode 42b, the first barrier electrodes 44a, 44b, and the second barrier electrode 47 and the fin 13 in a top view are set to 90 degrees. It is desirable that the widths W2 of the first gate electrode 42a and the second gate electrode 42b, the widths W3 of the first barrier electrodes 44a and 44b, and the width W4 of the second barrier electrode 47 and the width W1 of the fin 13 are set to the same value. In this case, the contour of the intersection area 51 in a top view is set to a square.

[0051] Next, the operation of the qubit element 41 will be explained. When a quantum dot is formed, electrons are confined within the fins 13 of the crystal 12a. When a voltage is applied perpendicular to the (111) plane of the crystal 12a constituting the fins 13 from the first gate electrode 42a and the second gate electrode 42b, and in an X-Y symmetrical manner within the X-Y plane, as shown in Figure 4 above, an inversion center is secured as site symmetry in the (111) oriented crystal, thus increasing the inversion symmetry. In other words, since the inversion symmetry is increased in the qubit element 41 according to the fourth embodiment, the spin-orbit interaction acting on the electrons becomes extremely small, and the direction of the electron spin is stabilized.

[0052] When voltage is supplied to the first barrier electrodes 44a, 44b and the second barrier electrode 47, a potential is induced perpendicular to the (111) plane of the crystal 12a constituting the fin 13 from the first barrier electrodes 44a, 44b and the second barrier electrode 47. As shown in Figure 17 above, the electric field forms barriers 46, 49 for the electrons. The movement of electrons in the linear direction of the fin 13 is restricted. Electrons are confined within the fin 13 under the first gate electrode 42a and the second gate electrode 42b. Under the first gate electrode 42a and the second gate electrode 42b, potentials are induced in the fin 13 from the first gate electrode 42a and the second gate electrode 42b, respectively, and the quantum dots 52 are well controlled. When a voltage is applied perpendicular to the (111) plane of the crystal 12a constituting the fin 13 from the first barrier electrodes 44a, 44b and the second barrier electrode 47, while maintaining inversion symmetry around each of the two quantum dots 52, as shown in Figure 4 above, an inversion center is secured as site symmetry in the (111) oriented crystal, and the inversion symmetry is increased. That is, in the qubit element 41 according to the fourth embodiment, the inversion symmetry is increased, so the spin-orbit interaction acting on the electrons confined in the fins 13 under the first gate electrode 42a and the second gate electrode 42b becomes extremely small, and the direction of electron spin is stabilized.

[0053] When a pulse signal is supplied to the second barrier electrode 47, the interaction between the two quantum dots 52 is controlled. This is achieved by manipulating spin-exchange coupling. For example, operations between two qubits, such as a swap gate, can be realized.

[0054] In the control method for the qubit element 41 according to the fourth embodiment, a voltage is applied to the first gate electrode 42a and the second gate electrode 42b formed on the crystal 12a, and this voltage forms an electric field perpendicular to the (111) plane of the crystal 12a. In this control method for the qubit element 41, potentials are induced in the first quantum dot 52a and the second quantum dot 52b within the fin 13 by the first gate electrode 42a and the second gate electrode 42b, respectively, and the electrons in the first quantum dot 52a and the electrons in the second quantum dot 52b and their interactions are controlled. This reduces the probability of computation errors occurring in the qubit element 41.

[0055] (Fifth Embodiment) A qubit element according to the fifth embodiment of the present invention will be described with reference to Figures 19 and 20. Figures 19 and 20 schematically show the configuration of a qubit element 41a according to the fifth embodiment of the present invention. The qubit element 41a comprises a substrate 12 having at least a silicon crystal 12a on its surface, similar to the qubit element 41 of the fourth embodiment described above. The substrate 12 is a silicon substrate oriented with a (111) plane perpendicular to the surface of the substrate 12. Fins 26 are formed on the surface of the crystal 12a, protruding from the surface of the crystal 12a and extending linearly with a predetermined width W1. Multiple rows of fins 26 may be arranged parallel to each other on a single substrate 12.

[0056] The fin 26 is formed by a laminate 27 in which a silicon crystal 27a is sandwiched at a heterojunction. In the crystal 27a, the (111) plane is oriented perpendicular to the plane of the substrate 12. The laminate 27 comprises a first silicon-germanium layer 27b having a surface that extends flush with the plane 15, and a second silicon-germanium layer 27c that sandwiches the crystal 27a between the first silicon-germanium layer 27b and the laminate 27. The first gate electrode 42a and the second gate electrode 42b extend linearly across the fin 26 with a predetermined width W2 on the plane 15, as described above (in the fourth embodiment). The first barrier electrodes 44a and 44b have a predetermined width W3, and the second barrier electrode 47 has a predetermined width W4. As described above (in the fourth embodiment), they extend linearly in parallel to the first gate electrode 42a and the second gate electrode 42b, on both sides of the first gate electrode 42a and the second gate electrode 42b, and cross the fin 26.

[0057] In the fin 26, electrons are confined within the crystal 27a in accordance with the heterojunction in the direction perpendicular to the plane of the substrate 12. When a voltage is applied perpendicular to the (111) plane of the crystal 27a and symmetrically in the X-Y plane from the first gate electrode 42a and the second gate electrode 42b, as shown in Figure 4 above, an inversion center is secured as site symmetry in the (111) oriented crystal, thus increasing the inversion symmetry. That is, since the inversion symmetry is increased in the qubit element 41a according to the fifth embodiment, the spin-orbit interaction acting on the electrons confined in the crystal 27a under the first gate electrode 42a and the second gate electrode 42b becomes extremely small, and the direction of electron spin is stabilized.

[0058] (Sixth Embodiment) A qubit element according to the sixth embodiment of the present invention will be described with reference to Figures 21 and 22. Figures 21 and 22 schematically show the configuration of the qubit element 41b according to the sixth embodiment of the present invention. The qubit element 41b, like the qubit element 41 of the fourth embodiment described above, comprises a substrate 12 having at least a silicon crystal 12a on its surface. The substrate 12 is a silicon substrate oriented with a (111) plane perpendicular to the surface of the substrate 12. Fins 31 are formed on the surface of the crystal 12a, protruding from the surface of the crystal 12a and extending linearly with a predetermined width W1. Multiple rows of fins 31 may be arranged parallel to each other on a single substrate 12.

[0059] The fin 31 is formed by a laminate 32 sandwiching a silicon crystal 32a. In the crystal 32a, the (111) plane is oriented perpendicular to the plane of the substrate 12. The laminate 32 comprises a first insulating layer 32b having a surface that extends flush with the plane 15, and a second insulating layer 32c that sandwiches the crystal 32a between the first insulating layer 32b and the laminate 32c. The first insulating layer 32b and the second insulating layer 32c are formed from an oxide film such as silicon oxide. The first gate electrode 42a and the second gate electrode 42b extend linearly across the fin 31 with a predetermined width W2 on the plane 15, as described above (in the fourth embodiment). The first barrier electrodes 44a and 44b have a predetermined width W3, and the second barrier electrode 47 has a predetermined width W4. As described above (in the fourth embodiment), they extend linearly in parallel to the first gate electrode 42a and the second gate electrode 42b, on both sides of the first gate electrode 42a and the second gate electrode 42b, and cross the fin 31.

[0060] In the fin 31, electrons are confined within the crystal 32a. When a voltage is applied perpendicular to the (111) plane of the crystal 32a and symmetrically in the X-Y plane from the first gate electrode 42a and the second gate electrode 42b, as shown in Figure 4 above, an inversion center is secured as site symmetry in the (111) oriented crystal, thus increasing the inversion symmetry. That is, in the qubit element 41b according to the sixth embodiment, the inversion symmetry is increased, so the spin-orbit interaction acting on the electrons confined in the crystal 32a under the first gate electrode 42a and the second gate electrode 42b becomes extremely small, and the direction of electron spin is stabilized.

[0061] (Seventh Embodiment) A qubit element according to the seventh embodiment of the present invention will be described with reference to Figures 23 to 30. Figure 23 schematically shows the configuration of a qubit element 61 according to the seventh embodiment of the present invention. The qubit element 61 comprises a substrate 12 having a silicon crystal 12a on at least its surface. The substrate 12 is a silicon substrate with a (111) plane oriented perpendicular to the surface of the substrate 12. The crystal 12a is single-crystal silicon, with a (111) plane oriented perpendicular to the surface, and silicon with nuclear spin 0 (mass number 28) is used as the material. Fins 13 are formed on the surface of the crystal 12a by processing the crystal 12a, extending linearly with a predetermined width W1 protruding from the surface of the crystal 12a. That is, the fins 13 are made of crystal 12a. Multiple rows of fins 13 may be arranged parallel to each other on a single substrate 12.

[0062] A gate electrode 62 is positioned on the crystal body 12a. The gate electrode 62 extends linearly on the surface of the crystal body 12a with a predetermined width W2 and crosses the fin 13. In this case, when viewed from above, the gate electrode 62 intersects the fin 13 at a 90-degree intersection angle. The gate electrode 62 is continuously stacked on the side, top, and sides of the fin 13. The gate electrode 62 is shaped to straddle the protruding fin 13.

[0063] An insulating layer 63 is formed between the gate electrode 62 and the crystal body 12a. The insulating layer 63 is made of, for example, silicon oxide. The insulating layer 63 insulates the gate electrode 62 from the fin 13. A quantum dot is established within the fin 13 located beneath the gate electrode 62. The gate electrode 62 induces a three-dimensionally uniform potential within the fin 13. Within this three-dimensionally uniform potential, electrons are confined to a position away from the interface between the fin 13 and the insulating layer 63, and are less affected by the interface. As a result, no interface-induced spin-orbit interaction acts on the electrons, and therefore the direction of electron spin is further stabilized in the qubit element 61 according to the seventh embodiment.

[0064] Two barrier electrodes 64 are arranged on the crystal body 12a. The barrier electrodes 64 extend linearly in parallel with the gate electrode 62 on both sides of the gate electrode 62 with a predetermined width W3, and cross the fin 13. Here, each individual barrier electrode 64 extends linearly parallel to the gate electrode 62. The individual barrier electrodes 64 are continuously stacked on the side, top, and sides of the fin 13. The barrier electrodes 64 are shaped to straddle the protruding fin 13.

[0065] An insulating layer 65 is formed between the barrier electrode 64 and the crystal body 12a. The insulating layer 65 is made of, for example, silicon oxide. The insulating layer 65 insulates the barrier electrode 64 from the fin 13. The barrier electrode 64 induces a three-dimensionally uniform potential within the fin 13. The barrier electrode 64 induces a potential within the fin 13, forming a barrier against the electrons of the quantum dots.

[0066] (First Modification of the Seventh Embodiment) Figure 24 shows the first modification of the qubit element 61. As shown in Figure 24, in the qubit element 61a, instead of the fin 13 described above (second embodiment), a fin 26 formed by a laminate 27 sandwiching a silicon crystal 27a in a heterojunction is used. In the crystal 27a, the (111) plane is oriented perpendicular to the plane of the substrate 12.

[0067] (Second Modification of the Seventh Embodiment) Figure 25 shows a second modification of the qubit element 61. As shown in Figure 25, in the qubit element 61b, similar to the third embodiment described above, a fin 31 is used instead of the fin 13, formed by a laminate 32 in which a silicon crystal 32a is sandwiched between a first insulating layer 32b and a second insulating layer 32c. In the crystal 32a, the (111) plane is oriented in the direction perpendicular to the surface of the substrate 12.

[0068] (Third Modification of the Seventh Embodiment) Figure 26 shows a third modification of the qubit element 61. As shown in Figure 26, in the qubit element 61c, similar to the fourth embodiment described above, a first gate electrode 42a and a second gate electrode 42b are used instead of the gate electrode 62, and a first barrier electrode 44a, 44b and a second barrier electrode 47 are used instead of the two barrier electrodes 64.

[0069] (Fourth Modification of the Seventh Embodiment) Figure 27 shows a fourth modification of the qubit element 61. As shown in Figure 27, in the qubit element 61d, similar to the fifth embodiment described above, a fin 26 formed by a laminate 27 sandwiching a silicon crystal 27a in a heterojunction is used instead of the fin 13. Furthermore, in the qubit element 61d, a first gate electrode 42a and a second gate electrode 42b are used instead of the gate electrode 62, and a first barrier electrode 44a, 44b and a second barrier electrode 47 are used instead of the two barrier electrodes 64. In the crystal 27a, the (111) plane is oriented in the direction perpendicular to the surface of the substrate 12.

[0070] (Fifth Modification of the Seventh Embodiment) Figure 28 shows a fifth modification of the qubit element 61. As shown in Figure 28, in the qubit element 61e, similar to the sixth embodiment described above, instead of the fin 13, a fin 31 is used which is formed by a laminate 32 in which a silicon crystal 32a is sandwiched between a first insulating layer 32b and a second insulating layer 32c. Furthermore, in the qubit element 61e, instead of the gate electrode 62, a first gate electrode 42a and a second gate electrode 42b are used, and instead of the two barrier electrodes 64, first barrier electrodes 44a, 44b and a second barrier electrode 47 are used. In the crystal 32a, the (111) plane is oriented in the direction perpendicular to the surface of the substrate 12.

[0071] (Sixth Modification of the Seventh Embodiment) Figure 29 shows a sixth modification of the qubit element 61. As shown in Figure 29, in the qubit element 61f, the height H1 of the fin 13 is set to the same value as the width W1 of the fin 13.

[0072] (Seventh Modification of the Seventh Embodiment) Figure 30 shows a seventh modification of the qubit element 61. As shown in Figure 30, in the qubit element 61g, the height H2 of the fin 13 is set to the same value as the width W1 of the fin 13. Furthermore, in the qubit element 61g, as described above (in the fourth embodiment), a first gate electrode 42a and a second gate electrode 42b are used instead of the gate electrode 62, and a first barrier electrode 44a, 44b and a second barrier electrode 47 are used instead of the two barrier electrodes 64.

[0073] (Eighth Embodiment) A qubit element according to the eighth embodiment of the present invention will be described with reference to Figures 31 to 35. Figure 31 schematically shows the configuration of a qubit element 71 according to the eighth embodiment of the present invention. The qubit element 71 comprises a substrate 12 having a silicon crystal 12a on at least its surface. The substrate 12 is a silicon substrate with a (111) plane oriented perpendicular to the surface of the substrate 12. The crystal 12a is single-crystal silicon, with a (111) plane oriented perpendicular to the surface, and silicon with nuclear spin 0 (mass number 28) is used as the material. Fins 72 are formed on the surface of the crystal 12a, protruding from the surface of the crystal 12a and extending linearly with a predetermined width W1. Multiple rows of fins 72 may be arranged parallel to each other on a single substrate 12.

[0074] The fin 72 is formed from a silicon crystal 73a and a composite 73 that surrounds the crystal 73a by a heterojunction. In the crystal 73a, the (111) plane is oriented perpendicular to the surface of the substrate 12. The composite 73 comprises a first silicon germanium layer 73b located on the upper surface of the crystal 73a, a second silicon germanium layer 73c sandwiching the crystal 73a between the first silicon germanium layer 73b and the composite 73c, and two silicon germanium walls 73d located on the sides of the first silicon germanium layer 73b, the crystal 73a, and the second silicon germanium layer 73c. ​​It is desirable that the height H and width W1 of the crystal 73a be set to the same value, in which case the cross section perpendicular to the extending direction of the crystal 73a is set to a square. The surface of the crystal 12a on which the fin 72 is not formed is covered with a silicon germanium film 74. The silicon germanium film 74 is continuous with the composite 73 (first silicon germanium layer 73b, second silicon germanium layer 73c, and silicon germanium wall 73d).

[0075] A gate electrode 62 is positioned on the silicon germanium film 74, the first silicon germanium layer 73b, and the silicon germanium wall 73d. The gate electrode 62 extends linearly with a predetermined width W2 and crosses the fin 72. In a top view, the gate electrode 62 intersects the fin 72 at a 90-degree angle. The gate electrode 62 is continuously stacked on the side, top, and sides of the fin 72. The gate electrode 62 is shaped to straddle the protruding fin 72.

[0076] Two barrier electrodes 64 are positioned on the silicon germanium film 74, the first silicon germanium layer 73b, and the silicon germanium wall 73d. The barrier electrodes 64 extend linearly in parallel with the gate electrode 62, on both sides of the gate electrode 62, with a predetermined width W3, and cross the fin 72. Here, each individual barrier electrode 64 extends linearly parallel to the gate electrode 62. The individual barrier electrodes 64 are continuously stacked on the side, top, and sides of the fin 72. The barrier electrodes 64 are shaped to straddle the protruding fin 72.

[0077] In the fin 72, electrons are confined within the crystal 73a in accordance with the three-dimensional heterojunction. The gate electrode 62 induces a three-dimensionally uniform potential within the crystal 73a. Within this three-dimensionally uniform potential, electrons are confined at a position away from the interface between the crystal 73a and the composite 73 (first silicon-germanium layer 73b, second silicon-germanium layer 73c, and silicon-germanium wall 73d), and are less affected by the interface. As a result, no interface-induced spin-orbit interaction acts on the electrons, and therefore the direction of electron spin is further stabilized in the qubit element 71 according to the eighth embodiment.

[0078] An insulating layer 63 is formed between the gate electrode 62, the silicon germanium film 74, the first silicon germanium layer 73b, and the silicon germanium wall 73d. The insulating layer 63 is made of, for example, silicon oxide. The insulating layer 63 insulates the gate electrode 62 from the fin 72. Quantum dots are established within the crystal 73a located beneath the gate electrode 62. The gate electrode 62 induces a three-dimensionally uniform potential within the crystal 73a.

[0079] An insulating layer 65 is formed between the barrier electrode 64, the silicon germanium film 74, the first silicon germanium layer 73b, and the silicon germanium wall 73d. The insulating layer 65 is made of, for example, silicon oxide. The insulating layer 65 insulates the barrier electrode 64 from the fin 72. The barrier electrode 64 induces a three-dimensionally uniform potential within the crystal 73a. The barrier electrode 64 induces a potential within the crystal 73a, forming a barrier against the electrons of the quantum dots.

[0080] In manufacturing the qubit element 71, a wafer 76 is prepared as shown in Figure 32. The wafer 76 is made of silicon crystals. On the wafer 76, the (111) plane is oriented perpendicular to the surface of the wafer 76. On the surface of the wafer 76, a silicon germanium layer 77a and a silicon crystal layer 77b are stacked in order. As shown in Figure 33, a fin 78 is formed on the surface of the wafer 76 based on the silicon germanium layer 77a and the silicon crystal layer 77b. The fin 78 is partitioned into a crystal 73a and a second silicon germanium layer 73c. ​​In forming the fin 78, as in the first embodiment described above, an etching mask 25 is placed on the surface of the silicon crystal layer 77b.

[0081] As shown in Figure 34, once the crystal 73a and the second silicon-germanium layer 73c are formed, a silicon-germanium layer 79 is deposited on the surface of the wafer 76. The silicon-germanium layer 79 covers the crystal 73a and the second silicon-germanium layer 73c. ​​The silicon-germanium layer 79 forms the first silicon-germanium layer 73b and the silicon-germanium wall 73d. Subsequently, the gate electrode 62 and the barrier electrode 64 are established on the wafer 76.

[0082] (Modification of the 8th Embodiment) Figure 35 shows a modified version of the qubit element 71. As shown in Figure 35, in the qubit element 71a, similar to the above (third modification of the 7th embodiment), a first gate electrode 42a and a second gate electrode 42b are used instead of the gate electrode 62, and a first barrier electrode 44a, 44b and a second barrier electrode 47 are used instead of the two barrier electrodes 64.

[0083] (Ninth Embodiment) A qubit element according to the ninth embodiment of the present invention will be described with reference to Figures 36 to 41. Figure 36 schematically shows the configuration of a qubit element 81 according to the ninth embodiment of the present invention. The qubit element 81 comprises a substrate 82 having a silicon crystal 82a on its surface. The substrate 82 is a silicon substrate with a (111) plane oriented perpendicular to the surface of the substrate 82. The crystal 82a is single-crystal silicon, with a (111) plane oriented perpendicular to the surface, and silicon with nuclear spin 0 (mass number 28) is used as the material. Dopants 83 are arranged on the crystal 82a according to rules determined in accordance with the (111) surface structure of the substrate 82. For example, phosphorus (P) atoms are used for the dopants 83. The crystal 82a is formed on the substrate 82 by epitaxial growth with a (111) plane oriented perpendicular to the surface, and the dopants 83 are embedded in this crystal 82a. On the surface 85 of the crystal 82a, metal 84 is arranged according to rules determined to match its surface structure.

[0084] Two first gate electrodes 86 and a first barrier electrode 87 are positioned on the surface 85 of the crystal body 82a. The first gate electrodes 86 extend linearly on the surface 85 with a predetermined width W5. As shown in Figure 37, the dopant 83 and the first gate electrodes 86 are aligned with a vertical plane 89 perpendicular to the surface 85. Here, the first gate electrodes 86 extend in a straight line. In the first gate electrodes 86, the edges extending in the linear direction each form a straight line. The first gate electrodes 86 only need to be set parallel to each other.

[0085] Similarly, the first barrier electrode 87 extends linearly on the surface 85 with a predetermined width W6. The first barrier electrode 87 is positioned midway between the two first gate electrodes 86. Here, the first barrier electrode 87 extends in a straight line. In the first barrier electrode 87, each edge extending in the linear direction forms a straight line. The first barrier electrode 87 only needs to be set parallel to the first gate electrodes 86.

[0086] An insulating layer 91 is formed between the first gate electrode 86 and the surface 85, and between the first barrier electrode 87 and the surface 85. The insulating layer 91 is made of, for example, silicon oxide. The insulating layer 91 insulates the first gate electrode 86 and the first barrier electrode 87 from the crystal 82a. As shown in Figure 37, electrons are confined in the crystal 82a beneath the first gate electrode 86 based on the potential of the dopant 83, and a quantum dot 92 is established. The first gate electrode 86 and the first barrier electrode 87 induce an electric field perpendicular to the (111) plane of the crystal 82a.

[0087] Next, the operation of the qubit element 81 will be explained. In establishing the quantum dot 92, electrons are confined to the crystal 82a based on the potential of the dopant 83. When a voltage is applied perpendicular to the (111) plane of the crystal 82a from the first gate electrode 86, as shown in Figure 4 above, an inversion center is secured as site symmetry in the (111) oriented crystal, thus increasing the inversion symmetry. That is, in the qubit element 81 according to the ninth embodiment, the inversion symmetry is increased, so the spin-orbit interaction acting on the electrons becomes extremely small, and the direction of the electron spin is stabilized.

[0088] In the qubit element 81 according to the ninth embodiment, a silicon substrate is used for the substrate 82, with the (111) plane oriented perpendicular to the surface of the substrate 82. The first gate electrode 86 is composed of a conductor stacked on the surface 85. When a voltage is supplied to the first gate electrode 86, a potential is induced from the first gate electrode 86 perpendicular to the (111) plane of the crystal 82a. A potential perpendicular to the (111) plane is induced simply by controlling the orientation of the crystal 82a.

[0089] When a pulse signal is supplied to the first barrier electrode 87, the interaction between the two quantum dots 92 is controlled. This is achieved by manipulating spin-exchange coupling. For example, operations between two qubits, such as a swap gate, can be realized.

[0090] Next, the manufacturing method of the qubit element 81 will be described. As shown in Figure 38, a wafer 94 is prepared. For convenience, Figure 38 shows regions corresponding to the rhombus-shaped surface structure unit shown in Figure 39. The wafer 94 is made of a silicon crystal. The wafer 94 is cut, for example, from a single crystal ingot. In the wafer 94, the (111) plane is oriented perpendicular to the surface of the wafer 94.

[0091] As shown in Figure 39, a 7x7 structure is established on the surface of a (111) oriented silicon substrate. In the 7x7 structure, adsorbed atoms are regularly arranged on surface-protruding adatoms according to the (111) orientation. The reactivity of corner adatoms located at the corners of the triangle is higher than that of center adatoms located in the middle of each side, and atoms are more selectively adsorbed onto corner adatoms. In addition, in the 7x7 lattice structure, the reactivity of corner adatoms is higher in the faulted half.

[0092] Wafer 94 is a phosphorus (P) gas (P ２ Exposed to gas. ２ When a (111)-oriented wafer 94 is exposed to a gas, phosphorus atoms 96 are adsorbed onto the surface of the wafer 94 in response to the action of corner adatoms 95, as shown in Figure 40. Corner adatoms 95 are replaced by phosphorus atoms 96. The phosphorus atoms 96 are arranged regularly.

[0093] As shown in Figure 41, silicon crystals 97 are epitaxially grown on the surface of a wafer 94. Phosphorus atoms 96 are embedded within the crystals 97. A quantum dot 92 is formed for each phosphorus atom 96. Subsequently, a material selectively deposited on the folded half is deposited on the surface of the crystals 97. These materials are selected from thallium, palladium, lead, tin, or silver atoms.

[0094] After depositing electrode material on the crystal 97 and the deposited material, an etching mask is placed on the surface of the electrode material. Since the selectively deposited material reveals a 7x7 structure, the etching mask is positioned based on this pattern. The electrode material other than the area protected by the mask is etched away to form the first gate electrode 86 and the first barrier electrode 87, and the shapes of the first gate electrode 86 and the first barrier electrode 87 are aligned with the crystal 97. Because the shapes of the first gate electrode 86 and the first barrier electrode 87 are aligned based on the material selectively deposited on the folded half, the first gate electrode 86 and the first barrier electrode 87 are precisely positioned relative to the phosphorus atoms 96 embedded in the crystal 97.

[0095] Although the present invention has been specifically described above based on embodiments, it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence.

[0096] (Tenth Embodiment) The qubit elements according to each of the embodiments described above may be configured to further enhance the stability of electron spin by confining electrons to an energy level corresponding to the L point rather than the X0 point in the band structure of the crystal. From the tenth embodiment onward, a qubit element in which the stability of electron spin is enhanced by confining electrons to an energy level corresponding to the L point in the band structure of the crystal will be described.

[0097] Here, Figure 42 is a conceptual diagram illustrating the band structure of silicon, schematically representing the energy distribution of the conduction band and valence band (the vertical axis shows energy (eV), and the horizontal axis shows the wave vector). The band structure of a silicon crystal has multiple conduction band minimums, represented by the X0 point on the Γ-Δ-X axis ((100) axis) and the L point on the Γ-Λ-L axis ((111) axis). The energy minimum of the conduction band is located at the X0 point, which extends from the Γ point in the (100) axis direction, and its indirect transition energy from the Γ point is approximately 1.1 eV. The L point is located in the (111) axis direction from the Γ point, and its indirect transition energy from the Γ point is approximately 2.1 eV, with its energy level being approximately 1 eV higher than that of the X0 point. The energy difference between point X0 and point L depends on the mechanical stress applied to the silicon crystal. When tensile stress is applied, the energy difference decreases, and when the tensile stress increases further, the relationship between the energies reverses, with point L becoming the energy minimum of the conduction band.

[0098] Point L is located at the position of highest crystal symmetry, and even when external voltage or mechanical stress is applied, the symmetry of the electron wave function is easily preserved, and spin-orbit interaction hardly acts. As shown in 43A of Figure 43, point L is located at the edge of the Brillouin zone B and has four equivalent valleys. On the other hand, as shown in 43B of Figure 43, point X0 has six equivalent valleys in the Brillouin zone B. For this reason, the energy degeneracy structure of point L is simpler than that of point X0.

[0099] Therefore, by confining electrons to the energy level corresponding to the L point, the electron spin can be stabilized. In particular, even if the degeneracy of multiple equivalent valleys is lifted at the L point, the energy level of the qubit element as a two-level system is not affected, so the spin coherence time of the qubit element can be maintained for a long time. In addition, since electrons can be controlled away from interfaces and electric field concentration areas, variations in energy levels and spin resonance conditions among multiple qubit elements can be reduced, improving the uniformity of operation. Consequently, each qubit element can operate stably at a more uniform energy level, improving spin stability and the reproducibility of quantum information.

[0100] Figure 44 is a conceptual diagram schematically showing the configuration of the qubit element 101 according to the tenth embodiment. Figure 45 is a conceptual diagram showing the top view configuration of the qubit element 101 shown in Figure 44. The qubit element 101 according to the tenth embodiment has a configuration in which a source region 102, a source electrode 127, a drain region 103, and a drain electrode 128 are provided on the qubit element 41 according to the fourth embodiment shown in Figure 16. Note that in Figures 44 and 45, the same reference numerals are used for components identical to those in Figure 16. Here, in order to avoid duplication of explanation, only an overview will be given for components identical to those in Figure 16, and the explanation will focus on the source region 102, source electrode 127, drain region 103, and drain electrode 128.

[0101] The qubit element 101 comprises a substrate 12 having a silicon crystal 12a. The substrate 12 is a silicon substrate with a (111) plane oriented perpendicular to the surface of the substrate 12. The crystal 12a is single-crystal silicon, with a (111) plane oriented perpendicular to the surface, and silicon with nuclear spin 0 (mass number 28) is used as the material. Fins 13 are formed on the surface of the crystal 12a by processing the crystal 12a, extending linearly with a predetermined width W1 protruding from the surface of the crystal 12a. Multiple rows of fins 13 may be arranged parallel to each other on a single substrate 12.

[0102] An oxide film 14, for example, made of silicon oxide, is formed on the surface of the crystal 12a. The oxide film 14 is formed to cover the side surfaces of the fin 13, the side surfaces of the source region 102, and the side surfaces of the drain region 103. The upper surface of the fin 13 is positioned flush with the planarized plane 15 of the oxide film 14. A first gate electrode 42a, a second gate electrode 42b, two first barrier electrodes 44a, 44b, a second barrier electrode 47, and furthermore, a source electrode 127 and a drain electrode 128 are arranged on the planarized plane 15. The first gate electrode 42a, the second gate electrode 42b, the two first barrier electrodes 44a, 44b, and the second barrier electrode 47 are provided on the plane 15 via corresponding insulating layers 43a, 43b, 45a, 45b, and 48, respectively. The first gate electrode 42a, the second gate electrode 42b, the two first barrier electrodes 44a and 44b, and the second barrier electrode 47, which are arranged in parallel on the plane 15, extend linearly with widths W2, W3, and W4, respectively, and cross the fin 13. In addition, the source electrode 127 and the drain electrode 128 are connected by making direct contact with the source region 102 and the drain region 103, respectively, and extend linearly with width W5, crossing the source region 102 and the drain region 103.

[0103] In Figures 44 and 45, the first barrier electrode 44a, the first gate electrode 42a, the second barrier electrode 47, the second gate electrode 42b, and the first barrier electrode 44b are arranged in that order from the source region 102 towards the drain region 103, which is the reverse of the arrangement in Figure 16.

[0104] The crossover region 51 shown in Figure 45 represents the region where the first gate electrode 42a and the second gate electrode 42b intersect with the fin 13. A first quantum dot 52a and a second quantum dot 52b are established within the fin 13 in the crossover region 51 located below the first gate electrode 42a and the second gate electrode 42b. When there is no need to distinguish between the first quantum dot 52a and the second quantum dot 52b, they are simply referred to as quantum dot 52. The first gate electrode 42a and the second gate electrode 42b apply a voltage perpendicular to the (111) plane of the crystal 12a constituting the fin 13. The first gate electrode 42a and the second gate electrode 42b induce a potential to confine electrons to the energy level corresponding to the L point in the band structure of the crystal 12a constituting the fin 13.

[0105] The first barrier electrodes 44a and 44b apply a voltage perpendicular to the (111) plane of the crystal 12a constituting the fin 13. The first barrier electrodes 44a and 44b induce a potential within the fin 13, forming a barrier 46 for electrons in the quantum dots 52. The second barrier electrode 47 applies a voltage perpendicular to the (111) plane of the crystal 12a constituting the fin 13. The second barrier electrode 47 induces a potential within the fin 13, forming a barrier 49 to control the interaction between two electrons in the two quantum dots 52.

[0106] In addition to this configuration, the qubit element 101 has a source electrode 127 and a drain electrode 128 connected via a source region 102, a fin 13, and a drain region 103. The source electrode 127 injects electrons into the crystal 12a, and the drain electrode 128 expels electrons from the crystal 12a.

[0107] A cubic or rectangular source region 102 is formed on the surface of the crystal 12a, connected to one end of the fin 13 in the longitudinal direction. The source region 102 is a diffusion layer formed by impurities being injected into the crystal 12a, and the source electrode 127 is formed by a conductive material such as Al, TiN, or Cu making direct contact with the source region 102. The size, material, and doping conditions of the source region 102 are selected so that a sufficient donor (electrons) is present inside. The surface surrounding the source region 102 is covered by an oxide film 14 that covers the side surface of the fin 13. The surface of the source region 102 and the surface of the oxide film 14 surrounding the source region 102 are flattened, and the upper surface of the fin 13 is flush with the surface.

[0108] Furthermore, a cubic or rectangular drain region 103 is formed on the surface of the crystal 12a, connected to the other end of the fin 13 in the longitudinal direction. The drain region 103 is a diffusion layer formed by impurities being injected into the crystal 12a, and the drain electrode 128 is formed by a conductive material such as Al, TiN, or Cu making direct contact with the drain region 103. The surface surrounding the drain region 103 is covered by an oxide film 14 that covers the side surface of the fin 13. The surface of the drain region 103 and the surface of the oxide film 14 surrounding the drain region 103 are flattened, and the upper surface of the fin 13 is flush with the surface.

[0109] As a result, electrons injected from the source region 102 into the crystal 12a by the source electrode 127 are sequentially guided to the first quantum dot 52a and the second quantum dot 52b formed below the first gate electrode 42a and the second gate electrode 42b via the fin 13, and are stably confined in the energy level corresponding to the L point in the band structure of the crystal 12a. Thereafter, the electron spin state is controlled by the voltage applied to the first gate electrode 42a and the second gate electrode 42b, and a quantum operation is performed by controlling the spin interaction between the two electrons in the two quantum dots 52 by the voltage applied to the second barrier electrode 47. Further, electrons are detected by moving the electrons toward the drain region 103 side. By these operations, the quantum bit element 101 performs information processing operations including operations and readouts of quantum states. Although an example of two quantum dots has been described here, the number may be three quantum dots or more, of course.

[0110] FIG. 46 is a conceptual diagram schematically showing the relationship between the conduction band energy level of the first quantum dot 52a and the Fermi level of the source region 102 in the quantum bit element 101 according to the tenth embodiment, and the relationship between the conduction band energy levels of the second quantum dot 52b and the first quantum dot 52a. 46A shows the state at the time of injecting electrons into all levels below the L point energy level of the first quantum dot 52a, and 46B shows the state in which only the electrons at the L point energy level of the first quantum dot 52a move to the L point energy level of the second quantum dot 52b and the electrons are confined in the L point energy level of the band structure of the crystal 12a. As shown in 46A, an energy barrier (barrier region B １ ) for controlling the injection of electrons is formed between the source region 102 and the first quantum dot 52a disposed adjacent to the source region 102 side. The source region 102 is formed to have a sufficient donor concentration, and the Fermi level (μ Ｓ ) of the source region 102 is set at a high position.

[0111] By the first barrier electrode 44a disposed on the source region 102 side, the barrier region B on the source region 102 side １The potential of the barrier region B can be controlled by applying a voltage to the first barrier electrode 44a. １ The potential is reduced, and electrons are injected into the first quantum dot 52a located on the source region 102 side. The quantum dot 52 has dimensions on the order of nanometers (a few nanometers or less), and the energy level within the first quantum dot 52a is quantized, so electrons are filled sequentially from the lower energy levels. When the electrons reach the energy level corresponding to the L point in the band structure of the crystal 12a, the electron injection is stopped, and the electrons are confined up to the energy level corresponding to the L point.

[0112] As shown in 46B of Figure 46, an energy barrier (barrier region B) controls electron movement between adjacent first quantum dots 52a and second quantum dots 52b. ２ ) is formed. 46B is a conceptual diagram illustrating a state in which electrons confined in the energy level corresponding to the L point of the band structure of the crystal 12a are transferred from the first quantum dot 52a on the source region 102 side to the adjacent second quantum dot 52b on the drain region 103 side by controlling the potential of the barrier region B2 between quantum dot 1 and quantum dot 2 with a second barrier electrode 47 positioned between the first quantum dot 52a and the second quantum dot 52b.

[0113] The second barrier electrode 47 controls the barrier region B ２ The potential of the barrier region B can be controlled. The voltage applied to the second barrier electrode 47 can be adjusted to control the potential of the barrier region B. ２ By reducing the potential, electrons in the first quantum dot 52a can be moved (shutled) to the second quantum dot 52b. At this time, barrier region B ２The potential is maintained such that only electrons in the energy level corresponding to point L in the first quantum dot 52a are transferred to the second quantum dot 52b. This allows only electrons corresponding to the energy level of point L to be loaded into the second quantum dot 52b with high precision. With this configuration, it becomes possible to selectively and stably move electrons in the energy level corresponding to point L between adjacent quantum dots 52, enabling highly reproducible quantum information transfer and mutual control of spin states between quantum dots 52.

[0114] In the control method for the qubit element 101 according to the tenth embodiment, a voltage is applied to the first gate electrode 42a and the second gate electrode 42b formed on the crystal 12a, and this voltage forms an electric field perpendicular to the (111) plane of the crystal 12a. In addition, in the control method for the qubit element 101, potentials are induced in the first quantum dot 52a and the second quantum dot 52b within the crystal 12a by the first gate electrode 42a and the second gate electrode 42b, respectively, and the first quantum dot 52a and the second quantum dot 52b are controlled. This makes it possible to reduce the probability of calculation errors occurring in the qubit element 101.

[0115] Furthermore, in the control method for the qubit element 101, the electric field formed by the voltage from the first gate electrode 42a and the second gate electrode 42b confines electrons in the first quantum dot 52a and the second quantum dot 52b within the crystal 12a to an energy level corresponding to the L point of the band structure of the crystal 12a, thereby controlling the spin state of the electrons. By confining electrons to the L point, it becomes unnecessary to confine electrons near the oxide film 14 interface, as was required in elements using the Si(100) plane. Therefore, variations in energy levels caused by irregularities at the oxide film 14 interface and non-uniformity at the oxide film 14 / crystal 12a interface can be suppressed. As a result, variations in the energy difference between the qubit elements 101 can be reduced, and the two-level system of qubit elements 101 operates stably.

[0116] In the embodiments described above, the quantum dot element according to the sixth embodiment shown in Figure 16 was used as an example to explain how the gate electrode of a quantum dot element induces a potential to confine electrons to an energy level corresponding to the L point of the band structure of the crystal. However, the present invention is not limited to this. For example, the gate electrode of various other quantum bit elements, such as the quantum bit element 61c shown in Figure 26 and the quantum bit element 61g shown in Figure 30, may be configured to induce a potential to confine electrons to an energy level corresponding to the L point of the band structure of the crystal. Also, although the example of two quantum dots was explained here, the number of quantum dots can of course be three or more.

[0117] (Eleventh Embodiment) Next, the eleventh embodiment will be described. The qubit element 101 according to the tenth embodiment described above uses a silicon crystal 12a and is configured to confine electrons to the energy level corresponding to the L point in the band structure of the crystal 12a by applying voltage through the first gate electrode 42a, the second gate electrode 42b, the first barrier electrodes 44a, 44b, the second barrier electrode 47, and the source electrode 127, thereby increasing the stability of electron spin. In the eleventh embodiment, however, the silicon crystal and germanium-containing Si （１－ｘ） Ge ｘ The structure consists of stacked layers (where x is 0.8 ≤ x ≤ 1) forming a fin, which confines electrons to the energy level corresponding to point L.

[0118] Here, according to a report by C. G. Van de Walle and R. M. Martin (Phys. Rev. B, Vol. 34, p. 5621, 1986), in SiGe, a eutectic of Si and Ge, it is known that in the composition region where the Ge composition ratio is approximately 80% or more, the lowest energy point of the conduction band transitions from point X0 to point L, and point L becomes the minimum point of the conduction band. Furthermore, according to a report by S. Zh. Karazhanov, A. Davletova and A. Ulyashin (J. Appl. Phys. Vol. 104, p. 24501, 2008), it is known that in Si itself, the lowest energy point of the conduction band also transitions from point X0 to point L due to mechanical stress (tensile stress). In other words, by increasing the Ge concentration in a SiGe / Si / SiGe stacked structure and utilizing the difference in lattice constants to create a state where tensile stress is generated in Si, it is possible to control the L point of the band structure in a silicon crystal to the lowest energy point of the conduction band, thereby stabilizing the electron energy level at the L point.

[0119] Therefore, in the 11th embodiment, this characteristic is utilized, and the fin structure is made into a stacked structure of a Strained Si (111) layer and a relaxed SiGe layer with a high Ge concentration (Ge ≥ 80%), thereby creating a configuration that naturally loads electrons into the L-point energy level. By adopting such a stacked structure of Si layer and SiGe layer, an energy level corresponding to the L-point of the band structure is naturally formed within the crystal due to the material composition and crystal structure. Therefore, it becomes possible to stably capture electrons into the energy level corresponding to the L-point without relying on external electric field control by gate voltage.

[0120] Figure 47 is a conceptual diagram showing the configuration of a top-view perspective of a qubit element according to the 11th embodiment. The qubit element 110 according to the 11th embodiment shown in Figure 47 differs from the qubit element 101 according to the 10th embodiment described above in that, in addition to the silicon crystal 12a, germanium is included in the fin 111, source region 112, and drain region 113. （１－ｘ） Ge ｘIt differs in that layers (x is 0.8 ≤ x ≤ 1) 114 and 116 are provided. In this embodiment, the fin 111, source region 112, and drain region 113 have a silicon crystal 12a as the bottom layer, with germanium-containing Si on top of it. （１－ｘ） Ge ｘ Layer (x is 0.8 ≤ x ≤ 1) 116, silicon crystal 115, germanium-containing Si （１－ｘ） Ge ｘ It has a structure in which layers (x is 0.8 ≤ x ≤ 1) 114 are stacked in order. （１－ｘ） Ge ｘ It is preferable that layers 116 and 114 (where x is 0.8 ≤ x ≤ 1) relieve stress, and the silicon crystal 115 is a Strained Si(111) layer.

[0121] Crystal 115 is single-crystal silicon, similar to crystal 12a, with its (111) plane oriented perpendicular to the plane, and uses silicon with nuclear spin 0 (mass number 28) as the material. The fin 111 is formed by an electric field applied by the first gate electrode 42a and the second gate electrode 42b, perpendicular to the (111) plane of the crystal 115 which has the (111) plane orientation, and electrons are confined to the energy level corresponding to the L point of the band structure of the crystal 115. Even with this configuration, electrons can be confined to the energy level corresponding to the L point, and the electron spin can be stabilized.

[0122] In the 11th embodiment described above, the fin 111, source region 112, and drain region 113 are configured with a silicon crystal 12a as the bottom layer, and Si （１－ｘ） Ge ｘ Layer (x is 0.8 ≤ x ≤ 1) 116, silicon crystal 115, Si （１－ｘ） Ge ｘ In this embodiment, layers (x is 0.8 ≤ x ≤ 1) 114 are stacked in this order, but the present invention is not limited to this. For example, in another embodiment, the configuration of the fin 111, source region 112, and drain region 113 is made of a silicon crystal and Si （１－ｘ） Ge ｘ A configuration in which a predetermined number of layers (where x is 0.8 ≤ x ≤ 1) are stacked alternately may also be used.

[0123] (Modification of the 11th embodiment) For example, as shown in 48A of Figure 48, Si （１－ｘ） Ge ｘ Layer (x is x < 0.8) 124, Si （１－ｘ） Ge ｘ Layer (x is 0.8 ≤ x < 1) 123, silicon crystal 122, Si （１－ｘ） Ge ｘ Layer (x is 0.8 ≤ x < 1) 129, and Si （１－ｘ） Ge ｘ A laminate 121 may be provided, in which layers (x, x < 0.8) 130 are stacked in order, and the fins, source region, and drain region may be formed by this laminate.

[0124] Furthermore, as shown in 48B of Figure 48, a Ge layer 126 and Si layer are placed on top of the crystalline body 12a (not shown). （１－ｘ） Ge ｘ Layer (x is 0.8 ≤ x < 1) 123, silicon crystal 122, Si （１－ｘ） Ge ｘ A laminate 133 may be provided, in which layers (x is 0.8 ≤ x < 1) 129 and a Ge layer 132 are stacked in order, and the fins, source region and drain region may be formed by this laminate.

[0125] Furthermore, as shown in 48C of Figure 48, a laminate 134 may be provided on a crystal body 12a (not shown) in which a Ge layer 126, a silicon crystal body 122, and a Ge layer 132 are sequentially stacked, and the fins, source region, and drain region may be formed by this laminate.

[0126] Furthermore, the Ge composition ratio in each layer can be gradually changed within a specified range to further alleviate stress in the SiGe layer. In all cases, even when employing any of the above layered structures, it is possible to confine electrons to the energy level corresponding to the L point in the band structure of the crystal 12a, thereby stabilizing electron spin.

[0127] Note that in Figures 47 and 48, Si is placed on the crystal 12a. （１－ｘ） Ge ｘThe present invention is configured to have at least two layers (where x is 0.8 ≤ x ≤ 1), but is not limited to this, and includes at least one fin on the crystal body 12a with one or more Si layers. （１－ｘ） Ge ｘ The configuration should include layers (where x is 0.8 ≤ x < 1). Alternatively, the source and drain regions may consist only of diffusion layers formed by impurities being injected into crystalline Si, and the source electrode 127 and drain electrode 128 may be formed by making direct contact with the source and drain regions using conductive materials such as Al, TiN, or Cu.

[0128] Next, we will explain the simulation results performed to compare the electric field and potential distribution in the fins 13 of the qubit element 11 according to the first embodiment shown in Figure 1 and the qubit element 61f according to the sixth modification of the seventh embodiment shown in Figure 29. 49A in Figure 49 is a conceptual diagram showing the configuration of the qubit element 11 according to the first embodiment shown in Figure 1, and 49B is a conceptual diagram schematically showing the simulation results of the electric field and potential distribution in the cross-section of the fin 13 in the qubit element 11 shown in 49A. 50A in Figure 50 is a conceptual diagram showing the configuration of the qubit element 61f according to the sixth modification of the seventh embodiment shown in Figure 29, and 50B is a conceptual diagram schematically showing the simulation results of the electric field and potential distribution in the cross-section of the fin 13 in the qubit element 61f shown in 50A.

[0129] In the configuration shown in Figure 49, the fin 13 is formed solely from a silicon single crystal (crystal body 12a), and the gate electrode 16 is positioned only on the upper surface 13a of the fin 13. In this case, the electric field applied from the gate electrode 16 is formed in one direction downward from the upper surface of the fin 13 (perpendicular to the (111) plane). Therefore, the electric field distribution within the fin 13 is concentrated near the upper surface 13a, the electron potential well becomes shallower, and electrons tend to be confined near the upper surface 13a.

[0130] On the other hand, in the configuration shown in Figure 50, the fin 13 is similarly formed only from the crystal body 12a, but the gate electrode 62 is positioned facing both the upper surface 13a and the side surface 13b of the fin 13. As a result, electric fields from the directions of the upper surface 13a and the side surface 13b are superimposed within the fin 13, and the component perpendicular to the (111) plane is strengthened. Consequently, the potential distribution within the fin 13 becomes more uniform, the electron potential well deepens, and electrons tend to be confined at positions away from the upper surface 13a.

[0131] In the configuration shown in Figure 50, by adjusting the voltage applied to the gate electrode 62, the potential distribution within the fin 13 changes, causing the position of the quantum dot where the electron wave function is localized to move vertically (see 51B in Figure 51, described later). With this configuration, the localization position of the quantum dot within the fin 13 can be dynamically controlled, enabling the transfer of quantum states while maintaining the electron spin state with high stability.

[0132] (Twelfth Embodiment) Next, a qubit element according to the twelfth embodiment, which is provided with a substrate bias electrode, will be described. Figure 51, 51A is a conceptual diagram showing the configuration of a qubit element 131 according to the twelfth embodiment, which is provided with a substrate bias electrode 132. Figure 51, 51A shows an example in which a substrate bias electrode 132 is provided on the back surface of the substrate 12 of the qubit element 61f (Figure 29), which is a sixth modification of the seventh embodiment shown in Figure 29, but the present invention is not limited thereto. Similarly, in all the qubit elements shown in the first to eleventh embodiments described above, a substrate bias electrode 132 may be provided on the back surface of the substrate.

[0133] Figure 51, part 51A, uses the same reference numerals as Figure 29 for the same parts. Here, we will omit the explanation of the same configuration as in Figure 29 and focus on the substrate bias electrode 132. As shown in Figure 51, part 51A, the qubit element 131 according to the twelfth embodiment has a substrate bias electrode 132 provided on the back side of a substrate 12 having a silicon single crystal (crystal body 12a). The substrate bias electrode 132 is positioned opposite the gate electrode 62 and is formed on the lower side of the crystal body 12a through the thickness direction of the substrate 12. A voltage is applied to the substrate bias electrode 132 independently of the gate electrode 62, and the potential of electrons in the crystal body 12a can be adjusted by this voltage. That is, by changing the voltage applied to the substrate bias electrode 132, the depth and shape of the potential well formed in the crystal body 12a can be controlled, and the energy levels and positions of electrons can be adjusted with high precision.

[0134] As shown in Figure 51B, by applying a voltage to the substrate bias electrode 132, an electric field from the gate electrode 62 on the upper surface 13a of the fin and an electric field from the substrate bias electrode 132 on the lower surface of the fin are superimposed inside the fin 13. By adjusting the voltages applied to the substrate bias electrode 132 and the gate electrode 62, the position of the electron 98 in the quantum dot (in Figure 51B, the electron 98 in the quantum dot when it is located on the upper side is denoted as 98a, and the electron 98 in the quantum dot when it is located on the upper side is denoted as 98b) can be moved vertically. That is, as shown in Figure 51B, the position of the electron 98 in the quantum dot is selectively formed either above or below the fin 13. With this configuration, quantum state switching and transfer can be performed with high precision while the electron is held in the energy level corresponding to the L point in the band structure of the crystal 12a.

[0135] Furthermore, by adjusting the voltage applied to the substrate bias electrode 132, the depth and position of the potential well formed inside the fin 13 can be controlled. This compensates for variations in the electric field / potential distribution from the gate electrode 62 and fluctuations in the electron energy level caused by differences in element dimensions. By combining the control of the overall band structure by the substrate bias electrode 132 with the local potential control by the gate electrode 62, it is possible to stably trap electrons in the energy level corresponding to the L point while homogenizing the operating conditions among multiple quantum dots 98. Moreover, by dynamically changing the voltage applied to the substrate bias electrode 132, the localization region of the electron wave function within the quantum dot 98 can be controlled, making it possible to dynamically switch the formation position of the quantum dot 98. Therefore, even during electron initialization, readout, or electron transfer operations to adjacent quantum dots 98, the electrons can be operated with high reproducibility while maintaining a state in which they are held in the energy level corresponding to the L point.

[0136] As described above, according to the qubit element 131 of the 12th embodiment, a substrate bias electrode 132 is provided on the back side of the substrate 12, and the potential of electrons in the crystal 12a is adjusted by the voltage applied from the substrate bias electrode 132, thereby stably forming quantum dots 98 where the electron wave function is localized. This significantly improves the stability of the electron spin state, reduces the probability of spin reversal and phase fluctuations occurring during calculations of the qubit element 131, and effectively reduces the probability of quantum calculation errors. Therefore, it is possible to further improve the operational reproducibility and reliability of the qubit element 131.

[0137] While the control method for the qubit element 11 has been described in the first, fourth, and eleventh embodiments, the control method is similar for the other embodiments as well. Therefore, to avoid repetition in this specification, their explanation is omitted.

[0138] 11 Quantum bit element 11a Quantum bit element 11b Quantum bit element 12 Substrate 12a Crystal 13 Fin 16 Gate electrode 18 Barrier electrode 26 Fin 27 Laminate 31 Fin 32 Laminate 41 Quantum bit element 41a Quantum bit element 41b Quantum bit element 42a First gate electrode 42b Second gate electrode 44a First barrier electrode 44b First barrier electrode 47 Second barrier electrode 61 Quantum bit element 61a-61g Quantum bit element 62 Gate electrode 64 Barrier electrode 71 Quantum bit element 71a Quantum bit element 72 Fin 81 Quantum bit element 82 Substrate 82a Crystal 83 Dopant 84 Metal 86 First gate electrode 87 First barrier electrode 94 Silicon substrate (wafer) 97 Crystal 101 Quantum bit element 110 Quantum bit element 131 Quantum bit element 132 Substrate bias electrode

Claims

1. A qubit element comprising a substrate having a silicon crystal on its surface, and a gate electrode formed on the crystal, which applies a voltage perpendicular to the (111) plane of the crystal, thereby inducing a potential in quantum dots within the crystal.

2. The qubit element according to claim 1, wherein the substrate is a silicon substrate in which the (111) plane is oriented in a direction perpendicular to the surface of the substrate.

3. The qubit element according to claim 1, comprising a fin that protrudes from the surface of the crystal and extends linearly with a first width, wherein the gate electrode extends linearly on the crystal with a second width and crosses the fin.

4. The qubit element according to claim 3, wherein the intersection angle between the gate electrode and the fin in a top view is set to 90 degrees.

5. The qubit element according to claim 3, wherein the second width of the gate electrode and the first width of the fin are set to the same value.

6. The qubit element according to claim 3, wherein the fin is formed of a crystalline body and a laminate that sandwiches the crystalline body at a heterojunction.

7. The qubit element according to claim 3, wherein the height of the fin is set to the same value as the first width of the fin.

8. The qubit element according to claim 3, comprising two barrier electrodes formed on the crystal, wherein a voltage is applied perpendicular to the (111) plane of the crystal to induce a potential within the crystal and form a barrier to electrons, the two barrier electrodes extending linearly on both sides of the gate electrode in parallel with the gate electrode with a third width and crossing the fin.

9. The qubit element according to claim 1, wherein the substrate is a silicon substrate having the (111) plane oriented perpendicular to the surface of the substrate, and dopants are arranged in the crystal body according to rules determined to conform to the surface of the silicon substrate.

10. The qubit element according to claim 9, wherein the crystal comprises atoms of an element selectively deposited on the folded half.

11. A substrate having a silicon crystal on its surface; a first gate electrode formed on the crystal and extending linearly with a first width, which induces a potential in a first quantum dot within the crystal when a voltage is applied perpendicular to the (111) plane of the crystal; a second gate electrode formed on the crystal in parallel to the first gate electrode and extending linearly with a second width, which induces a potential in a second quantum dot within the crystal when a voltage is applied perpendicular to the (111) plane of the crystal; and two first barrier electrodes located on either side of the combined first and second gate electrodes, each extending linearly with a third width in parallel to the first and second gate electrodes, which induce a potential within the crystal when a voltage is applied perpendicular to the (111) plane of the crystal, thereby forming a barrier against electrons. A qubit element comprising: a second barrier electrode located between the first gate electrode and the second gate electrode, extending linearly with a fourth width in parallel with the first gate electrode and the second gate electrode, and applying a voltage perpendicular to the (111) plane of the crystal to induce a potential within the crystal and form a barrier to electrons.

12. The qubit element according to claim 11, wherein the substrate is a silicon substrate in which the (111) plane is oriented in a direction perpendicular to the surface of the substrate.

13. The qubit element according to claim 12, comprising a fin that protrudes from the surface of the crystal and extends linearly with a fifth width, wherein the first gate electrode, the second gate electrode, the first barrier electrode, and the second barrier electrode cross the fin.

14. The qubit element according to claim 13, wherein the intersection angle between the first gate electrode, the second gate electrode, the first barrier electrode, and the second barrier electrode and the fin in a top view is set to 90 degrees.

15. The qubit element according to claim 13, wherein the first width of the first gate electrode, the second width of the second gate electrode, the third width of the first barrier electrode, the fourth width of the second barrier electrode, and the fifth width of the fin are set to the same value.

16. The qubit element according to claim 13, wherein the fin is formed of a crystalline body and a laminate that sandwiches the crystalline body at a heterojunction.

17. The qubit element according to claim 13, wherein the height of the fin is set to the same value as the fifth width of the fin.

18. A method for manufacturing a qubit element, comprising: a step of exposing a (111) oriented silicon substrate to phosphorus gas; a step of epitaxially growing silicon crystals on the surface of the silicon substrate; a step of depositing a material selectively deposited on a folded half on the surface of the crystals; a step of depositing an electrode material on the crystals and the selectively deposited material; and a step of aligning based on the selectively deposited material, placing a mask on the surface of the electrode material, and etching the electrode material other than the portion protected by the mask to form an electrode.

19. The method for manufacturing a qubit element according to claim 18, wherein the material is selected from thallium, palladium, lead, tin, or silver.

20. The qubit element according to claim 1, wherein the gate electrode induces a potential for confining electrons to an energy level corresponding to the L point of the band structure of the crystal.

21. The qubit element according to claim 11, wherein the first gate electrode and the second gate electrode induce a potential for confining electrons to an energy level corresponding to the L point of the band structure of the crystal.

22. Si containing germanium on the crystalline material （１－ｘ） Ge ｘ A layer (where x is 0.8 ≤ x ≤ 1) is formed, and the Si （１－ｘ） Ge ｘ A qubit element according to claim 20 or 21, wherein electrons are injected into the crystal through a layer.

23. The qubit element according to claim 1 or 11, wherein a substrate bias electrode is provided on the back side of the substrate, and the potential of electrons in the crystal is adjusted by the potential applied to the substrate bias electrode.

24. A method for controlling a qubit element comprising a substrate having a silicon crystal on its surface, wherein a voltage is applied perpendicular to the (111) plane of the crystal by a gate electrode formed on the crystal, thereby inducing a potential in a quantum dot within the crystal and controlling the quantum dot.

25. A method for controlling a qubit element according to claim 24, wherein electrons in the quantum dots within the crystal are confined to an energy level corresponding to the L point of the band structure of the crystal.

26. A method for controlling a qubit element comprising a substrate having a silicon crystal on its surface, wherein a voltage is applied perpendicular to the (111) plane of the crystal by a first gate electrode and a second gate electrode formed on the crystal, thereby inducing potentials in a first quantum dot and a second quantum dot within the crystal, and controlling the first quantum dot and the second quantum dot.

27. A method for controlling a qubit element according to claim 26, wherein electrons in the first quantum dot and the second quantum dot within the crystal are confined to energy levels corresponding to the L point of the band structure of the crystal.

28. A method for controlling a qubit element according to claim 24 or 26, wherein the potential of electrons in the crystal is adjusted by a voltage applied to a substrate bias electrode provided on the back side of the substrate.

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