Power conversion device and power conversion device control method
The described power converter configuration with a differential core and control method adjusts gate pulse delays to suppress current imbalance in parallel-connected converters, enhancing power density and current capacity by ensuring opposite and equal turn-on and turn-off voltage signs.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- HITACHI LTD
- Filing Date
- 2025-11-11
- Publication Date
- 2026-05-15
AI Technical Summary
When multiple power converters are connected in parallel, variations in semiconductor elements cause shifting switching timings, leading to potential differences at the output, resulting in current unbalance and deterioration of power density due to cross currents and the need for large reactors to suppress current imbalance.
A compact power converter configuration using a differential core to magnetically couple in-phase output sections of power converters, combined with a pickup coil and detection circuit to measure voltage differences, and a control method that adjusts gate pulse delays to ensure opposite and equal turn-on and turn-off voltage signs to suppress current imbalance.
This configuration effectively suppresses current imbalance accumulation without being affected by noise currents, increasing current capacity and power density by controlling gate pulse delays based on real-time imbalance measurements.
Smart Images
Figure JP2025039393_15052026_PF_FP_ABST
Abstract
Description
Power conversion device and control method for power conversion device
[0001] The present invention relates to a power conversion device and a control method for the power conversion device.
[0002] In order to increase the capacity of semiconductor power conversion devices, multiple power converters are connected in parallel due to reasons such as market availability of components, defect rates of components, and low costs.
[0003] However, when multiple power converters are connected in parallel without any particular countermeasures, due to factors such as variations in the characteristics of semiconductor elements that make up each power converter, the switching timing of the semiconductor elements may shift, resulting in a potential difference at the output of each power converter.
[0004] When a potential difference occurs at the output of each power converter, a current (cross current) flows through the bus connecting the power converters, causing the output currents of each power converter to become unbalanced.
[0005] Therefore, when determining the current capacity of the power converters connected in parallel, it is necessary to add the unbalance component of the current to the load current, which causes a deterioration in the power density of the power conversion device. Thus, suppression of this current unbalance is required.
[0006] In order to suppress current unbalance, for example, Japanese Patent Application Laid-Open No. 2010-193582 (Patent Document 1) provides a method for suppressing current unbalance using a reactor that magnetically couples the outputs as a balancer for the output current.
[0007] Japanese Patent Application Laid-Open No. 2010-193582
[0008] As shown in Patent Document 1, current unbalance can be easily suppressed by providing a reactor on the output side of the power conversion device. However, due to factors such as individual differences in semiconductor elements, if the switching characteristics of turn-on and turn-off vary, the current unbalance will not become "0", and the current unbalance will accumulate with each switching. For this reason, a reactor with a very large inductance is required, and the size increase of the reactor in addition to the power conversion device becomes an issue.
[0009] In particular, because there is a great demand for high power density in power converters, there is a strong need to miniaturize the output reactor, and the accumulation of current imbalance becomes too large to ignore.
[0010] To suppress current imbalance in a small reactor, a suppression method combining gate pulse delay adjustment control is effective. Since the gate pulse delay amount varies depending on various conditions such as current, temperature, semiconductor element degradation, and operating pattern, it is necessary to measure the current imbalance component in real time to adjust the gate pulse delay amount. However, voltage sensors and current sensors are affected by the responsiveness of the sensors themselves and noise currents such as noise via motor-to-ground capacitance, so their effect on suppressing the accumulation of current imbalance is minimal.
[0011] The object of the present invention is to provide a compact power converter that suppresses the accumulation of current imbalances occurring in the output currents of power converters connected in parallel, and a control method for the power converter.
[0012] The present invention comprises at least two power converters connected in parallel, a differential core that magnetically couples the in-phase output sections of each power converter, a pickup coil magnetically coupled to the differential core, a detection circuit that uses the pickup coil to detect the turn-on voltage value when each power converter is turned on and the turn-off voltage value when it is turned off, and a control means that controls the turn-on and turn-off timing of each power converter based on the output from the detection circuit, wherein the control means controls the turn-on and turn-off timing of each power converter by generating a gate pulse such that the signs of the turn-off voltage value Voff and the turn-on voltage value Von are opposite, and the turn-off voltage value Voff and the turn-on voltage value Von are equal.
[0013] According to the present invention, it is possible to provide a compact power converter that suppresses the accumulation of current imbalances occurring in the output currents of power converters connected in parallel, and a control method for the power converter.
[0014] This is a configuration diagram showing the configuration of a power converter according to the first embodiment of the present invention. This is a block diagram showing the configuration of a control device that controls the power converter shown in Figure 1. This is an explanatory diagram illustrating the gate pulse pattern of the power converter shown in Figure 1. This is an explanatory diagram illustrating the output waveform of the detection circuit shown in Figure 1. This is a flowchart illustrating the control operation of the control device shown in Figure 2. This is an explanatory diagram illustrating the first output waveform of the detection circuit shown in Figure 1. This is an explanatory diagram illustrating the second output waveform of the detection circuit shown in Figure 1. This is an explanatory diagram illustrating the first and second correction voltage values in the flowchart shown in Figure 5. This is an explanatory diagram illustrating the third correction voltage value in the flowchart shown in Figure 5. This is an explanatory diagram illustrating the fourth and fifth correction voltage values in the flowchart shown in Figure 5. This is a configuration diagram showing the configuration of a power converter according to the second embodiment of the present invention.
[0015] The embodiments of the present invention will be described in detail below with reference to the drawings, but the present invention is not limited to the embodiments described below, and various modifications and applications are also included within the scope of the technical concept of the present invention.
[0016] First, a first embodiment of the present invention will be described. Figure 1 shows the configuration of the power converter IVT of this embodiment.
[0017] The power converter IVT of this embodiment has a power converter (A) 10 having an upper arm and a lower arm, and a power converter (B) 11 having an upper arm and a lower arm connected in parallel, but is not limited to this, and may have three or more power converters (this will be explained in the second embodiment). The power converter IVT of this embodiment is assumed to be an inverter, but for example, a rectifier or converter may be connected, or a DC-DC converter may be connected.
[0018] A shared battery 12 is connected to the DC sections of both power converter (A) 10 and power converter (B) 11. Here, "P" indicates the positive terminal and "N" indicates the negative terminal. Power converter (A) 10 is provided with a positive terminal Pa and a negative terminal Na, which are connected to the positive terminal P and the negative terminal N. Similarly, power converter (B) 11 is provided with a positive terminal Pb and a negative terminal Nb, which are connected to the positive terminal P and the negative terminal N.
[0019] In this embodiment, the DC section is assumed to be a battery 12, but for example, a DC / DC converter may be connected, or an AC power source may be converted to DC power using an AC / DC converter.
[0020] Each phase output (Ua and Ub, Va and Vb, Wa and Wb) of each power converter 10, 11 is magnetically coupled by the differential core 13 for each corresponding in-phase. In other words, phase outputs Ua and Ub are magnetically coupled by the differential core 13. Similarly, phase outputs Va and Vb are magnetically coupled with phase outputs Wa and Wb by the differential core 13 (however, reference numbers are omitted).
[0021] Furthermore, the phase output lines of each power converter 10, 11 are arranged to face each other on the inner ring of the differential core 13. The pickup coil 14 is magnetically coupled to each differential core 13. The phase outputs of each power converter coupled by the differential core 13 are connected together for each phase and supply power to the load 15. In this embodiment, the load 15 is assumed to be a three-phase AC motor such as an induction motor or a synchronous motor, but it may also be an inductive load, for example.
[0022] The detection circuit 16 receives the output signal from the pickup coil 14 in order to measure the potential difference between the outputs of each power converter 10 and 11, which is the cause of current imbalance. The detection circuit 16 is equipped with an integration circuit 17. The output from the integration circuit 17, which represents the measured potential difference and time information (turn-on and turn-off timing information), is detected by the voltage sensor 18.
[0023] In this embodiment, the energy corresponding to the current imbalance is calculated from the measured potential difference using an integrating circuit, but the invention is not limited to this; for example, the energy component may be calculated from the current. Furthermore, the detection circuit 16 may be equipped with a noise suppression filter.
[0024] The power converter IVT is controlled by the control device (control means) CNT shown in Figure 2. The control device CNT comprises at least a switching signal control device 20, a pulse delay time adjustment circuit 21, a gate drive circuit (A) 22, and a gate drive circuit (B) 23.
[0025] The switching signal control device 20 generates pulse commands to supply the necessary power to the load and delay time information calculated from the voltage command value from the higher-level control device and the detected value from the voltage sensor 16, based on the voltage command value from the higher-level control device and the detected value from the voltage sensor 16. In other words, it has the function of determining the turn-on delay time and turn-off delay time of each power converter.
[0026] The pulse delay time adjustment circuit 21 generates a correction pulse command to suppress the accumulation of current imbalance based on the pulse command and delay time information. The correction pulse command adjusts, for example, the turn-off timing or the turn-on timing.
[0027] The gate drive circuit (A) 22 and the gate drive circuit (B) 23 generate switching signals for the respective gates of the power converter (A) 11 and the power converter (B) 11 based on the correction pulse command from the pulse delay time adjustment circuit 21.
[0028] Next, the gate pulse pattern of the IVT power converter of this embodiment will be explained with reference to Figure 3. Figure 3 shows the pattern according to this embodiment that suppresses the accumulation of current imbalance.
[0029] Figure 3 shows the repeating patterns of the gate voltage (Uag) and output voltage (Uav) of power converter (A) 10, and the gate voltage (Ubg) and output voltage (Ubv) of power converter (B) 11. This repeating pattern represents the U-phase pattern of power converter (A) 10 and the U-phase pattern of power converter (B) 11. Of course, the V-phase and W-phase also operate in a similar pattern.
[0030] For example, when the gate is turned on, if power converter (A) 10 turns on earlier than power converter (B) 11 by a time length Δt1, the output voltage difference between power converter (A) 10 (Uav) and power converter (B) 11 (Ubv) will be negative with a pulse width of time length Δt1 (expressed as "output voltage difference between power converters" = "output voltage value of power converter A" - "output voltage value of power converter B").
[0031] Similarly, when the gate is turned off, if power converter (A) 10 turns off earlier than power converter (B) 11 by a time length Δt2, the output voltage difference between power converter (A) 10 (Uav) and power converter (B) 11 (Ubv) will occur in the positive direction with a pulse width of time length Δt2 (expressed as "output voltage difference between power converters" = "output voltage value of power converter A" - "output voltage value of power converter B").
[0032] The difference in output voltage between each power converter, either in the positive or negative direction, is the cause of current imbalance. With each turn-on and turn-off, the output voltage difference between each power converter 10 and 11 continues to occur in either the negative or positive direction, causing the current imbalance to accumulate.
[0033] Furthermore, in order to suppress the accumulation of current imbalance, it is necessary to generate a gate pulse pattern such that the sign of the output voltage difference between each power converter 10 and 11, which occurs during turn-on and turn-off, is opposite. Of course, it would be more preferable if the voltage difference values were equal.
[0034] To achieve this, as shown in Figure 3, power converter (B) 11 should generate a pulse such that it turns off later than power converter (A) 10 by a time length Δt2 (equal to Δt1). This ensures that the output voltage difference between power converters 10 and 11 at turn-off is generated in the positive direction with a pulse width of time length Δt2, thereby suppressing the accumulation of a current imbalance in the negative direction with a time length Δt1. In this way, if Δt1 and Δt2 can be controlled to have the same time length, current imbalance can be suppressed.
[0035] According to this embodiment, a pickup coil magnetically coupled to a differential core connected to the output section of parallel-connected power converters can detect current imbalance components. Therefore, the accumulation of current imbalance can be suppressed without being affected by common-mode noise currents such as those transmitted via motor-to-ground capacitance, thereby enabling an increase in the current capacity per power converter and higher power density.
[0036] In the explanation in Figure 3, the sign of the output voltage difference between each power converter 10 and 11 at turn-off is determined based on the output voltage difference between each power converter 10 and 11 at turn-on (reference voltage value). Alternatively, the sign of the output voltage difference between each power converter 10 and 11 at turn-on can also be determined based on the output voltage difference between each power converter 10 and 11 at turn-off (reference voltage value).
[0037] In the following explanation, we will proceed using the case where the difference in output voltages of each power converter 10 and 11 at the time of turn-off is used as the reference voltage.
[0038] Figure 4 shows the output waveform of the voltage sensor 18 provided in the detection circuit 16 of this embodiment.
[0039] In Figure 4, for example, if pulses are generated such that power converter (B) 11 turns off later than power converter (A) 10 by a time length Δt2 during turn-off, the output voltage difference between each power converter 10 and 11 will occur in the positive direction with a pulse width of time length Δt2. Therefore, the output of the voltage sensor 18 will detect a voltage with a voltage peak value Voff in the positive direction (turn-off voltage value).
[0040] On the other hand, when a pulse is generated such that the power converter (B) 11 turns on with a time delay of Δt1 with respect to the power converter (A) 10 at turn-on, the output voltage difference between the power converters 10 and 11 occurs in the negative direction with a pulse width of the time length Δt1. Therefore, the output of the voltage sensor 18 detects a voltage (turn-on voltage value) with a negative voltage peak value Von in the negative direction.
[0041] Here, it can be understood that in order to suppress current imbalance, it is only necessary to make the peak voltage values of the voltage peak value Voff and the voltage peak value Von closer. Therefore, based on the output of the voltage sensor 18, by generating a pulse such that the signs of the voltage peak value Voff and the voltage peak value Von are opposite in sign and the voltage peak values are equal, the accumulation of current imbalance can be suppressed.
[0042] The voltage value detected by the voltage sensor 18 and the time information (turn-on / turn-off timing information) are determined by the switching signal control device 20 whether there is a sign inversion, and the peak hold circuit in the switching signal control device 20 etc. can determine and compare the voltage peak values at turn-off and turn-on.
[0043] FIG. 5 shows a control flow executed by the switching signal control device 20 to suppress the accumulation of current imbalance according to the present embodiment. Here, this control flow is the processing for the U phase described above. Of course, the same processing can be performed for the V phase and the W phase.
[0044] ≪Step S10≫ In step S10, it is determined whether the switching timing is turn-off based on a higher pulse command. If it is determined to be turn-off (YES determination), the process proceeds to step S11, and if it is determined not to be turn-off (= turn-on) (NO determination), the process proceeds to step S14.
[0045] <<Step S11>> - <<Step S13>>Since it was determined to be turned off in Step S10, in Step S11, the output voltage Voff of the voltage sensor at the time of turn-off is read. Next, in Step S12, the voltage peak value Voff at the time of turn-off and its positive / negative sign are calculated. Then, in Step S13, the voltage peak value Voff and its sign are stored in the memory. The memory can use, for example, an internal RAM.
[0046] <<Step S14>> - <<Step S16>>Since it was determined to be turned on in Step S10, in Step S14, the output voltage Von of the voltage sensor at the time of turn-on is read. Next, in Step S15, the voltage peak value Von at the time of turn-on and its positive / negative sign are calculated. Then, in Step S16, the voltage peak value Von and its sign are stored in the memory. The memory can use, for example, an internal RAM.
[0047] <<Step S17>>When the voltage peak value Voff and its sign, and the voltage peak value Von and its sign are obtained in Step S13 and Step S16, Step S17 (hereinafter referred to as determination A) is executed. In determination A, based on the information of the output voltages of the detection circuit 16 at the time of turn-off and turn-on stored in the memory, it is determined whether the signs of the voltage peak value Voff and the voltage peak value Von are opposite.
[0048] For example, if the voltage peak value Voff and the voltage peak value Von are as shown in FIG. 6, it is determined that the signs of the voltage peak value Voff and the voltage peak value Von are not opposite (both are "positive" in FIG. 6) (NO determination), and the process proceeds to Step S18.
[0049] On the other hand, for example, if the voltage peak value Voff and the voltage peak value Von are as shown in FIG. 7, it is determined that the signs of the voltage peak value Voff and the voltage peak value Von are opposite (YES determination), and the process proceeds directly to Step S19.
[0050] Step S18: Since both the voltage peak value Voff and the voltage peak value Von are determined to be "positive" in step S17, the voltage required to reverse the sign of either the voltage peak value Voff or Von is stored in memory. In this embodiment, the turn-off time is used as the reference, so the voltage required to reverse the sign is calculated from the sum of the voltage peak value Voff and the voltage peak value Von.
[0051] In other words, as shown in Figure 8, the voltage value required to reverse the sign of the voltage peak value Von relative to the voltage peak value Voff is determined, and by subtracting this voltage value from the voltage peak value Von, the signs of the voltage peak values Voff and Von are reversed. For example, the voltage value obtained by adding the voltage peak value Von (let's call it the first corrected voltage value Vamd1) and the voltage peak value Voff (let's call it the second corrected voltage value Vamd2) in Figure 6 is subtracted from the voltage peak value Von in Figure 8, resulting in a voltage peak value Von with a negative sign at turn-on.
[0052] In other words, the negative voltage peak value Von (Vamd1 + Vand2) is the negative voltage peak value Voff, which is the same voltage value as the voltage peak value Voff at turn-off. The obtained first corrected voltage value Vand1 and second corrected voltage value Vand2 are stored in memory (e.g., internal RAM).
[0053] Step S19: After the processing in steps S17 and S18 is completed, step S19 (hereinafter referred to as determination B) is executed. In determination B, it is determined whether the voltage values of the voltage peak value Voff and the voltage peak value Von are equal.
[0054] If the voltage values are equal, the process proceeds directly to step S21. On the other hand, if the respective voltage peaks are not equal, as shown in Figure 7, the process proceeds to step S20.
[0055] Step S20: In step S20, as shown in Figure 7, the respective voltage peaks are not equal, so a third correction voltage value Vamd3 is calculated to make the voltage values of the voltage peak value Voff and the voltage peak value Von equal. Here, the voltage peak value Von is corrected.
[0056] As shown in Figure 9, the third correction voltage value Vamd3 is obtained by subtracting the voltage peak value Von from the voltage peak value Voff.
[0057] In other words, it can be calculated using the formula "Vamd3 = Voff - Von". Therefore, by subtracting the third correction voltage value Vamd3 from the negative voltage peak value Von in Figure 9, the voltage values of the voltage peak value Voff and the voltage peak value Von can be made equal. This third correction voltage value Vamd3 is stored in memory (for example, internal RAM). Note that in actual devices, there are resolution and measurement errors, so it is also possible to set a judgment range in advance and determine that the voltage peaks are equal if they fall within this range.
[0058] Step S21: After the processing in steps S19 and S20 is completed, step S21 (hereinafter referred to as determination C) is executed. In determination C, in order to minimize the occurrence of current imbalance, it is determined whether the voltage peak value Voff is less than a predetermined voltage threshold Vref(+) or whether the voltage peak value Von exceeds a predetermined voltage threshold Vref(-). Here, the voltage threshold Vref is set to the same voltage value on both the positive and negative voltage sides.
[0059] Ideally, the voltage threshold Vref should be set to "0," but due to variations and resolution in the pulse delay time adjustment circuit 21, it is preferable to set a voltage value calculated in advance from the target current imbalance specifications.
[0060] If, in step S21, it is determined that the voltage peak value Voff is less than the voltage threshold Vref(+) and the voltage peak value Von exceeds the voltage threshold Vref(-) (YES determination), the process proceeds to step S23. On the other hand, if it is determined that the voltage peak value Voff is greater than or equal to the voltage threshold Vref(+) and the voltage peak value Von is less than or equal to the voltage threshold Vref(-) (NO determination), the process proceeds to step S22.
[0061] Step S22: In step S22, the system performs the operation of finding and storing a fourth correction voltage value Vamd4 in which the voltage peak value Voff is less than the voltage threshold Vref(+), and a fifth correction voltage value Vamd5 in which the voltage peak value Von exceeds the voltage threshold Vref(-).
[0062] First, a fourth correction voltage value, Vamd4, is determined so that the voltage peak value Voff is less than the voltage threshold Vref(+) when the system is turned off. In this case, it can be calculated using the formula "Vamd4 = Voff - Vref(+)". The correction voltage value Vamd4 is stored in memory (for example, internal RAM).
[0063] Next, a fifth correction voltage value, Vamd5, is calculated so that the voltage peak value Von exceeds the reference value Vref(-) when the device is turned on. In this case, it can be calculated using the formula "Vamd5 = Vref(-) - Von". The fifth correction voltage value Vamd5 is stored in memory (for example, internal RAM).
[0064] Once the fourth correction voltage value Vamd4 and the fifth correction voltage value Vamd5 are determined, the process proceeds to step S23.
[0065] ≪Step S23≫ In step S23, the next delay times Δt2adv and Δt1adv for the next switching are determined. Here, the next delay times Δt2adv and Δt1adv are determined from the delay times according to the execution order of the control steps.
[0066] Firstly, if a "YES" judgment is made in all three judgments (A, B, and C), the next delay times Δt2adv and Δt1adv are both set to "0". In other words, the current turn-off delay time Δt2 and turn-on delay time Δt1 are of the same length, so there is no need to correct the delay time.
[0067] Secondly, based on the "YES judgment" and "NO judgment" in judgments A, B, and C, the stored correction voltage values Vand1 to Vand5 are selected to calculate the next delay times Δt2adv and Δt1adv for the next switching.
[0068] In this embodiment, since the turn-off time is used as the reference, the next delay time Δt1adv at the turn-off time will reflect the correction voltage value Vamd4.
[0069] On the other hand, if, for example, the control steps are executed in the order of "Step S17 (NO judgment) ⇒ Step S18 ⇒ Step S19 (YES judgment) ⇒ Step 21 (NO judgment) ⇒ Step S22" when the vehicle is turned on, the correction voltage values stored in memory will be "Vamd1", "Vamd2", and "Vamd5". The final correction voltage value will then be the final correction voltage value obtained by the calculation "Vamd1 + Vamd2 + Vamd5".
[0070] Furthermore, for example, if the control steps are executed in the order of "Step S17 (YES decision) ⇒ Step S19 (NO decision) ⇒ Step 20 ⇒ Step S21 (NO decision) ⇒ Step S22" when the vehicle is turned on, the correction voltage values stored in memory will be "Vamd3" and "Vamd5". The final correction voltage value will then be the final correction voltage value obtained by the calculation "Vamd3 + Vamd5".
[0071] Here, the conversion from voltage information (final corrected voltage value) to time information (delay time during turn-off and turn-on) can be obtained by referring to a pre-prepared conversion table, or by using a conversion formula. However, from the standpoint of calculation speed, using a conversion table is preferable.
[0072] It goes without saying that the correction voltage value is appropriately selected according to the execution order of the control steps described above and converted into time information. Once the delay time for the next switching is determined, the process proceeds to step S24.
[0073] Step S24: In step S24, the current delay time is added to the next new turn-off delay time Δt2adv and turn-on delay time Δt1adv to correct the final turn-off delay time Δt2 and turn-on delay time Δt1 to the same length. Once the corrected turn-off delay time Δt2 and turn-on delay time Δt1 are determined, the process proceeds to step S25.
[0074] Step S25: In step S25, the corrected turn-off delay time Δt2 and turn-on delay time Δt1 are input to the pulse delay time adjustment circuit 21. The pulse delay time adjustment circuit 21 outputs gate pulses that reflect the corrected turn-off delay time Δt2 and turn-on delay time Δt1 to the gate drive circuit (A) 22 and the gate drive circuit (B) 23, driving the power conversion circuit (A) 10 and the power conversion circuit (B) 11. As the gate pulse command is corrected in this way, the accumulation of current imbalance is suppressed.
[0075] Thus, in this embodiment, by generating pulses such that the voltage peak value Voff at turn-off and the voltage peak value Von at turn-on have opposite signs and their respective voltage peak values are equal, it is possible to suppress the accumulation of current imbalance.
[0076] Next, a second embodiment of the present invention will be briefly described. Parts identical to those in the first embodiment are denoted by the same reference numerals and their descriptions are omitted; only the different parts will be described.
[0077] The power conversion device of the second embodiment shown in Figure 11 has three power converters connected in parallel: power converter (A) 10, power converter (B) 11, and power converter (C) 19.
[0078] The outputs of power converter (A) 10 and power converter (B) 11 are magnetically coupled by one differential core 13, and the outputs of power converter (B) 11 and power converter (C) 19 are magnetically coupled by another differential core 13. In other words, the outputs of adjacent power converters in the diagram are magnetically coupled by a differential core 13.
[0079] This allows for correction of the delay time in the switching pattern of each power converter, thereby suppressing the accumulation of current imbalance. When three power converters are connected in parallel, six differential cores 13 are required. Furthermore, when four power converters are connected in parallel, nine differential cores 13 are required. Thus, if the number of power converters connected in parallel is "n", the number of differential cores 13 required can be calculated as "3(n-1)".
[0080] As described above, the present invention comprises at least two power converters connected in parallel, a differential core that magnetically couples the in-phase output sections of each power converter, a pickup coil magnetically coupled to the differential core, a detection circuit that uses the pickup coil to detect the turn-on voltage value when each power converter is turned on and the turn-off voltage value when it is turned off, and a control means that controls the turn-on and turn-off timing of each power converter based on the output from the detection circuit, wherein the control means controls the turn-on and turn-off timing of each power converter by generating a gate pulse such that the signs of the turn-off voltage value Voff when it is turned off and the turn-on voltage value Von when it is turned on are opposite, and the turn-off voltage value Voff and the turn-on voltage value Von are equal.
[0081] This provides a compact power converter that suppresses the accumulation of current imbalances in the output currents of power converters connected in parallel, and a control method for the power converter.
[0082] Furthermore, the present invention is not limited to the embodiments described above, but includes various modifications. The embodiments described above are explained in detail to make the present invention easier to understand, and are not necessarily limited to those having all the configurations described. In addition, it is possible to replace parts of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. It is also possible to add, delete, or replace other configurations for the configuration of each embodiment.
[0083] 10...Power converter (A), 11...Power converter (B), 12...Battery, 13...Differential core, 14...Pickup coil, 15...Load, 16...Detection circuit, 17...Integration circuit, 18...Voltage sensor, CNT...Control device, 20...Switching signal control device, 21...Pulse delay time adjustment circuit, 222...Gate drive circuit (A), 23...Gate drive circuit (B).
Claims
1. A power converter comprising: at least two power converters connected in parallel; a differential core that magnetically couples the in-phase output sections of each of the power converters; a pickup coil magnetically coupled to the differential core; a detection circuit that uses the pickup coil to output a turn-on voltage value when each of the power converters is turned on and a turn-off voltage value when each of the power converters is turned off; and a control means that controls the turn-on and turn-off timing of each of the power converters based on the output from the detection circuit, wherein the control means controls the turn-on and turn-off timing of each of the power converters by generating a gate pulse such that the signs of the turn-on voltage value and the turn-off voltage value are opposite and the turn-on voltage value and the turn-off voltage value are equal.
2. The power converter according to claim 1, wherein the control means comprises: a voltage correction function that corrects one of the turn-on voltage value and the turn-off voltage value so that the voltage value of one of them is opposite in polarity to the voltage value of the other and is the same as the voltage value of the other; a delay time calculation function that converts the other voltage value and the corrected one voltage value into a time length to determine the turn-on delay time and the turn-off delay time of each of the power converters; and a power conversion function that turns on each of the power converters based on the turn-on delay time and turns off each of the power converters based on the turn-off delay time.
3. A power conversion device according to claim 2, wherein the control means corrects the voltage value of the other voltage value to a voltage value that occurs sequentially over time, with the polarity opposite to that of the reference voltage value, and the same as that of the reference voltage value, when the other voltage value is taken as a reference voltage value.
4. A power conversion device according to claim 3, characterized in that the other voltage value is the turn-off voltage value at the time of turn-off, and the one voltage value is the turn-on voltage value at the time of turn-on following the turn-off.
5. The power conversion device according to claim 4, wherein the voltage correction function stores the turn-on voltage value as a first correction voltage value and the turn-off voltage value as a second correction voltage value when the turn-off voltage value and the turn-on voltage value have the same polarity.
6. The power conversion device according to claim 5, wherein the voltage correction function stores a voltage value obtained by subtracting the turn-on voltage value from the turn-off voltage value as a third correction voltage value if the turn-off voltage value and the turn-on voltage value have different polarities and the turn-off voltage value and the turn-on voltage value are not equal.
7. A power converter according to claim 6, wherein the voltage correction function stores a voltage value obtained by subtracting the voltage threshold (+) from the turn-off voltage value as a fourth correction voltage value when the turn-off voltage value is equal to or greater than a predetermined voltage threshold (+), and the voltage correction function stores a voltage value obtained by subtracting the voltage threshold (-) from the turn-on voltage value as a fifth correction voltage value when the turn-on voltage value is equal to or less than a predetermined voltage threshold (-).
8. A power conversion device according to claim 7, wherein the delay time calculation function selects and adds the first correction voltage value, the second correction voltage value, the third correction voltage value, the fourth correction voltage value, and the fifth correction voltage value to obtain a final correction voltage value, and calculates the turn-off delay time and the turn-on delay time from the obtained final correction voltage value.
9. A power converter according to claim 2, characterized in that when the number of power converters connected in parallel is "n", the number of differential cores is determined to be "3(n-1)".
10. A control method for a power converter comprising: at least two power converters connected in parallel; a differential core that magnetically couples the in-phase output portions of each of the power converters; a pickup coil magnetically coupled to the differential core; a detection circuit that uses the pickup coil to output a turn-on voltage value when each of the power converters is turned on and a turn-off voltage value when each of the power converters is turned off; and a control means for controlling the turn-on and turn-off timing of each of the power converters based on the output from the detection circuit, wherein the control means is characterized by performing the steps of: correcting one of the turn-on voltage value and the turn-off voltage value so that the voltage value of one of them is opposite in polarity to the voltage value of the other and is the same as the voltage value of the other; converting the other voltage value and the corrected voltage value into time lengths to determine the turn-on delay time and the turn-off delay time of each of the power converters; and turning on each of the power converters based on the turn-on delay time and turning off each of the power converters based on the turn-off delay time.