Clock recovery circuit and data communication system capable of correcting glitch noise

Abstract

The present invention provides a clock recovery circuit and a data communication system including the clock recovery circuit, wherein, when it is determined that a malfunction has occurred due to glitch noise while input data is recovered by using a pulse signal generated by a pulse generator, a recovery process of the input data can be normalized by controlling the width of the pulse signal used to recover the input data.

Description

Clock recovery circuit and data communication system capable of correcting glitch noise

[0001] The present invention relates to a clock recovery circuit, and in particular, to a clock recovery circuit capable of normalizing the process of recovering input data by controlling the width of the pulse signal used to recover input data when it is determined that a malfunction has occurred due to glitch noise while recovering a clock signal from input data using a pulse signal generated by a pulse generator constituting the clock recovery circuit.

[0002] Digital data communication is a technology that transmits digital data between a computer and other devices. Generally, digital communication systems use a clock recovery circuit to recover digital data received from a counterpart device through a transmission channel.

[0003] To receive high-speed data, a clock synchronized with the data is required.

[0004] Figure 1 shows a conventional digital data communication system.

[0005] FIG. 1a is a conventional general serial interface system and FIG. 1b is an improved serial interface system.

[0006] Referring to FIG. 1a, a conventional traditional serial interface transmits the clock (CLK) used to generate the serial data to be transmitted from the transmitter to the receiver separately from the data. At the receiver, the received data is recovered using the received clock (CLK). However, in the system illustrated in FIG. 1a, there is a difference in the time it takes for the data and the clock (CLK) to arrive at the receiver due to a mismatch between two transmission channels, and as the data speed increases, this difference in reception time becomes a significant burden on data recovery.

[0007] Referring to FIG. 1b, in order to solve the disadvantages of the system shown in FIG. 1a, data containing clock (CLK) information is transmitted from the transmitter to the receiver, and the clock (CLK) included in the data is restored by adding a clock recovery circuit to the conventional technology shown in FIG. 1a.

[0008] MIPI C-PHY (Mobile Industry Processor Interface C-PHYsical layer), one of the data transmission and reception protocols, also performs a high-speed interface by embedding clock information within the data instead of transmitting the clock separately. Unlike other high-speed interfaces, MIPI C-PHY encodes information regarding the transition from the previous state to the next state into a 3-bit symbol and transmits the data through three wires.

[0009] Unlike traditional serial interfaces, where the state of the wire does not change when the same data is transmitted, MIPI C-PHY transitions the state of the wire every time, even when the same data is transmitted. The receiver of MIPI C-PHY utilizes the characteristic that the state of the wire changes every time to restore the existing clock, and uses a clock recovery circuit that includes a pulse generator that generates a pulse whenever there is a change in the input signal.

[0010] Figure 2 shows an example of a clock recovery circuit using a pulse generator and a timing diagram of the clock recovery circuit.

[0011] The clock recovery circuit illustrated in FIG. 2a uses a pulse generated by a pulse generator in response to an input signal (IN) to allow a D-flip-flop to recover the clock (CLK). REC It generates ). Referring to the timing diagram shown in Fig. 2b, a pulse signal (Pulse) is generated whenever the input signal (IN) transitions, and the recovery clock (CLK)REC It can be seen that ) can be reproduced using a pulse signal.

[0012] Figure 3 shows an example of a clock recovery session with an edge joining technique applied.

[0013] Referring to the clock recovery circuit applying the edge combining technique illustrated in FIG. 3a, since at least one of the three wires used in the actual C-PHY changes, the three pulse generators used in FIG. 2a and the three pulses (AB) generated from the three pulse generators Pulse ~ CA Pulse Edge-coupled pulses (CR) using a logic circuit (OR gate) that combines the edges of ) Pulse ) generates, and the D-flip-flop generates an edge-coupled pulse (CR Pulse Using the recovery clock (CLK REC Plays ).

[0014] While the pulse generator illustrated in FIG. 2a generates a pulse for a single input signal (IN), the pulse generator illustrated in FIG. 3a generates a pulse signal (AB) for a signal (AB, BC, CA) formed by combining two of three signals (ABC). Pulse , BC Pulse , CA Pulse There is a difference in that it generates ).

[0015] Referring to FIGS. 3b and 3c, in the case of a clock recovery circuit applying an edge combining technique, three pulse signals (AB) generated as the state of three signals (ABC) changes Pulse , BC Pulse , CA Pulse As ) passes through the OR gate, the edge-coupled pulse (CR Pulse It can be seen that ) is generated.

[0016] Depending on the degree to which the three pulse generators delay the three input signals (AB, BC, CA), three pulse signals (AB Pulse , BC Pulse , CAPulse The width of ) is determined.

[0017] 3 pulse signals (AB Pulse , BC Pulse , CA Pulse When the width of ) is within a preset range (Fig. 3b), a corresponding edge-coupled pulse (CR Pulse ) can be generated, so the recovery clock (CLK REC Can play ).

[0018] However, three pulse signals (AB Pulse , BC Pulse , CA Pulse If the width of ) exceeds a preset range (Fig. 3c), a plurality of edge-coupled pulses (CR Pulse ) can be generated, so the recovery clock (CLK REC It becomes impossible to reproduce ). Due to a small delay relative to the input signal, the edge-coupled pulse (CR Pulse It contains two or more short pulses, which is called glitch noise, and glitch noise causes malfunction of the lock recovery circuit.

[0019] A clock recovery circuit using a pulse generation circuit must be able to control an appropriate delay time to generate a pulse signal; however, since pulse signals are difficult to observe externally, there is a problem in that it is difficult to properly set the delay time due to process errors during the manufacturing of the clock recovery circuit.

[0020] The technical problem that the present invention aims to solve is to provide a clock recovery circuit that can normalize the input data recovery process by controlling the width of the pulse signal used for input data recovery when it is determined that a malfunction has occurred due to glitch noise while recovering input data using a pulse signal generated by a pulse generator.

[0021] Another technical problem that the present invention aims to solve is to provide a data communication system including a clock recovery circuit that can normalize the input data recovery process by controlling the width of the pulse signal used for input data recovery when it is determined that a malfunction has occurred due to glitch noise while recovering input data using a pulse signal generated by a pulse generator.

[0022] The technical problems to be solved by the present invention are not limited to those mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art to which the present invention belongs from the description below.

[0023] A clock recovery circuit according to the present invention for achieving the above technical problem is a clock recovery circuit that generates a recovery clock used to recover a plurality of input data, comprising: a pulse generator including at least one pulse generation block that generates a plurality of pulse signals corresponding to a plurality of CMOS data in response to a delay control signal; a first logic circuit that generates a pulse combination signal by logically combining the plurality of pulse signals; a clock recovery unit that generates the recovery clock using the pulse combination signal; and a clock recovery correction unit that generates the delay control signal by reflecting the result of comparing an even-numbered data and an odd-numbered data among the data recovered from the plurality of input data using the recovery clock, wherein the plurality of CMOS data is data formed by combining two different data among the plurality of input data.

[0024] A data communication system according to the present invention for achieving the above other technical objectives comprises: a receiving circuit that generates multiple CMOS data by comparing two different data among multiple input data received through multiple wires; a sampler that generates even-numbered data and odd-numbered data of combined data by combining the multiple CMOS data using the rising edge and falling edge of a recovery clock; and a clock recovery circuit described in claim 1 that generates multiple pulse signals corresponding to the multiple CMOS data using the even-numbered data and the odd-numbered data, and generates the recovery clock using the multiple pulse signals.

[0025] The technical problems to be solved by the present invention are not limited to those mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art to which the present invention belongs from the description below.

[0026] The clock recovery circuit and data communication system according to the present invention as described above have the advantage of being advantageous for verifying multiple chips because each chip can independently determine the delay time set in the pulse generator, which is one of the external control elements. Furthermore, even if the resolution of the controllable delay time is increased by increasing the number of bits in the counter, the same clock recovery circuit can be applied to systems of various transmission speeds because the control signal is actively determined rather than by an external control element.

[0027] The effects obtainable from the present invention are not limited to those mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art from the description below.

[0028] Figure 1 shows a conventional digital data communication system.

[0029] Figure 2 shows an example of a clock recovery circuit using a pulse generator and a timing diagram of the clock recovery circuit.

[0030] Figure 3 shows an example of a clock recovery session with an edge joining technique applied.

[0031] FIG. 4 is a block diagram of a digital data communication system including a clock recovery circuit according to the present invention.

[0032] Figure 5 shows an example of a receiving circuit.

[0033] Figure 6 shows an example of a sampler.

[0034] Figure 7 shows a part of the functional blocks constituting the clock recovery circuit.

[0035] Figure 8 shows an example of a clock recovery corrector.

[0036] Figure 9 shows the timing diagrams for normal operation and malfunction due to glitch noise of the clock recovery circuit.

[0037] FIG. 10 shows a timing diagram of a clock recovery circuit according to the present invention during normal operation and when glitch noise occurs.

[0038] Figure 11 shows the computer simulation results of the clock recovery circuit according to the present invention.

[0039] Figure 12 is an eye diagram of the final output when the clock recovery correction function is not enabled and when it is enabled, with 3 Gsps data as input.

[0040] In order to fully understand the present invention, the operational advantages of the present invention, and the objectives achieved by the implementation of the present invention, reference should be made to the accompanying drawings describing embodiments of the present invention and the contents described in the accompanying drawings.

[0041] The present invention will be described in detail below by explaining preferred embodiments of the invention with reference to the attached drawings. Identical reference numerals in each drawing indicate identical components.

[0042] The present invention relates to a clock recovery circuit capable of normalizing the input data recovery process by controlling the width of the pulse signal used for input data recovery when it is determined that a malfunction has occurred due to glitch noise while recovering input data using a pulse signal generated by a pulse generator.

[0043] FIG. 4 is a block diagram of a digital data communication system including a clock recovery circuit according to the present invention.

[0044] Referring to FIG. 4, the digital data communication system (400, data communication system) according to the present invention includes a receiving circuit (410), a clock recovery circuit (420), and a sampler (430).

[0045] The system illustrated in Fig. 4 here is referred to as a data communication system, taking into account that any communication system must include both a transmitter and a receiver. That is, since communication systems at both ends that transmit and receive information or signals generally perform both transmitting and receiving functions, a communication system must include both a transmitter and a receiver.

[0046] The receiving circuit (410) receives three input data (IN) through three wires (not shown). A , IN B , IN C Three CMOS data (AB, BC, CA) are generated by combining two different data. Therefore, [2:0] should be written as 3-bit data in the following description, but unless otherwise noted, DATA and DATA[2:0] will be used with the same meaning.

[0047] The sampler (430) restores the combined data (SDATA) using a clock (Clock RECEven-numbered data (EDATA) and odd-numbered data (ODATA) are generated by distinguishing between the rising edge and falling edge of the ). Here, combined data (SDATA) is data that combines three CMOS data (AB, BC, CA) output from the receiving circuit (410).

[0048] The clock recovery circuit (420) generates three pulse signals (Pul1, Pul2, Pul3) corresponding to three CMOS data (AB, BC, CA) output from the receiving circuit (410) using EDATA and ODATA, and uses the three pulse signals (Pul1, Pul2, Pul3) to recover the clock (Clock REC Creates ).

[0049] Figure 5 shows an example of a receiving circuit.

[0050] Referring to FIG. 5, the receiving circuit (410) includes three comparison function blocks (411 to 413), and each of the three comparison function blocks (411 to 413) has three input data (IN A , IN B , IN C 3 CMOS data (AB, BC, CA) are generated by comparing 2 of the data.

[0051] Figure 6 shows an example of a sampler.

[0052] Referring to FIG. 6, the sampler (430) is a recovery clock (Clock REC It includes a first classification circuit (431) that generates three even-numbered data (EDATA[2], EDATA[1], EDATA[0]) of combined data (SDATA) using the rising edge and falling edge of ), and a second classification circuit (432) that generates three odd-numbered data (ODATA[2], ODATA[1], ODATA[0]) of combined data (SDATA). The first classification circuit (431) includes a recovery clock (Clock RECWhile using ) as is, the second classification circuit (432) uses an inverter (433) to restore the clock (Clock REC Uses a clock with the phase inverted of ).

[0053] For example, the first classification circuit (431) is a restoration clock (Clock REC At the rising edge of ), the even-numbered data (EDATA) of the combined data (SDATA) is generated, and the second classification circuit (432) restores the clock (Clock REC Odd-numbered data (ODATA) of combined data (SDATA) can be generated at the polling edge of ).

[0054] According to an embodiment, the recovery clock (Clock) in the first classification circuit (431) and the second classification circuit (432) REC You can also reverse the way ) is used.

[0055] Each of the first classification circuit (431) and the second classification circuit (432) restores the combined data (SDATA) applied to the input terminal (D) using a clock REC ) or recovery clock (Clock REC It may include a D-flip-flop that generates even-numbered data (EDATA) and odd-numbered data (ODATA), respectively, using a clock whose phase is opposite.

[0056] Referring again to FIG. 4, the clock recovery circuit (420) according to the present invention includes a pulse generator (421), a first logic circuit (422), a clock recovery unit (423), and a clock recovery correction unit (424).

[0057] The pulse generator (421) is a delay control signal (Ctrl Delay In response to ), three pulse signals (Pul1~Pul3) corresponding to three CMOS data (AB, BC, CA) are generated.

[0058] The first logic circuit (422) logically combines three pulse signals (Pul1~Pul3) to form a pulse combination signal (NOR Out Creates ).

[0059] The clock restorer (423) is a pulse combination signal (NOR Out Using the recovery clock (Clock REC Creates ).

[0060] The clock recovery corrector (424) reflects the result of comparing even-numbered data (EDATA) and odd-numbered data (ODATA) to the delay control signal (Ctrl Delay Creates ).

[0061] Figure 7 shows a part of the functional blocks constituting the clock recovery circuit.

[0062] Referring to FIG. 7, the pulse generator (421) includes three pulse generation blocks (421-1 to 421-3), the first logic circuit (422) can be implemented with a 3-input NOR gate, and the clock restorer (423) has an input terminal (D) connected to a negative output terminal (QB) and a pulse combination signal (NOR Out Restore clock (Clock) to the positive output terminal (Q) according to the period of ). REC It can be seen that it can be implemented with a D-flip-flop that generates ).

[0063] Each of the pulse generation blocks (421-1 to 421-3) includes one XOR (XOR1 to XOR3) and one delay line (Delay Line1 to Delay Line3).

[0064] The first delay line (Delay Line1) constituting the first pulse generation block (421-1) delays the first CMOS data (AB) among the three CMOS data (AB, BC, CA) using a delay control signal (Ctrl Delay Delays in response to ). The first XOR (XOR1) generates the first pulse (Pul1) by performing an exclusive OR operation on the first CMOS data (AB) and the first CMOS delayed data that has been delayed by the first CMOS data (AB).

[0065] Since the second pulse generation block (421-1) and the third pulse generation block (421-3) have the same circuit configuration, only the input CMOS data is different, and only the generated pulses are different, the description of the second pulse generation block (421-1) and the third pulse generation block (421-3) is replaced by the description of the first pulse generation block (421-1).

[0066] The 3-input NOR gate constituting the first logic circuit (422) performs a negative logical OR of the three pulses (Pul1 ~ Pul3) output from the pulse generation blocks (421-1 ~ 421-3) to form a pulse combination signal (NOR Out Creates ).

[0067] In the following description, when referring to the three pulses (Pul1 ~ Pul3), Pul 1 / 2 / 3 It can also be expressed as.

[0068] Figure 8 shows an example of a clock recovery corrector.

[0069] Referring to FIG. 8, the clock recovery corrector (424) includes a second logic circuit (424-1) and a 4-bit counter (424-2).

[0070] The second logic circuit (424-1) compares the 3-bit even-numbered data (EDATA[2:0]) and the 3-bit odd-numbered data (ODATA[2:0]) respectively, and detects the moment when the two data become different, an error detection signal (Err CR It generates ), and to do this, includes three XOR (XOR4 ~ XOR6) and AND gates (AND).

[0071] Error detection signal (Err CR ) is used to adjust the delay values ​​of each delay line (Delay Line1 ~ Delay Line3) constituting the pulse generation block (421-1 ~ 421-3).

[0072] The 4th XOR (XOR4) performs an exclusive OR operation on the 1st even-numbered data (EDATA[2]) and the 1st odd-numbered data (ODATA[2]).

[0073] The 5th XOR (XOR4) performs an exclusive OR operation on the 2nd even-numbered data (EDATA[1]) and the 2nd odd-numbered data (ODATA[1]).

[0074] The 6th XOR (XOR4) performs an exclusive OR operation on the 3rd even-numbered data (EDATA[0]) and the 3rd odd-numbered data (ODATA[0]).

[0075] The AND gate performs a logical AND operation on the output signals of three XORs (XOR4 ~ XOR6) to produce an error detection signal (Err CR Creates ).

[0076] The 4-bit counter (424-2) is an error detection signal (Err CR Count ) and 4-bit delay control signal (Ctrl Delay Creates ).

[0077] First, the case where the clock recovery circuit does not operate normally is explained, and then the operation when the clock recovery circuit according to the present invention is activated is explained.

[0078] Figure 9 shows the timing diagrams for normal operation and malfunction due to glitch noise of the clock recovery circuit.

[0079] FIG. 9 is an example illustrating when the clock recovery circuit does not operate normally, and does not relate to the operation of the clock recovery circuit according to the present invention illustrated in FIG. 4.

[0080] Referring to Fig. 9, since the MIPI C-PHY adopts a signaling scheme using three voltage levels, three pulse signals (Pul 1 / 2 / 3 The edge of ) is the 3 received data (IN A , IN B , IN C A time difference of τ0 may occur depending on ).

[0081] At this time, the pulse signal (Pul) generated by the pulse generators (421-1 ~ 421-3) constituting the clock recovery circuit (420)1 / 2 / 3 If the width of ) is set to a value of τ1 greater than τ0, the pulse combination signal (NOR) is used even if the edges of the three CMOS data (AB / BC / CA) do not occur simultaneously. Out It can be seen that the rising edge of ) generates a single pulse using the edge combining technique, allowing clock recovery to proceed successfully (Clock recovery: success).

[0082] Successfully restored recovery clock (Clock) REC Combined data (SDATA[2:0]) is sampled in the sampler (430) using the rising and falling edges of ). At this time, the recovery clock (Clock REC Data sampled using the rising edge of ) becomes the even-numbered data (EDATA[2:0]), and data sampled using the falling edge becomes the odd-numbered data (ODATA[2:0]). Normally sampled EDATA and ODATA always have different values ​​due to the nature of C-PHY where SDATA is always changing.

[0083] However, the pulse signal (Pul) generated by the pulse generators (421-1 ~ 421-3) of the clock recovery circuit (420) 1 / 2 / 3 When the width of ) is τ2, which is smaller than τ0, two pulses are generated during the symbol change process, that is, when changing from symbol S4 to symbol S5, causing malfunction due to glitch noise.

[0084] Due to the two generated pulses, the recovered clock is toggled twice, generating both a rising edge and a falling edge, which results in the sampled EDATA and ODATA becoming identical (Clock recovery: fail).

[0085] In the following, it is explained that when the clock recovery circuit according to the present invention operates normally, it compensates for the case where clock recovery fails as exemplified in FIG. 9.

[0086] FIG. 10 shows a timing diagram of a clock recovery circuit according to the present invention during normal operation and when glitch noise occurs.

[0087] Referring to Fig. 10, it can be seen that the clock is restored normally from the state of symbol S0 to symbol S5 of the combined data (SDATA[2:0]), and the even-numbered data (EDATA[2:0]) and odd-numbered data (ODATA[2:0]) are classified normally.

[0088] However, glitch noise occurred during the state transition from symbol S5 to symbol S6, and at this time, the clock recovery corrector (424) according to the present invention detects an error detection signal (Err) at the moment when the even-numbered data (EDATA[2:0]) and the odd-numbered data (ODATA[2:0]) become identical to S6. CR Generates the generated error detection signal (Err CR ) controls the degree to which the delay generator (421-1 to 421-3) delays the three CMOS data (AB, BC, CA).

[0089] Delay control signal (Ctrl Delay [3:0]) changes in response to malfunctions such as glitch noise, so the clock recovery circuit (420) according to the present invention detects, on the one hand, that a malfunction has occurred due to glitch noise while recovering input data, and on the other hand, when it is determined that a malfunction has occurred, controls the width of the pulse signal used for recovering input data to normalize the process of recovering input data.

[0090] Figure 11 shows the computer simulation results of the clock recovery circuit according to the present invention.

[0091] Referring to FIG. 11, an edge-coupled pulse combination signal (NOR) at 29.4ns OUTA glitch noise occurred where the restored clock toggled abnormally fast due to the occurrence of ) twice in a single transition. Since the glitch noise occurred a total of two times, the delay value of the pulse generator's delay line was adjusted twice, and afterwards, it was confirmed that the clock was restored normally.

[0092] Figure 12 is an eye diagram of the final output when the clock recovery correction function is not enabled and when it is enabled, with 3 Gsps data as input.

[0093] Referring to FIG. 12, when the correction function of the clock recovery corrector (424) is not activated (wo / cal), an inappropriate delay time selection of the clock recovery circuit (420) causes failure in clock recovery and the distorted clock distorts the entire data.

[0094] On the other hand, when the correction function of the clock recovery corrector (424) is activated (w / cal), the clock corresponding to 3Gsps, 1.5GHz, is restored normally, and accordingly, it was confirmed that it is classified normally into 1.5Gsps EDATA (Even Data) and ODATA (Odd Data).

[0095] Although the technical concept of the present invention has been described above together with the accompanying drawings, this is merely an illustrative explanation of preferred embodiments of the present invention and is not intended to limit the invention. Furthermore, it is evident that any person skilled in the art to which the present invention pertains can make various modifications and imitations within the scope of the technical concept of the present invention without departing from its scope.

[0096] The present invention relates to a clock recovery circuit, and more specifically, to a clock recovery circuit capable of normalizing the input data recovery process by controlling the width of the pulse signal used for the recovery of input data when it is determined that a malfunction has occurred due to glitch noise while recovering a clock signal from input data using a pulse signal generated by a pulse generator constituting the clock recovery circuit.

Claims

1. A sensor unit that monitors the temperature, voltage, and current across a switch constituting a power semiconductor SoC, respectively; A switch control signal detector that receives an externally applied operation control signal; An OTP register comprising a first register portion used when manufacturing the power semiconductor SoC and a second register portion used when applying the power semiconductor SoC to a blockchain; and A control logic circuit that generates a gate signal for controlling the opening and closing of the switch in response to the above operation control signal, using the result of correcting the temperature, voltage, and current values ​​(hereinafter referred to as monitored values) monitored by the sensor unit and the correction value stored in the first register, and comparing the result with a pre-stored circuit protection condition; Power semiconductor SoC including 2. In Paragraph 1, It further includes a serial interface that receives a monitor control signal for monitoring the status of power and load from an MCU outside the power semiconductor SoC and transmits it to the control logic circuit. The above control logic circuit is a power semiconductor SoC that operates in response to the above operation control signal and the above monitor control signal.

3. In Paragraph 1, It further includes an ADC that converts an analog signal into a digital signal, The above control logic circuit converts the monitored value in analog form received from the sensor unit into a monitored value in digital form using the ADC, and applies a correction value stored in the first register to the converted value to correct it.

4. In Paragraph 3, The above first register unit includes an index register and a serial number register, and The index register stores a correction value including a correction temperature, a correction voltage, and a correction current used to correct a monitored value received from the sensor unit, and A power semiconductor SoC that stores a unique serial number assigned at the time of shipment in the above serial number register.

5. In paragraph 4, the serial number register is, Power semiconductor SoC capable of storing 34 bits.

6. In paragraph 3, the second register part is, A power semiconductor SoC including an LEDGER register that stores a key value collected through a security element designated by a power user for self-consumption purposes.

7. In paragraph 6, the above LEDGER register is, Power semiconductor SoC capable of storing 32 bytes.

8. In paragraph 1, the voltage level of the operation control signal is, A power semiconductor SoC having a voltage of 5V or higher when operating the above switch and 2.5V or lower when not operating the above switch.

9. In paragraph 1, the switch is, A power semiconductor SoC that switches a first voltage source connected to one terminal and a load connected to another terminal in response to the above gate signal.

10. In paragraph 1, the circuit protection condition is, A power semiconductor SoC including criteria for overheating, overvoltage, and overcurrent of the above switch.

11. A post-manufacturing test step in which a power semiconductor SoC is manufactured and, prior to shipment, a test is performed to store a correction temperature / voltage / current value in an index register, and a correction value is generated by applying the correction temperature / voltage / current value to the temperature, voltage, and current of a switch included in the power semiconductor SoC received from a sensor unit; A step of assigning a serial number to the power semiconductor SoC and storing the serial number in a serial number register in order to apply the power semiconductor SoC, which has undergone testing after manufacturing, to a blockchain; and The step of the power semiconductor SoC assigned a serial number storing a key value corresponding to a password in an LEDGER register at the time of generation of a token combined with the user's independent asset; Method of operating a power semiconductor SoC including

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