Ga2o3 vertical trench mosfet with MG-doped current blocking layer

Abstract

A vertical Ga₂O₃ metal-oxide-semiconductor field-effect transistor (MOSFET) is disclosed that includes a gallium oxide substrate, an undoped drift layer positioned on the substrate, and a magnesium-doped gallium oxide current blocking layer arranged on the drift layer. A source layer is positioned on the current blocking layer, and a trench extends through the source layer, the current blocking layer, and at least partially into the drift layer. A gate dielectric and gate contact are located within the trench. The device may include a source contact electrically connected to the source layer and a drain contact electrically connected to the substrate. Methods for forming the device include epitaxial growth and metal-organic chemical vapor deposition, with magnesium doping performed in-situ. The structure enables high-voltage operation with low leakage and improved breakdown characteristics for power electronics applications.

Description

GA2O3 VERTICAL TRENCH MOSFET WITH MG-DOPED CURRENT BLOCKING LAYERCross-Reference to Related Applications

[0001] This application claims priority to U. S. Provisional Patent Application No.63 / 717,887, filed on November 7, 2024, now pending, the entire contents of which are incorporated herein by reference.Statement Regarding Federally Sponsored Research

[0002] This invention was made with government support under grant numbers 2231026 awarded by National Science Foundation, DE-AR0001879 awarded by Department of Energy. The government has certain rights in the invention.Field of the Disclosure

[0003] The present disclosure relates generally to semiconductor devices and methods of their fabrication. More specifically, the disclosure pertains to vertical metal-oxide-semiconductor field-effect transistors (MOSFETs) utilizing gallium oxide and magnesium-doped current blocking layers, as well as processes for forming such devices.Background of the Disclosure

[0004] The market for energy efficient power devices has significantly increased in recent years and is predicted to reach $20 billion in the future. Current technologies using silicon-based devices are limited by the intrinsic materials properties. Wide-bandgap semiconductor materials have generated enormous attention in the field of power electronics due to their superior electron transport properties, higher operational power densities enabled by a larger bandgap, and higher temperature operation. These qualities help to reduce the size, weight, and cost of power devices and help to improve the energy efficiencies. Gallium oxide (Ga₂O₃) (Bandgap Eg= 4.9 eV) is an attractive wide bandgap semiconductor that has recently been investigated as a potential material for power conversion devices. Most of the previous Ga₂O₃ devices that have been demonstrated are configured as lateral devices. However, for grid applications, there is a need to develop power devices wi th high voltages which are configured as vertical gallium oxide devices. The lack of shallow acceptors (p-doping) in gallium oxide is amajor challenge for realizing vertical devices which require a robust current blocking layer (CBL).Brief Summary of the Disclosure

[0005] The present disclosure describes the fabrication and performance analysis of an enhancement-mode (E-mode) vertical β-Ga₂O₃ (010) trench MOSFET featuring a Mg-doped current blocking layer (CBL) for high-power applications. Utilizing metal-organic chemical vapor deposition (MOCVD), we achieved precise Mg doping of 1.3x1019cm-3within the CBL to enhance current blocking capability while maintaining a robust threshold voltage of 5 V and a low on-state resistance of 5 mΩ.cm2. The device achieved an on-current of 1.56 kA / cm2at VGS=20 V and VDS=40 V. The fabricated devices demonstrate a peak breakdown voltage of 101 V with an average breakdown field strength of up to 1.68 MV / cm The calculated power device Figure of Merit was 2 MW / cm2

[0006] A vertical trench MOSFET with metal-organic chemical vapor deposition grown Mg-doped current blocking layer includes a n-type gallium oxide substrate, drift layer underneath a Mg doped current blocking layer. On top of the CBL, highly n-doped gallium oxide may be grown and source contacts may be formed. A trench is defined by, for example, reactive ion etching, and a gate dielectric may be deposited by atomic layer deposition. A gate contact may be defined in the trench, and the drain contact may be defined at the bottom of the substrate.Description of the Drawings

[0007] For a fuller understanding of the nature and objects of the disclosure, reference should be made to the following detailed description taken in conjunction with the accompanying drawings.

[0008] Figure 1: A profile view of a current blocking layer (CBL) grown using MOCVD according to an embodiment of the present disclosure, and a chart of Mg concentration vs. depth from surface of the CBL (showing alternating Mg-doped layers and unintentionally doped (UID) layers). MOCVD: Low defect density, uniformity, precision, higher rate. Growth Temperature 880 °C; Pressure: 60 Torr. Mg doping varied with varying Mg precursor flow' rate. Controllable Mg acceptor doping ranging between mid-1017and low 1019cm

[0009] Figure 2: An overview of a U-shaped trench gate MOSFET according to an embodiment of the present disclosure.

[0010] Figure 3: A diagram of a CBL and TCAD simulations of an example design. With the increase of Mg-doping concentration, Vth shifts to the right. With the increase of oxide thickness, Vth also shifts to the right.

[0011] Figure 4: A method of fabricating a trench MOSFET according to another embodiment of the present disclosure.

[0012] Figure 5: A diagram of a trench MOSFET according to an embodiment of the present disclosure and scanning electron microscope images of details of an example transistor.

[0013] Figure 6: Electrical characteristics of example MOSFETs. Normally on mode with 4-6 V threshold voltage.

[0014] Figure 7: Additional electrical characteristics of example MOSFETs and showing a match to predicted performance using simulations. High on-current densities; non-linear IV suggesting ungated area; breakdown voltage 85-100 V; average field 1.4-1.6 MV / cm.

[0015] Figure 8: An example design for a 10 kV device according to another embodiment of the present disclosure.

[0016] Figure 9. (a) Cross-section schematic and process flow of a β-Ga₂O₃ vertical MOSFET with in-situ Mg doped current blocking layer (CBL). (b) Scanning electron microscope (SEM) image of the fabricated devices.

[0017] Figure 10. (a) TLM characteristics measured from circular (r=1 μm) patterns. DC characteristics of the in-situ Mg-doped CBL U-trench MOSFET: (b) ID-VGSat VDS=40 V; (c)V to 16V; 4V step, (d) Three-terminal breakdown characteristics from drain to gate (VDG) for two separate devices.

[0018] Figure 11. (a) Cross-section schematic indicating the leakage areas of the device, (b) Focused Ion Beam (FIB) image of the U-trench gate area showing regions of gate oxide thinning and gate metal discontinuity’.

[0019] Figure 12. (a) ATLAS SILVACO 2D simulation showing electric field distribution at VGS=0 V and VDS=220 V. (b) ID-VGScharacteristics at VDS=40 V of experimental and simulation showing good threshold voltage (Vr) agreement.

[0020] Figure 13. Benchmark of (a) breakdown voltage versus on-resistance for state-of-the-art enhancement-mode β-Ga₂O₃ MOSFETs; (b) threshold voltage versus current density for state-of-the-art enhancement-mode β-Ga₂O₃ MOSFETs.Detailed Description of the Disclosure

[0021] With reference to Figure 9(a), in a first aspect, the present disclosure may be embodied as a vertical MOSFET 10, and in particular a Ga2O3 MOSFET. The vertical MOSFET may be a trench MOSFET (having a trench as described below), such as, for example, a U-trench MOSFET. The MOSFET has a substrate 12, which may be formed of gallium oxide. In some embodiments, the substrate 12 may be Fe-doped gallium oxide or Sn-doped gallium oxide, providing enhanced electrical properties such as improved resistivity or carrier concentration control. For example, in some embodiments, the substrate comprises Sn-doped gallium oxide having a dopant concentration of approximately l*1018cm ' to 5zIO18cm ’, but other concentrations may be used.

[0022] A drift layer 14 is disposed on the substrate 12. The drift layer 14 may be, for example, a layer of gallium oxide which is undoped — i.e., no intentional doping, sometimes referred to as unintentionally doped (UID). The drift layer may have a dopant concentration (such as, for example, an unintentional dopant concentration) of, for example, ~1×1013cm-3to 5×1016cm-3, though other concentrations may be used. In some embodiments, the UID drift layer has a dopant concentration of 2×1016cm-3The drift layer may have a thickness ranging from, for example, 50 nm to 2000 nm, inclusive, or for example, betw een 500 nm and 1000 nm, inclusive. In some embodiments, the drift layer may have a thickness of 600 nm. Other drift layer thicknesses, whether greater than or less than the example ranges, may also be used, provided that the selected thickness achieves acceptable device performance (for example, supporting the target breakdown voltage, on-resistance characteristics, etc.) The drift layer 14 may serve as the primary region for carrier transport when the device is in operation.

[0023] A current blocking layer (CBL) 16 is disposed on the drift layer 14. The current blocking layer 16 is made up of magnesium-doped gallium oxide. In some embodiments, themagnesium dopant concentration in the current blocking layer 16 may be between 1 xlO16cm ' and 5* 1019cm-3, or between 1 * 1017cm-3and 2* 1019cm5. The current blocking layer 16 may be doped in-situ. For example, in some embodiments, the current blocking layer may be grown in-situ by metal-organic chemical vapor deposition (MOCVD). In various non-limiting examples, the MOCVD process may be performed at a temperature between 600 °C and 1000 °C, or between 850 °C and 900 °C, or substantially 880 °C, depending on the desired film quality and dopant incorporation. In some embodiments, the current blocking layer (CBL) may have a thickness selected from the range of between 50 nanometers (nm) to 500 nm, inclusive. This range is provided as an example and is not intended to be limiting. Other thicknesses, whether greater than 500 nm or less than 50 nm, may also be used, provided that the selected thickness achieves acceptable device performance. Acceptable performance may include, for example, sufficient current blocking capability, low leakage in the off-state, and compatibility with the desired breakdown voltage and on-resistance characteristics of the device. In some embodiments, the thickness of the CBL is 200 nm. The current blocking layer may include more than one doped layer alternating with UID lay ers (see Figure 1).

[0024] A source layer 18 is disposed on the current blocking layer 16. The source layer 18 may comprise gallium oxide doped with a Group IV element, such as silicon, to a concentration of at least 1×1020cm-3. In some embodiments, the source layer 18 may be described as n-doped or highly n-doped, providing a low-resistance path for carrier injection.

[0025] A trench 20 is formed in the device, extending through the source layer 18, the current blocking layer 16, and at least partially into the undoped drift layer 14. The trench 20 may be defined by reactive ion etching (RIE), which allows for precise control of the trench geometry and depth. The trench 20 may be U-shaped or have other suitable geometries, depending on the desired device characteristics.

[0026] A gate dielectric 22 may be disposed within the trench 20 (e.g, at least partially within the trench, etc.) The gate dielectric 22 may comprise silicon dioxide (SiO2) or other appropriate oxide. The gate dielectric may be formed by, for example, atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), or other suitable techniques. A gate contact 24 may be disposed within the trench 20 (e.g., at least partially within the trench, etc.) The gate contact may be formed by depositing a metal such as titanium, gold, or nickel, orcombinations (e.g., stacks of different metals, alloys, etc.), and patterning the metal to define the gate electrode.

[0027] The device may include a source contact 26 electrically coupled to the source layer 18, and a drain contact 28 electrically coupled to the substrate 12. For example, the source contact 26 may be formed on a top surface of the source layer 18. The drain contact 28 may be formed on a bottom surface of the substrate 12. In some embodiments, the source and drain contacts 26, 28 may be formed using ohmic metallization techniques, such as electron beam evaporation or sputtering, followed by rapid thermal annealing to ensure low contact resistance. The source contact and drain contact may be made from metals or metal alloys, such as, for example, titanium, gold, or nickel.

[0028] In some embodiments, the device may further include one or more transition layers 30 disposed between layers such as the CBL 16 and the source layer 18. The transition layer(s) 30 may each have a thickness of between 50 nm and 1000 nm, or between 100 nm and 200 nm, and may be formed of gallium oxide, such as, for example. UID gallium oxide (e.g.. Mg tail).

[0029] The layer thickness ranges are provided as examples and are not intended to be limiting. Other thicknesses, whether greater or smaller than the ranges described, may also be used, provided that the selected thickness achieves acceptable device performance. Acceptable performance may include, for example, sufficient current blocking capability, low leakage in the off-state, compatibility with the desired breakdown voltage, and maintenance of low on-resistance (these are example criteria and other criteria may be used in addition to or in place of these criteria). In some embodiments, transition layers may also be included, and such transition layers may have a thickness ranging from about 50 nm to about 2000 nm, or other thicknesses as appropriate, for example, to improve lattice matching and reduce defects. The choice of thickness for each layer may depend on the intended application, voltage rating, thermal management requirements, and / or other desired characteristics of the vertical Ga2O3 MOSFET.

[0030] Similarly, the dopant concentration ranges are provided as examples and are not intended to be limiting. Other concentrations, whether greater or smaller than the ranges described, may also be used, provided that the selected concentration achieves acceptable device performance. Acceptable performance may include, for example, sufficient conductivity in the source region for low contact resistance, adequate blocking capability' in the current blockinglayer, and / or compatibility with the desired breakdown voltage and on-resistance of the vertical Ga₂O₃ MOSFET (these are example criteria and other criteria may be used in addition to or in place of these criteria). The choice of dopant concentration for each layer may depend on the intended application, voltage rating, thermal management requirements, and / or other desired characteristics.

[0031] With reference to Figure 14, in another aspect, the present disclosure may be embodied as a method 100 for fabricating (manufacturing) a vertical trench MOSFET. The method 100 includes providing 103 (e.g., forming, obtaining, etc.) a gallium oxide substrate. In some embodiments, the substrate may be Fe-doped or Sn-doped gallium oxide. A gallium oxide drift layer is formed 106 on the substrate. The drift layer may be grown 106 by epitaxial deposition, such as MOCVD, molecular beam epitaxy (MBE), or other suitable methods. The thickness of the UID drift layer may be selected based on the desired breakdown voltage and on-resistance of the device.

[0032] A magnesium-doped gallium oxide current blocking layer is formed 109 on the drift layer. The current blocking layer may be formed 109 by growing the layer in-situ by MOCVD, using a magnesium precursor such as, for example, bis(cyclopentadienyl) magnesium. The doping concentration may be controlled by adjusting the precursor flow rate, growth temperature, and / or pressure. In some embodiments, the current blocking layer may be grown in-situ directly on the UID drift layer. The current blocking layer may be grown in several sublayers, such as layers of Mg-doped gallium oxide alternating with UID gallium oxide (see, for example, Figure 1).

[0033] A source layer is formed 112 on the magnesium-doped current blocking layer. The source layer may be formed 112 by depositing or growing gallium oxide doped with a Group IV element, such as silicon, to a desired concentration.

[0034] A trench is defined 115, extending through the source layer, the magnesium-doped current blocking layer, and at least partially into the drift layer. The trench may be defined using reactive ion etching, which provides precise control over the trench profile and depth. A gate dielectric is formed 118 within the trench (at least within the trench). The gate dielectric may include silicon dioxide, and may be deposited by ALD, PECVD. or other suitable techniques. A gate contact is formed 121 within the trench (at least within the trench). For example, the contact may be formed by depositing and patterning a metal layer.

[0035] Additional steps may include forming 124 a source contact electrically coupled to the source layer, and forming 127 a drain contact electrically coupled to the substrate. The contacts 124, 127 may be formed by metallization and annealing processes to ensure low contact resistance.

[0036] Characteristics — such as, for example, dopant concentration, thickness, etc. — of the various layers formed during fabrication may be the same as described above with respect to the MOSFET device.

[0037] In various embodiments, the present disclosure provides a trench MOSFET incorporating an in-situ Mg-doped current blocking layer achieved without using ultra-high temperature processes or costly sub-micron fin structures.

[0038] The market for energy efficient power devices has significantly increased in recent years and is predicted to reach $20 billion in the future. Current technologies using silicon-based devices are limited by the intrinsic materials properties. Wide-bandgap semiconductor materials have generated enormous attention in the field of power electronics due to their superior electron transport properties, higher operational power densities enabled by a larger bandgap, and higher temperature operation. These qualities help to reduce the size, weight, and cost of power devices and help to improve the energy efficiencies. Gallium oxide (Ga₂O₃) (Bandgap Eg= 4.9 eV) is an attractive wide bandgap semiconductor that has recently been investigated as a potential material for power conversion devices. Most of the previous Ga2O3 devices that have been demonstrated are configured as lateral devices. However, for grid applications, there is need to develop power devices with high voltages which are configured as vertical gallium oxide devices. The lack of shallow acceptors (p-doping) in gallium oxide is a major challenge for realizing vertical devices which require a robust current blocking layer (CBL).

[0039] The present disclosure provides a vertical trench MOSFET in gallium oxide using an in-situ Mg-doped current blocking layer and related methods and devices.

[0040] Gallium oxide semiconductors have been recognized as a next-generation power semiconductor technology for high power applications. Vertical MOSFETs can be advantageous to avoid surface-related failures and to obtain low specific on -resistances. Previous MOSFET designs use narrow FINs to obtain vertical configurations. These designs have high fabricationcosts due to the sub-micron lithography needed to fabricate the fins. The complexity of the process also leads to lower yields. Other previous trench MOSFET designs use ion-implantation techniques to fabricate current blocking layers. However, the ultra-high temperature annealing process for implanted current blocking layers does not provide full control over the thickness and profile of the implanted layer thus limiting the device performance.

[0041] In some embodiments, the present disclosure provides a trench MOSFET device incorporating a doped current blocking layer (such as in-situ doped current blocking layer ) that does not require the use of ultra-high temperature processing. The design, growth, and fabrication of gallium oxide trench MOSFET incorporating Mg-doped current blocking layer is disclosed here.

[0042] Figure 3 shows the design of the trench MOSFET and technology computer-aided design (TCAD) simulations. The simulation gives 5*1017cm-3as an advantageous design which corresponds to 1.5×1019Mg taking into the effective doping of Mg. The structure shown at the top of Figure 3 may be grown by MOCVD. Figure 4 shows an example fabrication process for manufacturing the MOSFET.

[0043] In another aspect, the present disclosure may be embodied as a semiconductor device. The semiconductor device has a first gallium oxide layer and a first doped gallium oxide layer disposed on the first gallium oxide layer. The first doped gallium oxide layer comprises a magnesium dopant. The magnesium dopant has a concentration (e.g., a dopant concentration) of between l*1016cm-3and 5*1019cm-3, or l*1018cm ' and 2*1019cm-3. In a particular example (see, e.g., Figure 4), the first doped gallium oxide layer has a concentration of ~1.3×1019cm-3For example, the first gallium oxide layer may be, for example, an unintentionally doped (UID) drift layer having a concentration of ~2xl016cm-3. The semiconductor device may have a second gallium oxide layer deposited on the first doped gallium oxide layer. The second gallium oxide layer may be considered, for example, a transition UID layer (e.g., a Mg tail). The semiconductor device may further include a n’ layer, such as, for example, a Si-doped n+layer, deposited on the second gallium oxide layer. For example, the Si-doped n+ layer may have a concentration of greater than IxlO20cm-3. The semiconductor device may have one or more additional doped gallium oxide layers (e.g., a second doped gallium oxide layer, a third doped gallium oxide layer, etc.) Such doped gallium oxide layers may be arranged with alternating UID layers (see, e.g.. Figure 1). The semiconductor device may be fabricated using metal-organicchemical vapor deposition (MOCVD). The MOCVD process is performed at a temperature between 600 °C and 1000 °C, or between 850 °C and 900 °C, or substantially 880 °C.

[0044] The first gallium oxide layer and the first doped gallium oxide layer may each have a thickness of between 50 nm and 2000 nm, or between 200 nm and 300 nm. For example, the first gallium oxide layer and / or the first doped gallium oxide layer may have a thickness of 240 nm or 300 nm.

[0045] In some embodiments, the semiconductor device has a substrate, and the first gallium oxide layer is disposed on the substrate. The substrate may be, for example, Fe-doped gallium oxide, Sn-doped gallium oxide, or other suitable substrates.

[0046] In another aspect, the present disclosure may be embodied as a vertical trench MOSFET having a Mg-doped gallium oxide current blocking layer (CBL). The CBL may be fabricated using any of the methods disclosed herein.

[0047] Discussion

[0048] The following discussion is provided to facilitate understanding of the disclosed subject matter. However, such discussion is not intended to limit the scope of the disclosure in any way.

[0049] I. Introduction

[0050] β-Ga₂O₃, with a bandgap of 4.8 eV and a critical breakdown field of 8 MV / cm, has emerged as a promising candidate for high voltage high-power applications, supported by the development of high-quality, low-defect single crystals. While β-Ga₂O₃ MOSFETs have shown great promise, current devices still underperform relative to theoretical limits. Structurally, β-Ga₂O₃ MOSFETs can be lateral or vertical, with vertical designs favored for high-power use due to their superior volume utilization and scalable break down voltage with drift layer thickness. However, β-Ga₂O₃ poses significant challenges for vertical devices due to difficulty in p-type doping, limiting design flexibility. Vertical β-Ga₂O₃ MOSFET architectures include fin-type transistors (FinFETs), vertical diffused barrier FETs (VDBFETs), and current aperture-type FETs (CAVETs), each with unique performance attributes and trade-offs. For instance, FinFETs achieve high breakdown voltages but require sub-micron sized fins which can reduce device yield.

[0051] The U-shaped gate trench MOSFETs (UMOSFETs), successful in other materials for their ability to achieve higher packing density and lower input capacitance, have not been heavily investigated compared to lateral -GaiG MOSFETs. Another advantage compared to FinFET devices is less stringent lithographic feature sizes which could potentially reduce the cost. A major challenge in P-G 1G gate trench MOSFET development is the lack of effective p-type doping due to self-trapped holes and the high ionization energy' of dopants. While N-implanted current blocking layer (CBL) devices have been demonstrated, the high temperature annealing and precise doping profile control provide challenges. Whereas Mg is potentially the preferred acceptor like dopant for CBL given its low formation and activation energy. However, high diffusivity of Mg during necessary high-temperature annealing complicates the CBL profile and device design. CBL layers defined with in-situ epitaxy (MBE or MOCVD) could enable effective CBLs for high-performance vertical power devices overcoming the challenges seen in ion-implanted CBL. Recent studies have shown that Mg acceptors in Ga₂O₃ exhibit semiinsulating behavior by capturing electrons at the substrate / epilayer interface, which helps lower the conductivity' of n-type Ga₂O₃ in in-situ Mg-doped GaiO? thin films. Moreover, most vertical MOSFETs are demonstrated in HVPE grown (001) gallium oxide. The anisotropy of gallium oxide crystal may offer higher breakdown voltage in alternate orientations.

[0052] In this section, we describe the successful fabrication and characterization of nonlimiting example embodiments of vertical -GaiGi U-trench MOSFETs utilizing an in-situ Mg-doped CBL layer grown by metal-organic chemical vapor deposition (MOCVD) on (010) substrates. The devices show- robust enhancement-mode operation, high on-current, low on-resistances, and high breakdown field strengths.

[0053] II. Fabrication Process

[0054] A cross-section schematic of the fabricated U-trench MOSFET with in-situ Mg doped CBL is shown in Figure 9(a). Epitaxial layers were grown via MOCVD on a commercially available Sn-doped (010) Ga2O? substrate. Mg doping was introduced via bis(cyclopentadienyl) magnesium (Cp2Mg). The Mg tail layer acted as a UID Ga^O? buffer to limit Mg diffusion into the n++source layer which can increase the contact resistance. The Mg flow rate was set at 106.6 nmol / min, targeting a doping concentration of 1.3xl019cm ’’, as confirmed by prior SIMS results. The top layer was doped with silicon (1* 102° cm-3).

[0055] The example process flow is shown in Figure 9(a). Fabrication started with a BCh / Ar reactive-ion etching (RIE) on the back side to remove 1 «m Ga / O? layer. A Ti / Au (75 / 150) ohmic metal stack was deposited on the backside via electron beam evaporation followed by rapid thermal annealing (RTA) in an N2 ambient at 470 °C for 1 minute. Next, top Ti / Au / Ni (75 / 150 / 15) ohmic source contacts were patterned using e-beam lithography (EBL). The devices were then mesa-isolated using the BCh based RIE process. The next step involved etching a U-shaped trench using RIE. Both trench and mesa isolation depths reached approximately 650 nm, extending into the UID drift layer (Figure 9(a)). A 50 nm SiCh layer was deposited by plasma-enhanced chemical vapor deposition (PECVD) as the gate dielectric, followed by Ti / Au gate metal deposition using e-beam evaporation. Figure 9(b) shows the top view of the scanning electron microscope (SEM) image of the fabricated trench MOSFET.

[0056] III. Results and Discussions

[0057] Circular transmission line model (TLM) measurements gave a transfer length (L / ) 1.02 «m. contact resistance (Rc) 0.21 Q.mm, sheet resistance (Rs / / ) 103 Q.sq. and contact resistivity (pC) L08xl0"6Q.cm2(Figure 10(a)). The low resistances showthe effectiveness of the in-situ Mg doping without degrading the source resistance. The device features a rectangular gate trench measuring 1 / / m x215 «m and a 0.6 «m thick drift layer. Accounting for a 45-degree lateral current spreading in the drift layer, the active area used for normalizing current density and specific ON-resistance is calculated as (1+0.6) x (215+0.6) urn2or 344.96 wm2This normalization allows for a more accurate comparison of the device’s performance metrics. Figure 10(b) illustrates the DC transfer characteristics measured at VD=40 V indicating a normally-off operation with a threshold voltage of 5 V. The experiment successfully demonstrated the operation of a transistor, indicating that it is possible to form a channel at high VGSfor electron conduction in the CBL created using in-situ MOCVD. A noticeable modulation of IDSwas achieved with alow to moderate on / off ratio of 7.3 xlO2, suggesting the formation of an electron conduction path. The off-state current is likely limited by peripheral leakage in the device, as indicated by measurements from process control monitor samples. We observe that the drain current (ID) increases exponentially with Vcuntil about 10 V, after which it begins to saturate. At VGS=20 V, the drain current (ID) reaches approximately 1.56 kA / cm2(Figure 10(b)).

[0058] Figure 10(c) illustrates the DC output characteristics of the U-trench MOSFET. The drain current (ID) is plotted against the drain-source voltage (VDS) for various gate-sourcevoltages (VGS), ranging from 0 V to l6 V in 4 V increments. The device exhibited a maximum on-state current of 1.3 kA / cm2and an on-state resistance of 5 m.crn2at VGS=16 V. The nonlinear current characteristics found at low VDScan be explained by channel -related variables, including defect-induced electron barriers, electron depletion at the etched surface, and potential redistribution caused by etching morphology. Furthermore, it could be associated with the stepped sidewall, which leads to a lack of a strong transverse electric field to propel electrons at low VDS. Use of wet chemical etching to remove etch damage or use of plasma-free etching can mitigate this.

[0059] Three terminal off-state breakdown characteristics were measured at room temperature using a KeysightN1268A UHV system. The sample was fully merged in Fluorinert FC-40 solution to avoid air arcing which causes the devices to bum out prematurely. The measured breakdow n characteristics of two devices are presented in Figure 10(d).

[0060] The devices demonstrated a drain-to-gate breakdown voltage betw een 83 and 101 V, marking the first successful realization of a vertical / >-Ga2O- MOSFET with in-situ Mg doping. The highest average breakdown field strength is found to be 1.68 MV. cm1using the drift layer thickness is 600 nm, which is either higher or very close to previously reported U-trench MOSFETs. This value is also comparable to the recent demonstration of lateral P-GasOi MOSFET with a breakdown voltage of over 8.5 kV. The highest calculated power device Figure of Merit is 2 \1W.cm2

[0061] Figure 11 displays the focused ion beam (FIB) image of the edge of the U-trench gate area. Our analysis focused on the gate metal contact within the U trench, the side walls, and the gate wing overlap. The images reveal a highly uniform metal deposition and gate oxide (SiO2) in the U-trench area, as illustrated in Figure 11(b). How ever, thinning of SiO2 near the trench edge is observed. This SiO2 thinning may compromise the insulation between the gate metal and the highly n1 1doped layer, potentially causing unexpected leakage. Additionally, discontinuity / breaking in the gate metal, particularly within the titanium (Ti) layer is observed. The gaps in Ti may lead to un-gated regions which could be attributed to the observed nonlinearity in the IQ-^DS characteristics. Using a sputtered gate metal process could eliminate this issue. While SiCh thinning is likely a contributor to the observed leakage, other factors such as non-uniform gate trench and device isolation etching could also play a role. As seen in Figure 9(b), the gate pad overlaps only slightly with the isolated device which could furthercontribute to the observed leakage current. These fabrication-related challenges likely contribute to the below- average on-off ratio and non-linear current characteristics observed at low VDS.

[0062] A simulation using ATLAS SILVACO for the experimental device design at VGS=0 V reveals that the electric field peak reaches the theoretical critical field strength of SiCh (15 MV / cm) at VDS=220 V, which could result in device breakdown (Figure 12(a)). The ID-VGScharacteristics at VDS=40 V (Figure 12(b)) show close agreement between experimental and simulated threshold voltage (Vr). These results indicate that addressing the previously identified leakage paths could improve the breakdown voltage by up to 2.5 times.

[0063] Figure 13(a) presents the breakdown voltage (Vbr) and on-resistance (Row) benchmarks for recent state-of-the-art CBL-type Ga₂O₃ vertical MOSFETs. While our device’s breakdown voltage is slightly lower, it achieves an exceptionally low on-resistance. Figure 13(b) compares the current density and threshold voltage, demonstrating that the present device surpasses many state-of-the-art devices, achieving a higher current density while maintaining a competitive threshold voltage.

[0064] IV. Conclusion

[0065] In summan-, this work demonstrates the successful fabrication and characterization of an enhancement-mode ^-GazOj (010) U-trench MOSFET featuring an in-situ Mg-doped current blocking layer (CBL) grown using MOCVD. The device achieved positive threshold voltages (5 V). showcasing strong gate control, and achieving high cunent densities (1.56 kA / cm2). They exhibited stable blocking voltages (100 V) with an average field strength of 1.68 MV / cm. Additional optimization of CBL thickness, Mg doping, and drift layer thickness may be beneficial to improve the breakdown characteristics for high-power applications.

[0066] Although the present disclosure has been described with respect to one or more particular embodiments, it w ill be understood that other embodiments of the present disclosure may be made without departing from the spirit and scope of the present disclosure.

Claims

What is claimed is:

1. A vertical Ga2O? metal-oxide-semiconductor field-effect transistor (MOSFET) comprising:a gallium oxide substrate;a drift layer on the substrate;a current blocking layer comprising magnesium-doped gallium oxide on the drift layer; a source layer on the current blocking layer;a trench extending through the source layer, the current blocking layer, and at least partially into the drift layera gate dielectric and gate contact formed within the trench;2. The vertical Ga2O3 MOSFET of claim 1, wherein the current blocking layer is grown in-situ by metal-organic chemical vapor deposition (MOCVD).

3. The vertical Ga20s MOSFET of claim 2, wherein the MOCVD process is performed at a temperature between 600 °C and 1000 °C, or between 850 °C and 900 °C, or substantially 880 °C.

4. The vertical Ga₂O₃ MOSFET of claim 1, wherein the current blocking layer is doped in-situ.

5. The vertical Ga2O? MOSFET of claim 1, where the drift layer has no intentional doping (a UID drift layer).

6. The vertical Ga₂O₃ MOSFET of claim 1, wherein the source layer comprises highly n-doped gallium oxide, for example, having a doping concentration greater than 1 x IO20cm5.

7. The vertical Ga₂O₃ MOSFET of claim 1, wherein the trench is defined by reactive ion etching; 8. The vertical Ga2O? MOSFET of claim 1, wherein the current blocking layer has a magnesium dopant concentration of between 1 x l()l6cm-3and 5xl019cm5. or IxlO18cm5and 2*1019cm-3.

9. The vertical Ga₂O₃ MOSFET of claim 1, wherein the substrate is Fe-doped gallium oxide or Sn-doped gallium oxide.

10. The vertical Ga₂O₃ MOSFET of claim 1, further comprising a gallium oxide transition layer between the current blocking layer and the source layer, the transition layer having a thickness of between 50 nm and 2000 nm, or between 200 nm and 300 nm.

11. The vertical Ga20s MOSFET of claim 1, further comprising a source contact electrically coupled to the source layer.

12. The vertical Ga₂O₃ MOSFET of claim 1, further comprising a drain contact electrically coupled to the gallium oxide substrate.

13. A method of fabricating a vertical Ga2O? MOSFET. comprising:forming a gallium oxide substrate;forming a gallium oxide drift layer on the substrate;forming a magnesium-doped gallium oxide current blocking layer on the undoped drift layer; forming a source layer on the magnesium-doped current blocking layer;defining a trench extending through the source layer, the magnesium-doped current blocking layer, and at least partially into the undoped drift layer, wherein the trench is defined using reactive ion etching;forming a gate dielectric within the trench; andforming a gate contact within the trench.

14. The method of claim 13, wherein forming the magnesium-doped gallium oxide current blocking layer comprises growing the magnesium-doped gallium oxide current blocking layer by metal-organic chemical vapor deposition (MOCVD).

15. The method of claim 14, wherein the magnesium-doped gallium oxide current blocking layer is grown in-situ on the drift layer.

16. The method of claim 14, wherein the MOCVD process is performed at a temperature between 600 °C and 1000 °C, or between 850 °C and 900 °C, or substantially 880 °C.

17. The method of claim 13, wherein the current blocking layer has a magnesium dopant concentration of between 1 x 1016cm-3and 5xl019cm5, or 1 x 1018cm-3and 2x 1019cm \ 18. The method of claim 13, wherein forming the drift layer comprises growing the drift layer by epitaxial deposition.

19. The method of claim 13, where the drift layer has no intentional doping (a UID drift layer).

20. The method of claim 13, wherein the source layer comprises highly n-doped gallium oxide, for example, having a doping concentration greater than 1 x IO20cm-3.

21. The method of claim 13, wherein the magnesium-doped gallium oxide current blocking layer is grown by metal-organic chemical vapor deposition (MOCVD) at a temperature between 850 °C and 900 °C, and at a pressure of 60 Torr.

22. The method of claim 13, wherein the magnesium precursor used for doping is bis(cyclopentadienyl) magnesium (CpaMg), and the precursor flow rate is set to achieve a magnesium dopant concentration of approximately 1.3*1019cm ’.

23. The method of claim 13, wherein the magnesium-doped current blocking layer comprises alternating sub-layers of magnesium-doped gallium oxide and unintentionally doped (UID) gallium oxide.

24. The method of claim 13, wherein the trench depth is approximately 650 nm, extending into the UID drift layer.

25. The method of claim 13, further comprising depositing a gate dielectric comprising silicon dioxide (SiCh) by plasma-enhanced chemical vapor deposition (PECVD) to a thickness of 50 nm within the trench.

26. The method of claim 13, further comprising forming source and drain contacts by depositing a Ti / Au metal stack via electron beam evaporation, followed by rapid thermal annealing (RTA) in an N2 ambient at 470 °C for 1 minute.

27. The method of claim 13, wherein the source layer is formed by doping gallium oxide with silicon to a concentration greater than lz1020cm ’28. The method of claim 13, wherein the magnesium-doped current blocking layer has a thickness between 50 nm and 500 nm, inclusive.

29. The method of claim 13, further comprising forming a transition layer of unintentionally doped gallium oxide between the current blocking layer and the source layer, the transition layer having a thickness between 100 nm and 200 nm.

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