Semiconductor device and manufacturing method therefor
By alternating the first lead and pseudo-line in the 3D DRAM structure, combined with the staggered second lead structure, the parasitic capacitance problem is solved, the device speed is improved and the power consumption is reduced.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- RUILI INTEGRATED CIRCUIT CO LTD
- Filing Date
- 2025-03-05
- Publication Date
- 2026-05-21
AI Technical Summary
In existing 3D DRAM structures, the parasitic capacitance between word lines or bit lines has not been effectively resolved, affecting device performance.
By employing an alternating first lead-out line and first pseudo-line structure, and through a staggered arrangement of second lead-out lines, the spacing between the first lead-out lines between layers is reduced, thereby lowering parasitic capacitance.
It effectively reduces parasitic capacitance, improves the performance of semiconductor devices, and meets the requirements of high speed and low power consumption.
Smart Images
Figure CN2025080721_21052026_PF_FP_ABST
Abstract
Description
Semiconductor devices and their fabrication methods
[0001] This disclosure is based on and claims priority to Chinese Patent Application No. 202411622327.2, filed on November 13, 2024, entitled “Semiconductor Device and Method for Fabrication Thereof”, the entire contents of which are incorporated herein by reference. Technical Field
[0002] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor device and its fabrication method. Background Technology
[0003] The development of dynamic memory (DRAM) pursues performance indicators such as high speed, high integration density, and low power consumption. As the size of semiconductor device structures shrinks, the technological barriers encountered by existing structures are becoming increasingly apparent. Therefore, developing more novel structures based on existing structures is a powerful means to break through existing technological barriers.
[0004] The emergence of three-dimensional dynamic random access memory (3D DRAM), especially 3D DRAM that includes multilayer horizontal cell (MHC), typically comprising multiple transistors stacked on a substrate, has met the above requirements.
[0005] In the current 3D DRAM architecture, reducing the parasitic capacitance between word lines or bit lines is an urgent problem to be solved. Summary of the Invention
[0006] According to a first aspect of the present disclosure, a semiconductor device is provided, comprising:
[0007] Substrate; common electrode structure, the common electrode structure is stacked on the substrate along a first direction, the first direction intersecting the substrate;
[0008] A stacked array structure, the stacked array structure includes a first electrode structure, the first electrode structure is stacked on a substrate along a first direction and is electrically connected to a common electrode structure disposed on the same layer;
[0009] The first lead structure is stacked along a first direction and connected to a common electrode structure disposed on the same layer. The first lead structure includes a first lead wire and a first pseudo wire disposed opposite to each other. In the first direction, the first lead wire and the first pseudo wire of different first lead structures are alternately disposed.
[0010] The second lead-out structure includes a second contact pad and a second contact plug. The second contact pad is disposed in the same layer as the corresponding first lead-out line and is electrically connected to the corresponding common electrode structure through the corresponding first lead-out line. The second contact plug is disposed on the second contact pad and is staggered from each other in a first direction.
[0011] In some embodiments, the first lead-out structure extends along a third direction, and the second lead-out structures are staggered along the third direction, which is parallel to the substrate.
[0012] In some embodiments, a first lead-out structure extends along a third direction, which is parallel to the substrate; a second lead-out structure is provided in a second direction, which overlaps with the projection portion of the first direction onto the substrate, and the second direction is parallel to the substrate and intersects with the third direction.
[0013] In some embodiments, the first leads connected to the second lead structure that overlaps with the projection portion of the substrate along the first direction are spaced at least one layer apart.
[0014] In some embodiments, the first electrode structure includes a bit line structure or a word line structure.
[0015] In some embodiments, both ends of the first lead-out structure are connected to a common electrode structure.
[0016] In some embodiments, the second contact pad is integrally formed with the first lead wire.
[0017] In some embodiments, the second contact pad and the second contact plug are integrally formed.
[0018] In some embodiments, the first pseudoline comprises a polysilicon and silicon nitride stack.
[0019] According to a second aspect of the present disclosure, a method for fabricating a semiconductor device is provided, comprising:
[0020] A substrate is provided on which a multilayer structure is formed;
[0021] A common electrode structure is formed in the stacked structure;
[0022] A stacked array structure is formed in the stacked structure, the stacked array structure including a first electrode structure;
[0023] A first lead-out structure is formed in the stacked structure. The first lead-out structure includes a first lead-out line and a first pseudo-line disposed opposite to each other. In a first direction, the first lead-out lines and the first pseudo-lines of different first lead-out structures are alternately disposed, and the first direction intersects with the substrate.
[0024] A second lead-out structure is formed in the stacked structure, the second lead-out structure including a second contact pad and a second contact plug;
[0025] The common electrode structure is electrically connected to the first electrode structure formed in the same layer, and the second lead structure is electrically connected to the common electrode structure through the first lead wire; the second contact plug is formed on the second contact pad, and in the first direction, the second contact plugs are staggered from each other.
[0026] In some embodiments, the first lead wire, the second contact pad, and the second contact plug are formed in the same step.
[0027] In some embodiments, the step of forming the first lead-out structure includes first forming a filler layer, wherein the filler layer occupies the position of the first lead-out structure;
[0028] Form the trench structure corresponding to the second lead-out structure and expose the corresponding filler layer;
[0029] Remove the exposed packing layer;
[0030] The first lead wire, the second contact pad, and the second contact plug are formed; the remaining filler layer forms the first pseudowire.
[0031] In some embodiments, the filler layer is formed by deposition of a polysilicon and silicon nitride stack.
[0032] In some embodiments, forming a stacked structure includes alternating silicon layers and silicon-germanium layers.
[0033] By alternating the arrangement of the first lead and the first pseudo-line, the spacing between the first leads of the layers can be increased, thereby reducing the parasitic capacitance. Attached Figure Description
[0034] Figure 1 is a schematic diagram of a semiconductor device according to an exemplary embodiment;
[0035] Figure 2 is a schematic diagram of a semiconductor device according to an exemplary embodiment;
[0036] Figures 3a, 4a, 5a, and 13a are schematic cross-sectional views along the first lead of a semiconductor device during fabrication according to an exemplary embodiment, showing the D1-D3 cross-section.
[0037] Figures 3b, 4b, 5b, 6b, 7-12, 13b, 14, and 15 are schematic cross-sectional views of a semiconductor device along a second lead structure position during fabrication, according to an exemplary embodiment.
[0038] Figure 6a is a schematic cross-sectional view along D1-D3 of a semiconductor device during fabrication, according to an exemplary embodiment, showing the position between the first lead and the first pseudo-line. Detailed Implementation
[0039] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.
[0040] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.
[0041] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.
[0042] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
[0043] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.
[0044] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.
[0045] According to a first aspect of the embodiments of this disclosure, as shown in Figures 1-2...
[0046] A semiconductor device includes: a substrate 100; a common electrode structure 200, wherein the common electrode structure is stacked on the substrate along a first direction D1, and the first direction intersects the substrate;
[0047] The stacked array structure 20 includes a first electrode structure 300, which is stacked on a substrate along a first direction and electrically connected to a common electrode structure disposed on the same layer.
[0048] The first lead structure 400 is stacked along a first direction and connected to a common electrode structure disposed on the same layer. The first lead structure includes a first lead line 401 and a first pseudo line 402 disposed opposite to each other. In the first direction, the first lead lines and first pseudo lines of different first lead structures are alternately disposed.
[0049] The second lead-out structure 500 includes a second contact pad 501 and a second contact plug 502. The second contact pad is disposed in the same layer as the corresponding first lead-out line and is electrically connected to the corresponding common electrode structure through the corresponding first lead-out line. The second contact plug is disposed on the second contact pad and is staggered from each other in the first direction.
[0050] In some embodiments, the first lead-out structure extends along a third direction D3, and the second lead-out structures are staggered along the third direction, which is parallel to the substrate. Optionally, the second lead-out structures are distributed on both sides of the first lead-out structure along the third direction.
[0051] In some embodiments, a second lead-out structure is provided in the second direction D2, and the projections of the second lead-out structures onto the substrate along the first direction partially overlap, with the second direction being parallel to the substrate and intersecting with the third direction. Optionally, in the second lead-out structures provided along the second direction, the projection of the second lead-out structure closer to the first lead-out structure onto the substrate along the first direction falls into the projection of the second lead-out structure farther from the first lead-out structure onto the substrate along the first direction. Optionally, the first lead-out structure corresponding to the second lead-out structure closer to the first lead-out structure is located on a higher layer than the one farther away, and the second contact pad of the second lead-out structure farther from the first lead-out structure passes through the corresponding first lead-out structure in the lower layer.
[0052] In some embodiments, the first leads connected to the second lead structures that overlap in the projection portion of the substrate along the first direction are spaced at least one layer apart. Optionally, the second lead structures that overlap in the projection portion of the substrate along the first direction are spaced multiple times to connect the corresponding first leads, such as three or five layers.
[0053] In some embodiments, a second lead-out structure is provided on both sides of the first lead-out structure, distributed along a third direction, and includes a second lead-out structure disposed along a second direction.
[0054] In some embodiments, in a first direction, first leads and first pseudo-lines with different first lead-out structures are alternately arranged, as shown in FIG1. In the first direction, the position where the first lead is set in the first layer corresponds to the position where the first pseudo-line is set in the second layer, the position where the first pseudo-line is set in the second layer corresponds to the position where the first lead is set in the third layer, the position where the first lead is set in the third layer corresponds to the position where the first pseudo-line is set in the fourth layer, and so on. The first pseudo-line only fills the position and has no effect on the operation of the semiconductor device. Optionally, the first pseudo-line includes a polysilicon and silicon nitride stack.
[0055] In some embodiments, as shown in FIG2, both ends of the first lead-out structure are connected to a common electrode structure, and the common electrode structure can be connected to multiple stacked array structures.
[0056] In some embodiments, the second contact pad is integrally formed with the first lead wire; optionally, the second contact pad is integrally formed with the second contact plug; optionally, the second contact pad, the second contact plug, and the first lead wire are integrally formed.
[0057] In some embodiments, the first electrode structure is a bit line structure or a word line structure.
[0058] In some embodiments, the stacked array structure includes multiple memory cells, each memory cell including a transistor and a memory node. Optionally, the memory node is selected from one or more of the following: a memory capacitor, a phase-change memory, a magnetoresistive memory, or a ferroelectric memory. The stacked array structure includes multiple layers, each layer having multiple spaced-apart memory cells, with memory cells in different layers corresponding to each other. A transistor includes a first source / drain, a second source / drain, and a gate. The first source / drain is connected to a bit line structure, and the second source / drain is connected to a memory node. Optionally, when the first electrode structure is a bit line structure, the first source / drain of memory cells in the same layer of the stacked array structure is connected to the same bit line structure, and the gates of memory cells in different layers are connected to the same word line structure, or form a word line structure. Optionally, when the first electrode structure is a word line structure, the first source / drain of memory cells in different layers of the stacked array structure is connected to the same bit line structure or forms the same bit line structure, and the gates of memory cells in the same layer are connected to the same word line structure or form the same word line structure.
[0059] In some embodiments, the common electrode structure connects to multiple stacked array structures. Optionally, the stacked array structures are spaced apart along the extension direction of the common electrode structure. Optionally, multiple stacked array structures are provided on both sides of the common electrode structure.
[0060] In some embodiments, the storage node is a storage capacitor. Optionally, the bottom electrode of the storage capacitor is discretely disposed and connected to the second source and drain of the transistor, and the storage capacitors in the same stacked array structure share a top electrode, with a dielectric material disposed between the bottom electrode and the top electrode. The dielectric material of the storage capacitor may be formed from at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, or may include at least one of, for example, hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.
[0061] According to a second aspect of the present disclosure, a method for fabricating a semiconductor device is provided, as shown in FIG2, FIG3a and FIG3b, comprising: providing a substrate, forming a stacked structure on the substrate, and forming a common electrode structure 200 in the stacked structure.
[0062] Optionally, a stacked structure is formed on the substrate, the stacked structure consisting of alternating material layers M1 and M2, where material layers M1 and M2 represent two different selected materials. The stacked structure can be formed from alternating deposited silicon nitride and silicon oxide, or from single-crystal silicon and single-crystal silicon germanium fabricated by epitaxial growth, or from alternating preparation of two different thin film materials with high etching selectivity. Optionally, the stacked structure consisting of alternating materials can be replaced by an etching and deposition process to form a stacked structure consisting of material layers M1 and M2.
[0063] Optionally, the etching process for creating the stacked structure includes anisotropic etching or isotropic etching, such as dry etching or wet etching.
[0064] Optionally, deposition processes for fabricating layered structures include physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, epitaxial growth (EPI), etc.
[0065] Furthermore, as shown in Figures 4a-4b, a first lead-out trench is formed at the corresponding position of the first lead-out structure in the stacked structure, and the material layer M2 is etched laterally along the first lead-out trench to form a first lead-out groove, with the common electrode structure exposed at both ends of the first lead-out groove.
[0066] In some embodiments, the method for forming the first lead-out trench may be through a patterning process. Specifically, the patterning process includes forming photoresist on a substrate, exposing and developing the photoresist to form a pre-defined pattern of photoresist, and etching the stacked structure with the patterned photoresist to form the first lead-out trench. Optionally, the etching process includes anisotropic etching or isotropic etching, such as dry etching or wet etching.
[0067] In some embodiments, the patterning process further includes forming a hard mask on a substrate, forming photoresist on the hard mask, exposing and developing the photoresist to form a preset pattern, etching the hard mask with the patterned photoresist to transfer the preset pattern onto the hard mask, stripping the photoresist, and etching the stacked structure with the patterned hard mask to form a first lead-out trench.
[0068] In some embodiments, as semiconductor fabrication processes advance, integration density increases and dimensions shrink. A single patterning process cannot form the predetermined width required for active regions and isolation trenches, necessitating multiple patterning processes. Examples include two-stage exposure and etching (LELE), self-aligned dual patterning (SADP), and self-aligned quad patterning (SAQP).
[0069] In some embodiments, the method for lateral etching of material layer M2 can be a liquid phase etching process. Optionally, the etching rate of the etchant in the liquid phase etching process on material layer M2 is greater than the etching rate of the etchant on material layer M1.
[0070] Furthermore, as shown in Figures 5a-5b, a material layer M3 is formed in the first lead-out groove, and the material layer M3 fills the first lead-out groove and covers the sidewall of the first lead-out groove.
[0071] In some embodiments, the material of the material layer M3 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or metal oxides such as tantalum oxide, hafnium oxide, aluminum oxide, or polycrystalline silicon and combinations thereof. Preferably, the material of the material layer M3 includes polycrystalline silicon.
[0072] In some embodiments, the method for forming the material layer M3 is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, and other processes.
[0073] Furthermore, as shown in Figures 6a-6b, the material layer M3 on the sidewall of the first lead-out trench is removed, and the remaining material layer M3 in the first lead-out groove forms a filler layer, which is then filled with the first lead-out insulating layer P1.
[0074] In some embodiments, the process for removing the material layer M3 from the sidewall of the first lead-out trench is an anisotropic etching process, including dry etching, plasma etching, etc.
[0075] In some embodiments, the material of the first lead-out insulating layer P1 is selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or metal oxides such as tantalum oxide, hafnium oxide, aluminum oxide, and combinations thereof. Preferably, the first lead-out insulating layer P1 is a stack of silicon oxide and silicon nitride. Optionally, the method for forming the first lead-out insulating layer P1 is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, rapid thermal oxidation, etc. Preferably, the deposition method of the first lead-out insulating layer P1 is chemical vapor deposition (CVD).
[0076] In some embodiments, the method of forming the first lead-out insulating layer P1 further includes: removing the first lead-out insulating layer P1 that extends beyond the first lead-out trench when forming the first lead-out insulating layer P1, such that the upper surface of the first lead-out insulating layer P1 is flush with the first lead-out trench. The method for removing the gate insulating layer material on the substrate surface is selected from etching processes and chemical mechanical polishing (CMP).
[0077] In some embodiments, as shown in FIG7, before forming the material layer M3, a barrier layer M3-1 is first formed in the first lead-out trench, the barrier layer M3-1 covering the surface of the first lead-out groove and the sidewall of the first lead-out trench; the material layer M3 is formed in the first lead-out trench where the barrier layer M3-1 is formed, the material layer M3 filling the first lead-out groove where the barrier layer M3-1 is formed and covering the sidewall of the first lead-out trench where the barrier layer M3-1 is formed; the material layer M3 on the sidewall of the first lead-out trench is removed, and the remaining material layer M3 in the first lead-out groove and the barrier layer M3-1 in contact with the material layer M3 together form a filler layer; the first lead-out insulating layer P1 is filled in the first lead-out trench.
[0078] In some embodiments, the material of material layer M3-1 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or metal oxides such as tantalum oxide, hafnium oxide, aluminum oxide, and combinations thereof. Preferably, the material of material layer M3-1 is silicon nitride.
[0079] In some embodiments, the method for forming material layer M3-1 is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, and other processes. Preferably, the method for forming material layer M3-1 is atomic layer deposition (ALD).
[0080] In some embodiments, when removing the material layer M3 of the first lead-out trench sidewall, the blocking layer M3-1 of the first lead-out trench sidewall is also removed, and the remaining material layer M3 and blocking layer M3-1 in the first lead-out groove together form a filler layer.
[0081] Further, as shown in Figures 8-11, contact holes of corresponding depths are formed at corresponding positions in the stacked structure using a patterning process. Optionally, contact holes are formed on one or both sides of the first lead-out trench. A material layer M4 is deposited within the contact holes, and an anisotropic etching process is used to remove the material layer M4 at the bottom of the contact holes, exposing the corresponding material layer M3. An isotropic etching process is then used to etch away part of the exposed material layer M3 to form a second contact pad groove, exposing the corresponding filler layer.
[0082] In some embodiments, the method of forming contact holes includes anisotropic etching or isotropic etching, such as dry etching or wet etching.
[0083] In some embodiments, the material of the material layer M4 is selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or metal oxides such as tantalum oxide, hafnium oxide, aluminum oxide, and combinations thereof. Preferably, the material of the material layer M4 is selected from a silicon oxide and silicon nitride stack. Optionally, the method for forming the material layer M4 is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, rapid thermal oxidation, etc. Preferably, the method for forming the material layer M4 is atomic layer deposition (ALD).
[0084] In some embodiments, the method of forming material layer M4 further includes: forming material layer M4 on the upper surface of the stacked structure during the formation of material layer M4, and removing material layer M4 from the upper surface of the stacked structure, so that material layer M4 is formed only in the contact holes. The method for removing material layer M4 from the upper surface of the stacked structure is selected from etching processes and chemical mechanical polishing (CMP).
[0085] In some embodiments, the anisotropic etching process for the material layer M4 at the bottom of the hole includes dry etching, plasma etching, etc.
[0086] In some embodiments, etching to remove part of the exposed material layer M3 to form a second contact pad groove employs an isotropic etching process, including wet etching.
[0087] Furthermore, as shown in Figure 12, the corresponding filler layer is removed by etching the second contact pad groove through the contact hole, forming the first lead groove and exposing the corresponding common electrode structure.
[0088] In some embodiments, isotropic etching processes are used to remove portions of the filler layer, including wet etching.
[0089] Furthermore, as shown in Figures 13a-13b, a material layer M5 is formed in the contact hole, the second contact pad groove, and the first lead groove. Simultaneously, the first lead, the second contact pad, and the second contact plug are formed as an integral structure at corresponding positions. The first lead is electrically connected to the corresponding common electrode structure. A filler layer retained at a position opposite to the first lead forms a first pseudo-wire.
[0090] In some embodiments, the material of the material layer M5 is selected from metals, metal nitrides, metal oxides, metal silicides, conductive carbon, doped or undoped polycrystalline silicon, doped or undoped monocrystalline silicon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), aluminum titanium nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), aluminum tantalum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof. Preferably, the material layer M5 is a stack of titanium nitride (TiN) and tungsten (W). The method for forming the material layer M5 is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc. Preferably, the method for forming the material layer M5 is atomic layer deposition (ALD).
[0091] In some embodiments, the method of forming material layer M5 further includes: forming material layer M5 on the upper surface of the stacked structure during the formation of material layer M5; and removing material layer M5 from the upper surface of the stacked structure, such that material layer M5 is formed only in the contact hole, the second contact pad groove, and the first lead groove. The method for removing material layer M5 from the upper surface of the stacked structure is selected from etching processes and chemical mechanical polishing (CMP).
[0092] In some embodiments, when the filler layer, as shown in FIG7, is formed by the material layer M3 and the barrier layer M3-1, and a second contact pad groove for exposing the filler layer is formed, the barrier layer M3-1 in the filler layer is first removed by etching through the contact hole and the second contact pad groove, and then the material layer M3 in the filler layer is removed, thus exposing the corresponding common electrode structure.
[0093] In some embodiments, when the filler layer is formed by the material layer M3 and the barrier layer M3-1 in the remaining first lead-out groove, the entire filler layer can be removed in two steps, including first removing the barrier layer M3-1 by a first isotropic etching process, and then removing the material layer M3 by a second isotropic etching process.
[0094] In some embodiments, after forming the contact hole, the second contact pad groove, and the first lead groove, the first lead, the second contact pad, and the second contact plug can be formed in steps. Optionally, the first lead is formed first, then the second contact pad is formed, and finally the second contact plug is formed; alternatively, the first lead and the second contact pad are formed as an integral structure in the same step, and then the second contact plug is formed; alternatively, the first lead is formed first, and then the second contact pad and the second contact plug are formed as an integral structure in the same step.
[0095] In some embodiments, the first lead, second contact pad, and second contact plug are formed in steps. The step of forming the first lead separately may involve first forming a first lead material layer, filling the first lead groove through a contact hole and a second contact pad groove, and then removing excess first lead material layer by wet etching, leaving the remaining first lead material layer in the first lead groove to form the first lead. The step of forming the second contact pad separately may involve first forming a second contact pad material layer, filling the second contact pad groove through a contact hole, and then removing excess second contact pad material layer by wet etching, leaving the remaining second contact pad material layer in the second contact pad groove to form the second contact pad. The step of forming the second contact plug separately may involve first forming a second contact plug material layer, filling the contact hole, and then removing excess second contact plug material layer by etching or chemical mechanical polishing (CMP), leaving the remaining second contact plug material layer in the contact hole to form the second contact plug. Similarly, the first lead wire and the second contact pad are formed in the same step, and then the second contact plug is formed; the first lead wire is formed first, and then the second contact pad and the second contact plug are formed in the same step; similar to the aforementioned forming method.
[0096] In some embodiments, the materials of the first lead wire material layer, the second contact pad material layer, and the second contact plug material layer may be the same or different, and each may be individually selected from metals, metal nitrides, metal oxides, metal silicides, conductive carbon, doped or undoped polycrystalline silicon, doped or undoped monocrystalline silicon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof. The formation methods of the first lead material layer, the second contact pad material layer, and the second contact plug material layer can be the same or different, and each can be selected individually from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc. Preferably, the formation method of the first lead material layer, the second contact pad material layer, or the second contact plug material layer is atomic layer deposition (ALD).
[0097] In some embodiments, when multiple second lead-out structures are provided along a second direction on one side of the first lead-out structure, as shown in Figures 14-15, contact holes of corresponding depths are formed at corresponding positions in the stacked structure using a patterning process. A material layer M4 is deposited within the contact holes. An anisotropic etching process is used to remove the material layer M4 at the bottom of the hole, exposing the corresponding material layer M3. An isotropic etching process is used to etch away part of the exposed material layer M3 to form a second contact pad groove, exposing the corresponding filler layer. Through the contact holes, the second contact pad groove is etched to remove the corresponding filler layer, forming a first lead-out groove and exposing the corresponding common electrode structure. A material layer M5 is formed in the contact holes, the second contact pad groove, and the first lead-out groove. The first lead, second contact pad, and second contact plug are simultaneously formed at corresponding positions as an integral structure. The first lead is electrically connected to the corresponding common electrode structure. In a second lead-out structure disposed on the same side of the first lead-out structure along the second direction, the second contact pad of the second lead-out structure farther from the first lead-out structure is located below the second contact pad closer to the first lead-out structure, and is separated by at least one material layer M3, thereby forming a first lead-out line and a first pseudo-line that are staggered along the first direction. Optionally, three material layers M3 or five material layers M3 may be spaced apart.
[0098] In some embodiments, a stacked array structure is formed in the stacked structure. The stacked array structure can be fabricated before or after the first lead-out structure is completed. The stacked array structure can also be fabricated before or after the second lead-out structure is completed. The stacked array structure forms multiple memory cells, each memory cell having a transistor and a memory node. Optionally, the memory node is selected from one or more of the following: a memory capacitor, a phase-change memory, a magnetoresistive memory, or a ferroelectric memory. Each layer in the stacked array structure forms multiple spaced-apart memory cells, with memory cells in different layers correspondingly arranged. The transistor forms a first source / drain, a second source / drain, and a gate. The first source / drain is connected to a bit line structure, and the second source / drain is connected to a memory node. Optionally, when the first electrode structure is a bit line structure, the first source / drain of memory cells in the same layer of the stacked array structure is connected to the same bit line structure, and the gates of memory cells in different layers are connected to the same word line structure, or form a word line structure. Optionally, when the first electrode structure is a word line structure, the first source and drain of the memory cells corresponding to different layers in the stacked array structure are connected to the same bit line structure or form the same bit line structure, and the gates of the memory cells in the same layer are connected to the same word line structure or form the same word line structure.
[0099] In some embodiments, the active region material of the transistor is selected from one or more of single-crystal silicon, single-crystal silicon germanium, polycrystalline silicon, or oxide semiconductor materials, or doped with other elements. The oxide semiconductor material may include indium gallium zinc oxide (InxGayZnzO, IGZO), indium gallium silicon oxide (InxGaySiZO, IGSO), indium tin zinc oxide (InxSnyZnzO, ITZO), indium gallium tin oxide (InxGaySnzO, IGTO), indium zinc oxide (InxZnyO, IZO), zinc oxide (ZnxO, ZnO), zinc tin oxide (ZnxSnyO, ZTO), and zinc oxynitride (ZnxO, ZnO). Zinc zinc tin oxide (ZrxZnySnzO, ZZTO), tin oxide (SnxO, SnO), hafnium indium zinc oxide (HfxInyZnzO, HIZO), gallium zinc tin oxide (GaxZnySnzO, GZTO), aluminum zinc tin oxide (AlxZnySnzO, AZTO), yttrium gallium zinc oxide (YbxGayZnzO, YGZO), indium gallium oxide (InxGayO, IGO), or combinations thereof.
[0100] In some embodiments, the gate material is selected from metals, metal nitrides, metal oxides, metal silicides, conductive carbon, doped or undoped polycrystalline silicon, doped or undoped monocrystalline silicon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), aluminum titanium nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), aluminum tantalum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof. The gate material is formed by physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc., preferably, the gate material is formed by atomic layer deposition (ALD).
[0101] In some embodiments, the gate surface is covered with a gate insulating layer, the gate insulating layer material being selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or metal oxides such as tantalum oxide, hafnium oxide, aluminum oxide, and combinations thereof. The gate insulating layer is formed by physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc. Preferably, the gate material is formed by atomic layer deposition (ALD).
[0102] In some embodiments, the bitline structure material includes materials selected from metals, metal nitrides, metal oxides, metal silicides, conductive carbon, doped or undoped polycrystalline silicon, doped or undoped monocrystalline silicon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), aluminum titanium nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), aluminum tantalum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof. The method for forming the bitline structure material is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc., preferably, the method for forming the bitline structure material is atomic layer deposition (ALD).
[0103] In some embodiments, the storage node is selected from a storage capacitor, and the lower electrode of the storage capacitor is selected from metals, metal nitrides, metal oxides, metal silicides, conductive carbon, doped or undoped polycrystalline silicon, doped or undoped monocrystalline silicon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof. Preferably, the lower electrode is titanium nitride (TiN). The method for forming the lower electrode is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc. Preferably, the method for forming the bit line structure material is atomic layer deposition (ALD).
[0104] In some embodiments, the storage node is selected from a storage capacitor, and the upper electrode of the storage capacitor is selected from metals, metal nitrides, metal oxides, metal silicides, conductive carbon, doped or undoped polycrystalline silicon, doped or undoped monocrystalline silicon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), aluminum titanium nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), aluminum tantalum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof. Preferably, the upper electrode is a stack of titanium nitride (TiN) and polycrystalline silicon. The upper electrode is formed by a method selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc.
[0105] In some embodiments, the common electrode structure connects to multiple stacked array structures. Optionally, the stacked array structures are spaced apart along the extension direction of the common electrode structure. Optionally, multiple stacked array structures are formed on both sides of the common electrode structure.
[0106] Understandably, the alternating arrangement of first leads and first pseudo-lines on different layers in this disclosure can increase the distance between the first leads on different layers, thereby reducing parasitic capacitance.
[0107] On the other hand, since the distance between the first leads of different layers is increased, the first leads can be made wider, thereby reducing the resistance of the first leads and thus reducing the loss of semiconductor devices.
[0108] On the other hand, since the first lead, the second contact pad and the second contact plug are integrally formed; or the first lead and the second contact pad are integrally formed; or the second contact pad and the second contact plug are integrally formed, the contact resistance can be reduced, thereby reducing the loss of the semiconductor device.
[0109] On the other hand, when the second contact pad of the second contact pad that is closer to the first contact structure is connected to the first contact structure that is located on a higher layer than the second contact pad that is farther away from the first contact structure, and the second contact pad of the second contact structure that is farther away from the first contact structure passes through the corresponding first contact structure in the lower layer, the parasitic capacitance between different layers of second contact pads that overlap in the projection portion of the substrate along the first direction can be reduced.
[0110] The various semiconductor devices illustrated in this specific embodiment can be used in electronic devices with storage functions. These electronic devices can be terminal devices, such as mobile phones, tablets, and smart bracelets, or personal computers (PCs), servers, workstations, etc. The storage function in these electronic devices can be implemented using the following types of memory: Dynamic Random Access Memory (DRAM), Ferroelectric Random Access Memory (FRAM), Phase-Change Memory (PCM), Magnetic Random Access Memory (MRAM), or Resistive Random Access Memory (RRAM).
[0111] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. A semiconductor device (10), characterized by, include: Substrate (100); A common electrode structure (200) is stacked on the substrate along a first direction (D1), the first direction intersecting the substrate; A stacked array structure (20) includes a first electrode structure (300), which is stacked on the substrate along the first direction and electrically connected to the common electrode structure disposed in the same layer. A first lead-out structure (400) is stacked along a first direction and connected to the common electrode structure disposed in the same layer. The first lead-out structure includes a first lead-out line (401) and a first pseudo-line (402) disposed opposite to each other. In the first direction, the first lead-out line and the first pseudo-line of different first lead-out structures are alternately disposed. The second lead-out structure (500) includes a second contact pad (501) and a second contact plug (502). The second contact pad is disposed in the same layer as the corresponding first lead-out line and is electrically connected to the corresponding common electrode structure through the corresponding first lead-out line. The second contact plug is disposed on the second contact pad and is staggered from each other in the first direction.
2. The semiconductor device according to claim 1, characterized in that, The first lead-out structure extends along a third direction (D3), and the second lead-out structures are staggered along the third direction, which is parallel to the substrate.
3. The semiconductor device according to claim 1, characterized in that, The first lead-out structure extends along a third direction, which is parallel to the substrate; a second lead-out structure is provided in a second direction (D2), which overlaps with the projection of the second lead-out structure onto the substrate along the first direction, which is parallel to the substrate and intersects the third direction.
4. The semiconductor device according to claim 3, characterized in that, The first lead wires connected to the second lead structure, which overlaps with the projection portion of the substrate along the first direction, are spaced at least one layer apart.
5. The semiconductor device according to claim 1, characterized in that, The first electrode structure includes a bit line structure or a word line structure.
6. The semiconductor device according to claim 1, characterized in that, Both ends of the first lead-out structure are connected to the common electrode structure.
7. The semiconductor device according to claim 1, characterized in that, The second contact pad is integrally formed with the first lead wire.
8. The semiconductor device according to claim 1, characterized in that, The second contact pad and the second contact plug are integrally formed.
9. The semiconductor device according to claim 1, characterized in that, The first pseudo-line comprises a polysilicon and silicon nitride stack.
10. A method of manufacturing a semiconductor device, characterized by, include: A substrate is provided on which a multilayer structure is formed; A common electrode structure is formed in the stacked structure; A stacked array structure is formed in the stacked structure, the stacked array structure including a first electrode structure; A first lead-out structure is formed in the stacked structure, the first lead-out structure including a first lead-out line and a first pseudo-line disposed opposite to each other; in a first direction, the first lead-out line and the first pseudo-line of different first lead-out structures are alternately disposed, and the first direction intersects the substrate; A second lead-out structure is formed in the stacked structure, the second lead-out structure including a second contact pad and a second contact plug; The common electrode structure is electrically connected to the first electrode structure formed in the same layer, and the second lead structure is electrically connected to the common electrode structure through the first lead line; the second contact plug is formed on the second contact pad, and the second contact plugs are staggered in the first direction.
11. The method for fabricating the semiconductor device according to claim 10, characterized in that, The first lead wire, the second contact pad, and the second contact plug are formed in the same step.
12. The method for fabricating the semiconductor device according to claim 10, characterized in that, The step of forming the first lead-out structure includes first forming a filler layer, wherein the filler layer occupies the position of the first lead-out structure; Form a trench structure corresponding to the second lead-out structure and expose the corresponding filler layer; Remove the exposed filler layer; The first lead wire, the second contact pad, and the second contact plug are formed; the remaining filler layer forms the first pseudowire.
13. The method for fabricating the semiconductor device according to claim 12, characterized in that, The filler layer is formed by depositing polycrystalline silicon and silicon nitride in a stack.
14. The method for fabricating a semiconductor device according to claim 10, characterized in that, The formation of the stacked structure includes alternating silicon layers and silicon-germanium layers.