Semiconductor packaging structure and preparation method therefor, and electronic device

Abstract

The present application relates to the technical field of semiconductors, and discloses a semiconductor packaging structure and a preparation method therefor, and an electronic device. The semiconductor packaging structure comprises a first redistribution layer, a chip structure layer, a first plastic packaging layer, a conductive interconnection structure, and a conductive bump; the chip structure layer is located on a second surface of the first redistribution layer; the first plastic packaging layer is located on a first surface of the first redistribution layer; the conductive interconnection structure passes through the first plastic packaging layer and is connected to a first pad on the first surface; the conductive bump is located on the side of the first plastic packaging layer facing away from the first redistribution layer and is connected to the conductive interconnection structure. In this way, the first plastic packaging layer is used to mitigate or even eliminate warpage, thereby improving packaging efficiency and yield, and improving the reliability of the semiconductor packaging structure.

Description

A semiconductor packaging structure, fabrication method, and electronic device

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411624008.5, filed on November 13, 2024, with the State Intellectual Property Office of the People's Republic of China, entitled "A Semiconductor Packaging Structure, Preparation Method and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of semiconductor technology, and in particular to a semiconductor packaging structure, fabrication method, and electronic device. Background Technology

[0004] With the rapid development of the semiconductor industry, chip sizes are shrinking and the number of signal contacts is increasing, making traditional packaging insufficient to meet the demands of high contact counts. Fan-out package-on-package (FOPoP) technology, based on a redistribution layer (RDL), offers advantages such as a large number of input / output ports and good integration flexibility, and is widely used in the semiconductor industry. However, during the FOPoP packaging process, mismatches in the coefficients of thermal expansion (CTE) of the packaging materials at different locations can easily lead to warping of the resulting package structure, thus affecting packaging efficiency and yield. Summary of the Invention

[0005] This application provides a semiconductor packaging structure, a fabrication method, and an electronic device to improve warpage, increase packaging efficiency, and improve yield.

[0006] In a first aspect, embodiments of this application provide a semiconductor packaging structure, comprising: a first redistribution layer, a chip structure layer, a first molding compound layer, a conductive interconnect structure, and conductive bumps. The first redistribution layer includes opposing first and second surfaces. The chip structure layer is located on the second surface of the first redistribution layer. The first molding compound layer is located on the first surface of the first redistribution layer. The conductive interconnect structure penetrates the first molding compound layer and is connected to a first pad on the first surface. The conductive bumps are located on the side of the first molding compound layer facing away from the first redistribution layer and are connected to the conductive interconnect structure. By providing a first molding compound layer between the first redistribution layer and the conductive bumps, warpage can be improved or even eliminated, thereby increasing packaging efficiency and yield, and improving the reliability of the semiconductor packaging structure.

[0007] In this embodiment, by setting a conductive interconnect structure that penetrates the first molding layer, the conductive bump and the first pad are electrically connected by the conductive interconnect structure, thereby enabling signal transmission.

[0008] In this embodiment, the first molding layer is disposed on the first surface of the first redistribution layer, which can also improve the strength of the first redistribution layer, thereby improving the overall strength and reliability of the semiconductor packaging structure.

[0009] In one possible implementation, the coefficient of thermal expansion of the first molding layer is 7ppm / ℃ to 10ppm / ℃, so as to be flexibly designed according to the actual warpage requirements and to achieve different warpage control.

[0010] In one possible implementation, the modulus of the first molding layer is 10 GPa to 28 GPa, which can be flexibly designed according to the actual warpage requirements to achieve different warpage control.

[0011] In one possible implementation, the conductive interconnect structure includes metal pillars, which can improve the reliability of the electrical connection and reduce signal delay. For example, the metal pillars are copper pillars, which not only improve conductivity but also maintain their shape well during the formation of the conductive bumps 350, ensuring smooth signal flow.

[0012] In one possible implementation, the metal pillars include copper pillars, which not only improve conductivity but also maintain their shape well during the formation of conductive bumps, ensuring smooth signal flow.

[0013] In one possible implementation, the conductive bumps include one or a combination of copper pillars, microbumps, and solder balls, which not only enable electrical connections but also provide higher reliability.

[0014] In one possible implementation, the first redistribution layer includes multiple first dielectric layers and a first conductive layer located between the first dielectric layers. Circuit wiring is provided in the first conductive layer, and contact holes are provided in the first dielectric layer for connecting the circuit wiring in different first conductive layers.

[0015] In one possible implementation, the chip structure layer includes a first chip and a second molding compound layer. The first chip is located on a second surface of the first redistribution layer and is connected to a second pad in the second surface. The second molding compound layer at least covers the sides of the first chip. This allows for electrical connection between the first chip and the first redistribution layer, and also enables the encapsulation of the first chip, improving packaging strength and reliability.

[0016] In one possible implementation, the coefficient of thermal expansion of the first molding layer is greater than that of the second molding layer, which is beneficial for controlling warpage.

[0017] In one possible implementation, the chip structure layer further includes a second chip, a second redistribution layer, and a third molding compound layer. The second redistribution layer is located on the side of the first chip facing away from the first redistribution layer, and the second chip is located on the side of the second redistribution layer facing away from the first redistribution layer. The second chip is connected to a third pad in the second surface through the second redistribution layer, and the third molding compound layer covers the side of the second chip facing away from the second redistribution layer. This improves integration density and reduces chip footprint. Furthermore, using a third molding compound layer to encapsulate the second chip improves the strength and reliability of the semiconductor package structure.

[0018] In one possible implementation, the second redistribution layer includes multiple layers of second dielectric layers and a second conductive layer located between the second dielectric layers. Circuit wiring is provided in the second conductive layer, and contact holes are provided in the second dielectric layer for connecting the circuit wiring in different second conductive layers.

[0019] In one possible implementation, the coefficient of thermal expansion of the first molding layer is greater than that of the third molding layer, which is beneficial for controlling warpage.

[0020] In one possible implementation, the coefficient of thermal expansion of the second molding layer is greater than that of the third molding layer, further improving warpage and packaging reliability.

[0021] In one possible implementation, the first chip has opposing first and second sides, the first side having conductive contacts connected to second pads, and the second side having a first adhesive layer between it and the second redistribution layer. This allows the semiconductor package structure to be formed as a chip-first structure in the FOPoP structure, thereby improving the performance, integration, and cost-effectiveness of the semiconductor package structure, making it suitable for various high-performance and high-integration applications.

[0022] In one possible implementation, the first chip has opposing first and second sides, the first side having conductive contacts connected to a first redistribution layer, and the second side having a heat sink. This allows the semiconductor package structure to be formed as a chip-last structure in a FOPoP structure, which not only improves the performance, integration, and cost-effectiveness of the semiconductor package structure, making it suitable for various high-performance and high-integration applications, but also enhances heat dissipation.

[0023] In one possible implementation, a second underfill layer is provided between the first side of the first chip and the first redistribution layer. This not only tightly bonds the first chip, solder joints, and the first redistribution layer together, but also reduces the stress generated at the solder joints due to CTE mismatch between the first chip and the first redistribution layer, thereby improving the thermal fatigue life of the solder joints. Exemplarily, the material of the second underfill layer includes, but is not limited to, epoxy resin.

[0024] In one possible implementation, a first underfill layer is provided between the second chip and the second redistribution layer. This not only tightly bonds the second chip, the transition solder balls, and the second redistribution layer together, but also reduces the stress on the transition solder balls caused by CTE mismatch between the second chip and the second redistribution layer, thereby improving the thermal fatigue life of the transition solder balls. Exemplarily, the material of the first underfill layer includes, but is not limited to, epoxy resin.

[0025] In one possible implementation, the second redistribution layer has a cutout area, and a heat sink is disposed in the cutout area, thereby enabling the heat sink to be integrated inside the semiconductor package structure without increasing the overall height of the semiconductor package structure, thus improving the heat dissipation effect.

[0026] Secondly, embodiments of this application also provide a method for fabricating a semiconductor packaging structure, comprising:

[0027] A first redistribution layer and a chip structure layer are formed respectively. The first redistribution layer includes a first surface and a second surface opposite to each other. The chip structure layer is located on the second surface of the first redistribution layer.

[0028] A first molding layer is formed, the first molding layer being located on the first surface of the first redistribution layer;

[0029] A conductive interconnect structure is formed, which penetrates the first molding layer and is connected to the first pad in the first surface;

[0030] Conductive bumps are formed on the side of the first molding layer opposite to the first redistribution layer and are connected to the conductive interconnect structure.

[0031] In one possible implementation, forming a conductive interconnect structure includes: forming the conductive interconnect structure using an electroplating process.

[0032] In one possible implementation, forming the first encapsulation layer includes forming the first encapsulation layer using a compression molding or flow molding process.

[0033] In one possible implementation, a first molding layer is formed after the conductive interconnect structure is formed.

[0034] Thirdly, embodiments of this application also provide an electronic device, which includes a circuit board and a semiconductor package structure, the semiconductor package structure being disposed on the circuit board. The semiconductor package structure is the semiconductor package structure of the first aspect or the embodiments of the first aspect, or the semiconductor package structure is a semiconductor package structure prepared using the methods of the second aspect or the embodiments of the second aspect. Since the semiconductor package structure in the embodiments of this application has better performance, the electronic device including the semiconductor package structure also has better performance. Furthermore, the technical effects of the corresponding solutions in the third aspect can be referred to the technical effects obtainable by the corresponding solutions in the first and second aspects; repeated details are not elaborated here. Attached Figure Description

[0035] Figure 1 is a schematic diagram of the structure of an electronic device according to an embodiment of this application;

[0036] Figure 2 is a schematic diagram of a semiconductor packaging structure in an embodiment of this application;

[0037] Figure 3 is a schematic diagram of a warping in an embodiment of this application;

[0038] Figure 4 is a schematic diagram of another type of warping in an embodiment of this application;

[0039] Figures 5 to 10 are schematic diagrams of the semiconductor packaging structure fabrication process in the embodiments of this application.

[0040] Figure 11 is a schematic diagram of another semiconductor packaging structure in an embodiment of this application;

[0041] Figures 12 and 13 are schematic diagrams of another structure in the fabrication process of the semiconductor packaging structure in the embodiments of this application;

[0042] Figure 14 is a flowchart of the preparation method in the embodiments of this application.

[0043] Reference numerals: 100-Housing; 200-Circuit board; 300-Semiconductor package structure; 310-First redistribution layer; 311-First pad; 312-Second pad; 313-Third pad; 314-First dielectric layer; 315-First conductive layer; 320-Chip structure layer; 321-First chip; 3211-Conductive contact; 322-Second molding compound layer; 323-Second chip; 3231-Die; 3232-Adapter board; 3233-Adapter solder ball; 324-Second redistribution layer; 3241-Second dielectric layer; 3242-Second conductive layer; 3243-Fourth pad; 3244-Fifth pad; 325-Solder joint; 326-Vertical interlock 327-First adhesive layer; 328-First bottom filler layer; 329-Second bottom filler layer; 330-First molding layer; 340-Conductive interconnect structure; 341-Copper pillar; 350-Conductive bump; 351-Solder ball; 360-Capacitor; 371-Heat sink; 372-Second adhesive layer; 381-Third molding layer; 410-Substrate; 421-Support substrate; 422-Adhesive; 431-Groove; BQ-Clearing area; S1-First surface; S2-Second surface. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The specific operational methods in the method embodiments can also be applied to the device embodiments or system embodiments. It should be noted that in the description of this application, "multiple" can be understood as "at least two". Furthermore, it should be understood that in the description of this application, terms such as "first" and "second" are used only for distinguishing purposes and should not be construed as indicating or implying relative importance, nor as indicating or implying order.

[0045] It should be noted that the same reference numerals in the accompanying drawings of this application denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but may be modified as needed, and all modifications are included within the scope of protection of this application. The accompanying drawings of this application are for illustrating relative positional relationships only and do not represent actual scale.

[0046] The semiconductor packaging structure, fabrication method, and electronic device provided in the embodiments of this application are described below with reference to the accompanying drawings.

[0047] Figure 1 is a schematic diagram of an electronic device according to an embodiment of this application. Referring to Figure 1, the electronic device includes: a housing 100, a circuit board 200 disposed within the housing 100, and a semiconductor package structure 300 fixed on the circuit board 200. The semiconductor package structure 300 and the circuit board 200 can be connected by bonding or other methods to achieve an electrical connection between them, thereby enabling signal transmission between them.

[0048] For example, electronic devices include, but are not limited to, terminal devices and communication devices. Terminal devices include, but are not limited to, mobile phones, computers, televisions, set-top boxes, watches, personal computers (PCs), wearable devices, workstations, etc. Communication devices include, but are not limited to, wireless network devices, fixed network devices, servers, smart broadband devices, etc. It is understood that the specific implementation of the electronic device can be determined according to the actual application scenario and is not limited herein.

[0049] For example, circuit board 200 includes, but is not limited to, a printed circuit board (PCB).

[0050] For example, the semiconductor package structure 300 includes, but is not limited to, logic circuits, memory circuits, and system-on-chip (SOC) devices that integrate logic and memory circuits, etc., which are not listed here. As an example, the logic circuit is a processor or input / output (I / O) device. The processor includes, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), an artificial intelligence (AI) processor, a digital signal processor, and a neural network processor. As an example, the memory circuit is a memory, including, but not limited to, random access memory (RAM) and read-only memory (ROM). Among them, random access memory includes, but is not limited to, dynamic random access memory (DRAM), static random access memory (SRAM), magnetoresistive random access memory (MRAM), phase change memory (PCM), etc.

[0051] Figure 2 is a schematic diagram of a semiconductor packaging structure according to an embodiment of this application. Referring to Figure 2, the semiconductor packaging structure 300 provided in this embodiment includes: a first redistribution layer 310, a chip structure layer 320, a first molding compound layer 330, a conductive interconnect structure 340, and a conductive bump 350. The first redistribution layer 310 includes a first surface S1 and a second surface S2 opposite to each other. The chip structure layer 320 is located on the second surface S2 of the first redistribution layer 310. The first molding compound layer 330 is located on the first surface S1 of the first redistribution layer 310. The first surface S1 has a first pad 311. The conductive interconnect structure 340 penetrates the first molding compound layer 330 and is connected to the first pad 311 in the first surface S1. The conductive bump 350 is located on the side of the first molding compound layer 330 facing away from the first redistribution layer 310 and is connected to the conductive interconnect structure 340. Therefore, by setting a first molding compound 330 between the first redistribution layer 310 and the conductive bump 350, the first molding compound 330 is used to improve or even eliminate warpage, thereby improving packaging efficiency and yield, and enhancing the reliability of the semiconductor package structure 300. Furthermore, by providing a conductive interconnect structure 340 that penetrates the first molding compound 330, an electrical connection is achieved between the conductive bump 350 and the first pad 311 of the first redistribution layer 310, enabling signal transmission. Additionally, the first molding compound 330 is disposed on the first surface S1 of the first redistribution layer 310, which also improves the strength of the first redistribution layer 310, thereby enhancing the overall strength and reliability of the semiconductor package structure 300.

[0052] For example, based on the different warpage directions, warpage types can be divided into "smiley face warpage" and "crying face warpage." For instance, "smiley face warpage" refers to the situation where, without the first molding compound 330, the CTE of the packaging material at different locations is mismatched, causing stress in the semiconductor packaging structure to concentrate in the edge region. This results in a greater degree of warpage in the edge region than in the middle region, leading to a semiconductor packaging structure with a downward-concave center and upward-curving edges, thus approximating the smiley face shape shown in Figure 3(a). "Crying face warpage" refers to the same situation where, without the first molding compound 330, the CTE of the packaging material at different locations is mismatched, causing stress in the semiconductor packaging structure to concentrate in the middle region. This results in a greater degree of warpage in the middle region than in the edge region, leading to a semiconductor packaging structure with an upward-curving center and downward-curving edges, thus approximating the crying face shape shown in Figure 4(a). In this embodiment of the application, by setting a first molding layer 330, the stress of the semiconductor packaging structure is balanced by the first molding layer 330, warpage is improved, or even warpage is eliminated, so that the shape of the semiconductor packaging structure is approximately the shape shown in Figure 3(b) and Figure 4(b).

[0053] This application does not limit the CTE of the first molding compound 330. In specific implementations, the CTE of the first molding compound 330 can be flexibly designed according to the actual warpage requirements, thereby achieving different warpage control. For example, to improve warpage, the CTE of the first molding compound 330 can be set to 7ppm / ℃ to 10ppm / ℃. Exemplarily, the CTE of the first molding compound 330 is 7ppm / ℃, 8ppm / ℃, 9ppm / ℃, 10ppm / ℃, etc.

[0054] This application does not limit the modulus of the first molding compound 330. In specific implementations, the modulus of the first molding compound 330 can be flexibly designed according to the actual warpage requirements, thereby achieving different warpage control. For example, to improve warpage, the modulus of the first molding compound 330 can be 10 GPa to 28 GPa, such as 10 GPa, 12 GPa, 15 GPa, 18 GPa, 20 GPa, 23 GPa, 25 GPa, 28 GPa, etc.

[0055] The thickness of the first molding layer 330 is not limited in this embodiment. In specific implementation, the thickness of the first molding layer 330 can be flexibly designed according to the actual warpage requirements, so as to achieve different warpage control.

[0056] This application does not limit the material of the first molding layer 330. In specific implementations, the material of the first molding layer 330 can be flexibly designed according to the actual warpage requirements, thereby achieving different warpage control. For example, to improve warpage, the material of the first molding layer 330 can be set as epoxy molding compound (EMC).

[0057] It is understood that the CTE, modulus, thickness and material mentioned above are merely illustrative examples. In other embodiments of this application, other parameters of the first molding layer 330 can be flexibly designed to achieve different warpage control.

[0058] For example, referring to Figure 2, there are multiple first pads 311, multiple conductive bumps 350, and multiple conductive interconnect structures 340, with each conductive bump 350, first pad 311, and conductive interconnect structure 340 connected in a one-to-one correspondence. For example, the conductive bumps 350 include, but are not limited to, copper pillars, microbumps, and solder balls, or a combination thereof. For instance, referring to Figure 2, the conductive bumps 350 are formed using solder balls 351, which can achieve advantages such as high density, rapid production, low cost, improved connection strength and yield, good heat dissipation, stable signal transmission, low assembly cost, and convenient rework. For example, the solder balls include one of tin balls, copper balls, titanium balls, nickel balls, gold balls, and silver balls. Furthermore, the solder balls can be distributed using a ball grid array (BGA) method.

[0059] Exemplary examples show that the conductive interconnect structure 340 includes, but is not limited to, metal pillars, enabling the conductive bump 350 and the first pad 311 to be electrically connected via the metal pillars, thereby improving the reliability of the electrical connection and reducing signal delay. As an example, referring to Figure 2, the metal pillars are set as copper pillars 341, which not only improve conductivity but also maintain their shape well during the formation of the conductive bump 350, ensuring smooth signal flow. In other embodiments of this application, the metal pillars can also be flexibly designed using other metal materials, and are not limited here.

[0060] To improve integration and reduce chip footprint, in some embodiments of this application, multiple chips are stacked vertically in the chip structure layer 320. For example, referring to FIG2, the chip structure layer 320 may include a first chip 321, a second molding compound layer 322, a second chip 323, a second redistribution layer 324, and a third molding compound layer 381. The first chip 321 is located on the second surface S2 of the first redistribution layer 310, and the second molding compound layer 322 is located between the second redistribution layer 324 and the first redistribution layer 310, and the second molding compound layer 322 at least covers the side of the first chip 321, thereby molding the first chip 321 through the second molding compound layer 322. Furthermore, the second redistribution layer 324 is located on the side of the first chip 321 facing away from the first redistribution layer 310, and the second chip 323 is located on the side of the second redistribution layer 324 facing away from the first redistribution layer 310. The third molding compound layer 381 covers the side of the second chip 323 facing away from the second redistribution layer 324, thereby molding the second chip 323 through the third molding compound layer 381. Additionally, the second surface S2 has a second pad 312 and a third pad 313. The first chip 321 is connected to the second pad 312 in the second surface S2, and the second chip 323 is connected to the third pad 313 in the second surface S2 through the second redistribution layer 324.

[0061] For example, referring to FIG2, the first redistribution layer 310 may include: multiple first dielectric layers 314 and first conductive layers 315 located between the first dielectric layers 314. Circuit wiring is provided in the first conductive layers 315, and contact holes are provided in the first dielectric layers 314 for connecting the circuit wiring in different first conductive layers 315.

[0062] In this embodiment, the implementation of the second redistribution layer 324 can be the same as that of the first redistribution layer 310. For example, referring to FIG2, the second redistribution layer 324 may include: multiple second dielectric layers 3241 and a second conductive layer 3242 located between the second dielectric layers 3241. Circuit wiring is provided in the second conductive layer 3242, and contact holes are provided in the second dielectric layers 3241. The contact holes are used to connect the circuit wiring in different second conductive layers 3242. The side of the second redistribution layer 324 facing the first redistribution layer 310 has a fourth pad 3243, and the side of the second redistribution layer 324 facing away from the first redistribution layer 310 has a fifth pad 3244. Each fifth pad 3244 is connected to the circuit wiring on the second conductive layer 3242 and the fourth pad 3243 respectively through the contact holes. Each fourth pad 3243 is connected to the third pad 313 on the first redistribution layer 310 respectively, thereby realizing signal flow between the first redistribution layer 310 and the second chip 323.

[0063] Furthermore, there are multiple second pads 312 and third pads. Some of the second pads 312 can be connected to the first conductive layer 315 and a portion of the third pads 313 through contact holes in the first redistribution layer 310, thereby enabling signal transmission between the first chip 321 and the second chip 323. The remaining portions of the second pads 312 and the remaining portions of the third pads 313 are connected to the first pads 311 one-to-one through contact holes in the first redistribution layer 310 and the first conductive layer 315, thereby enabling signal flow between the second pads 312 and the third pads 313 and the first pads 311 respectively.

[0064] For example, the first pad 311 connected to the second pad 312 includes a first portion of the first pad 311 and a second portion of the first pad 311. The first portion of the first pad 311 can be used to transmit power supply voltage signals, which may include, for example, one or a combination of high power supply voltage signals and low power supply voltage signals. The second portion of the first pad 311 can be used to transmit data signals.

[0065] For example, the first pad 311 connected to the third pad 313 can be used to transmit a power supply voltage signal, which may include, for example, one or a combination of a high power supply voltage signal and a low power supply voltage signal. Alternatively, the first pad 311 connected to the third pad 313 can also be used to transmit a data signal.

[0066] For example, the materials of the first dielectric layer 314 and the second dielectric layer 3241 include, but are not limited to, polyimide, and the materials of the first conductive layer 315, the second conductive layer 3242, and the contact holes include, but are not limited to, metallic materials, including, but are not limited to, one or a combination of W, Ru, Ni, Mo, Ni, Pt, Co, Ti, Al, Cu, TiN, TaN, WN, and MoN.

[0067] For example, referring to FIG2, the first chip 321 has a first side and a second side facing each other. The first side of the first chip 321 has a conductive contact 3211, which is connected to the second pad 312 of the first redistribution layer 310, thereby enabling the first chip 321 to transmit signals through the first redistribution layer 310. For example, referring to FIG2, a bonding process (e.g., hybrid bonding) can be used to connect the conductive contact 3211 of the first chip 321 to the second pad 312 of the first redistribution layer 310, thereby creating a solder joint 325 (e.g., a metal pillar or solder ball) between the conductive contact 3211 of the first chip 321 and the second pad 312 of the first redistribution layer 310.

[0068] For example, referring to FIG2, a second bottom filler layer 329 is filled between the first side of the first chip 321 and the first redistribution layer 310. This second bottom filler layer 329 fills the space between the first chip 321 and the first redistribution layer 310, which not only tightly bonds the first chip 321, solder joint 325, and first redistribution layer 310 together, but also reduces the stress generated on the solder joint 325 due to the CTE mismatch between the first chip 321 and the first redistribution layer 310, thereby improving the thermal fatigue life of the solder joint 325. For example, the material of the second bottom filler layer 329 includes, but is not limited to, epoxy resin.

[0069] As an example, the first chip 321 can be a processor or a System-on-a-Chip (SoC). Exemplarily, the processor or SoC can be a die or a packaged device.

[0070] For example, referring to FIG2, the second chip 323 has a first side and a second side. The first side of the second chip 323 has a transition solder ball 3233. The transition solder ball 3233 of the second chip 323 is connected to the third pad 313 of the first redistribution layer 310 through the second redistribution layer 324, thereby enabling the second chip 323 to transmit signals through the first redistribution layer 310. For example, referring to FIG2, a bonding process can be used to connect the transition solder ball 3233 of the second chip 323 to the fifth pad 3244 of the second redistribution layer 324. As an example, the second chip 323 has multiple transition solder balls 3233, multiple fifth pads 3244, and multiple fourth pads 3243. Each transition solder ball 3233 is connected to a fifth pad 3244 in a one-to-one correspondence. Each fifth pad 3244 is connected to the fourth pad 3243 in a one-to-one correspondence through a contact hole and a circuit wiring on the second conductive layer 3242.

[0071] For example, referring to FIG2, the second chip 323 may have a die 3231 and an adapter board 3232. The die 3231 is disposed on the adapter board 3232, and the adapter board 3232 has adapter solder balls 3233 on the side facing away from the die 3231. The die 3231 may be connected to the adapter board 3232 by wire bonding, thereby electrically connecting the die 3231 to the adapter solder balls 3233 through the adapter board. In other embodiments of this application, other bonding methods (e.g., hybrid bonding) may also be flexibly used to connect the die 3231 and the adapter board 3232. As an example, the second chip 323 may be a memory, and the die 3231 may be a memory die. In other embodiments of this application, the second chip 323 may also be directly set as a die. In addition, the third molding compound layer also wraps the leads connecting the die 3231 and the adapter board 3232.

[0072] For example, referring to FIG2, a first underfill layer 328 is filled between the second chip 323 and the second redistribution layer 324. This first underfill layer 328 fills the space between the second chip 323 and the second redistribution layer 324, which not only tightly bonds the second chip 323, the transition solder ball 3233, and the second redistribution layer 324 together, but also reduces the stress generated on the transition solder ball 3233 due to the CTE mismatch between the second chip 323 and the second redistribution layer 324, thereby improving the thermal fatigue life of the transition solder ball 3233. For example, the material of the first underfill layer 328 includes, but is not limited to, epoxy resin.

[0073] For example, referring to FIG2, the fourth pad 3243 and the third pad 313 can be interconnected via a vertical interconnect structure 326. Furthermore, the orthographic projections of the fourth pad 3243, the third pad 313, and the vertical interconnect structure 326 onto the first redistribution layer 310 do not overlap with the orthographic projection of the first chip 321 onto the first redistribution layer 310. The orthographic projection of the vertical interconnect structure 326 onto the first redistribution layer 310 is surrounded by the orthographic projection of the second molding compound layer 322, thereby disposing the vertical interconnect structure 326 within and penetrating the second molding compound layer 322. This allows one end of the vertical interconnect structure 326 to be connected to the third pad 313, and the other end to be connected to the fourth pad 3243. As an example, the vertical interconnect structure 326 may include metal pillars, including but not limited to copper pillars.

[0074] This application does not limit the CTE of the second molding compound 322. In specific implementations, the CTE of the second molding compound 322 can be flexibly designed according to the actual molding requirements to achieve different molding control. For example, to improve warpage, the CTE of the second molding compound 322 can be set to 7ppm / ℃ to 10ppm / ℃, such as 7ppm / ℃, 8ppm / ℃, 9ppm / ℃, 10ppm / ℃, etc. Exemplarily, to further improve warpage, the CTE of the first molding compound 330 is greater than the CTE of the second molding compound 322, which is beneficial for controlling warpage. In other embodiments of this application, the relationship between the CTE of the first molding compound 330 and the CTE of the second molding compound 322 can also be flexibly designed. For example, the CTE of the first molding compound 330 can be less than or equal to the CTE of the second molding compound 322.

[0075] This application does not limit the CTE of the third molding compound 381. In specific implementations, the CTE of the third molding compound 381 can be flexibly designed according to the actual molding requirements, thereby achieving different molding control. For example, to improve warpage, the CTE of the third molding compound 381 can be set to 7ppm / ℃ to 10ppm / ℃, such as 7ppm / ℃, 8ppm / ℃, 9ppm / ℃, 10ppm / ℃, etc. Exemplarily, to further improve warpage, the CTE of the first molding compound 330 can be greater than the CTE of the third molding compound 381, which is beneficial for controlling warpage. In other embodiments of this application, the relationship between the CTE of the first molding compound 330 and the CTE of the third molding compound 381 can also be flexibly designed. For example, the CTE of the first molding compound 330 can be less than or equal to the CTE of the third molding compound 381.

[0076] As an example, the CTE of the second molding layer 322 can also be made greater than the CTE of the third molding layer 381 to further improve warpage and improve package reliability.

[0077] This application does not limit the modulus of the second molding compound 322. In specific implementations, the modulus of the second molding compound 322 can be flexibly designed according to the actual warpage requirements, thereby achieving different warpage control. For example, to improve warpage, the modulus of the second molding compound 322 can be 10 GPa to 28 GPa, such as 10 GPa, 12 GPa, 15 GPa, 18 GPa, 20 GPa, 23 GPa, 25 GPa, 28 GPa, etc. Exemplarily, to further improve warpage, the relationship between the modulus of the second molding compound 322 and the modulus of the first molding compound 330 can be flexibly designed. For example, the modulus of the second molding compound 322 can be equal to, greater than, or less than the modulus of the first molding compound 330.

[0078] This application does not limit the modulus of the third molding compound 381. In specific implementations, the modulus of the third molding compound 381 can be flexibly designed according to the actual warpage requirements, thereby achieving different warpage control. For example, to improve warpage, the modulus of the third molding compound 381 can be 10 GPa to 28 GPa, such as 10 GPa, 12 GPa, 15 GPa, 18 GPa, 20 GPa, 23 GPa, 25 GPa, 28 GPa, etc. Exemplarily, to further improve warpage, the relationship between the modulus of the third molding compound 381 and the modulus of the first molding compound 330 can be flexibly designed. For example, the modulus of the third molding compound 381 can be equal to, greater than, or less than the modulus of the first molding compound 330.

[0079] The embodiments of this application do not limit the thickness of the second molding layer 322 and the third molding layer 381. In specific implementation, the thickness of the second molding layer 322 and the third molding layer 381 can be flexibly designed according to the object to be molded, thereby improving the reliability of molding.

[0080] This application does not limit the materials of the second molding layer 322 and the third molding layer 381. In specific implementations, the materials of the second molding layer 322 and the third molding layer 381 can be flexibly designed according to the actual object to be molded, thereby improving the reliability of the molding process. For example, the materials of the second molding layer 322 and the third molding layer 381 can be set to EMC.

[0081] It is worth mentioning that during the packaging process, the chip has a relatively small impact on warpage, while the molding compound has a relatively large impact on warpage. Based on this, by flexibly designing the relevant parameters (such as CTE, modulus, thickness, material, etc.) of the first molding compound 330, the second molding compound 322, and the third molding compound 381, warpage can be improved or even eliminated.

[0082] In some embodiments of this application, the semiconductor packaging structure in this application embodiment can be formed using FOPoP technology. That is, the semiconductor packaging structure in this application embodiment can be an FOPoP structure, thereby improving the performance, integration, and cost-effectiveness of the semiconductor packaging structure, and is suitable for various high-performance and high-integration application scenarios. For example, referring to FIG2, the semiconductor packaging structure in this application embodiment can be a chip-first structure in an FOPoP structure, that is, after forming the second redistribution layer 324, the first chip 321 is bonded to the second redistribution layer 324, and then the first redistribution layer 310 is formed. Based on this, a first adhesive layer 327 is provided between the second side of the first chip 321 and the second redistribution layer 324.

[0083] It is understood that, in order to clearly illustrate the semiconductor packaging structure in the embodiments of this application, the first chip 321 and the second chip 323 in FIG2 are each illustrated as one example. In other embodiments of this application, there may be multiple first chips 321, and these multiple first chips 321 can be stacked in the vertical direction. Similarly, there may be one or more dies 3231 in the second chip 323, and these multiple dies 3231 can be stacked in the vertical direction. Furthermore, in other embodiments of this application, the semiconductor packaging structure can be flexibly designed in terms of the number of first chips 321 and second chips 323 according to the needs of actual applications. For example, only the first chip 321 may be provided, without the second chip 323, thus the second chip 323 is not integrated inside the semiconductor packaging structure. Additionally, the vertical direction may be perpendicular to the layer where the first redistribution layer 310 is located.

[0084] In some embodiments of this application, all conductive bumps 350 can be connected to the circuit board 200 for signal transmission. Alternatively, only some conductive bumps 350 can be connected to the circuit board 200 for signal transmission, with passive devices connected to some of the conductive bumps 350. For example, referring to FIG2, a capacitor 360 is connected to some of the conductive bumps 350. In other embodiments of this application, resistors, inductors, and other devices can also be connected, and this is not limited thereto.

[0085] This application also provides a method for fabricating a semiconductor packaging structure, as shown in FIG14, including:

[0086] S1. A first redistribution layer and a chip structure layer are formed respectively. Exemplarily, the first redistribution layer includes opposing first and second surfaces, and the chip structure layer is located on the second surface of the first redistribution layer;

[0087] S2. Forming a first molding layer. Exemplarily, the first molding layer is located on the first surface of the first redistribution layer;

[0088] S3. Form a conductive interconnect structure. Exemplarily, the conductive interconnect structure extends through the first molding compound and is connected to a first pad in the first surface;

[0089] S4. Form conductive bumps. Exemplarily, the conductive bumps are located on the side of the first molding layer opposite to the first redistribution layer and are connected to the conductive interconnect structure.

[0090] It is worth noting that the embodiments of this application do not limit the order of steps S2 and S3. For example, step S3 can be performed after step S2, or step S2 can be performed after step S3.

[0091] The following describes in detail the fabrication process of the semiconductor packaging structure in the embodiments of this application, taking the semiconductor packaging structure shown in Figure 2 as an example, in conjunction with Figures 5 to 10.

[0092] Step 1, referring to Figure 5, uses suitable processes such as photolithography and electroplating to form a second redistribution layer 324 and a vertical interconnect structure 326 on the substrate 410. Then, an adhesive layer is used to bond the first chip 321 to the second redistribution layer 324. Next, a suitable process such as molding or flow molding is used to form a second molding compound 322, and a process such as chemical mechanical polishing (CMP) is used to expose the first chip 321. Then, a suitable process such as photolithography and electroplating is used to form a first redistribution layer 310, and the first chip 321 is connected to the first pad 311 on the first redistribution layer 310.

[0093] Step 2, referring to FIG6, the support substrate 421 is bonded to the side of the first redistribution layer 310 opposite to the second redistribution layer 324 using adhesive 422, and then the substrate 410 is removed. Afterwards, a groove 431 is formed, exposing the fifth pad 3244. Exemplarily, the adhesive 422 includes, but is not limited to, epoxy resin, dry film, benzocyclobutene, polyimide, and UV-curable compounds. The support substrate 421 includes, but is not limited to, a glass plate.

[0094] Step 3, referring to Figure 7, bond the second chip 323 to the fifth pad 3244 and mount the second chip 323. Then, fill the space between the second chip 323 and the second redistribution layer 324 with a first underfill layer 328. Next, using a suitable process such as molding or flow molding, cover the second chip 323 with a third molding layer 381 to encapsulate the second chip 323.

[0095] Step 4, referring to Figure 8, remove the support substrate 421 and adhesive 422 to expose the first pad 311. Then, using a suitable process such as electroplating, form a conductive interconnect structure 340 (e.g., a copper pillar) on the first pad 311.

[0096] Step 5, referring to Figure 9, using a suitable process such as compression molding or flow molding, cover the side of the first redistribution layer 310 with the conductive interconnect structure 340 (e.g., copper pillars) with a first molding compound 330, and use a process such as CMP to polish and expose the conductive interconnect structure 340 (e.g., copper pillars).

[0097] Step 6, referring to Figure 10, capacitor 360 and solder balls 351 are formed through under bump metallization (UBM) process, surface mounted technology (SMT) process, and ball-mounting process.

[0098] Figure 11 is a schematic diagram of another semiconductor packaging structure in an embodiment of this application. Referring to Figure 11, this embodiment modifies the implementation method in the above embodiments. The similarities are not repeated here. The difference is that the semiconductor packaging structure in this embodiment can be the chip last structure in the FOPoP structure. That is, after forming the first redistribution layer 310, the first chip 321 is bonded to the second pad 312 on the first redistribution layer 310, and then the second redistribution layer 324 is formed. Based on this, in order to improve the heat dissipation effect of the first chip 321, a heat sink 371 can be provided on the second side of the first chip 321. It is understood that in other embodiments of this application, the heat sink 371 may not be provided.

[0099] For example, referring to FIG11, a second adhesive layer 372 can be provided between the heat sink 371 and the first chip 321 to adhere the heat sink 371 to the first chip 321. As an example, the heat sink 371 is a silicon wafer, which can achieve high thermal conductivity, achieve good heat dissipation, and also has the advantages of high strength and corrosion resistance, which can extend the service life of the heat sink 371. In other embodiments of this application, the heat sink 371 can also be made of other materials, which are not limited here.

[0100] To further reduce the height of the semiconductor package structure, when setting the heat sink 371, referring to Figure 11, a slot is made in a part of the second redistribution layer 324 to form a hollow area BQ. The heat sink 371 is set in the hollow area BQ. The heat sink 371 can be integrated inside the semiconductor package structure without increasing the overall height of the semiconductor package structure, thereby improving the heat dissipation effect.

[0101] For example, the orthographic projection of the heat sink 371 onto the first redistribution layer 310 may fall within the orthographic projection of the first chip 321 onto the first redistribution layer 310; alternatively, the orthographic projection of the heat sink 371 onto the first redistribution layer 310 may coincide with the orthographic projection of the first chip 321 onto the first redistribution layer 310; or alternatively, the orthographic projection of the first chip 321 onto the first redistribution layer 310 may fall within the orthographic projection of the heat sink 371 onto the first redistribution layer 310. Therefore, the form of the heat sink 371 can be flexibly designed to meet the needs of semiconductor packaging structures of different sizes.

[0102] For example, the orthographic projection of the cutout region BQ onto the first redistribution layer 310 can fall within the orthographic projection of the first chip 321 onto the first redistribution layer 310. In order to further improve the strength and reliability of the semiconductor packaging structure, referring to FIG11, the second molding layer 322 also covers the surface of the second side of the first chip 321 that is not covered by the heat sink 371.

[0103] For example, in order to further improve the strength and reliability of the semiconductor package structure, the first bottom filler layer 328 may also wrap the heat sink 371 and the second adhesive layer 372.

[0104] The fabrication process for forming the semiconductor package structure shown in Figure 11 can be obtained by modifying steps 1 to 6 in the above embodiments. The similarities in the fabrication process will not be repeated here. The differences will be explained below with reference to Figures 12 and 13.

[0105] Step 1, referring to Figure 12, uses suitable processes such as photolithography and electroplating to form a first redistribution layer 310 and a vertical interconnect structure 326 on the substrate 410. Then, the first chip 321 is bonded to the second pad 312 on the first redistribution layer 310. Next, a second molding compound 322 is formed. Then, using suitable processes such as photolithography and electroplating, a second redistribution layer 324 is formed. Then, a laser process is used to create grooves in the second redistribution layer 324, exposing at least a portion of the surface of the second side of the first chip 321.

[0106] Step 2, referring to Figure 13, attach the heat sink 371 to the first chip 321 through the second adhesive layer 372.

[0107] The above description is only a specific implementation of this application, but the protection scope of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the protection scope of this application.

Claims

1. A semiconductor package structure, comprising: include: The first redistribution layer includes opposing first and second surfaces; A chip structure layer is located on the second surface of the first redistribution layer; A first molding layer is located on the first surface of the first redistribution layer; A conductive interconnect structure extends through the first molding layer and is connected to a first pad in the first surface; The conductive bump is located on the side of the first molding layer opposite to the first redistribution layer and is connected to the conductive interconnect structure.

2. The semiconductor packaging structure according to claim 1, characterized in that, The coefficient of thermal expansion of the first molding compound is 7 ppm / ℃ to 10 ppm / ℃; or, The modulus of the first molding layer is 10 GPa to 28 GPa.

3. The semiconductor packaging structure according to claim 1 or 2, characterized in that, The conductive interconnect structure includes metal pillars.

4. The semiconductor packaging structure according to claim 3, characterized in that, The metal pillars include copper pillars.

5. The semiconductor packaging structure according to any one of claims 1-4, characterized in that, The conductive bumps include one or a combination of copper pillars, microbumps, and solder balls.

6. The semiconductor packaging structure according to any one of claims 1-5, characterized in that, The chip structure layer includes a first chip and a second molding layer; The first chip is located on the second surface of the first redistribution layer, and the first chip is connected to the second pad in the second surface; The second molding layer covers at least the sides of the first chip.

7. The semiconductor packaging structure according to claim 6, characterized in that, The coefficient of thermal expansion of the first molding layer is greater than that of the second molding layer.

8. The semiconductor packaging structure according to claim 6 or 7, characterized in that, The chip structure layer also includes a second chip, a second redistribution layer, and a third molding layer; The second redistribution layer is located on the side of the first chip opposite to the first redistribution layer; The second chip is located on the side of the second redistribution layer opposite to the first redistribution layer, and the second chip is connected to the third pad in the second surface through the second redistribution layer; The third molding layer covers the side of the second chip facing away from the second redistribution layer.

9. The semiconductor packaging structure according to claim 8, characterized in that, The coefficient of thermal expansion of the first molding compound is greater than that of the third molding compound; or, the coefficient of thermal expansion of the second molding compound is greater than that of the third molding compound.

10. The semiconductor packaging structure according to claim 8 or 9, characterized in that, The first chip has a first side and a second side opposite to each other. The first side has a conductive contact connected to the second pad, and the second side has a first adhesive layer between itself and the second redistribution layer.

11. The semiconductor packaging structure according to claim 8 or 9, characterized in that, The first chip has a first side and a second side opposite to each other. The first side has a conductive contact connected to the first redistribution layer, and the second side has a heat sink.

12. The semiconductor packaging structure according to claim 11, characterized in that, The second redistribution layer has a hollowed-out area, and the heat sink is disposed in the hollowed-out area.

13. A method for fabricating a semiconductor packaging structure, characterized in that, include: A first redistribution layer and a chip structure layer are formed respectively. The first redistribution layer includes a first surface and a second surface opposite to each other. The chip structure layer is located on the second surface of the first redistribution layer. A first molding layer is formed, the first molding layer being located on the first surface of the first redistribution layer; A conductive interconnect structure is formed, which penetrates the first molding layer and is connected to a first pad in the first surface; Conductive bumps are formed on the side of the first molding layer opposite to the first redistribution layer and are connected to the conductive interconnect structure.

14. The method according to claim 13, characterized in that, The formation of the conductive interconnect structure includes: The conductive interconnect structure is formed using an electroplating process.

15. The method according to claim 13 or 14, characterized in that, The formation of the first molding layer includes: The first encapsulation layer is formed using compression molding or flow molding processes.

16. An electronic device, characterized in that, include: A circuit board and a semiconductor package structure, wherein the semiconductor package structure is disposed on the circuit board; The semiconductor packaging structure is the semiconductor packaging structure as described in any one of claims 1-12, or the semiconductor packaging structure is a semiconductor packaging structure prepared by the method described in any one of claims 13-15.

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