Semiconductor device and manufacturing method therefor, and electronic device
By forming cavities and porous semiconductor pillars within the substrate, the impact of minute differences in integrated circuits on device performance was resolved, enabling the growth of higher-density memory cell arrays and thicker epitaxial layers, thereby improving device performance.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- BEIJING SUPERSTRING ACAD OF MEMORY TECH
- Filing Date
- 2025-07-14
- Publication Date
- 2026-05-21
AI Technical Summary
In integrated circuit technology, as the critical dimensions of devices shrink, the impact of minute differences on device performance becomes increasingly significant. How to increase the number of devices on a finite substrate and reduce mismatch dislocations and through dislocations, and increase the critical thickness of the epitaxial layer, has become a challenge.
By forming cavities within the substrate, the effective thickness of the substrate is reduced. By employing porous semiconductor pillars and buffer layers, stress is released, lattice mismatch is accommodated, and thicker epitaxial layers are supported for the growth of multilayer memory cell arrays.
This technology enables flexible substrates, reduces mismatch dislocations and through dislocations, supports the growth of thicker epitaxial layers, increases the number of stacked layers, and enhances device performance.
Smart Images
Figure CN2025108455_21052026_PF_FP_ABST
Abstract
Description
A semiconductor device and its manufacturing method, and an electronic device.
[0001] This application claims priority to Chinese Patent Application No. 202411630324.3, filed on November 14, 2024, entitled "A Semiconductor Device and a Method for Manufacturing the Same Thereof, and an Electronic Device", the contents of which shall be construed as incorporated herein by reference. Technical Field
[0002] This disclosure relates to, but is not limited to, device design and manufacturing in the field of semiconductor technology, and particularly to a semiconductor device and its manufacturing method, and electronic equipment. Background Technology
[0003] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.
[0004] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention
[0005] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.
[0006] This application provides a semiconductor device, including: a substrate and a multilayer memory cell array stacked on the substrate in a direction perpendicular to the substrate;
[0007] The substrate includes a base, a plurality of semiconductor pillars extending perpendicular to the base and spaced apart on the base, and a buffer layer disposed on the side of the plurality of semiconductor pillars facing away from the base; the buffer layer covers the surface of the plurality of semiconductor pillars facing away from the base; the plurality of semiconductor pillars and the base form an integral structure; a cavity is formed between the surface of the buffer layer facing the base, the surface of the base facing the buffer layer, and the sidewalls of the plurality of semiconductor pillars; the multilayer memory cell array is disposed on the side of the buffer layer facing away from the semiconductor pillars.
[0008] In some embodiments, a plurality of semiconductor pillars are arrayed along a first direction parallel to the substrate and a second direction parallel to the substrate, and the cavity includes a plurality of first trenches extending along the first direction and a plurality of second trenches extending along the second direction, spaced apart from the plurality of semiconductor pillars, wherein the first direction and the second direction intersect.
[0009] In some embodiments, the height of the semiconductor pillar is 9 micrometers to 13 micrometers, and the aspect ratios of both the first trench and the second trench are greater than 13.
[0010] In some embodiments, the semiconductor pillar is a solid structure or a porous structure.
[0011] In some embodiments, the porosity of the porous structure is 35% to 75%.
[0012] In some embodiments, the buffer layer comprises silicon, silicon-germanium, or tin-germanium.
[0013] This disclosure provides a method for manufacturing a semiconductor device, including:
[0014] Provide the initial base;
[0015] The initial substrate is etched to form a substrate and a plurality of spaced semiconductor pillars disposed on the substrate and extending in a direction perpendicular to the substrate;
[0016] A buffer layer film is epitaxially grown on the surface of a plurality of semiconductor pillars away from the substrate, and the buffer layer films epitaxially grown on different semiconductor pillars are connected to each other to form a buffer layer, and a cavity is formed between the surface of the buffer layer facing the substrate, the surface of the substrate facing the buffer layer, and the sidewalls of the plurality of semiconductor pillars.
[0017] A multilayer storage cell array is formed on the buffer layer, stacked along a direction perpendicular to the substrate.
[0018] In some embodiments, etching the initial substrate to form a substrate and a plurality of spaced semiconductor pillars disposed on the substrate and extending in a direction perpendicular to the substrate includes:
[0019] The initial substrate is etched to form a plurality of first trenches extending along a first direction parallel to the initial substrate and a plurality of second trenches extending along a second direction parallel to the initial substrate, thereby forming the substrate and a plurality of semiconductor pillars disposed on the substrate extending along a direction perpendicular to the substrate; the plurality of first trenches are spaced apart along the second direction, the plurality of second trenches are spaced apart along the first direction, and the first direction and the second direction intersect.
[0020] In some embodiments, before epitaxially growing buffer layer films on the surfaces of the plurality of semiconductor pillars away from the substrate and connecting the epitaxially grown buffer layer films on different semiconductor pillars to form a buffer layer, the method further includes: processing the semiconductor pillars to form a porous structure.
[0021] In some embodiments, forming a multilayer memory cell array stacked along a direction perpendicular to the substrate on the buffer layer includes:
[0022] A stacked structure comprising multiple alternately stacked semiconductor structure layers and sacrificial layers is formed on the buffer layer;
[0023] The multi-layer storage cell array is formed based on the stacked structure;
[0024] The buffer layer and the sacrificial layer are both made of silicon and germanium, and the concentration of germanium in the buffer layer is equal to the concentration of germanium in the sacrificial layer * the thickness of the sacrificial layer / (the thickness of the semiconductor structure layer + the thickness of the sacrificial layer).
[0025] This disclosure provides an electronic device, including any of the semiconductor devices described above, or a semiconductor device formed by a manufacturing method of any of the semiconductor devices described above.
[0026] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings.
[0027] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.
[0028] Overview of the attached figures
[0029] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.
[0030] Figure 1 is a schematic cross-sectional view of the semiconductor device provided in the embodiment of this disclosure along the direction perpendicular to the substrate;
[0031] Figure 2 is a schematic cross-sectional view of a semiconductor device provided in another embodiment along the direction perpendicular to the substrate;
[0032] Figure 3A is a top view of a semiconductor device provided in some embodiments (only a portion of the film layer is shown), and Figure 3B is a schematic cross-section of a semiconductor device provided in some embodiments, perpendicular to the substrate.
[0033] Figure 4 is a schematic cross-sectional view of the initial substrate provided in some embodiments;
[0034] Figure 5 is a schematic cross-sectional view of the semiconductor pillars after they have been formed, along the direction perpendicular to the substrate, according to some embodiments.
[0035] Figure 6 is a schematic cross-sectional view of the epitaxially grown buffer layer film provided in some embodiments, along the direction perpendicular to the substrate.
[0036] Figure 7 is a schematic cross-sectional view of the buffer layer after it has been formed in some embodiments, along the direction perpendicular to the substrate.
[0037] Figure 8 is a schematic cross-sectional view of the stacked structure after it has been formed along the direction perpendicular to the substrate, according to some embodiments.
[0038] Figure 9A is a cross-sectional view along the direction parallel to the substrate after the semiconductor layer is formed according to some embodiments, and Figure 9B is a schematic cross-sectional view along the direction perpendicular to the substrate after the semiconductor layer is formed according to some embodiments.
[0039] Figure 10A is a cross-sectional view along the direction parallel to the substrate after the support layer is formed according to some embodiments, and Figure 10B is a schematic cross-sectional view along the direction perpendicular to the substrate after the support layer is formed according to some embodiments.
[0040] Figure 11 is a schematic cross-sectional view of the section perpendicular to the substrate after the sacrificial layer has been removed, according to some embodiments;
[0041] Figure 12A is a top view (only a portion of the film layers) after the formation of the gate insulating layer, word line and first insulating layer according to some embodiments; Figure 12B is a cross-sectional schematic diagram along the direction perpendicular to the substrate after the formation of the gate insulating layer, word line and first insulating layer according to some embodiments.
[0042] Figure 13A is a top view (only a portion of the film layer is shown) after forming the dielectric layer, the second capacitor electrode, and the second insulating layer according to some embodiments. Figure 13B is a cross-sectional schematic diagram along the direction perpendicular to the substrate after forming the dielectric layer, the second capacitor electrode, and the second insulating layer according to some embodiments.
[0043] Figure 14 is a cross-sectional view of the semiconductor pillars forming a porous structure along the direction perpendicular to the substrate provided in some embodiments;
[0044] Figure 15 is a schematic cross-sectional view of a semiconductor device provided in some embodiments along a direction perpendicular to the substrate.
[0045] Detailed Explanation
[0046] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments of this disclosure and the features thereof can be combined arbitrarily with each other.
[0047] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains.
[0048] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values shown in the drawings.
[0049] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.
[0050] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the disclosure is not limited to the terms used herein and may be appropriately replaced as appropriate.
[0051] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to physical or signal connections, contact or integral connections; direct connections, indirect connections via intermediate components, or internal communication between two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure according to the specific circumstances.
[0052] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.
[0053] In this disclosure, "connection" includes the situation where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.
[0054] In this disclosure, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.
[0055] In this embodiment of the disclosure, "A and B are an integral structure" can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected membrane layers on a single membrane layer. For example, A and B may be formed using the same material as a single membrane layer and simultaneously created through the same patterning process, resulting in a structure with interconnected relationships.
[0056] When epitaxially stacking silicon / silicon-germanium (Si / SiGe) layers on a conventional silicon substrate, the entire stack is subjected to compressive stress from the substrate due to lattice mismatch. As the number of stacks increases, stress accumulates. When the stress reaches its maximum, it is released through the generation of mismatch or through-dislocations, affecting device performance. In this embodiment, by forming a cavity in the substrate, the effective thickness of the substrate is reduced, stress is released, mismatch dislocations and through-dislocations are reduced, and the growth of thicker epitaxial layers is supported, i.e., the critical thickness of the epitaxial layer is increased.
[0057] Figure 1 is a schematic diagram of a semiconductor device provided in an embodiment of this disclosure. As shown in Figure 1, an embodiment of this disclosure provides a semiconductor device, including: a substrate 10 and a multilayer memory cell array 20 stacked on the substrate 10 along a direction perpendicular to the substrate 10; the substrate 10 may include a base 1, a plurality of semiconductor pillars 2 disposed on the base 1 extending along a direction perpendicular to the base 1 and spaced apart, and a buffer layer 3 disposed on the side of the plurality of semiconductor pillars 2 facing away from the base 1; the buffer layer 3 covers the surface of the plurality of semiconductor pillars 2 facing away from the base 1. The plurality of semiconductor pillars 2 form an integral structure with the base 1, and cavities are formed between the surface of the buffer layer 3 facing the base 1, the surface of the base 1 facing the buffer layer 3, and the sidewalls of the plurality of semiconductor pillars 2; the multilayer memory cell array 20 is disposed on the side of the buffer layer 3 facing away from the semiconductor pillars 2. The buffer layer 3 may extend in a direction parallel to the base 1. The buffer layer 3 forms a planar film layer and extends continuously on the surface of the plurality of semiconductor pillars 2 facing away from the base 1. The buffer layer 3 does not cover the sidewalls of the semiconductor pillars 2. The space between the semiconductor pillars 2 is not filled by the buffer layer 3, thus forming a cavity.
[0058] The solution provided in this disclosure reduces the effective thickness of the substrate and lowers its rigidity by forming a cavity in the substrate, thereby achieving a flexible substrate that can be slightly deformed to release the stress of the epitaxial layer, adapt to lattice mismatch with the stacked layers, reduce mismatch dislocations and through dislocations, reduce dislocation density, and can support the growth of thicker epitaxial layers, increase the critical thickness of the stacked layers, and increase the number of stacked layers.
[0059] In some embodiments, a plurality of semiconductor pillars 2 are arranged in an array along a first direction X parallel to the substrate 1 and a second direction Y parallel to the substrate 1. The cavity includes a plurality of first trenches extending along the first direction X and a plurality of second trenches extending along the second direction Y, spaced apart from the plurality of semiconductor pillars 2. The first direction X and the second direction Y intersect. In some embodiments, the first direction X and the second direction Y are perpendicular. The plurality of first trenches are spaced apart along the second direction Y, and the plurality of second trenches are spaced apart along the first direction X.
[0060] In some embodiments, the height of the semiconductor pillar 2 (i.e., the dimension along the direction perpendicular to the substrate 1) can be 9 micrometers to 13 micrometers.
[0061] In some embodiments, the aspect ratios of both the first and second trenches can be greater than 13. This dimension effectively reduces stress.
[0062] In some embodiments, the buffer layer 3 may be silicon, silicon germanium (SiGe), tin germanium (SnGe), etc.
[0063] In some embodiments, the semiconductor pillar 2 can be a solid structure (as shown in Figure 1) or a porous structure. A porous semiconductor pillar 2 is shown in Figure 2. When the semiconductor pillar 2 is a porous structure, the rigidity of the substrate 10 can be further reduced, stress can be better released, mismatch dislocations and through dislocations can be reduced, the critical thickness of the stack can be increased, and the number of stacked layers can be increased.
[0064] In some embodiments, the porosity of the porous semiconductor pillar 2 can be from 35% to 75%. This porosity can better balance the need to reduce the rigidity of the substrate 10 and maintain the strength of the semiconductor pillar 2. For example, the porosity can be 40%, 50%, or 70%. However, the embodiments disclosed herein are not limited to this, and the porosity can be other than 35% to 75%.
[0065] Figure 3A is a top view of a semiconductor device provided in some embodiments (only showing a portion of the film layers), and Figure 3B is a cross-sectional schematic diagram of a semiconductor device provided in some embodiments along a direction perpendicular to the substrate 1. As shown in Figures 3A and 3B, in this embodiment, each layer of the multilayer memory cell array 20 may include: a plurality of memory cells distributed along a first direction X and a second direction Y. The memory cells may include transistors and capacitors. The transistors may include: a semiconductor layer 23 extending along a direction parallel to the substrate 1. The memory cell array may also include word lines 40 surrounding the semiconductor layer 23, a gate insulating layer 24 disposed between the semiconductor layer 23 and the word lines 40, a second capacitor electrode 42 surrounding the semiconductor layer 23, and a dielectric layer 43 disposed between the semiconductor layer 23 and the second capacitor electrode 42. The multilayer memory cell array may also include: a plurality of bit lines 30 extending along a direction perpendicular to the substrate 1 and penetrating the multilayer memory cells, the bit lines 30 being connected to the sidewalls of the multilayer semiconductor layer 23; the word lines 40 extend along the second direction Y and surround a column of semiconductor layers 23 distributed along the second direction Y. The memory cell arrays shown in Figures 3A and 3B are merely examples. The embodiments disclosed herein are not limited thereto; the substrate 10 can serve as the substrate for various memory cell arrays, such as a 2T0C memory cell array.
[0066] This disclosure provides a method for manufacturing a semiconductor device, which may include:
[0067] Provide the initial base;
[0068] The initial substrate is etched to form a substrate and a plurality of spaced semiconductor pillars disposed on the substrate and extending in a direction perpendicular to the substrate;
[0069] A buffer layer film is epitaxially grown on the surface of a plurality of semiconductor pillars away from the substrate, and the buffer layer films epitaxially grown on different semiconductor pillars are connected to each other to form a buffer layer, and a cavity is formed between the surface of the buffer layer facing the substrate, the surface of the substrate facing the buffer layer, and the sidewalls of the plurality of semiconductor pillars.
[0070] A multilayer storage cell array is formed on the buffer layer, stacked along a direction perpendicular to the substrate.
[0071] In some embodiments, etching the initial substrate to form a substrate and a plurality of spaced semiconductor pillars disposed on the substrate and extending in a direction perpendicular to the substrate may include:
[0072] The initial substrate is etched to form a plurality of first trenches extending along a first direction parallel to the initial substrate and a plurality of second trenches extending along a second direction parallel to the initial substrate, thereby forming the substrate and a plurality of semiconductor pillars disposed on the substrate extending along a direction perpendicular to the substrate; the plurality of first trenches are spaced apart along the second direction, the plurality of second trenches are spaced apart along the first direction, and the first direction and the second direction intersect.
[0073] In some embodiments, before epitaxially growing buffer layer films on the surfaces of the plurality of semiconductor pillars opposite to the substrate and connecting the epitaxially grown buffer layer films on different semiconductor pillars to form a buffer layer, the process may further include: treating the semiconductor pillars to form a porous structure. The treatment may be an electrochemical etching of the semiconductor pillars.
[0074] In some embodiments, forming a multilayer memory cell array stacked along a direction perpendicular to the substrate on the buffer layer may include:
[0075] A stacked structure comprising multiple alternately stacked semiconductor structure layers and sacrificial layers is formed on the buffer layer;
[0076] The multi-layer storage cell array is formed based on the stacked structure;
[0077] The buffer layer and the sacrificial layer are both made of silicon and germanium, and the concentration of germanium in the buffer layer is equal to the concentration of germanium in the sacrificial layer * the thickness of the sacrificial layer / (the thickness of the semiconductor structure layer + the thickness of the sacrificial layer).
[0078] The technical solution of this embodiment is further illustrated below through the manufacturing process of the semiconductor device in this embodiment. In this embodiment, the "patterning process" may include deposition of a film layer, coating with photoresist, mask exposure, development, etching, and photoresist stripping, which are mature manufacturing processes in related technologies. The "photolithography process" mentioned in this embodiment includes coating of a film layer, mask exposure, and development, which are mature manufacturing processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film of a certain material manufactured on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or photolithography process during the entire manufacturing process, it can also be called a "layer." If the "thin film" requires a patterning process or photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or photolithography process contains at least one "pattern."
[0079] In one exemplary embodiment, the manufacturing process of the semiconductor device may include:
[0080] 1) Provide an initial substrate 1', as shown in Figure 4, which is a cross-sectional schematic diagram of the initial substrate 1' provided in some embodiments.
[0081] In some embodiments, the initial substrate 1' is, for example, a silicon substrate.
[0082] 2) Form semiconductor pillar 2;
[0083] The initial substrate 1' is patterned to form a first trench T1 extending along a first direction X and a second trench T2 extending along a second direction Y. The depth of the first trench T1 (not shown in the figure) and the second trench T2 is less than the thickness of the initial substrate 1', such that the initial substrate 1' forms a substrate 1 and a plurality of semiconductor pillars 2 disposed on the substrate 1 extending in a direction perpendicular to the substrate 1; as shown in FIG5, FIG5 is a cross-sectional schematic diagram along the direction perpendicular to the substrate 1 after the semiconductor pillars 2 are formed according to some embodiments.
[0084] 3) Epitaxial growth of buffer layer film;
[0085] A buffer layer film is epitaxially grown on the surface of the semiconductor pillar 2 away from the substrate 1 to form a buffer sublayer 3'. The buffer layer films epitaxially grown on different semiconductor pillars 2 are connected to each other to close the first trench T1 and the second trench T2 (that is, formed at the opening of the first trench T1 and the second trench T2, but not formed inside the first trench T1 and the second trench T2, and the first trench T1 and the second trench T2 are retained to form a cavity), as shown in Figure 6. Figure 6 is a cross-sectional schematic diagram along the direction perpendicular to the substrate 1 after epitaxial growth of the buffer layer film provided in some embodiments.
[0086] In some embodiments, the material of the buffer layer film may be the same as one of the semiconductor layers and sacrificial layers that are alternately stacked during the subsequent fabrication of the memory cell array. For example, if silicon and silicon-germanium are subsequently stacked alternately, the buffer layer film may be silicon or silicon-germanium.
[0087] In some embodiments, the epitaxially grown buffer layer film can be grown at a low temperature, which can be less than 600°C. Low-temperature epitaxial growth can yield a buffer layer of better quality.
[0088] In some embodiments, the buffer layer film may be SiGe, and the germanium concentration in the buffer layer film can be determined based on the thickness of the subsequently alternately stacked semiconductor structure layer 23' and sacrificial layer 12, and the germanium concentration in the sacrificial layer 12. In some embodiments, the germanium concentration in the buffer layer film = germanium concentration in the sacrificial layer 12 * sacrificial layer 12 thickness / (semiconductor structure layer 23' thickness + sacrificial layer 12 thickness). Taking a semiconductor structure layer 23' as Si, a sacrificial layer 12 as SiGe, a semiconductor structure layer 23' thickness of 50 nanometers (nm), a sacrificial layer 12 thickness of 10 nm, and a Ge concentration of 0.25 in the sacrificial layer 12 as an example, the germanium concentration in the buffer layer film = 0.25 * 10 / (50 + 10) ≈ 0.04, or approximately 4%.
[0089] 4) Forming buffer layer 3;
[0090] Continue to epitaxially grow a buffer layer film on the buffer sublayer 3' to a preset thickness, for example, the thickness of the buffer layer film can be greater than or equal to 1 micrometer; at this time, the Ge concentration in the epitaxially grown buffer layer film is the same as the Ge concentration in the buffer layer film in step 3).
[0091] The buffer layer film is ground flat to form buffer layer 3; as shown in Figure 7, Figure 7 is a cross-sectional schematic diagram of the buffer layer 3 after it is formed in some embodiments along the direction perpendicular to the substrate 1.
[0092] In some embodiments, smoothing can be chemical mechanical polishing (CMP) to obtain a smooth and flat surface.
[0093] 5) Form multiple alternating stacked semiconductor structure layers 23' and sacrificial layers 12;
[0094] Semiconductor thin films and sacrificial thin films are epitaxially grown alternately on the buffer layer 3 to form a stacked structure including multiple alternately arranged semiconductor structure layers 23' and sacrificial layers 12, as shown in FIG8. FIG8 is a cross-sectional schematic diagram along the direction perpendicular to the substrate 1 after the stacked structure is formed according to some embodiments.
[0095] In some embodiments, the semiconductor structure layer 23' may include silicon, the sacrificial layer 12 may include silicon germanium, and the concentration of germanium in the sacrificial layer 12 may be greater than the concentration of germanium in the buffer layer 3, for example, 30% to 50% of the concentration of germanium in the sacrificial layer 12.
[0096] 6) Forming semiconductor layer 23;
[0097] The stacked structure is patterned to form a plurality of third trenches T3. The third trenches T3 penetrate the stacked structure along a direction perpendicular to the substrate 1 and extend along a first direction X. The semiconductor structure layer 23' is divided into a plurality of semiconductor layers 23 by the plurality of third trenches T3, as shown in Figures 9A and 9B. Figure 9A is a cross-sectional view along a direction parallel to the substrate 1 after the semiconductor layer 23 is formed according to some embodiments. Figure 9B is a cross-sectional schematic diagram along a direction perpendicular to the substrate 1 after the semiconductor layer 23 is formed according to some embodiments.
[0098] 7) Form a support layer 13;
[0099] The stacked structure is patterned to form a plurality of fourth trenches T4. The fourth trenches T4 penetrate the stacked structure along a direction perpendicular to the substrate 1 and extend along the second direction Y. Two columns of storage cells are defined between two adjacent fourth trenches T4 along the first direction X.
[0100] Based on the fourth trench T4, the sacrificial layer 12 is etched laterally (along a direction parallel to the substrate 10) to form a lateral trench T41;
[0101] A support layer film is deposited, which fills the fourth trench T4 and the transverse trench T41 to form a support layer 13; as shown in Figures 10A and 10B, Figure 10A is a cross-sectional view along the direction parallel to the substrate 1 after the support layer 13 is formed according to some embodiments, and Figure 10B is a cross-sectional schematic diagram along the direction perpendicular to the substrate 1 after the support layer 13 is formed according to some embodiments.
[0102] In some embodiments, the support layer film may be a low-K dielectric layer, such as silicon nitride (SiN).
[0103] 8) Remove sacrificial layer 12;
[0104] Based on the third trench T3 etching, the sacrificial layer 12 between adjacent semiconductor layers 23 along the direction perpendicular to the substrate 1 is removed, as shown in FIG11. FIG11 is a cross-sectional schematic diagram along the direction perpendicular to the substrate 1 after the removal of the sacrificial layer 12 provided in some embodiments.
[0105] At this time, the two sidewalls of the semiconductor layer 23 parallel to the substrate 1 and the two sidewalls perpendicular to the substrate 1 are exposed.
[0106] 9) Forming gate insulating layer 24, word line 40 and first insulating layer 14;
[0107] A gate insulating film, a first conductive film, and a first insulating film are sequentially deposited, and a gate insulating layer 24, a word line 40, and a first insulating layer 14 are etched to form them. The gate insulating layer 24 surrounds the semiconductor layer 23, and the word line 40 surrounds the semiconductor layer 23. The first insulating layer 14 fills the region between adjacent word lines 40 along a direction perpendicular to the substrate 1, as shown in Figures 12A and 12B. Figure 12A is a top view (only a portion of the film layers) after the formation of the gate insulating layer 24, word line 40, and first insulating layer 14 according to some embodiments. Figure 12B is a cross-sectional schematic diagram along a direction perpendicular to the substrate 1 after the formation of the gate insulating layer 24, word line 40, and first insulating layer 14 according to some embodiments.
[0108] In some embodiments, the gate insulating layer 24 may comprise one or more high-K dielectric materials, such as dielectric materials with a dielectric constant K ≥ 3.9. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, it may include, but is not limited to, at least one of the following high-K materials: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc.
[0109] In some embodiments, the first conductive film may be one or more of the following different types of materials:
[0110] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can be a metal alloy containing these metals.
[0111] Alternatively, it can be conductive metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as conductive metal oxide materials like indium tin oxide (ITO), indium zinc oxide (IZO), and indium oxide (InO); or conductive metal nitride materials like titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN).
[0112] Alternatively, it could be polycrystalline silicon, silicon, germanium, silicon-germanium, etc., which become conductive after doping.
[0113] The materials of the second and third conductive films are similar to those of the first conductive film, and will not be described in detail here.
[0114] In some embodiments, the first insulating film may be a low-K dielectric layer with an etching selectivity ratio to the support layer film, i.e., a dielectric layer with a dielectric constant K < 3.9, including but not limited to silicon oxide, such as silicon dioxide (SiO2). The subsequent second insulating film material is similar to the first insulating film material and will not be described further.
[0115] 10) Forming a dielectric layer 43, a second capacitor electrode 42, and a second insulating layer 15;
[0116] A dielectric thin film, a second conductive thin film, and a second insulating thin film are sequentially deposited to form a dielectric layer 43, a second capacitor electrode 42, and a second insulating layer 15. The dielectric layer 43 surrounds the semiconductor layer 23, the second capacitor electrode 42 surrounds the semiconductor layer 23, and the second insulating layer 15 fills the region between adjacent second capacitor electrodes 42 along a direction perpendicular to the substrate 1. The semiconductor layer 23 may include a first region, a channel region, and a second region sequentially distributed along a first direction X. The word line 40 surrounds the channel region of the semiconductor layer 23, and the second capacitor electrode 42 surrounds the first region of the semiconductor layer 23, as shown in Figures 13A and 13B. Figure 13A is a top view (only showing a portion of the film layers) after forming the dielectric layer 43, the second capacitor electrode 42, and the second insulating layer 15 according to some embodiments. Figure 13B is a cross-sectional schematic diagram along a direction perpendicular to the substrate 1 after forming the dielectric layer 43, the second capacitor electrode 42, and the second insulating layer 15 according to some embodiments.
[0117] In some embodiments, a conductive thin film may be deposited on the surface of the semiconductor layer 23 to form a first capacitor electrode, and then the dielectric layer 43 and the second capacitor electrode 42 may be formed in sequence. This application does not limit this.
[0118] In some embodiments, the dielectric layer 43 may be a Low-K material, such as silicon oxide. Alternatively, it may be a High-K material, such as a dielectric material with a dielectric constant K ≥ 3.9. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, it may include, but is not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and other high-K materials.
[0119] 11) Forming bit line 30;
[0120] A hole K1 is formed through the stacked structure in a direction perpendicular to the substrate 1, and the hole K1 disconnects the adjacent semiconductor layer 23 in the first direction X; the sidewall of the hole K1 exposes the semiconductor layer 23;
[0121] A third conductive film is deposited to fill the hole K1, forming a bit line 30, as shown in Figures 3A and 3B. The bit line 30 is connected to the second region of the semiconductor layer 23.
[0122] In another embodiment, after forming the semiconductor pillar 2 and before epitaxially growing the buffer layer film, the semiconductor pillar 2 can be processed to form a porous semiconductor pillar 2, as shown in FIG14. FIG14 is a cross-sectional view along the direction perpendicular to the substrate 1 after forming the porous semiconductor pillar 2 according to some embodiments.
[0123] In some embodiments, processing the semiconductor pillar 2 may include performing the following electrochemical treatment: in an O-ring electrochemical cell, using an electrolyte consisting of hydrofluoric acid (concentration may be 49%) and anhydrous ethanol in a volume ratio of 1:3 and a concentration of 50 mA / cm². 2 Anodizing treatment is performed on the semiconductor pillar 2 using a current density of [missing information], which etches the semiconductor pillar 2 and causes it to form a porous structure. This electrochemical treatment is merely an example, and the embodiments disclosed herein are not limited thereto. Parameters can be adjusted to achieve different porosities, or other materials can be used for treatment.
[0124] The above steps 3) to 11) are then performed to form the semiconductor device shown in Figure 15.
[0125] This disclosure also provides an electronic device, including the semiconductor device described in any of the foregoing embodiments, or a semiconductor device formed by the manufacturing method of the semiconductor device described in any of the foregoing embodiments. The electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.
[0126] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.
Claims
1. A semiconductor device, comprising: A substrate and a multilayer memory cell array stacked on the substrate in a direction perpendicular to the substrate; The substrate includes a base, a plurality of semiconductor pillars disposed on the base and extending perpendicular to the base and spaced apart, and a buffer layer disposed on the side of the plurality of semiconductor pillars facing away from the base. The buffer layer covers the surface of the plurality of semiconductor pillars on the side opposite to the substrate; The plurality of semiconductor pillars form an integral structure with the substrate; a cavity is formed between the surface of the buffer layer facing the substrate, the surface of the substrate facing the buffer layer, and the sidewalls of the plurality of semiconductor pillars; The multilayer memory cell array is disposed on the side of the buffer layer away from the semiconductor pillar.
2. The semiconductor device of claim 1, wherein, The plurality of semiconductor pillars are arranged in an array along a first direction parallel to the substrate and a second direction parallel to the substrate. The cavity includes a plurality of first trenches extending along the first direction and a plurality of second trenches extending along the second direction, spaced apart from the plurality of semiconductor pillars. The first direction and the second direction intersect.
3. The semiconductor device of claim 2, wherein, The height of the semiconductor pillar is 9 micrometers to 13 micrometers, and the aspect ratio of both the first trench and the second trench is greater than 13.
4. The semiconductor device of claim 1, wherein, The semiconductor pillar can be a solid structure or a porous structure.
5. The semiconductor device of claim 4, wherein, The porosity of the porous structure is 35% to 75%.
6. The semiconductor device according to any one of claims 1 to 5, wherein The buffer layer comprises silicon, silicon-germanium, or tin-germanium.
7. A method for manufacturing a semiconductor device, comprising: Provide the initial base; The initial substrate is etched to form a substrate and a plurality of spaced semiconductor pillars disposed on the substrate and extending in a direction perpendicular to the substrate; A buffer layer film is epitaxially grown on the surface of a plurality of semiconductor pillars away from the substrate, and the buffer layer films epitaxially grown on different semiconductor pillars are connected to each other to form a buffer layer, and a cavity is formed between the surface of the buffer layer facing the substrate, the surface of the substrate facing the buffer layer, and the sidewalls of the plurality of semiconductor pillars. A multilayer storage cell array is formed on the buffer layer, stacked along a direction perpendicular to the substrate.
8. The method of manufacturing a semiconductor device according to claim 7, wherein Etching the initial substrate to form a substrate and a plurality of spaced semiconductor pillars disposed on the substrate and extending in a direction perpendicular to the substrate include: The initial substrate is etched to form a plurality of first trenches extending along a first direction parallel to the initial substrate and a plurality of second trenches extending along a second direction parallel to the initial substrate, thereby forming the substrate and a plurality of semiconductor pillars disposed on the substrate extending along a direction perpendicular to the substrate; the plurality of first trenches are spaced apart along the second direction, the plurality of second trenches are spaced apart along the first direction, and the first direction and the second direction intersect.
9. The method for manufacturing a semiconductor device according to claim 7, wherein, Before the buffer layer film is epitaxially grown on the surface of the plurality of semiconductor pillars away from the substrate and the buffer layer films epitaxially grown on different semiconductor pillars are connected to each other to form a buffer layer, the method further includes: processing the semiconductor pillars to form a porous structure.
10. The method of manufacturing a semiconductor device according to any one of claims 7 to 9, wherein Forming a multilayer memory cell array stacked along a direction perpendicular to the substrate on the buffer layer includes: A stacked structure comprising multiple alternately stacked semiconductor structure layers and sacrificial layers is formed on the buffer layer; The multi-layer storage cell array is formed based on the stacked structure; The buffer layer and the sacrificial layer are both made of silicon and germanium, and the concentration of germanium in the buffer layer is equal to the concentration of germanium in the sacrificial layer * the thickness of the sacrificial layer / (the thickness of the semiconductor structure layer + the thickness of the sacrificial layer).
11. An electronic device comprising a semiconductor device as claimed in any one of claims 1 to 6, or a semiconductor device formed by a method of manufacturing a semiconductor device according to any one of claims 7 to 10.