High-voltage nldmos structure and manufacturing method therefor
By introducing an N-type injection region and a P-type doped layer into the high-voltage NLDMOS structure, combined with gate structure and metal layer design, the problem of insufficient breakdown voltage was solved, and a significant improvement in breakdown voltage was achieved.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- SHANGHAI HUAHONG GRACE SEMICON MFG CORP
- Filing Date
- 2025-08-06
- Publication Date
- 2026-05-21
AI Technical Summary
The breakdown voltage of existing high-voltage LDMOS structures is insufficient and cannot meet practical requirements.
In a high-voltage NLDMOS structure, an N-type injection region, an epitaxial layer, a P-well, and a P-type doped layer are introduced. Combined with the gate structure and metal layer design, the breakdown voltage is improved by self-adjusting the surface electric field intensity.
By increasing the drain depletion region area and introducing a new electric field peak, the surface electric field peak is reduced, thereby significantly increasing the breakdown voltage by approximately 130V.
Smart Images
Figure CN2025112978_21052026_PF_FP_ABST
Abstract
Description
High-voltage NLDMOS structure and its manufacturing method Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a high-voltage NLDMOS structure and its manufacturing method. Background Technology
[0002] High-voltage (e.g., 1100V) LDMOS combines the high-voltage, high-current characteristics of discrete devices with the advantages of high-density intelligent logic control of low-voltage integrated circuits. A single chip can accomplish the functions that previously required multiple chips, greatly reducing the area, lowering costs, and improving energy efficiency. This aligns with the development trend of miniaturization, intelligence, and low energy consumption in modern power electronic devices.
[0003] Breakdown voltage is a critical parameter for evaluating high-voltage devices. Existing technologies can increase the depletion of the drift region by forming a PTOP layer (a P-type doped layer near the upper surface of the epitaxial layer) on the surface of the drift region (as shown in Figure 1), thereby reducing the surface electric field (Resurf). However, the breakdown voltage of this structure still does not meet the actual requirements.
[0004] To solve the above problems, a novel high-voltage NLDMOS structure and its manufacturing method are needed. Summary of the Invention
[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a high-voltage NLDMOS structure and its manufacturing method, so as to solve the problem that the breakdown voltage of high-voltage LDMOS needs to be improved in the prior art.
[0006] To achieve the above and other related objectives, the present invention provides a high-voltage NLDMOS structure, comprising:
[0007] A P-type substrate has an N-type injection region formed in the region near the drain end of the substrate;
[0008] An N-type epitaxial layer is formed on the substrate, and a field oxide layer is formed on the field oxide region of the epitaxial layer;
[0009] A P-well is formed on the epitaxial layer, and a P-type doped layer is formed on the epitaxial layer near the upper surface of the epitaxial layer at the source end and below the field oxide layer.
[0010] A gate structure and a drain polysilicon field plate, wherein the gate structure includes a gate dielectric layer and a gate polysilicon layer, one end of the gate polysilicon layer extends to the P-well and the other end extends to the adjacent field oxide layer, and the drain polysilicon field plate is located on the field oxide layer near the drain end.
[0011] The source and drain heavily doped regions of N-type and the P-well heavily doped regions of P-type.
[0012] An interlayer dielectric layer is located between the source and drain terminals, and contacts for leading out the polysilicon field plate of the drain terminal are formed on the interlayer dielectric layer;
[0013] The first and second metal layers are located at the source and drain ends. The first metal layer serves as the lead-out end of the heavily doped region at the source end, the lead-out end of the P-well lead-out region, and the metal field plate at the source end. The second metal layer serves as the contact element, the lead-out end of the heavily doped region at the drain end, and the metal field plate at the drain end.
[0014] Preferably, the gate dielectric layer is a thermal oxide layer.
[0015] Preferably, the material of the interlayer dielectric layer is silicon dioxide.
[0016] Preferably, the material of the first and second metal layers is aluminum.
[0017] Preferably, the N-type injection region is composed of multiple spaced injection regions.
[0018] The present invention also provides a method for manufacturing the above-mentioned high-voltage NLDMOS structure, comprising:
[0019] Step 1: Provide a P-type substrate and use ion implantation to form an N-type implantation region in the region of the substrate near the drain end;
[0020] Step 2: An N-type epitaxial layer is formed on the substrate, and a field oxide layer is formed on the field oxide region of the epitaxial layer;
[0021] Step 3: Form a P-well on the epitaxial layer by ion implantation, and form a P-type doped layer near the upper surface of the epitaxial layer on the source end and the epitaxial layer below the field oxide layer by ion implantation.
[0022] Step 4: Forming a gate structure and a drain polysilicon field plate. The gate structure includes a gate dielectric layer and a gate polysilicon layer. One end of the gate polysilicon layer extends to the P-well, and the other end extends to the adjacent field oxide layer. The drain polysilicon field plate is located on the field oxide layer near the drain end.
[0023] Step 5: Use ion implantation to form N-type source-end heavily doped regions and drain-end heavily doped regions, and P-type heavily doped P-well extraction regions;
[0024] Step 6: Form an interlayer dielectric layer between the source and drain terminals; form a contact on the interlayer dielectric layer for leading out the polysilicon field plate of the drain terminal; form a first and a second metal layer at the source and drain terminals, wherein the first metal layer serves as the lead-out terminal of the heavily doped region of the source terminal, the lead-out terminal of the P-well region, and the metal field plate of the source terminal; and the second metal layer serves as the contact, the lead-out terminal of the heavily doped region of the drain terminal, and the metal field plate of the drain terminal.
[0025] Preferably, the N-type injection region in step one is composed of multiple spaced injection regions.
[0026] Preferably, the method for forming the field oxide layer in step two includes: forming trenches on the epitaxial layer using photolithography and etching; and forming the field oxide layer that fills the trenches.
[0027] Preferably, the method for forming the gate structure and the drain polysilicon field plate in step four includes: forming the gate dielectric layer; depositing a polysilicon layer; and patterning the gate dielectric layer and the polysilicon layer using photolithography and etching methods to form the gate polysilicon layer and the drain polysilicon field plate.
[0028] Preferably, the gate dielectric layer is formed in step four using a thermal oxidation method.
[0029] Preferably, the material of the interlayer dielectric layer in step six is silicon dioxide.
[0030] Preferably, the material of the first and second metal layers in step six is aluminum.
[0031] As described above, the high-voltage NLDMOS structure and its manufacturing method of the present invention have the following beneficial effects:
[0032] The N-type injection region of the present invention increases the area of the drain depletion region, which can introduce a new electric field peak between the peak values of the surface U-shaped electric field, thereby reducing the peak value of the surface U-shaped electric field and improving the breakdown voltage. Attached Figure Description
[0033] Figure 1 shows a schematic diagram of a high-voltage NLDMOS structure in the prior art;
[0034] Figure 2 shows a schematic diagram of the process flow of the present invention;
[0035] Figure 3 shows a schematic diagram of the N-type injection region layout of the present invention;
[0036] Figure 4 shows a schematic diagram of forming an N-type implantation region and an epitaxial layer on a substrate according to the present invention.
[0037] Figure 5 shows a schematic diagram of the formation field oxide layer of the present invention;
[0038] Figure 6 shows a schematic diagram of the formation of the P-trap according to the present invention;
[0039] Figure 7 shows a schematic diagram of the formation of the P-type doped layer according to the present invention;
[0040] Figure 8 shows a schematic diagram of the formation of the gate structure and the drain polysilicon field plate of the present invention;
[0041] Figure 9 shows a schematic diagram of the formation of the source-end heavily doped region, the drain-end heavily doped region, and the P-well extraction region according to the present invention.
[0042] Figure 10 shows a schematic diagram of the formation of the first and second metal layers according to the present invention;
[0043] Figure 11 shows a comparative schematic diagram of the surface electric field of the prior art structure of the present invention and an embodiment of the present invention. Detailed Implementation
[0044] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0045] Please refer to Figure 10. This invention provides a high-voltage NLDMOS structure, comprising:
[0046] A P-type substrate 101 has an N-type implantation region 102 formed in the region of the substrate 101 near the drain end;
[0047] In some embodiments, the N-type injection region 102 is composed of a plurality of spaced injection regions.
[0048] Referring to Figure 3, by adjusting the layout, N-type implantation is spaced out in the W (width) and L (length) directions. Through diffusion, the doping concentration of N-type implantation in the L and W directions can be self-regulated in a single implantation step. Where the surface electric field strength is high, the electric field can be further reduced; where the surface electric field strength is low, the electric field can be increased, achieving self-regulation of the surface electric field. The breakdown voltage can be increased by approximately 130V. Simultaneously, spaced implantation prevents excessive longitudinal diffusion, which could affect the doping concentration on the device surface.
[0049] An N-type epitaxial layer 103 is formed on the substrate 101, and a field oxide layer 104 is formed on the field oxide region of the epitaxial layer 103.
[0050] A P-well 105 is formed on the epitaxial layer 103, and a P-type doped layer 106 is formed on the epitaxial layer 103 near the upper surface of the epitaxial layer 103 at the source end and below the field oxide layer 104.
[0051] The gate structure includes a gate dielectric layer 107 and a gate polysilicon layer 108a. One end of the gate polysilicon layer 108a extends to the P-well 105, and the other end extends to the adjacent field oxide layer 104. The drain polysilicon field plate 108b is located on the field oxide layer 104 near the drain end.
[0052] In some embodiments, the gate dielectric layer 107 is a thermal oxide layer.
[0053] The N-type source-end heavily doped region 109b and drain-end heavily doped region 109a and the P-type heavily doped P-well extraction region 110.
[0054] An interlayer dielectric layer 111 is located between the source and drain terminals, and contacts for leading out the polysilicon field plate 108b at the drain terminal are formed on the interlayer dielectric layer 111.
[0055] In some embodiments, the material of the interlayer dielectric layer 111 is silicon dioxide.
[0056] The first and second metal layers located at the source and drain ends are as follows: the first metal layer 112a serves as the lead-out terminal of the heavily doped region 109b at the source end, the lead-out terminal of the P-well lead-out region 110, and the metal field plate at the source end; the second metal layer 112b serves as the contact element, the lead-out terminal of the heavily doped region 109a at the drain end, and the metal field plate at the drain end. The metal field plates at the source end and the metal field plates at the drain end play a role in increasing the peak electric field on the surface of the drift region, which can improve the breakdown voltage.
[0057] In some embodiments, the first and second metal layers are made of aluminum.
[0058] Please refer to Figure 11, which shows a comparative schematic diagram of the surface electric field of a prior art structure and a structure of an embodiment of the present invention. An N-type implantation region 102 is injected near the drain end of the drift region. Since it is injected before the formation of the N-type epitaxial layer 103, its depth is deeper than that of the P-type doped layer 106. The N-type implantation region 102 increases the area of the drain depletion region and can introduce a new electric field peak between the peak values of the surface U-shaped electric field, thereby reducing the electric field peak value of the surface U-shaped electric field and improving the breakdown voltage.
[0059] Referring to Figure 2, the present invention also provides a method for manufacturing the above-mentioned high-voltage NLDMOS structure, comprising:
[0060] Step 1: Provide a P-type substrate 101, and use ion implantation to form an N-type implantation region 102 in the region near the drain end of the substrate 101, forming the structure shown in Figure 4;
[0061] Referring to Figure 3, by adjusting the layout, N-type implantation is spaced out in the W and L directions. Through diffusion, the doping concentration of N-type implantation in the L and W directions can be self-regulated in a single implantation step. Where the surface electric field strength is high, the electric field can be further reduced; where the surface electric field strength is low, the electric field can be increased, achieving self-regulation of the surface electric field. The breakdown voltage can be increased by approximately 130V. Simultaneously, spaced implantation prevents excessive longitudinal diffusion, which could affect the doping concentration on the device surface.
[0062] Step 2: An N-type epitaxial layer 103 is formed on the substrate 101. The N-type epitaxial layer 103 serves as a drift region. A field oxide layer 104 is formed on the field oxide region of the epitaxial layer 103, forming the structure shown in Figure 5.
[0063] In some embodiments, the method for forming the field oxide layer 104 in step two includes: forming trenches on the epitaxial layer 103 using photolithography and etching methods; and forming a field oxide layer 104 that fills the trenches.
[0064] Step 3: A P-well 105 is formed on the epitaxial layer 103 by ion implantation. The P-well 105 serves as the body region, forming the structure shown in Figure 6. A P-type doped layer 106 is formed on the epitaxial layer 103 near the upper surface of the epitaxial layer 103 by ion implantation at the source end and below the field oxide layer 104, forming the structure shown in Figure 7.
[0065] Step 4: Forming the gate structure and drain polysilicon field plate 108b. The gate structure includes a gate dielectric layer 107 and a gate polysilicon layer 108a. One end of the gate polysilicon layer 108a extends to the P-well 105, and the other end extends to the adjacent field oxide layer 104. The drain polysilicon field plate 108b is located on the field oxide layer 104 near the drain end, forming the structure shown in Figure 8.
[0066] In some embodiments, the method of forming the gate structure and the drain polysilicon field plate 108b in step four includes: forming a gate dielectric layer 107; depositing a polysilicon layer; and using photolithography and etching to pattern the gate dielectric layer 107 and the polysilicon layer to form the gate polysilicon layer 108a and the drain polysilicon field plate 108b.
[0067] In some embodiments, the gate dielectric layer 107 is formed in step four using a thermal oxidation method.
[0068] Step 5: Using ion implantation, an N-type source-end heavily doped region 109b and a drain-end heavily doped region 109a and a P-type heavily doped P-well extraction region 110 are formed, resulting in the structure shown in Figure 9.
[0069] Step 6: Form an interlayer dielectric layer 111 between the source and drain terminals. Form a contact on the interlayer dielectric layer 111 for leading out the polysilicon field plate 108b at the drain terminal. Form a first and a second metal layer at the source and drain terminals. The first metal layer 112a serves as the lead-out terminal of the heavily doped region 109b at the source terminal, the lead-out terminal of the P-well region 110, and the metal field plate at the source terminal. The second metal layer 112b serves as the contact, the lead-out terminal of the heavily doped region 109a at the drain terminal, and the metal field plate at the drain terminal, forming the structure shown in Figure 10. The metal field plate at the source terminal and the metal field plate at the drain terminal play a role in increasing the peak electric field on the surface of the drift region, which can improve the breakdown voltage.
[0070] In some embodiments, the material of the interlayer dielectric layer 111 in step six is silicon dioxide.
[0071] In some embodiments, the materials of the first and second metal layers in step six are aluminum.
[0072] Please refer to Figure 11, which shows a comparative schematic diagram of the surface electric field of a prior art structure and a structure of an embodiment of the present invention. An N-type implantation region 102 is injected near the drain end of the drift region. Since it is injected before the formation of the N-type epitaxial layer 103, its depth is deeper than that of the P-type doped layer 106. The N-type implantation region 102 increases the area of the drain depletion region and can introduce a new electric field peak between the peak values of the surface U-shaped electric field, thereby reducing the electric field peak value of the surface U-shaped electric field and improving the breakdown voltage.
[0073] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0074] In summary, the N-type injection region of this invention increases the area of the drain-end depletion region, introducing a new electric field peak between the peak values of the surface U-shaped electric field, thereby reducing the peak value of the surface U-shaped electric field and improving the breakdown voltage. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.
[0075] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A high voltage NLDMOS structure, characterized in that, At least including: A P-type substrate has an N-type injection region formed in the region near the drain end of the substrate; An N-type epitaxial layer is formed on the substrate, and a field oxide layer is formed on the field oxide region of the epitaxial layer; A P-well is formed on the epitaxial layer, and a P-type doped layer is formed on the epitaxial layer near the upper surface of the epitaxial layer at the source end and below the field oxide layer. A gate structure and a drain polysilicon field plate, wherein the gate structure includes a gate dielectric layer and a gate polysilicon layer, one end of the gate polysilicon layer extends to the P-well and the other end extends to the adjacent field oxide layer, and the drain polysilicon field plate is located on the field oxide layer near the drain end. The source and drain heavily doped regions of N-type and the P-well heavily doped regions of P-type. An interlayer dielectric layer is located between the source and drain terminals, and contacts for leading out the polysilicon field plate of the drain terminal are formed on the interlayer dielectric layer; The first and second metal layers are located at the source and drain ends. The first metal layer serves as the lead-out end of the heavily doped region at the source end, the lead-out end of the P-well lead-out region, and the metal field plate at the source end. The second metal layer serves as the contact element, the lead-out end of the heavily doped region at the drain end, and the metal field plate at the drain end.
2. The high voltage NLDMOS structure of claim 1, wherein: The gate dielectric layer is a thermal oxide layer.
3. The high voltage NLDMOS structure of claim 1, wherein: The first and second metal layers are made of aluminum.
4. The high voltage NLDMOS structure of claim 1, wherein: The N-type injection region consists of multiple spaced injection regions.
5. The method of claim 1 to 4, wherein At least including: Step 1: Provide a P-type substrate and use ion implantation to form an N-type implantation region in the region of the substrate near the drain end; Step 2: An N-type epitaxial layer is formed on the substrate, and a field oxide layer is formed on the field oxide region of the epitaxial layer; Step 3: Form a P-well on the epitaxial layer by ion implantation, and form a P-type doped layer near the upper surface of the epitaxial layer on the source end and the epitaxial layer below the field oxide layer by ion implantation. Step 4: Forming a gate structure and a drain polysilicon field plate. The gate structure includes a gate dielectric layer and a gate polysilicon layer. One end of the gate polysilicon layer extends to the P-well, and the other end extends to the adjacent field oxide layer. The drain polysilicon field plate is located on the field oxide layer near the drain end. Step 5: Use ion implantation to form N-type source-end heavily doped regions and drain-end heavily doped regions, and P-type heavily doped P-well extraction regions; Step 6: Form an interlayer dielectric layer between the source and drain terminals; form a contact on the interlayer dielectric layer for leading out the polysilicon field plate of the drain terminal; form a first and a second metal layer at the source and drain terminals, wherein the first metal layer serves as the lead-out terminal of the heavily doped region of the source terminal, the lead-out terminal of the P-well region, and the metal field plate of the source terminal; and the second metal layer serves as the contact, the lead-out terminal of the heavily doped region of the drain terminal, and the metal field plate of the drain terminal.
6. The method of claim 5, wherein: The N-type injection region in step one consists of multiple spaced injection regions.
7. The method of claim 5, wherein: The method for forming the field oxide layer in step two includes: forming trenches on the epitaxial layer using photolithography and etching; and forming the field oxide layer that fills the trenches.
8. The method of claim 5, wherein: The method for forming the gate structure and the drain end polysilicon field plate in step four includes: forming the gate dielectric layer; depositing a polysilicon layer; patterning the gate dielectric layer and the polysilicon layer by using photolithography and etching to form the gate polysilicon layer and the drain end polysilicon field plate.
9. The method of claim 5, wherein: The gate dielectric layer in step four is formed by using thermal oxidation.
10. The method of claim 5, wherein: The material of the first and second metal layers in step six is aluminum.