Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a highly reliable semiconductor device. The semiconductor device comprises a vertical transistor. The semiconductor device comprises first and second insulating layers. The semiconductor layer of the vertical transistor contains indium oxide. The first insulating layer includes a region positioned over a lower electrode of the vertical transistor, and an opening overlapping the lower electrode. The second insulating layer, the semiconductor layer of the vertical transistor, a gate insulating layer, and a gate electrode have regions positioned in the opening. The semiconductor layer includes: a region in the opening, said region being in contact with the side surface of the second insulating layer; a region positioned over the first insulating layer; and a region positioned over the second insulating layer. An upper electrode of the vertical transistor is positioned over the first insulating layer and has a region in contact with the upper surface of the semiconductor layer.

Description

Semiconductor device, method for manufacturing a semiconductor device

[0001] One aspect of the present invention relates to a transistor, a semiconductor device, a memory device, and an electronic device. Another aspect of the present invention relates to a method for manufacturing a transistor and a semiconductor device.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), methods for driving them, or methods for manufacturing them.

[0003] In this specification, a semiconductor device refers to a device that utilizes semiconductor properties, including circuits containing semiconductor elements (transistors, diodes, photodiodes, etc.), and devices having such circuits. It also refers to any device that can function by utilizing semiconductor properties. For example, integrated circuits, chips equipped with integrated circuits, and electronic components with chips housed in packages are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices, and may each have semiconductor devices.

[0004] A technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces is attracting attention. These transistors are widely applied in electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors are also gaining attention as other materials.

[0005] Furthermore, transistors using oxide semiconductors are known to have extremely low leakage current in the off state. For example, Patent Document 1 discloses a low-power CPU (Central Processing Unit) that utilizes the low leakage current characteristic of transistors using oxide semiconductors. Also, for example, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the low leakage current characteristic of transistors using oxide semiconductors.

[0006] Furthermore, examples of oxide semiconductors applicable to the active layer of transistors include indium oxide and indium gallium zinc oxide. Non-patent document 1 states that In ２ O ３ Its use in thin-film transistors has been reported. Non-patent document 2 discloses a thin-film transistor using polycrystalline indium hydride oxide formed by low-temperature solid-phase crystallization as the active layer.

[0007] Japanese Patent Publication No. 2012-257187 Japanese Patent Publication No. 2011-151383

[0008] Dhananjay and C. W. Chu, Realization of In▲2▼O▲3▼ thin film transistors through reactive evaporation process. Appl. Phys. Lett. 91, 132111 (2007). Y. Magari et al. Takashi Koida, “High-mobility hydrogenerated polycrystalline In2O3 (In2O3:H) thin-film transistors”, Nature Communications, 13, 1078 (2022) Takashi Koida, “High-mobility transparent conductive film”, National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Presentation Meeting 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0009] One aspect of the present invention aims to provide a transistor with good electrical characteristics. One aspect of the present invention aims to provide a transistor with a large on-current. One aspect of the present invention aims to provide a transistor with low parasitic capacitance. One aspect of the present invention aims to provide a highly reliable transistor, semiconductor device, or memory device. One aspect of the present invention aims to provide a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated. One aspect of the present invention aims to provide a semiconductor device or memory device with low power consumption. One aspect of the present invention aims to provide a semiconductor device or memory device with a high operating speed. One aspect of the present invention aims to provide a novel transistor, semiconductor device, or memory device. One aspect of the present invention aims to provide a method for manufacturing the above-mentioned transistor, semiconductor device, or memory device.

[0010] Furthermore, the description of these problems does not preclude the existence of other problems. One aspect of the present invention does not necessarily have to solve all of these problems. It is possible to extract other problems from the description in the specification, drawings, and claims.

[0011] One aspect of the present invention comprises a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, a second insulating layer, a third insulating layer, and a semiconductor layer, wherein the first insulating layer has a region located on the first conductive layer, the first insulating layer has a first opening overlapping with the first conductive layer, the second insulating layer has a region located inside the first opening, and the semiconductor layer has a region in contact with the first conductive layer, a region in contact with the side surface of the second insulating layer inside the first opening, a region located on the first insulating layer, and a region located on the second insulating layer. A semiconductor device having a region and a semiconductor layer, the second conductive layer being located on the first insulating layer and having a region in contact with the upper surface of the semiconductor layer, the second conductive layer having a second opening that overlaps with the first opening, the third insulating layer having a region located inside the first opening, a region located inside the second opening, and a region located on the second conductive layer, the third conductive layer being provided on the third insulating layer such that it has a region located inside the first opening, the semiconductor layer having indium oxide, and the semiconductor layer having crystal grains.

[0012] Alternatively, in the above embodiment, the side surface of the second conductive layer at the second opening may protrude from the side surface of the semiconductor layer opposite to the side surface in contact with the second insulating layer.

[0013] Alternatively, in the above embodiment, the second insulating layer may have gallium and oxygen.

[0014] Alternatively, in the above embodiment, the semiconductor device has a fourth insulating layer, the fourth insulating layer is provided inside the first opening so as to cover the side surface of the second insulating layer opposite to the semiconductor layer and the lower end, the semiconductor layer has a region located on the fourth insulating layer, and the fourth insulating layer may have hafnium and oxygen.

[0015] Alternatively, in the above embodiment, the second conductive layer may have a first layer having a region in contact with the upper surface of the semiconductor layer, and a second layer on the first layer, wherein the first layer has an oxide conductor, and the second layer has a material with higher conductivity than the oxide conductor.

[0016] Alternatively, in the above embodiment, the first layer may have at least one of indium tin oxide, silicon-containing indium tin oxide, indium zinc oxide, and indium titanium oxide, and the second layer may have at least one of tungsten, copper, and aluminum.

[0017] Alternatively, one aspect of the present invention is a method for manufacturing a semiconductor device, comprising: forming a first conductive layer; forming a first insulating layer so as to cover the first conductive layer; forming a first opening in the first insulating layer that reaches the first conductive layer; forming a second insulating layer inside the first opening; forming a semiconductor layer having a region in contact with the first conductive layer, a region in contact with the side surface of the second insulating layer, a region located on the first insulating layer, and a region located on the second insulating layer; forming a sacrificial layer so as to fill the first opening; performing heat treatment; forming a second conductive layer having a region in contact with the upper surface of the semiconductor layer and a region located on the sacrificial layer; forming a second opening in the second conductive layer that overlaps with the first opening; removing the sacrificial layer; and forming a third insulating layer on the semiconductor layer and on the second conductive layer, with the third conductive layer having a region located inside the first opening.

[0018] Alternatively, in the above embodiment, after the sacrificial layer is formed, a seed layer may be formed so as to be in contact with the upper surface of the semiconductor layer and overlapping with the first insulating layer, heat treatment may be performed after the seed layer is formed, and the seed layer may be removed after the heat treatment.

[0019] According to one aspect of the present invention, a transistor with good electrical characteristics can be provided. According to one aspect of the present invention, a transistor with a large on-current can be provided. According to one aspect of the present invention, a transistor with low parasitic capacitance can be provided. According to one aspect of the present invention, a highly reliable transistor, semiconductor device, or memory device can be provided. According to one aspect of the present invention, a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated can be provided. According to one aspect of the present invention, a semiconductor device or memory device with low power consumption can be provided. According to one aspect of the present invention, a semiconductor device or memory device with a fast operating speed can be provided. According to one aspect of the present invention, a novel transistor, semiconductor device, or memory device can be provided. According to one aspect of the present invention, a method for manufacturing the above-mentioned transistor, semiconductor device, or memory device can be provided.

[0020] Furthermore, the description of these effects does not preclude the existence of other effects. One aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description, drawings, and claims.

[0021] Figures 1A and 1B are perspective views showing an example of the configuration of a semiconductor device. Figures 2A and 2B are plan views showing an example of the configuration of a semiconductor device. Figures 3A and 3B are plan views showing an example of the configuration of a semiconductor device. Figures 4A and 4B are cross-sectional views showing an example of the configuration of a semiconductor device. Figure 5 is a cross-sectional view showing an example of the configuration of a semiconductor device. Figures 6A and 6B are cross-sectional views showing an example of the configuration of a semiconductor device. Figure 7 is a cross-sectional view showing an example of the configuration of a semiconductor device. Figure 8 is a cross-sectional view showing an example of the configuration of a semiconductor device. Figures 9A and 9B are cross-sectional views showing an example of the configuration of a semiconductor device. Figures 10A and 10B are plan views showing an example of the configuration of a semiconductor device. Figures 10C and 10D are cross-sectional views showing an example of the configuration of a semiconductor device. Figure 11A is a plan view showing an example of the configuration of a semiconductor device. Figures 11B, 11C, and 11D are cross-sectional views showing an example of the configuration of a semiconductor device. Figure 12 is a cross-sectional view showing an example of the configuration of a semiconductor device. Figures 13A and 13B are cross-sectional views showing an example of the configuration of a semiconductor device. Figures 14A, 14B, 14C, 14D, 14E, 14F, 14G, and 14H are cross-sectional views showing examples of semiconductor device manufacturing methods. Figures 15A, 15B, 15C, 15D, and 15E are cross-sectional views showing examples of semiconductor device manufacturing methods. Figures 16A and 16B illustrate the carrier concentration dependence of Hall mobility. Figure 16C is a cross-sectional view illustrating an indium oxide film. Figure 17A is a plan view showing an example of a memory device configuration. Figures 17B and 17C are cross-sectional views showing examples of memory device configurations. Figure 18A is a plan view showing an example of a memory device configuration. Figures 18B and 18C are cross-sectional views showing examples of memory device configurations. Figure 19 is a cross-sectional view showing an example of a memory device configuration. Figure 20 is a block diagram showing an example of a semiconductor device configuration. Figures 21A, 21B, 21C, 21D, 21E, 21F, 21G, and 21H show examples of memory cell circuit configurations. Figures 22A and 22B are perspective views showing examples of semiconductor device configurations. Figure 23 is a block diagram of a CPU. Figures 24A and 24B are perspective views showing examples of semiconductor device configurations. Figures 25A and 25B are perspective views showing examples of semiconductor device configurations. Figure 26A is an equivalent circuit diagram of a logic circuit. Figure 26B is a circuit symbol of a logic circuit.Figure 26C is a timing chart showing the operation of a logic circuit. Figure 27 is a cross-sectional view showing an example of the configuration of a semiconductor device. Figures 28A and 28D are equivalent circuit diagrams of logic circuits. Figures 28B, 28C, 28E, and 28F are circuit symbols for logic circuits. Figure 29A is an equivalent circuit diagram of a DFF circuit. Figure 29B is the circuit symbol for a DFF circuit. Figure 30A is a diagram showing an example of the configuration of a shift register circuit. Figure 30B is a timing chart showing the operation of a shift register circuit. Figures 31A and 31B are diagrams showing examples of electronic components. Figures 32A, 32B, and 32C are diagrams showing examples of large-scale computers. Figure 32D is a diagram showing an example of space equipment. Figure 32E is a diagram showing an example of a storage system applicable to data centers.

[0022] Embodiments will be described in detail with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the present invention. Accordingly, the present invention shall not be construed as being limited to the descriptions of the embodiments shown below.

[0023] In the invention described below, the same reference numerals are used in common across different drawings for identical parts or parts having similar functions, and repeated explanations are omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used, and reference numerals may not be assigned.

[0024] Furthermore, the position, size, and scope of each component shown in the drawings may not represent the actual position, size, and scope for the sake of ease of understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, and scope disclosed in the drawings.

[0025] In this specification, the ordinal numbers "first" and "second" are used for convenience only and do not limit the number of components or the order of components (for example, process order or stacking order). Furthermore, the ordinal numbers used for components in one part of this specification may not be the same as those used for the same components in other parts of this specification or in the claims.

[0026] Furthermore, a transistor is a type of semiconductor device that can perform functions such as amplifying current or voltage, and switching operations that control conduction or non-conductivity. Transistors in this specification include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0027] In this specification, transistors using an oxide semiconductor or metal oxide in the semiconductor layer, and transistors having an oxide semiconductor or metal oxide in the channel formation region, may be referred to as OS (Oxide Semiconductor) transistors. Furthermore, transistors having silicon in the channel formation region may be referred to as Si transistors.

[0028] Furthermore, the functions of "source" and "drain" may be reversed when transistors with different polarities are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably.

[0029] In this specification, an oxidized nitride is a material containing oxygen and nitrogen, and the nitrogen and oxygen content in its composition is not limited. In other words, oxidized nitrides include materials in which the oxygen content is greater than the nitrogen content, and materials in which the nitrogen content is greater than the oxygen content.

[0030] In this specification, the terms "film" and "layer" can be interchanged as needed or depending on the context. For example, the term "conductive layer" can be changed to the term "conductive film." Alternatively, the term "insulating film" can be changed to the term "insulating layer."

[0031] Furthermore, in this specification, "parallel" means a state in which two lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Furthermore, "approximately parallel" means a state in which two lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" means a state in which two lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Furthermore, "approximately perpendicular" means a state in which two lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0032] In this specification, "connection" includes, for example, "electrical connection." The term "electrical connection" is sometimes used to define the connection relationship of circuit elements as a physical object. Furthermore, "electrical connection" includes both "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the use of circuit elements (e.g., transistors, switches, etc.; however, wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected through one or more circuit elements. A, B, and C (described later) refer to objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0033] For example, assuming a circuit including A and B is in operation, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected" as physical objects. Furthermore, even if there is a timing during the circuit's operation when no electrical signals are exchanged or potential interactions occur between A and B, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected."

[0034] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where "A and B are not indirectly connected" is when an insulator is interposed in the path from A to B. Specifically, this includes cases where a capacitive element is connected between A and B, or where a transistor gate insulating film is interposed between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of a transistor are indirectly connected."

[0035] Another example of a situation where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via source and drain in the path from A to B, and a constant potential V is supplied from a power supply, GND, etc., to the nodes between the transistors.

[0036] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable that there is a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. The side surface of the structure, the substrate surface, and the surface to be formed do not necessarily have to be perfectly flat, and may be substantially planar with a small curvature, or substantially planar with fine irregularities.

[0037] In this specification, "heights match" refers to a configuration in which the heights from a reference surface (for example, a flat surface such as the substrate surface) are equal in a cross-sectional view. For example, if there are two layers with different heights (here referred to as layer A and layer B) with respect to the reference surface, the heights match if the difference between the height of the top surface of layer A and the height of the top surface of layer B is 10 nm or less.

[0038] In this specification, "side edges coincide" means that, in a plan view, at least a portion of the contours of the stacked layers overlap. For example, in the case of two stacked layers (here referred to as layer A and layer B), if the shortest distance from the side edge of layer A to the side edge of layer B in a plan view is 10 nm or less, then the side edges also coincide.

[0039] In general, it can be difficult to clearly distinguish between "exact match" and "approximate match." Therefore, in this specification, "match" may include both exact matches and approximate matches.

[0040] In drawings and other illustrations relating to this specification, arrows indicating the X, Y, and Z directions may be included. In this specification, the "X direction" refers to the direction along the X-axis, and unless explicitly stated, forward and reverse directions may not be distinguished. The same applies to the "Y direction" and "Z direction." Furthermore, the X, Y, and Z directions are directions that intersect each other. For example, the X, Y, and Z directions are directions that are orthogonal to each other.

[0041] In this specification, the cubic crystal structure is sometimes referred to as cubic crystal, cubic structure, etc. The same applies to other crystal systems (hexagonal, trigonal, tetragonal, orthorhombic, monoclinic, and triclinic).

[0042] In this specification, the high power supply potential VDD (hereinafter also simply referred to as "VDD") refers to a power supply potential that is higher than the low power supply potential VSS (hereinafter also simply referred to as "VSS"). The low power supply potential VSS refers to a power supply potential that is lower than the high power supply potential VDD.

[0043] Potential H is the potential that turns an n-channel field-effect transistor (also called an "n-type transistor") on, and the potential that turns a p-channel field-effect transistor (also called a "p-type transistor") off. Similarly, potential L is the potential that turns an n-type transistor off, and the potential that turns a p-type transistor on. Therefore, potential H is higher than potential L. Potential H may be equal to VDD, and potential L may be equal to VSS.

[0044] In this specification and the like, the space group is represented using the Short notation of the international notation (or Hermann-Mauguin symbol). Also, the crystal planes and crystal orientations are represented using Miller indices. In crystallography, the notations of the space group, crystal planes, and crystal orientations are numbers with a bar above them, but in this specification and the like, due to formatting constraints, instead of putting a bar above the numbers, a - (minus sign) may be attached before the numbers for representation. Also, individual orientations indicating the orientation within the crystal are represented by [ ], set orientations indicating all equivalent orientations are represented by < >, individual planes indicating crystal planes are represented by ( ), and set planes having equivalent symmetries are represented by {}.

[0045] In this specification and the like, the content ratio of a certain metal element in a metal oxide refers to the ratio of the number of atoms of that element to the total number of atoms of the metal element contained in the metal oxide. For example, if the metal oxide contains metal element X, metal element Y, and metal element Z, and the number of atoms of metal element X, metal element Y, and metal element Z contained in the metal oxide are A Ｘ 、A Ｙ 、A Ｚ respectively, the content ratio of metal element X can be expressed as A Ｘ / (A Ｘ + A Ｙ + A Ｚ ). Also, when the ratio of the number of atoms (atomic ratio) of metal element X, metal element Y, and metal element Z in the metal oxide is B Ｘ : B Ｙ : B Ｚ respectively, the content ratio of metal element X can be expressed as B Ｘ / (B Ｘ + B Ｙ + B Ｚ ).

[0046] In this specification and the like, "island-like" indicates a state in which two or more layers made of the same material formed in the same process are physically separated.

[0047] (Embodiment 1) This embodiment describes a semiconductor device according to one aspect of the present invention. The semiconductor device according to one aspect of the present invention has a vertical transistor. The semiconductor layer of the vertical transistor has a metal oxide. That is, the vertical transistor in the semiconductor device according to one aspect of the present invention is an OS transistor. Here, indium oxide can be used as the metal oxide. In this case, the vertical transistor in the semiconductor device according to one aspect of the present invention can be called an I / O transistor.

[0048] In this specification, a vertical transistor refers to a transistor in which the source electrode and drain electrode are located at different heights. For example, a transistor in which the bottom surface of the source electrode and the bottom surface of the drain electrode are located at different heights can be called a vertical transistor. Here, of the source electrode and the drain electrode, the electrode with the lower height from the reference plane is called the lower electrode, and the electrode with the higher height is called the upper electrode. The reference plane can be the top surface of the substrate, the top surface of the underlying insulating layer, the top surface of the interlayer insulating layer, etc.

[0049] An insulating layer is provided between the lower electrode and the upper electrode. A vertical transistor has a channel length that has a component in the height direction (vertical direction). A vertical transistor is also called a VFET (Vertical Field Effect Transistor), vertical channel transistor, or vertical channel type transistor.

[0050] A semiconductor device according to one aspect of the present invention includes a first insulating layer and a second insulating layer. The first insulating layer has a region located on the lower electrode of a vertical transistor. The first insulating layer also has a first opening that overlaps with the lower electrode. Inside the first opening, from the outside (side wall side of the first opening), are provided the second insulating layer, the semiconductor layer of the vertical transistor, the gate insulating layer, and the gate electrode. Here, the height of the upper end of the second insulating layer from the reference plane is less than or equal to the height of the upper surface of the first insulating layer from the reference plane.

[0051] In this specification, the side wall of an opening refers to the side surface within the opening of the layer in which the opening is formed. Similarly, the side wall of a recess refers to the side surface within the recess of the layer in which the recess is formed.

[0052] The semiconductor layer of the vertical transistor has a region inside the first opening that is in contact with the side surface of the second insulating layer. The semiconductor layer also has a region located on the first insulating layer and a region located on the second insulating layer outside the first opening. In the region overlapping with the first opening, the semiconductor layer has a region that is in contact with the lower electrode of the vertical transistor, for example, a region that is in contact with the upper surface of the lower electrode. Furthermore, at least a portion of the region located inside the first opening in the semiconductor layer functions as a channel-forming region of the vertical transistor.

[0053] The upper electrode of the vertical transistor is located on the first insulating layer and has a region that contacts the upper surface of the semiconductor layer. That is, the upper electrode has a region that contacts the upper surface of the semiconductor layer outside the first opening. The upper electrode also has a second opening that overlaps with the first opening.

[0054] The gate insulating layer of a vertical transistor has a region located inside the first opening, a region located inside the second opening, and a region located on the upper electrode of the vertical transistor. The gate insulating layer of the vertical transistor can be provided so as to cover the upper electrode and the semiconductor layer.

[0055] The gate electrode of a vertical transistor is provided on the gate insulating layer such that it has a region located inside the first opening. The gate electrode can be provided, for example, to fill the first opening and the second opening.

[0056] When the semiconductor layer of a vertical transistor is, for example, an indium oxide film, it is preferable that the semiconductor layer is crystalline, and more preferably a single-crystal film. Since a single-crystal film does not have grain boundaries, carrier scattering at grain boundaries can be suppressed. Therefore, a transistor with high field-effect mobility can be realized. Furthermore, a highly reliable transistor can be realized.

[0057] One method for crystallizing the semiconductor layer of a vertical transistor involves forming a seed layer having a region in contact with the semiconductor layer, followed by heat treatment. The seed layer functions as a seed or nucleus for crystal growth in the semiconductor layer. Therefore, the seed layer can also be called a seed crystal, crystal nucleus, etc. However, if the heat treatment is performed after the formation of the upper electrode of the vertical transistor, oxygen contained in the semiconductor layer and oxygen contained in the heat treatment atmosphere may be absorbed by the upper electrode, causing oxidation of the upper electrode. This may result in, for example, an increase in the electrical resistance of the upper electrode.

[0058] In one aspect of the present invention, as described above, an upper electrode is provided on the semiconductor layer of the vertical transistor. This allows the upper electrode to be formed after the heat treatment described above. Thus, the semiconductor layer can be crystallized while, for example, oxidation of the upper electrode can be suppressed. As a result, a transistor exhibiting good electrical characteristics and high reliability can be provided. Furthermore, a highly reliable semiconductor device can be provided.

[0059] Furthermore, in one aspect of the present invention, an insulating film having barrier properties against oxygen is used as the second insulating layer. This suppresses the diffusion of oxygen contained in the semiconductor layer of the vertical transistor, specifically the channel formation region, to the first insulating layer, thereby preventing the formation of oxygen vacancies in the channel formation region. As a result, fluctuations in the electrical characteristics of the vertical transistor can be suppressed, and reliability can be improved. Therefore, a highly reliable semiconductor device can be provided.

[0060] <Example of Semiconductor Device Configuration 1> Figure 1A is a perspective view showing an example of the configuration of a semiconductor device according to one embodiment of the present invention. Figure 1B is a perspective view obtained by cutting a part of Figure 1A. Figure 2A is a plan view of the semiconductor device shown in Figures 1A and 1B. In Figure 2A, some elements have been omitted for clarity. Some elements may also be omitted in subsequent plan views.

[0061] Figure 2B is a plan view with some elements omitted from Figure 2A. Figure 3A is a plan view with some elements further omitted from Figure 2B. Figure 3B is a plan view with some elements further omitted from Figure 3A.

[0062] Figure 4A is a cross-sectional view between the dashed lines A1 and A2 shown in Figures 2A to 3B. Figure 4B is a cross-sectional view between the dashed lines B1 and B2 shown in Figures 2A to 3B. Figure 5 is a cross-sectional view between the dashed lines C1 and C2 shown in Figure 4A. Figure 5 is also called a plan view.

[0063] The semiconductor device shown in Figures 1A to 5 includes an insulating layer 87 on a substrate (not shown), insulating layers 62, 74a, and 74b on the insulating layer 87, a transistor 50 on the insulating layer 87, and an insulating layer 88 on the transistor 50. At least one of the insulating layers 87, 62, 74a, 74b, and 88 may be considered a component of the transistor 50.

[0064] The insulating layer 87 functions as a base insulating layer or an interlayer insulating layer. The insulating layer 62 functions as an interlayer insulating layer.

[0065] The transistor 50 has a conductive layer 55 on an insulating layer 87, a semiconductor layer 51 on the conductive layer 55, on the insulating layer 62, on the insulating layer 74a, and on the insulating layer 74b, a conductive layer 56 on the semiconductor layer 51, an insulating layer 52 on the semiconductor layer 51 and on the conductive layer 56, and a conductive layer 53 on the insulating layer 52. The insulating layer 62, insulating layer 74a, and insulating layer 74b have regions located on the conductive layer 55. The insulating layer 88 has regions located on the conductive layer 53 and regions located on the insulating layer 52. Here, in Figure 2B, the conductive layer 53 shown in Figure 2A is omitted. Also, in Figure 3A, the semiconductor layer 51 and conductive layer 56 shown in Figure 2B are omitted. Furthermore, in Figure 3B, the insulating layer 74b shown in Figure 3A is omitted. Figures 1A to 4B show an example in which the conductive layer 55 and conductive layer 53 extend in the X direction, and the conductive layer 56 extends in the Y direction.

[0066] In transistor 50, the conductive layer 53 functions as a gate electrode. The insulating layer 52 functions as a gate insulating layer. The conductive layer 55 functions as one of the source electrode and drain electrode. The conductive layer 56 functions as the other of the source electrode and drain electrode. The conductive layer 53 has a region that functions as gate wiring.

[0067] As shown in Figures 1A to 5, the insulating layer 62 has an opening 63. The opening 63 overlaps with the conductive layer 55, and specifically reaches the conductive layer 55. Figures 2A to 3B and Figure 5 show an example where the opening 63 is circular in plan view. By making the opening 63 circular in plan view, the processing accuracy when forming the opening 63 can be improved. Therefore, the size of the opening 63 can be miniaturized.

[0068] The insulating layer 74a and insulating layer 74b have regions located inside the opening 63. The insulating layer 74a and insulating layer 74b are provided to reflect the shape of the opening 63. The side surface of insulating layer 74a has a region in contact with the side surface of insulating layer 62 in the opening 63. The bottom surface of insulating layer 74a may have a region in contact with the upper surface of conductive layer 55. Insulating layer 74b is provided on insulating layer 74a. Insulating layer 74b is provided further inside the opening 63 than insulating layer 74a (on the opposite side of the side wall of the opening 63).

[0069] The insulating layer 74a is provided so as to cover the side and lower end of the insulating layer 74b. Specifically, the insulating layer 74a is provided so as to cover the side and lower end of the insulating layer 74b opposite to the semiconductor layer 51. More specifically, the insulating layer 74a is provided so as to cover the side and lower end of the insulating layer 74b opposite to the side in contact with the semiconductor layer 51. The side end of the insulating layer 74a can be made to coincide with the side of the insulating layer 74b. Note that the insulating layer 74a and the insulating layer 74b may be considered together as a single insulating layer. Hereafter, the insulating layer 74a and the insulating layer 74b may be referred to collectively as the insulating layer 74.

[0070] Figures 4A and 4B show an example where the height of the upper end of insulating layer 74a from the reference plane and the height of the upper end of insulating layer 74b from the reference plane coincide with the height of the upper surface of insulating layer 62 from the reference plane. However, the height of the upper end of insulating layer 74a from the reference plane and the height of the upper end of insulating layer 74b from the reference plane may be lower than the height of the upper surface of insulating layer 62 from the reference plane. Thus, the height of the upper end of insulating layer 74a from the reference plane and the height of the upper end of insulating layer 74b from the reference plane can be less than or equal to the height of the upper surface of insulating layer 62 from the reference plane. Although Figures 4A and 4B show an example where the height of the upper end of insulating layer 74a from the reference plane coincides with the height of the upper end of insulating layer 74b from the reference plane, these heights do not have to coincide. For example, the height of the upper end of insulating layer 74b from the reference plane may be lower than the height of the upper end of insulating layer 74a from the reference plane.

[0071] In the example described above, the reference surface can be, for example, the top surface of the substrate or the top surface of the insulating layer 87. In subsequent examples, the top surface of the substrate or the top surface of the insulating layer 87 may also be used as the reference surface.

[0072] The semiconductor layer 51 has a region located inside the opening 63. Within the opening 63, the semiconductor layer 51 has a region in contact with the side surface of the insulating layer 74b. The semiconductor layer 51 may also have a region in contact with the side edge of the insulating layer 74a.

[0073] In the semiconductor layer 51, the region located inside the opening 63 has a shape that reflects the shape of the opening 63. The semiconductor layer 51 also has a region located on the insulating layer 62, a region located on the insulating layer 74a, and a region located on the insulating layer 74b outside the opening 63. For example, the semiconductor layer 51 has a region in contact with the upper surface of the insulating layer 62. The semiconductor layer 51 may also have a region in contact with the upper end of the insulating layer 74a and a region in contact with the upper end of the insulating layer 74b.

[0074] The semiconductor layer 51 has a region that is in contact with the conductive layer 55. For example, the bottom surface of the semiconductor layer 51 is in contact with the top surface of the conductive layer 55. The semiconductor layer 51 can be in contact with the conductive layer 55 in the region that overlaps with the opening 63.

[0075] The thickness of the semiconductor layer 51 can be 1 nm or more and 50 nm or less, preferably 2.5 nm or more and 30 nm or less, more preferably 2.5 nm or more and 20 nm or less, more preferably 3 nm or more and 20 nm or less, and more preferably 3 nm or more and 10 nm or less. It is preferable that the semiconductor layer 51 has at least a portion of the above-mentioned thickness regions.

[0076] The conductive layer 56 is located on the insulating layer 62 and has a region that contacts the upper surface of the semiconductor layer 51. That is, the conductive layer 56 has a region that contacts the upper surface of the semiconductor layer 51 outside the opening 63. The conductive layer 56 also has an opening 64 that overlaps with the opening 63. The conductive layer 56 may also have a region located on the insulating layer 74a or a region located on the insulating layer 74b. The conductive layer 56 can also contact the upper surface of the semiconductor layer 51 in these regions.

[0077] The insulating layer 52 has a region located inside the opening 63, a region located inside the opening 64, a region located on the conductive layer 56, and a region located on the insulating layer 62. The insulating layer 52 can be provided so as to cover the conductive layer 56 and the semiconductor layer 51. The insulating layer 52 has recesses that reflect the shape of the recesses in the semiconductor layer 51 and the shape of the opening 64.

[0078] The insulating layer 52 can be made from an insulating material as described in the section [Insulating Layer] below.

[0079] The conductive layer 53 is provided on the insulating layer 52 such that it has a region located inside the opening 63. The conductive layer 53 may have a region located inside the opening 64. The conductive layer 53 may also have a region located on the conductive layer 56.

[0080] The conductive layer 53 is provided to fill at least a portion of the recesses in the insulating layer 52. The conductive layer 53 can be provided to fill, for example, the openings 63 and 64. Inside the opening 63, the conductive layer 53 has a region that faces the semiconductor layer 51 with the insulating layer 52 in between.

[0081] The conductive layer 53 can be made of a conductive material as described in the [Conductive Layer] section below. Preferably, the conductive layer 53 is made of a conductive material mainly composed of tungsten, copper, or aluminum. The conductive layer 53 may also be made of a laminated structure. For example, it can be made of a laminated structure of a titanium nitride film and a tungsten film on the titanium nitride film.

[0082] The semiconductor layer 51 has a region that faces the conductive layer 53 via an insulating layer 52, for example, inside the opening 63. At least a portion of this region functions as the channel formation region of the transistor 50. The region of the semiconductor layer 51 near the conductive layer 55 functions as either the source region or the drain region. The region of the semiconductor layer 51 near the conductive layer 56 functions as the other source region or drain region. Thus, the channel formation region is sandwiched between the source region and the drain region.

[0083] The semiconductor layer 51 has a region provided inside the opening 63 along the side surface of the insulating layer 74b. Furthermore, one of the source and drain electrodes of the transistor 50 (here, the conductive layer 55) is located below the insulating layer 74b. Additionally, the other source and drain electrode of the transistor 50 (here, the conductive layer 56) is located above the insulating layer 74b. As a result, at least a portion of the channel of the transistor 50 is formed inside the opening 63 along the side surface of the insulating layer 74b. In other words, the transistor 50 has a configuration in which current flows in the vertical direction. This allows the transistor 50 to reduce its occupied area compared to a planar transistor where the channel formation region, source region, and drain region are provided separately on the XY plane. Therefore, the semiconductor device can be highly integrated. Furthermore, when a semiconductor device according to one embodiment of the present invention is used as a memory device, the storage capacity per unit area can be increased. It can be said that the channel length direction of the transistor 50 has a component in the height direction (vertical direction).

[0084] From the above, it can be concluded that transistor 50 is a vertical transistor. Furthermore, the conductive layer 55 is the lower electrode of transistor 50. In addition, the conductive layer 56 is the upper electrode of transistor 50.

[0085] A metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as a semiconductor can be used as the semiconductor layer 51. In this case, the transistor 50 can be called an OS transistor.

[0086] For the semiconductor layer 51, it is preferable to use an indium-containing oxide, and particularly preferable to use indium oxide. The band gap of the indium-containing oxide is 2.0 eV or more, or 2.5 eV or more. By using a metal oxide with a large band gap for the semiconductor layer 51, the off-current of the transistor can be reduced. Because the OS transistor has a small off-current, the power consumption of the semiconductor device can be sufficiently reduced. In addition, because the OS transistor has high frequency characteristics, the semiconductor device can be operated at high speed. When indium oxide is used as the semiconductor layer 51, the transistor 50 can be called an I / O transistor.

[0087] For information on indium oxide that can be used as the semiconductor layer 51, please refer to the description in Embodiment 2. A detailed explanation is omitted here.

[0088] When an indium oxide film is used as the semiconductor layer 51, it is preferable that the semiconductor layer 51 is crystalline. For example, it is preferable that the semiconductor layer 51 has crystal grains. Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains. A polycrystalline film is composed of two or more crystal grains, while a single-crystal film can be considered to be composed of one crystal grain. In polycrystalline films, crystal grain boundaries (also called grain boundaries) can be observed, whereas in single-crystal films, crystal grain boundaries cannot be observed.

[0089] Furthermore, unlike polycrystalline films, no grain boundaries are observed in the channel formation region of a single-crystal film. Impurities that inhibit carrier flow (typically insulating impurities, insulating oxides, etc.) tend to segregate at grain boundaries. Therefore, if grain boundaries are present in the channel formation region, the variation in transistor characteristics at the grain boundaries becomes large. On the other hand, in a single-crystal film according to one aspect of the present invention, no grain boundaries are observed in the channel formation region, so the variation in the characteristics of the transistor 50 caused by these grain boundaries can be suppressed. In addition, by using a single-crystal film as the semiconductor layer 51, carrier scattering at the grain boundaries can be suppressed. Therefore, the transistor 50 can be a transistor with high field-effect mobility. Furthermore, the transistor 50 can be a highly reliable transistor.

[0090] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel formation region, a semiconductor layer in which the channel formation region is contained within a single crystal grain, or a semiconductor layer in which the crystal axis directions are the same in at least two regions within the channel formation region can be called a single crystal film. Alternatively, a semiconductor layer in which at least one crystal orientation is oriented in one direction in the channel formation region can be called a single crystal film. In the above cases, the grain size of the crystal grains can be made larger than both the channel length and channel width of the transistor. Note that if the grain size of the crystal grains of a semiconductor layer is larger than both the channel length and channel width of the transistor, the semiconductor layer may be considered a single crystal film.

[0091] In this specification, indium oxide having at least a crystalline portion or crystalline region in a film is referred to as crystalline indium oxide (Crystal IO) or crystalline indium oxide (Crystalline IO). Examples of Crystal IO or Crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0092] The semiconductor layer 51 may be a polycrystalline film or an amorphous film containing crystal grains. In this case, it is preferable that no crystal grain boundaries are observed or that there are few grain boundary components in the channel formation region. For example, by having one crystal grain located in the channel formation region, it is possible to create a configuration in which no crystal grain boundaries are observed in the channel formation region. Even with such a configuration, the same effects as the configuration in which the indium oxide film is a single crystal film can be achieved.

[0093] The crystallinity of the semiconductor layer 51 can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for the analysis.

[0094] Crystal grains can be identified, for example, in high-resolution TEM images. Furthermore, crystal grain boundaries can sometimes be identified, for example, in high-resolution TEM images. In other words, crystal grains and crystal grain boundaries can sometimes be observed in high-resolution TEM images of crystalline films. The overall magnification when acquiring TEM images is preferably 2 million times or more, and more preferably 4 million times or more.

[0095] One method for crystallizing the semiconductor layer 51 is to form a seed layer having a region in contact with the semiconductor layer 51, and then perform heat treatment. The seed layer functions as a seed or nucleus for the crystal growth of the semiconductor layer 51. However, if the heat treatment is performed after the formation of the conductive layer 56, oxygen contained in the semiconductor layer 51 and oxygen contained in the heat treatment atmosphere may be absorbed by the conductive layer 56, causing the conductive layer 56 to oxidize. This may result in an increase in the electrical resistance of the conductive layer 56.

[0096] In one aspect of the present invention, as described above, a conductive layer 56 is provided on the semiconductor layer 51. This allows the conductive layer 56 to be formed after the heat treatment described above. Thus, the semiconductor layer 51 can be crystallized while, for example, oxidation of the conductive layer 56 can be suppressed. As a result, a transistor exhibiting good electrical characteristics and high reliability can be provided. Furthermore, a highly reliable semiconductor device can be provided.

[0097] OS transistors have oxygen vacancies (V) in the channel formation region of an oxide semiconductor. Ｏ The presence of oxygen vacancies (V) and impurities can easily lead to fluctuations in electrical properties and reduced reliability. Ｏ Oxygen vacancies (sometimes referred to as H) can generate electrons that act as carriers. Therefore, if oxygen vacancies and impurities are present in the channel formation region of an oxide semiconductor, the OS transistor is likely to exhibit normally-on characteristics. Consequently, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region of an oxide semiconductor. In other words, it is preferable that the carrier concentration in the channel formation region of an oxide semiconductor is reduced and that it is i-type (intrinsic) or substantially i-type.

[0098] On the other hand, the source and drain regions of an OS transistor have more oxygen vacancies than the channel formation region. Ｏ It is preferable that the carrier concentration increases and the resistance decreases due to a high concentration of H, or a high concentration of impurities such as hydrogen, nitrogen, and metal elements. In other words, it is preferable that the source region and drain region of an OS transistor have a higher carrier concentration and be an n-type region (low-resistance region) compared to the channel formation region.

[0099] Therefore, in one aspect of the present invention, an insulating film having barrier properties against oxygen is used as the insulating layer 74b. This prevents oxygen contained in the semiconductor layer 51, specifically the channel formation region, from diffusing into the insulating layer 62 and suppressing the formation of oxygen vacancies in the channel formation region. Thus, fluctuations in the electrical characteristics of the transistor 50 can be suppressed, and reliability can be improved. Consequently, a highly reliable semiconductor device can be provided.

[0100] For example, an insulating film having gallium and oxygen can be used as the insulating layer 74b. Alternatively, an insulating film having aluminum and oxygen can be used as the insulating layer 74b. For example, gallium oxide or aluminum oxide can be used as the insulating layer 74b.

[0101] It is particularly preferable to use gallium oxide as the insulating layer 74b. The ionic radius of gallium is close to that of indium compared to that of aluminum. In other words, the difference between the ionic radii of indium and gallium is smaller than the difference between the ionic radii of indium and aluminum. Therefore, when indium oxide is used as the semiconductor layer 51, using gallium oxide as the insulating layer 74b increases the frequency of bonding between the indium atoms in the semiconductor layer 51 and the gallium atoms in the insulating layer 74b via oxygen atoms. Thus, it is possible to suppress the generation of oxygen vacancies or oxygen with dangling bonds at the interface between the semiconductor layer 51 and the insulating layer 74b.

[0102] As the insulating layer 74a, an insulating film having the function of capturing or fixing hydrogen (also called an insulating film having the function of gettering) is used. This allows hydrogen contained in the semiconductor layer 51 to be captured or fixed. Therefore, the amount of hydrogen contained in the semiconductor layer 51 can be reduced. Consequently, the formation of VoH in the semiconductor layer 51, specifically in the channel formation region, can be suppressed. As a result, it is possible to prevent the transistor 50 from exhibiting normally-on characteristics. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be provided. Furthermore, a highly reliable semiconductor device can be provided. Note that a semiconductor device according to one embodiment of the present invention does not need to have the insulating layer 74a. Also, a semiconductor device according to one embodiment of the present invention does not need to have both the insulating layer 74a and the insulating layer 74b.

[0103] For example, an insulating film containing hafnium and oxygen can be used as the insulating layer 74a. Specifically, as the insulating layer 74a, hafnium oxide, hafnium zirconium oxide, an oxide containing hafnium and silicon, etc., can be used.

[0104] Here, gallium oxide and aluminum oxide are insulating materials with lower hydrogen barrier properties than, for example, silicon nitride. Therefore, even when an insulating layer 74b is provided in a semiconductor device according to one embodiment of the present invention, by using gallium oxide or aluminum oxide for the insulating layer 74b, for example, hydrogen in the semiconductor layer 51 can permeate through the insulating layer 74b. Thus, hydrogen in the semiconductor layer 51 can be captured or fixed to the insulating layer 74a.

[0105] Figures 4A and 4B show an example in which the conductive layer 55 has a recess (hereinafter sometimes referred to as the first recess) that overlaps with the insulating layer 74a. By having the first recess in the conductive layer 55, the volume of the insulating layers 74a and 74b can be increased compared to the case in which the first recess does not exist. In addition, the contact area between the insulating layer 74b and the semiconductor layer 51 can be increased. Therefore, the diffusion of oxygen contained in the semiconductor layer 51 into the insulating layer 62 can be effectively suppressed.

[0106] Furthermore, Figures 4A and 4B show an example in which the conductive layer 55 has a recess that overlaps with the opening 64. To distinguish it from the first recess mentioned above, this recess is sometimes referred to as the second recess. By having the second recess in the conductive layer 55, the height of the bottom surface of the insulating layer 52 and the height of the bottom surface of the conductive layer 53 in the region overlapping with the opening 63 can be made lower compared to the case without the second recess, and can be made lower than, for example, the height of the upper surface of the conductive layer 55 in contact with the insulating layer 62. As a result, the gate electric field is more easily applied to the semiconductor layer 51, and the electrical characteristics of the transistor 50 can be improved.

[0107] Furthermore, because the conductive layer 55 has a second recess, the semiconductor layer 51 contacts not only the bottom of the second recess (the upper surface of the conductive layer 55) but also the side walls of the second recess. Therefore, the contact area between the semiconductor layer 51 and the conductive layer 55 can be increased. Consequently, the contact resistance between the semiconductor layer 51 and the conductive layer 55 can be reduced.

[0108] In the semiconductor device shown in Figures 4A and 4B, the conductive layer 55 has a first recess and a second recess located inside the first recess. The second recess is deeper than the first recess. In other words, the bottom surface of the second recess is located below (towards the insulating layer 87) the bottom surface of the first recess. The first recess is provided in the conductive layer 55 when forming the opening 63. The second recess is provided in the conductive layer 55 when forming the opening 64. Therefore, in the example shown in Figures 4A and 4B, the side wall of the first recess coincides with the side surface of the insulating layer 62 in the opening 63. Also, the side wall of the second recess coincides with the side edge of the insulating layer 74a on the semiconductor layer 51 side and the side surface of the insulating layer 74b on the semiconductor layer 51 side.

[0109] The bottom of the second recess preferably has a curved portion. The semiconductor layer 51, insulating layer 52, etc., provided on the curved portion may also have a curved portion. This reduces the concentration of the electric field on the insulating layer 52 near the second recess, improves the dielectric breakdown voltage of the transistor 50, and suppresses electrostatic discharge breakdown of the transistor 50. Therefore, the reliability of the semiconductor device can be improved.

[0110] The conductive layer 55 and the conductive layer 56 can be made from conductive materials described in the [Conductive Layer] section below. In particular, it is preferable to use conductive materials that are resistant to oxidation, materials that maintain conductivity even when absorbing oxygen, or conductive materials that have a function to suppress the diffusion of oxygen, respectively, for the conductive layer 55 and the conductive layer 56. Examples of such conductive materials include conductive materials containing nitrogen and conductive materials containing oxygen (also called oxide conductors). This makes it possible to suppress a decrease in the conductivity of the conductive layer 55 and the conductive layer 56.

[0111] It is particularly preferable that the conductive layer 55 and the conductive layer 56 have an oxide conductor. For example, it is preferable that the conductive layer 55 and the conductive layer 56 have at least one of the following: indium tin oxide (In-Sn oxide, also called ITO), silicon-containing ITO (In-Sn-Si oxide, also called ITSO), indium zinc oxide (In-Zn oxide), and indium titanium oxide (In-Ti oxide). These materials are preferred because, compared to materials composed of metallic elements (also called metallic materials), they are more likely to maintain conductivity even when absorbing oxygen. Furthermore, it is preferable that the contact resistance between the conductive layer 55 and the semiconductor layer 51, and the contact resistance between the conductive layer 56 and the semiconductor layer 51 can be reduced.

[0112] Furthermore, if the conductive layer 55 and conductive layer 56 have oxide conductors, the conductive layer 55 may function as one of the source region and drain region, and the conductive layer 56 may function as the other of the source region and drain region. This makes the entire semiconductor layer 51 i-type (intrinsic) or substantially i-type. In other words, it becomes unnecessary to create separate i-type (intrinsic) or substantially i-type regions and n-type regions (low-resistance regions) in the semiconductor layer 51. Therefore, even when the distance between the conductive layer 55 and the conductive layer 56 is shortened, a channel-forming region can be provided, resulting in a transistor that exhibits good electrical characteristics. Consequently, miniaturization or high integration of semiconductor devices can be achieved.

[0113] Figures 4A and 4B show an example in which the conductive layer 55 has a two-layer structure consisting of conductive layer 55_1 and conductive layer 55_2 on top of conductive layer 55_1. Similarly, Figures 4B show an example in which the conductive layer 56 has a two-layer structure consisting of conductive layer 56_1 and conductive layer 56_2 on top of conductive layer 56_1.

[0114] It is preferable that the conductive layer 55_2 and conductive layer 56_1, which have a region in contact with the semiconductor layer 51, have the above-mentioned oxide conductor. This makes it possible to lower the contact resistance between the conductive layer 55 and the semiconductor layer 51, and between the conductive layer 56 and the semiconductor layer 51. Furthermore, it is preferable that the conductive layer 55_1 that does not contact the semiconductor layer 51 has a material with higher conductivity than conductive layer 55_2. This makes it possible to make the conductivity of conductive layer 55_1 higher than that of conductive layer 55_2. Thus, the conductivity of conductive layer 55 can be made higher than when conductive layer 55 does not have conductive layer 55_1. Similarly, it is preferable that the conductive layer 56_2 that does not contact the semiconductor layer 51 has a material with higher conductivity than conductive layer 56_1, as this makes it possible to increase the conductivity of conductive layer 56. The conductive layer 55_1 and conductive layer 56_2 can have, for example, at least one of tungsten, copper, and aluminum. Here, by configuring the conductive layer 55 such that the second recess does not reach the conductive layer 55_1, it is possible to prevent the semiconductor layer 51 from coming into contact with the conductive layer 55_1. This prevents the conductive layer 55_1 from being oxidized by the oxygen contained in the semiconductor layer 51, thereby preventing an increase in the contact resistance between the semiconductor layer 51 and the conductive layer 55.

[0115] Preferably, the insulating layer 87 has barrier properties against hydrogen. By having a barrier property against hydrogen in the insulating layer 87 provided below the semiconductor layer 51, the diffusion of hydrogen from below the transistor 50 to the semiconductor layer 51 can be suppressed.

[0116] Since the insulating layer 87 functions as an interlayer insulating layer, a material with a low dielectric constant can be used. By using a material with a low dielectric constant for the interlayer insulating layer, parasitic capacitance between wirings can be reduced.

[0117] Figure 1B and others show an example where the insulating layer 87 has a single-layer structure. However, the insulating layer 87 can have a laminated structure of two or more layers. For example, the insulating layer 87 can have a two-layer structure consisting of a first insulating layer and a second insulating layer on the first insulating layer. For example, it is preferable to use a material with a low dielectric constant as the first insulating layer and a barrier insulating layer against hydrogen as the second insulating layer in contact with the conductive layer 55. Specifically, it is preferable to use a silicon oxide film as the first insulating layer and a silicon nitride film as the second insulating layer.

[0118] An insulating layer 88 is provided on the conductive layer 53 and on the insulating layer 52. Preferably, the insulating layer 88 has the function of suppressing hydrogen diffusion. For example, it is preferable to use silicon nitride, which has higher hydrogen barrier properties than silicon oxide, for the insulating layer 88.

[0119] In this way, by surrounding the top and bottom of the transistor 50 with a barrier insulating layer against hydrogen, the diffusion of hydrogen into the semiconductor layer 51 is suppressed, and the V in the channel formation region is reduced. Ｏ This allows for a reduction in H. This, in turn, improves the electrical characteristics and reliability of the transistor 50.

[0120] Figures 2A to 3B and Figure 5 show an example where the openings 63 and 64 are circular in plan view. By making them circular, the processing accuracy when forming the openings 63 and 64 can be improved, and openings of a fine size can be formed. Furthermore, by forming the opening 63 to be circular in plan view, the semiconductor layer 51, the insulating layer 52, and the conductive layer 53 are arranged concentrically. As a result, the distance between the conductive layer 53 and the semiconductor layer 51 becomes approximately uniform, so that the gate electric field can be applied to the semiconductor layer 51 approximately uniformly. In addition, the side surface of the conductive layer 53 located at the center of the opening 63 faces the side surface of the semiconductor layer 51 via the insulating layer 52. In other words, in plan view, the entire perimeter of the semiconductor layer 51 becomes the channel formation region. In this case, the channel width of the transistor 50 is determined by the length of the outer circumference, the length of the inner circumference, or the length midway between the outer and inner circumferences of the semiconductor layer 51. If the opening 63 is circular in plan view, the channel width can be calculated, for example, by multiplying the value obtained by subtracting twice the thickness of the insulating layer 74a and twice the thickness of the insulating layer 74b from the width (diameter) of the opening 63 by pi (π).

[0121] By increasing the width of the aperture 63, the channel width per unit area can be increased, and the on-current can be increased. On the other hand, by decreasing the width of the aperture 63, the area occupied by the transistor 50 can be reduced, and the semiconductor device can be highly integrated. The area occupied by the transistor 50, for example, the area of ​​the transistor 50 in a plan view, is roughly determined according to the width of the aperture 63.

[0122] The width of the opening 63 is determined by the thickness of the insulating layer 74a, insulating layer 74b, semiconductor layer 51, insulating layer 52, and conductive layer 53 provided inside the opening 63. The width of the opening 63 is preferably, for example, 5 nm to 100 nm, more preferably 10 nm to 60 nm, more preferably 20 nm to 50 nm, more preferably 20 nm to 40 nm, and even more preferably 20 nm to 30 nm.

[0123] The width of the opening 63 is preferably greater than the width of the opening 64. This allows the insulating layers 74a and 74b to be positioned outside the opening 64 in a plan view, in other words, so as not to overlap with the opening 64. Therefore, the channel width per unit area can be increased compared to the case where the insulating layer 74 is provided inside the opening 64, i.e., where the insulating layers 74a and 74b are provided so as to overlap with the opening 64. Thus, the on-current of the transistor 50 can be increased. Furthermore, the width of the opening 63 is preferably smaller than the width of the conductive layer 55. This makes it easier to align the conductive layer 55 with the opening 63, and can increase the manufacturing yield.

[0124] In plan view, the openings 63 and 64 are not limited to being circular, but can be, for example, a circle or an ellipse, a triangle, a quadrilateral (including rectangles, rhombuses, and squares), a pentagon, a star polygon, or any of these polygons with rounded corners. The circle is not limited to a perfect circle. Furthermore, the polygon can be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles of 180 degrees or less).

[0125] The channel length of transistor 50 is the distance between the source region and the drain region. In other words, the channel length of transistor 50 is roughly determined by the thickness of the insulating layer 62 on the conductive layer 55, or the height of the insulating layer 74 on the conductive layer 55. Therefore, the channel length of transistor 50 does not affect the area occupied by transistor 50, for example, the area of ​​transistor 50 in a plan view. The channel length of transistor 50 can be considered, for example, as the distance between the upper end of the region where the semiconductor layer 51 and the conductive layer 55 are in contact and the end of the region where the semiconductor layer 51 and the conductive layer 56 are in contact, in a cross-sectional view.

[0126] The height of the insulating layer 62 on the conductive layer 55 can be 0.1 nm to 500 nm, 1 nm to 300 nm, 5 nm to 100 nm, 5 nm to 60 nm, 5 nm to 50 nm, 5 nm to 40 nm, 5 nm to 30 nm, 5 nm to 20 nm, or 5 nm to 10 nm. Typically, it can be 1 nm to 300 nm, preferably 5 nm to 100 nm. This improves productivity and yield in the formation of the insulating layer 62, the formation of the openings 64, etc. Furthermore, it increases the on-current of the transistor 50, improving the frequency characteristics.

[0127] Figures 1A to 2B and 4B show a configuration in which the edges of the conductive layer 56 and the semiconductor layer 51 coincide outside the opening 64. The conductive layer 56 and the semiconductor layer 51 can be manufactured by processing using the same mask. Therefore, it is preferable that the number of masks required to manufacture the semiconductor device can be reduced. However, the present invention is not limited to this. For example, the edge of the semiconductor layer 51 may be located inside or outside the edge of the conductive layer 56 in one or both of the X and Y directions.

[0128] As shown in Figure 2A and other figures, the transistor 50 is provided at the intersection of a conductive layer 53 extending in the X direction and a conductive layer 56 extending in the Y direction. Thus, the transistor 50 has a structure that allows for high integration.

[0129] Figures 4A and 4B show an example where the side surface of the insulating layer 62 at the opening 63 is perpendicular to the reference plane. The side surface of the insulating layer 62 at the opening 63 may have a tapered shape. Having a tapered side surface at the opening 63 of the insulating layer 62 improves the coverage of the layer (semiconductor layer 51, etc.) provided inside the opening 63, and reduces defects such as porosity. When the side surface of the insulating layer 62 at the opening 63 has a tapered shape, the tapered angle of the side surface is preferably 45 degrees or more and less than 90 degrees. Specifically, a taper angle of 80 degrees or more and less than 90 degrees is preferable as it allows for miniaturization or high integration of the semiconductor device.

[0130] <Example of Semiconductor Device Configuration 2> Below, an example of a semiconductor device according to one aspect of the present invention, different from that shown in Figures 1A to 5, will be described. Note that explanations of parts that overlap with the above will be omitted, and only the differences will be explained in detail. Furthermore, even if components differ in position or shape, if their function is the same, they may be given the same reference numerals and their explanations may be omitted.

[0131] Figures 6A, 6B, and 7 are enlarged views of region R shown in Figure 4B. Region R includes the conductive layer 55_2, insulating layer 62, insulating layer 74a, insulating layer 74b, semiconductor layer 51, conductive layer 56, insulating layer 52, and conductive layer 53. Region R also includes openings 63 and 64.

[0132] Figure 6A shows an example in which the insulating layer 52 has a three-layer structure consisting of an insulating layer 52_1 in contact with the semiconductor layer 51, an insulating layer 52_2 on insulating layer 52_1, and an insulating layer 52_3 on insulating layer 52_2. The insulating layer 52_1 has an oxygen barrier property, which suppresses the diffusion of oxygen contained in the semiconductor layer 51 into the conductive layer 53 and the oxidation of the conductive layer 53. The insulating layer 52_1 can be made of the same material that can be used for the insulating layer 74b. For example, gallium oxide or aluminum oxide is preferably used for the insulating layer 52_1, and gallium oxide is particularly preferred.

[0133] Furthermore, it is preferable to use a material with a high dielectric constant (high-k) for the insulating layer 52_1. By using a high-k material as the insulating layer 52_1, the potential applied to the conductive layer 53 during operation of the transistor 50 can be lowered while maintaining the physical film thickness of the insulating layer 52, which functions as the gate insulating layer of the transistor 50. In addition, it becomes possible to thin the equivalent oxide thickness (EOT) of the insulating layer 52. As the above-mentioned gallium oxide and aluminum oxide are also high-k materials, they can be suitably used for the insulating layer 52_1. In addition to gallium oxide and aluminum oxide, other high-k materials that can be used for the insulating layer 52_1 include, for example, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxidized nitrides having aluminum and hafnium, oxides having silicon and hafnium, oxidized nitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0134] For example, it is preferable to use a material with a low dielectric constant as the insulating layer 52_2. For example, it is preferable that the insulating layer 52_2 has a silicon oxide film or a silicon oxidizride film.

[0135] The insulating layer 52_3 preferably has barrier properties against hydrogen. This configuration suppresses the diffusion of hydrogen into the semiconductor layer 51. Furthermore, the insulating layer 52_3 preferably has barrier properties against oxygen. The insulating layer 52_3 is provided between the channel-forming region and the conductive layer 53. This configuration suppresses the diffusion of oxygen contained in the channel-forming region into the conductive layer 53, preventing the formation of oxygen vacancies in the channel-forming region. It also suppresses the diffusion of oxygen contained in the semiconductor layer 51 into the conductive layer 53, preventing the conductive layer 53 from oxidizing. The insulating layer 52_3 preferably has less oxygen permeability than the insulating layer 52_2. Furthermore, the insulating layer 52_3 preferably has a function to suppress hydrogen diffusion. This prevents impurities such as hydrogen contained in the conductive layer 53 from diffusing into the semiconductor layer 51. For example, silicon nitride is preferably used as the insulating layer 52_3.

[0136] Figure 6B shows an example in which an insulating layer 52_4 is provided between insulating layer 52_2 and insulating layer 52_3 shown in Figure 6A. An insulating material applicable to insulating layer 74a can be used as insulating layer 52_4. For example, by providing an insulating layer 52_4 having the function of capturing or fixing hydrogen between insulating layer 52_3 and insulating layer 52_2, hydrogen contained in insulating layer 52_2, etc., can be captured or fixed.

[0137] Preferably, the insulating layer 52 has a four-layer structure in which a gallium oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in that order from the semiconductor layer 51 side. With this configuration, hydrogen in the semiconductor layer 51 diffuses into the insulating layer 52_4, and the hydrogen can be captured or fixed there. Therefore, the hydrogen concentration in the semiconductor layer 51 can be reduced.

[0138] The insulating layer 52 is preferably a thin film. For example, by setting the thickness of the insulating layer 52 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, the subthreshold swing value (also called the S value) can be reduced. The S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude while the drain voltage is constant in the subthreshold region.

[0139] Furthermore, the film thickness of each layer constituting the insulating layer 52 is preferably 0.1 nm to 20 nm, more preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, more preferably 1.0 nm to less than 5.0 nm, and even more preferably 1.0 nm to 3.0 nm. It is preferable that each layer constituting the insulating layer 52 has at least a portion of the above-mentioned film thickness region.

[0140] In addition, the insulating layer 52 may be configured without insulating layer 52_3 in the four-layer insulating layer 52. For example, insulating layer 52_1 may be an insulating layer having the function of capturing or fixing oxygen, insulating layer 52_2 may be an insulating layer having a low dielectric constant, and insulating layer 52_4 may be an insulating layer having the function of capturing or fixing hydrogen. Specifically, the insulating layer 52 can be a three-layer structure in which an aluminum oxide film, a silicon oxide film, and a hafnium oxide film are stacked in that order from the semiconductor layer 51 side.

[0141] To make the insulating layers 52_1 to 52_4 as thin as described above, it is preferable to deposit them using the atomic layer deposition (ALD) method. Furthermore, to form insulating layers 52_1 to 52_4 with good coverage inside the openings 63 and 64, it is preferable to deposit them using the ALD method.

[0142] Furthermore, in forming the insulating layer 52 having a laminated structure of multiple insulating films, it is preferable to use the ALD process two or more times. For example, it is preferable that two or more of the multiple insulating films of the insulating layer 52 are formed using the ALD process. By forming at least two or more insulating films using the ALD process, the coverage and uniformity of the film thickness of the insulating layer 52 can be improved. In addition, productivity can be increased by continuously forming, for example, two or more insulating films using the ALD process.

[0143] Although the above describes a configuration in which the insulating layer 52 has a three-layer or four-layer structure, the present invention is not limited to these. The insulating layer 52 can have a configuration having at least one of insulating layers 52_1 to 52_4. By configuring the insulating layer 52 with one, two, or three layers from insulating layers 52_1 to 52_4, the manufacturing process of semiconductor devices can be simplified and productivity can be improved.

[0144] Figure 7 shows an example in which the semiconductor layer 51 has a three-layer structure consisting of a semiconductor layer 51_1 in contact with the conductive layer 55_2, the insulating layer 74b, etc., a semiconductor layer 51_2 on semiconductor layer 51_1, and a semiconductor layer 51_3 on semiconductor layer 51_2. Here, semiconductor layer 51_3 has a region in contact with the conductive layer 56_1 and a region in contact with the insulating layer 52.

[0145] The semiconductor layers 51_1, 51_2, and 51_3 can all contain indium and oxygen. For example, indium oxide can be used for all three semiconductor layers 51_1, 51_2, and 51_3. In this case, for example, the deposition conditions for semiconductor layer 51_2 can be different from those for semiconductor layers 51_1 and 51_3. However, the deposition conditions for semiconductor layer 51_1 and semiconductor layer 51_3 can be the same.

[0146] For semiconductor layer 51_1 and semiconductor layer 51_3, films with higher film density and fewer defects than semiconductor layer 51_2 are used. For semiconductor layer 51_2, a film with higher carrier mobility than semiconductor layer 51_1 and semiconductor layer 51_3 is used.

[0147] As a result, the transistor 50 can be made into a transistor with high field-effect mobility and high reliability. Furthermore, by making the carrier mobility of the semiconductor layer 51_2 higher than the carrier mobility of the semiconductor layer 51_3 that is in contact with the insulating layer 52 inside the opening 63, the main path for carrier flow can be moved away from the interface between the insulating layer 52 and the semiconductor layer 51, compared to, for example, the case where the semiconductor layer 51_2 is in contact with the insulating layer 52 inside the opening 63. This reduces the effect of surface scattering. Therefore, for example, the on-current of the transistor 50 can be increased. In addition, the transistor becomes an embedded channel type transistor with the channel moved away from the interface of the gate insulating layer, and the field-effect mobility of the transistor 50 can be increased.

[0148] Here, we will explain the reliability of transistors. One of the indicators for evaluating the reliability of a transistor is the GBT (Gate Bias Temperature) stress test, which involves applying an electric field to the gate and holding it at a high temperature. Among these, a test in which a positive potential (positive bias) is applied to the gate relative to the source potential and drain potential and held at a high temperature is called the PBTS (Positive Bias Temperature Stress) test, and a test in which a negative potential (negative bias) is applied to the gate and held at a high temperature is called the NBTS (Negative Bias Temperature Stress) test. Furthermore, the PBTS test and NBTS test, which are performed under light irradiation, are referred to as the PBTIS (Positive Bias Temperance Illumination Stress) test and the NBTIS (Negative Bias Temperance Illumination Stress) test, respectively.

[0149] In n-channel transistors, a positive potential is applied to the gate when the transistor is turned on (current is flowing). Therefore, the variation in the threshold voltage during PBTS testing is one of the important indicators of transistor reliability that should be considered.

[0150] Semiconductor layer 51_1 and semiconductor layer 51_3 may contain indium, oxygen, and a first element that has a stronger bonding force with oxygen than indium. Specifically, indium oxide can be used for semiconductor layer 51_2, and indium oxide containing the first element can be used for semiconductor layers 51_1 and 51_3. This will result in oxygen vacancies and V near the surface of semiconductor layer 51. Ｏ The formation of H can be suppressed. Therefore, carrier scattering near the surface of the semiconductor layer 51, for example, near the surface of the semiconductor layer 51 on the insulating layer 52 side, can be reduced. Consequently, the transistor 50 can be a transistor with a large on-current.

[0151] The first element is preferably one or more selected from gallium, aluminum, yttrium, scandium, titanium, tungsten, molybdenum, tin, zirconium, hafnium, and tantalum. The first element is more preferably gallium, aluminum, yttrium, scandium, titanium, tungsten, molybdenum, or tin. The first element is even more preferably gallium, aluminum, yttrium, or scandium.

[0152] Gallium, aluminum, yttrium, and scandium mainly exist as trivalent cations, just like indium atoms. Therefore, by using gallium, aluminum, yttrium, or scandium as the first element, the carrier concentration in semiconductor layer 51_1 and semiconductor layer 51_3 can be kept low. When indium oxide is used as the semiconductor layer 51, as shown in Embodiment 2, the lower the carrier concentration in the semiconductor layer 51, the higher the field-effect mobility of the transistor 50 can be. As described above, by using gallium, aluminum, yttrium, or scandium as the first element, the transistor 50 can be made into a transistor with high field-effect mobility.

[0153] Furthermore, titanium and tungsten have a stronger bonding force with oxygen compared to molybdenum and tin. Therefore, when titanium or tungsten is used as the first element contained in semiconductor layer 51_1 and semiconductor layer 51_3, oxygen vacancies and V are less likely to be present in semiconductor layer 51 than when molybdenum or tin is used. Ｏ The formation of H can be suppressed. On the other hand, molybdenum and tin have bond lengths with oxygen that are closer to the bond length between indium and oxygen compared to titanium and tungsten. Therefore, when molybdenum or tin is used as the first element, it is easier to maintain the crystal structure of semiconductor layer 51 even if the content of the first element in semiconductor layer 51_1 and semiconductor layer 51_3 is increased compared to when titanium or tungsten is used.

[0154] For example, indium oxide with gallium added can be used for semiconductor layers 51_1 and 51_3, and indium oxide can be used for semiconductor layer 51_2. Alternatively, indium oxide with tungsten added can be used for semiconductor layers 51_1 and 51_3, and indium oxide can be used for semiconductor layer 51_2.

[0155] For example, in the semiconductor layer 51_3, the ratio of the number of atoms of the first element to the sum of the number of atoms of indium and the first element is preferably 0.1% to 5%, and more preferably 0.5% to 3%. This prevents oxygen vacancies and V in the semiconductor layer 51_3 and near the interface between the semiconductor layer 51_3 and the insulating layer 52. Ｏ This suppresses the formation of H and reduces scattering near the surface of the semiconductor layer 51 on the insulating layer 52 side. Furthermore, it reduces the amount of carriers generated by the inclusion of the first element, preventing the carrier concentration of the semiconductor layer 51 from increasing. Therefore, it prevents the field-effect mobility of the transistor 50 from decreasing.

[0156] As mentioned above, aluminum atoms, gallium atoms, yttrium atoms, and scandium atoms in metal oxides mainly exist as trivalent cations, just like indium atoms. Therefore, when the semiconductor layer 51_3 contains at least one of aluminum, gallium, yttrium, or scandium as the first element, the carrier concentration can be kept low even if the ratio of the number of atoms of the first element to the sum of the number of atoms of indium and the first element in the semiconductor layer 51_3 is greater than the above range. This makes the transistor 50 a transistor with high field-effect mobility. However, in order to reduce scattering due to cation disorder, it is preferable to set the above ratio in the semiconductor layer 51_3 to the above range. Here, the ratio of the number of atoms of the first element to the sum of the number of atoms of indium and the first element in the semiconductor layer 51_1 can also be set to the same range as the range that the ratio in the semiconductor layer 51_3 can take.

[0157] The content of the first element in semiconductor layer 51_2 is lower than at least the content of the first element in semiconductor layer 51_1 and the content of the first element in semiconductor layer 51_3. For example, the ratio of the number of atoms of the first element to the sum of the number of atoms of indium and the first element in semiconductor layer 51_2 is preferably less than 0.1%. Furthermore, it is preferable that it is below the detection limit in analysis using secondary ion mass spectrometry (SIMS), also known as SIMS analysis. The detection limit can be rephrased as background. The background in SIMS analysis differs for each element due to differences in ionization rate, detection sensitivity, etc., but when detecting metallic elements, it is generally about 1 × 10⁻⁶. １８ atoms / cm ３ For example, in titanium, 7 x 10 １５ atoms / cm ３ In tin, 2 x 10 １７ atoms / cm ３ This reduces the carrier concentration in the semiconductor layer 51_2, thereby increasing the field-effect mobility of the transistor 50. Furthermore, it reduces scattering originating from cation disorder in the semiconductor layer 51_2. Therefore, a transistor with a high on-current can be provided.

[0158] Furthermore, when indium oxide is used as semiconductor layer 51_2, and indium oxide containing the first element is used as semiconductor layers 51_1 and 51_3, the band gaps of semiconductor layer 51_1 and semiconductor layer 51_3 may be larger than the band gap of semiconductor layer 51_2. Also, for example, the lower end of the conduction band of semiconductor layer 51_1 and semiconductor layer 51_3 may be located closer to the vacuum level than the lower end of the conduction band of semiconductor layer 51_2. In other words, the electron affinity of semiconductor layer 51_1 and semiconductor layer 51_3 may be smaller than the electron affinity of semiconductor layer 51_2. Because the electron affinity of semiconductor layer 51_3 is smaller than that of semiconductor layer 51_2, the main path for carrier flow can be moved further away from the interface between the insulating layer 52 and the semiconductor layer 51 compared to the case where the electron affinity of semiconductor layer 51_3 is greater than or equal to that of semiconductor layer 51_2. This reduces the effect of surface scattering. Therefore, for example, the on-current of transistor 50 can be increased. The same may also be true when indium oxide containing the first element is used as semiconductor layer 51_2, and the content of the first element is lower than that of semiconductor layer 51_3.

[0159] It is preferable that the film thickness of semiconductor layer 51_1 and semiconductor layer 51_3 is thinner than the film thickness of semiconductor layer 51_2. For example, when the film thickness of semiconductor layer 51_2 is 4 nm or more, the film thickness of semiconductor layer 51_1 and semiconductor layer 51_3 are preferably 0.1 nm or more and 3 nm or less, more preferably 0.1 nm or more and 2 nm or less, more preferably 0.1 nm or more and 1 nm or less, and even more preferably 0.2 nm or more and 1 nm or less. This makes it possible to make the transistor 50 capable of applying a high electric field and having high field-effect mobility. Furthermore, it is possible to miniaturize or highly integrate the semiconductor device. Note that the boundary (also called the interface) between semiconductor layer 51_1 and semiconductor layer 51_2, and the boundary (also called the interface) between semiconductor layer 51_2 and semiconductor layer 51_3 may not be clearly visible. Therefore, in Figure 7, these interfaces are shown with dashed lines. In subsequent drawings as well, these interfaces are shown with dashed lines.

[0160] Figure 7 shows an example where the semiconductor layer 51 has a three-layer structure, but the present invention is not limited to this. The semiconductor layer 51 can have, for example, a two-layer structure, specifically a two-layer structure consisting of semiconductor layer 51_2 and semiconductor layer 51_3. In this case, semiconductor layer 51_2 is in contact with the conductive layer 55_2, the insulating layer 74b, etc.

[0161] Figures 1A, 1B, 4A, and 4B show an example where the side surface of the opening 64 of the conductive layer 56 coincides with the side surface of the semiconductor layer 51, specifically the side surface opposite to the side surface in contact with the insulating layer 74b. However, the present invention is not limited to this example. Figure 8 shows the region R shown in Figure 4B, illustrating an example where the side surface of the opening 64 of the conductive layer 56 protrudes from the side surface of the semiconductor layer 51 opposite to the side surface in contact with the insulating layer 74b. Due to the semiconductor device manufacturing process, the conductive layer 56 may have the configuration shown in Figure 8.

[0162] Figures 9A and 9B show an example where the insulating layer 62 shown in Figure 4A has a three-layer structure consisting of insulating layer 62_1, insulating layer 62_2 on insulating layer 62_1, and insulating layer 62_3 on insulating layer 62_2. Figure 9A shows an example where the upper surfaces of insulating layer 62_2 and insulating layer 62_3 are flat. Figure 9B shows an example where the upper surfaces of insulating layer 62_2 and insulating layer 62_3, as well as the upper surface of insulating layer 62_1, are flat.

[0163] It is preferable to use an oxygen barrier insulating layer for insulating layer 62_1 and insulating layer 62_3. By using an oxygen barrier insulating layer for insulating layer 62_1, oxidation of the conductive layer 55 and an increase in electrical resistance can be suppressed. By using an oxygen barrier insulating layer for insulating layer 62_3, the supply of oxygen to the region of the semiconductor layer 51 that overlaps with the conductive layer 56 can be suppressed. As a result, oxygen vacancies are more likely to form in the other of the source region and drain region of the semiconductor layer 51. Therefore, it is easier to reduce the resistance of the other of the source region and drain region of the semiconductor layer 51. Note that the insulating layer 62 may have a two-layer structure, for example, insulating layer 62_1 and insulating layer 62_2 on insulating layer 62_1. In other words, the insulating layer 62 does not have to have insulating layer 62_3.

[0164] It is preferable to use a material with a lower dielectric constant for the insulating layer 62_2 than for insulating layers 62_1 and 62_3. This suppresses the formation of parasitic capacitance between, for example, the conductive layer 55 and the conductive layer 56, and enables the provision of a semiconductor device capable of high-speed operation. In particular, it is preferable that the thickness of the insulating layer 62_2 is greater than the thickness of the insulating layer 62_1 and the insulating layer 62_3 in the region between the conductive layer 55 and the conductive layer 56, as this reduces the parasitic capacitance between the conductive layer 55 and the conductive layer 56.

[0165] For example, silicon nitride can be used as the insulating layer 62_1 and insulating layer 62_3. For example, silicon oxide can be used as the insulating layer 62_2. However, if an insulating material that is more permeable to oxygen than silicon nitride, such as silicon oxide, is used as the insulating layer 62_2, the conductive layer 55_1 may oxidize if the insulating layer 62_2 has a region in contact with the conductive layer 55_1. For example, during the heat treatment performed to crystallize the semiconductor layer 51, oxygen in the heat treatment atmosphere may be absorbed by the conductive layer 55_1, causing the conductive layer 55_1 to oxidize. This may increase the electrical resistance of the conductive layer 55_1. Therefore, in a semiconductor device according to one aspect of the present invention, the conductive layer 55 is covered with an insulating layer 62_1 that has barrier properties against oxygen, and an insulating layer 62_2 containing oxygen is provided on the insulating layer 62_1. This makes it possible to suppress oxidation of the conductive layer 55_1 while reducing the parasitic capacitance between the conductive layer 55 and the conductive layer 56. As a result, a semiconductor device that is highly reliable and capable of high-speed operation can be provided. Furthermore, when the insulating layer 62 is a single-layer structure as shown in Figures 1A, 1B, 4A, and 4B, the insulating layer 62 can be made from a material that can be used for insulating layer 62_1, for example. That is, silicon nitride can be used as the insulating layer 62.

[0166] Furthermore, silicon nitride also possesses hydrogen barrier properties. Therefore, by using silicon nitride as one or both of the insulating layer 62_1 and insulating layer 62_3, the diffusion of hydrogen into the semiconductor layer 51 can be suppressed.

[0167] It is preferable that the concentration of impurities such as water and hydrogen in the insulating layer 62 is reduced. In particular, it is preferable that the concentration of impurities such as water and hydrogen in the thicker insulating layer 62_2 is reduced. This suppresses the incorporation of impurities such as water and hydrogen into the channel formation region of the semiconductor layer 51. One method for reducing the concentration of impurities such as water and hydrogen in the insulating layer 62 is to perform heat treatment after the formation of insulating layer 62_2 and before the formation of insulating layer 74a. This allows impurities such as water and hydrogen in the insulating layer 62 to diffuse outward. Furthermore, by forming insulating layer 62_2 after forming insulating layer 62_1, oxidation of the conductive layer 55_1 can be suppressed even during the heat treatment. Alternatively, heat treatment may be performed after the formation of insulating layer 62_2 and before the formation of insulating layer 62_3.

[0168] Figure 10A is a plan view showing an example configuration of a semiconductor device having a transistor 50A. Figure 10B is a plan view of Figure 10A with some elements omitted. Figure 10C is a cross-sectional view between the dashed lines A1 and A2 shown in Figures 10A and 10B. Figure 10D is a cross-sectional view between the dashed lines B1 and B2 shown in Figures 10A and 10B. For the cross-sectional view between the dashed lines C1 and C2 shown in Figure 10C, please refer to Figure 5.

[0169] The semiconductor devices shown in Figures 10A to 10D differ from those shown in Figures 1A to 5 mainly in that they have a conductive layer 77, an insulating layer 89, and an insulating layer 86. In Figure 10B, the conductive layer 77 shown in Figure 10A is omitted.

[0170] In transistor 50A, the configuration from the conductive layer 55 to the insulating layer 52 is the same as that of transistor 50 described above, so a detailed explanation is omitted.

[0171] As shown in Figures 10C and 10D, the insulating layer 89 is provided so as to be located on the insulating layer 52. The insulating layer 89 also has an opening 66 that reaches the insulating layer 52, located at a position overlapping with the opening 64. The insulating layer 86 is provided on top of the insulating layer 89.

[0172] In the examples shown in Figures 10A to 10D, the conductive layer 53 is provided in an island-like manner. The conductive layer 53 has a region located inside the opening 63, a region located inside the opening 64, and a region located inside the opening 66. The conductive layer 53 can be provided so as to embed the openings 63, 64, and 66. The conductive layer 53 may have regions in contact with the insulating layer 52 inside the opening 63 and inside the opening 64. The conductive layer 53 may also have a region in contact with the insulating layer 89 inside the opening 66.

[0173] The conductive layer 77 is provided on the insulating layer 89, the insulating layer 86, and the conductive layer 53, and is in contact with the upper surface of the conductive layer 53. The conductive layer 53 and the conductive layer 77 are connected. The conductive layer 77 may be considered as a component of the transistor 50A. The height of the upper surface of the conductive layer 53, the height of the upper surface of the insulating layer 86, and the height of the upper end of the insulating layer 89 are the same.

[0174] The conductive layer 77 functions as gate wiring. The conductive layer 77 can be made from materials applicable to the conductive layer 53. For example, the conductive layer 77 can be made from high-melting-point materials such as tungsten or molybdenum, which offer both heat resistance and conductivity. Alternatively, low-resistance conductive materials such as aluminum or copper can be used. Using low-resistance conductive materials reduces wiring resistance.

[0175] The region of the conductive layer 77 that does not overlap with the opening 66 is mainly located on the insulating layer 86. Therefore, the conductive layer 77 overlaps with the conductive layer 56 mainly via the insulating layer 86 and the insulating layer 89. This allows for a greater physical distance between the gate wiring and the conductive layer 56 than in a semiconductor device having a transistor 50. Thus, the parasitic capacitance between the conductive layer 77 and the conductive layer 56 can be made smaller than the parasitic capacitance between the conductive layer 53 and the conductive layer 56 in a semiconductor device having a transistor 50. Note that the conductive layer 77 and the conductive layer 56 may have overlapping regions without the insulating layer 86.

[0176] Transistor 50A has a configuration in which the parasitic capacitance between the source electrode, the other drain electrode, and the gate wiring is reduced compared to transistor 50. Therefore, the frequency characteristics of a circuit using this transistor can be improved. On the other hand, a semiconductor device having transistor 50 can be manufactured with fewer steps than a semiconductor device having transistor 50A.

[0177] Although Figures 10A and 10B show an example where the opening 66 is circular in a plan view, the present invention is not limited to this. The shapes applicable to the opening 66 are the same as the shapes applicable to the opening 64 described above.

[0178] The insulating layer 89 preferably has the function of capturing or fixing hydrogen. This configuration allows for the capture or fixing of hydrogen contained in the semiconductor layer 51. Therefore, the amount of hydrogen contained in the semiconductor layer 51 can be reduced. The insulating layer 89 can be made from the same material used for the insulating layer 74a.

[0179] Furthermore, the insulating layer 89 can be used as a barrier insulating layer against hydrogen. This suppresses the diffusion of hydrogen from above the insulating layer 89 into the semiconductor layer 51. Since silicon nitride and silicon oxynitride are both poor permeability to oxygen and hydrogen, they can be suitably used for the insulating layer 89.

[0180] Furthermore, the insulating layer 89 may have a laminated structure consisting of an insulating layer having the function of capturing or fixing hydrogen and a barrier insulating layer against hydrogen. The insulating layer 89 may, for example, have a laminated film of an aluminum oxide film and a silicon nitride film on the aluminum oxide film.

[0181] Since the insulating layer 86 functions as an interlayer insulating layer, it is preferable to use a material with a low dielectric constant. For example, it is preferable that the insulating layer 86 has a silicon oxide film.

[0182] Figure 11A is a plan view showing an example configuration of a semiconductor device having a transistor 50B. Figure 11B is a cross-sectional view between the dashed lines A1 and A2 shown in Figure 11A. Figure 11C is a cross-sectional view between the dashed lines B1 and B2 shown in Figure 11A. Figure 11D is a cross-sectional view between the dashed lines C1 and C2 shown in Figure 11B.

[0183] The semiconductor device shown in Figures 11A to 11D differs from the semiconductor device shown in Figures 1A to 5 mainly in that an insulating layer 65 is provided between the insulating layer 62 and the semiconductor layer 51, and between the insulating layer 62 and the insulating layer 52. Also, the transistor 50B differs from the transistor 50 mainly in that it has a conductive layer 60.

[0184] The conductive layer 60 is located on the insulating layer 62. The conductive layer 60 has a region facing the conductive layer 53, with the insulating layer 74a, insulating layer 74b, semiconductor layer 51, and insulating layer 52 sandwiched between them. Figures 11A to 11D show an example in which the conductive layer 60 extends in the X direction.

[0185] The insulating layer 65 is located on the conductive layer 60 and the insulating layer 62. The semiconductor layer 51 also has a region located on the insulating layer 65. The opening 63 is provided not only in the insulating layer 62 but also in the conductive layer 60 and the insulating layer 65.

[0186] In transistor 50B, one of the conductive layer 53 and conductive layer 60 can be used as the gate electrode, and the other as the back gate electrode. Transistor 50B may be particularly suitable in which conductive layer 53 is used as the gate electrode and conductive layer 60 as the back gate electrode. By using conductive layer 53 as the gate electrode, where the region facing the side surface of the semiconductor layer 51 inside the opening 63 is larger than that of conductive layer 60, the gate electric field is applied to the semiconductor layer 51 more efficiently. Therefore, the electrical characteristics of transistor 50B may be improved. When conductive layer 53 functions as the gate electrode and conductive layer 60 functions as the back gate electrode, insulating layer 52 functions as the gate insulating layer, and insulating layers 74a and 74b function as the back gate insulating layer. Conductive layer 60 has a region that functions as a back gate wiring.

[0187] As described above, transistor 50B has a back gate electrode. Therefore, the threshold voltage of transistor 50B can be controlled by the potential applied to the back gate electrode. By controlling the threshold voltage of transistor 50B, transistor 50B can be easily made into a normally-off transistor.

[0188] The conductive layer 60 can be made of a conductive material applicable to the conductive layer 53. The insulating layer 65 can be made of an insulating material applicable to the insulating layer 62.

[0189] In one embodiment of the present invention, the transistor in the semiconductor device may have a conductive layer 60 but may not have a conductive layer 53. In this case, the conductive layer 60 functions as the gate electrode of the transistor. The insulating layers 74a and 74b also function as gate insulating layers of the transistor. If the transistor does not have a conductive layer 53, it may also not have an insulating layer 52.

[0190] Figure 12 is an enlarged view of region R shown in Figure 11C. Region R shown in Figures 11C and 12 includes conductive layer 55_2, insulating layer 62, insulating layer 65, insulating layer 74a, insulating layer 74b, semiconductor layer 51, conductive layer 60, conductive layer 56, insulating layer 52, and conductive layer 53. Region R also includes openings 63 and 64. In Figure 12, the semiconductor layer 51 is shown as a three-layer structure consisting of semiconductor layer 51_1, semiconductor layer 51_2, and semiconductor layer 51_3, similar to the semiconductor layer 51 shown in Figure 7.

[0191] When indium oxide is used for all three semiconductor layers 51_1, 51_2, and 51_3, as described above, semiconductor layers 51_1 and 51_3 use films with a higher film density and fewer defects than semiconductor layer 51_2. Furthermore, semiconductor layer 51_2 uses a film with a higher carrier mobility than semiconductor layers 51_1 and 51_3. By making the carrier mobility of semiconductor layer 51_2 higher than that of semiconductor layer 51_1 and semiconductor layer 51_3, the main paths through which carriers flow can be moved away from the interface between the insulating layer 74b and semiconductor layer 51, and the interface between the insulating layer 52 and semiconductor layer 51, compared to the case where semiconductor layer 51 is, for example, a single layer of semiconductor layer 51_2. This reduces the effect of surface scattering. Therefore, for example, the on-current of transistor 50B can be increased. Furthermore, the transistor becomes an embedded channel type with the channel located away from the interface of the gate insulating layer and the back gate insulating layer, which increases the field-effect mobility of transistor 50B. In addition, by using films with a higher film density and fewer defects than semiconductor layer 51_2 as semiconductor layer 51_1 in contact with insulating layer 74b and semiconductor layer 51_3 in contact with insulating layer 52, the reliability of transistor 50B can be improved compared to the case where semiconductor layer 51_2 is in contact with insulating layer 74b and insulating layer 52.

[0192] As described above, semiconductor layer 51_1 and semiconductor layer 51_3 may contain indium, oxygen, and a first element that has a stronger bonding force with oxygen than indium. Specifically, indium oxide can be used for semiconductor layer 51_2, and indium oxide containing the first element can be used for semiconductor layer 51_1 and semiconductor layer 51_3. This will prevent oxygen vacancies and V-voids from forming near the surface of semiconductor layer 51 on the insulating layer 74b side and near the surface of insulating layer 52 side. Ｏ The formation of H can be suppressed. Therefore, carrier scattering near the surface of the semiconductor layer 51 on the insulating layer 74b side and near the surface of the insulating layer 52 side can be reduced. Consequently, the transistor 50B can be a transistor with a large on-current.

[0193] In semiconductor layer 51_1, the ratio of the number of atoms of the first element to the sum of the number of atoms of indium and the first element is preferably 0.1% to 5%, and more preferably 0.5% to 3%, similar to semiconductor layer 51_3 described above. This prevents oxygen vacancies and V in semiconductor layer 51_1 and near the interface between semiconductor layer 51_1 and insulating layer 74b. Ｏ This suppresses the formation of H and reduces scattering near the surface of the semiconductor layer 51 on the insulating layer 74b side. Furthermore, it reduces the amount of carriers generated by the inclusion of the first element, preventing the carrier concentration of the semiconductor layer 51 from increasing. Therefore, it prevents the field-effect mobility of the transistor 50B from decreasing.

[0194] As described above, when indium oxide is used as semiconductor layer 51_2, and indium oxide containing the first element is used as semiconductor layer 51_1 and semiconductor layer 51_3, the electron affinity of semiconductor layer 51_1 and semiconductor layer 51_3 may be smaller than the electron affinity of semiconductor layer 51_2. As a result, compared to the case where the electron affinity of semiconductor layer 51_1 and semiconductor layer 51_3 is greater than or equal to the electron affinity of semiconductor layer 51_2, the main paths through which carriers flow can be moved away from the interface between insulating layer 74b and semiconductor layer 51, and the interface between insulating layer 52 and semiconductor layer 51. This reduces the effect of surface scattering. Therefore, for example, the on-current of transistor 50B can be increased. The same may be true when indium oxide containing the first element is used as semiconductor layer 51_2, and the content of the first element is lower than that of semiconductor layer 51_1 and semiconductor layer 51_3.

[0195] Figures 13A and 13B show examples where the insulating layer 62 shown in Figure 11B has a three-layer structure, similar to the examples shown in Figures 9A and 9B. Also, Figures 13A and 13B show examples where the insulating layer 65 shown in Figure 11B has a three-layer structure consisting of insulating layer 65_1, insulating layer 65_2 on insulating layer 65_1, and insulating layer 65_3 on insulating layer 65_2. In Figure 13A, an example is shown where the top surfaces of insulating layer 62_2, insulating layer 62_3, insulating layer 65_2, and insulating layer 65_3 are flat. In Figure 13B, an example is shown where the top surfaces of insulating layer 62_2, insulating layer 62_3, insulating layer 65_2, and insulating layer 65_3 are flat, as are the top surfaces of insulating layer 62_1 and insulating layer 65_1.

[0196] The insulating layer 65_1 can be made of the same material that can be used for insulating layer 62_1. The insulating layer 65_3 can be made of the same material that can be used for insulating layer 62_3. For example, silicon nitride can be used for insulating layer 65_1 and insulating layer 65_3. Therefore, insulating layer 65_1 and insulating layer 65_3 can serve as barrier insulating layers against oxygen. The insulating layer 65_2 can be made of the same material that can be used for insulating layer 62_2, for example, silicon oxide can be used.

[0197] As mentioned above, silicon nitride also has barrier properties against hydrogen. Therefore, by using silicon nitride as at least one of the insulating layers 62_1, 62_3, 65_1, and 65_3, the diffusion of hydrogen into the semiconductor layer 51 can be suppressed.

[0198] By configuring the insulating layer 62 and insulating layer 65 as shown in Figure 13A or Figure 13B, the conductive layer 60 can be covered with insulating layer 62_3 and insulating layer 65_1 in addition to insulating layer 74a. Since insulating layer 62_3 and insulating layer 65_1 have barrier properties against oxygen, oxidation of the conductive layer 60 can be suppressed. This prevents the conductive layer 60 from becoming highly resistive. Furthermore, because insulating layer 65_3 has barrier properties against oxygen, the supply of oxygen to the region of the semiconductor layer 51 that overlaps with the conductive layer 56 can be suppressed. Therefore, it becomes easier to reduce the resistance of the source region and the other drain region of the semiconductor layer 51. Note that insulating layer 65 may have a two-layer structure, for example, insulating layer 65_1 and insulating layer 65_2 on insulating layer 65_1. In other words, insulating layer 65 does not have to have insulating layer 65_3.

[0199] <Example of Semiconductor Device Fabrication Method> Below, an example of a semiconductor device fabrication method according to one embodiment of the present invention will be described using Figures 14A to 15E. Figures 14A to 15E correspond to the cross-sectional view shown in Figure 4A.

[0200] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed using methods such as sputtering, chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), atomic layer deposition (ALD), and molecular beam epitaxy (MBE). CVD methods include plasma enhanced CVD (PECVD), thermal CVD, and photo CVD. Furthermore, thermal CVD methods include metal-organic vapor deposition (MOCVD) and metal CVD.

[0201] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by methods such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, slit coating, roll coating, and curtain coating.

[0202] Thin films constituting semiconductor devices can be processed using photolithography or other methods. Alternatively, thin films may be processed by nanoimprint lithography, lift-off lithography, or other methods. Furthermore, island-like thin films may be directly formed using a deposition method employing a shielding mask such as a metal mask.

[0203] Etching can be performed using methods such as dry etching or wet etching.

[0204] The following describes examples of methods for manufacturing semiconductor devices shown in Figures 1A to 5.

[0205] First, as shown in Figure 14A, an insulating layer 87 is formed on a substrate (not shown).

[0206] Next, as shown in Figure 14A, a conductive layer 55 is formed on the insulating layer 87. Figure 14A shows an example in which a conductive layer 55_1 and a conductive layer 55_2 on the conductive layer 55_1 are formed as the conductive layer 55. As mentioned above, the conductive layer 55_1 can be formed using, for example, at least one of tungsten, copper, and aluminum. The conductive layer 55_2 can be formed using an oxide conductor such as ITO.

[0207] Figure 14A shows an example where the side surface of the conductive layer 55 is perpendicular to the surface to be formed. Depending on the processing conditions of the conductive film that will become the conductive layer 55, the side surface of the conductive layer 55 may have a tapered shape that is inclined with respect to the surface to be formed.

[0208] Next, as shown in Figure 14A, an insulating layer 62 is formed on the conductive layer 55. The insulating layer 62 can be formed so as to cover the conductive layer 55.

[0209] As shown in Figure 14A, it is preferable to perform a planarization treatment on the upper surface of the insulating layer 62. Furthermore, if the insulating layer 62 has a laminated structure, it is preferable to perform the planarization treatment on at least one layer. For example, the CMP (Chemical Mechanical Polishing) method can be used for the planarization treatment.

[0210] It is preferable to perform heat treatment after forming the insulating layer 62. This allows impurities such as water and hydrogen in the insulating layer 62 to diffuse outward. Therefore, the concentration of impurities such as water and hydrogen in the insulating layer 62 can be reduced.

[0211] There are no special limitations on the equipment used for heat treatment; it may be an equipment that heats the workpiece by heat conduction or thermal radiation from a heat source such as a resistance heating element. For example, an electric furnace or an RTA (Rapid Thermal Anneal) equipment such as an LRTA (Lamp Rapid Thermal Anneal) or a GRTA (Gas Rapid Thermal Anneal) equipment can be used. An LRTA equipment is an equipment that heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp. A GRTA equipment is an equipment that performs heat treatment using high-temperature gas.

[0212] As the insulating layer 62, for example, as shown in Figures 9A and 9B, an insulating layer 62_1, an insulating layer 62_2 on insulating layer 62_1, and an insulating layer 62_3 on insulating layer 62_2 can be formed. As mentioned above, insulating layer 62_1 and insulating layer 62_3 can be formed using materials that have barrier insulating properties against oxygen, such as silicon nitride. In addition, insulating layer 62_2 can be formed using an insulating material with a lower dielectric constant than silicon nitride, such as silicon oxide. By forming insulating layer 62_2 after forming insulating layer 62_1 and then performing the heat treatment described above, oxidation of the conductive layer 55, specifically oxidation of conductive layer 55_1, caused by the heat treatment can be suppressed.

[0213] Next, as shown in Figure 14A, an opening 63 reaching the conductive layer 55 is formed in the insulating layer 62. For example, a resist mask is formed in the region other than the region that will become the opening 63, and the insulating layer 62 in the region where the resist mask is not formed is removed by etching. After etching, the resist mask is removed. At this point, due to the formation of the opening 63, a recess may be formed in the conductive layer 55, specifically the conductive layer 55_2, that overlaps with the opening 63.

[0214] Next, as shown in Figure 14B, insulating layers 74a and 74b are sequentially formed on the insulating layer 62 and the conductive layer 55. Insulating layer 74a is formed to cover the side walls and bottom of the opening 63. Insulating layer 74b is formed on top of insulating layer 74a. When insulating layers 74a and 74b are formed using, for example, the ALD method, it is preferable to form insulating layers 74a and 74b with good coverage.

[0215] Next, insulating layers 74b and 74a are processed by anisotropic etching. This removes the areas of insulating layers 74b and 74a located on the insulating layer 62, in other words, the areas located outside the opening 63, as shown in Figure 14C. In addition, a portion of the areas of insulating layers 74b and 74a that overlap with the opening 63 is also removed, exposing the upper surface of the conductive layer 55, specifically the upper surface of conductive layer 55_2. Figure 14C shows an example where the height of the upper end of insulating layer 74a from the reference plane and the height of the upper end of insulating layer 74b from the reference plane coincide with the height of the upper surface of insulating layer 62 from the reference plane. Note that the height of the upper end of insulating layer 74a from the reference plane and the height of the upper end of insulating layer 74b from the reference plane may be lower than the height of the upper surface of insulating layer 62 from the reference plane. Furthermore, while Figure 14C shows an example where the height of the upper end of the insulating layer 74b from the reference plane is the same as the height of the upper end of the insulating layer 74a from the reference plane, the height of the upper end of the insulating layer 74b from the reference plane may be lower than, for example, the height of the upper end of the insulating layer 74a from the reference plane.

[0216] As shown in Figure 14C, a second recess may be formed in the conductive layer 55, specifically the conductive layer 55_2, due to the processing of the insulating layer 74b and the insulating layer 74a. As described above, the second recess can be formed to be deeper than the first recess in the region overlapping with the insulating layer 74a.

[0217] Next, as shown in Figure 14D, the semiconductor layer 51 is formed having a region in contact with the conductive layer 55_2, a region in contact with the side surface of the insulating layer 74b, a region located on the insulating layer 74a, a region located on the insulating layer 74b, and a region in contact with the upper surface of the insulating layer 62. The semiconductor layer 51 can also be formed to have a region in contact with the side edge of the insulating layer 74a. The semiconductor layer 51 can be formed to cover the insulating layer 74a and the insulating layer 74b.

[0218] The semiconductor layer 51 is preferably formed using the ALD method. Since the ALD method is a film deposition method with superior coverage compared to the sputtering method, the coverage of the semiconductor layer 51 can be improved by forming the semiconductor layer 51 using the ALD method. Furthermore, by using the ALD method, which deposits atoms individually during film deposition, rather than the sputtering method, which impacts the surface to be formed with particles, the formation of crystal nuclei in the film can be suppressed. For example, a precursor and an oxidizing agent can be used to form the semiconductor layer 51. The precursor preferably contains indium. In this case, a film containing indium and oxygen is formed as the semiconductor layer 51. When the precursor contains indium, the thermal ALD method can be used as the ALD method.

[0219] Indium-containing precursors that can be used include trimethylindium, triethylindium, ethyldimethylindium, tris(1-methylethyl)indium, tris(2,2,6,6-tetramethyl-3,5-heptanedionic acid)indium, cyclopentadienylindium, indium(III) acetylacetonate, (3-(dimethylamino)propyl)dimethylindium, (diethylphosphino)dimethylindium, chlorodimethylindium, bromodimethylindium, and dimethyl(2-propanolat)indium.

[0220] Furthermore, inorganic precursors that do not contain hydrocarbons may be used as indium precursors. Examples of indium-containing inorganic precursors include halogenated indium compounds such as trifluoroindium (indium(III) fluoride), indium trichloride (indium(III) chloride), indium tribromide (indium(III) bromide), and indium triiodide (indium(III) iodide). Indium trichloride has a decomposition temperature of approximately 500°C to 700°C. Therefore, by using indium trichloride, film deposition by the ALD method can be performed while heating the substrate at approximately 400°C to 600°C, for example, at 500°C.

[0221] In the method for forming the semiconductor layer 51, it is preferable to use a precursor with a low impurity concentration, i.e., a high purity precursor. For example, by using a precursor with a purity of 3N (99.9%) or higher, preferably 4N (99.99%) or higher, more preferably 5N (99.999%) or higher, and even more preferably 6N (99.9999%) or higher, the impurities in the semiconductor layer 51 can be sufficiently reduced.

[0222] The gallium content and aluminum content of the indium-containing precursor are preferably 1000 ppm or less, more preferably 500 ppm or less, even more preferably 100 ppm or less, even more preferably 50 ppm or less, even more preferably 10 ppm or less, and even more preferably 1 ppm or less. By using a precursor with a low gallium content, the gallium concentration in the semiconductor layer 51 can be reduced, thereby improving the reliability of the transistor. Furthermore, by using a precursor with a low aluminum content, the aluminum concentration in the semiconductor layer 51 can be reduced, thereby improving the crystallinity of the semiconductor layer 51.

[0223] Furthermore, it is preferable to use a precursor that has been purified by two or more distillations (also called rectification or precision distillation) as the precursor used in this embodiment. Using such a precursor makes it easier to form a metal oxide film with fewer impurities, which is preferable. Performing distillation multiple times is preferable because it can further suppress the retention of impurities in the precursor that originate from the starting materials used in the manufacture of the precursor. However, the present invention is not limited to the above, and a precursor purified by one distillation, i.e., simple distillation, may also be used. Using simple distillation is preferable because it can reduce manufacturing costs. By performing distillation one or more times, the aluminum content of the indium-containing precursor can be set to 100 ppm or less, 1 ppm or less, or 1 ppb (0.001 ppm) or less.

[0224] Examples of oxidizing agents include ozone (O ３ ), oxygen (O ２ ), water (H ２ O), Nitrogen dioxide (NO) ２ ), nitrous oxide (N ２ O), hydrogen peroxide (H ２ O ２ ) and others can be used, and two or more of these may be used.

[0225] Unless otherwise specified in this specification, when ozone, oxygen, or water are used as oxidizing agents, these shall include not only gaseous or molecular states, but also plasma states, radical states, or ionic states.

[0226] When forming single crystals or polycrystalline materials with large grain sizes, it is preferable to use an oxidizing agent containing hydrogen to suppress the formation of crystal nuclei in the initial stages of film formation. For example, H ２ O, or H ２ O ２ It is preferable to use . After forming a film with few crystal nuclei, crystal growth can be achieved by heat applied during film formation or by heat treatment after film formation, thereby forming a single crystal film or a polycrystalline film with a large grain size. On the other hand, when reducing the hydrogen and nitrogen concentrations in the film, O is used as the oxidizing agent. ２ or O ３ It is preferable to use O３ It is preferable to use

[0227] When introducing the precursor into the reaction chamber, the substrate heating temperature is preferably set to a temperature corresponding to the decomposition temperature of the precursor. In the case of a thermal ALD method using triethylindium as the precursor containing indium, for example, the substrate heating temperature can be 100°C to 350°C, preferably 150°C to 300°C. When a seed layer 57 is provided, the substrate heating temperature can be room temperature (25°C) to 300°C, preferably room temperature to 200°C, and more preferably room temperature to 150°C.

[0228] The semiconductor layer 51 can also be formed using sputtering, CVD, MBE, or PLD. For example, when forming the semiconductor layer 51 using sputtering, the sputtering gas is hydrogen (H ２ It is preferable that the following are included. By introducing hydrogen when forming the semiconductor layer 51 using the sputtering method, a semiconductor layer 51 with low crystallinity can be formed. In addition, the generation of crystal nuclei can be suppressed or the disappearance of crystal nuclei can be promoted during the formation of the semiconductor layer 51. Note that a noble gas (typically argon) or a single gas of oxygen, or a mixed gas of a noble gas and oxygen can also be used as the sputtering gas.

[0229] Furthermore, when forming the semiconductor layer 51 using the sputtering method, the substrate temperature during film formation of the semiconductor layer 51 is preferably between room temperature (25°C) and 250°C, more preferably between room temperature and 200°C, and even more preferably between room temperature and 140°C. For example, setting the substrate temperature to between room temperature and 140°C is preferable because it increases productivity. It is also preferable because it suppresses the generation of crystal nuclei. In addition, the semiconductor layer can be formed at room temperature or without heating the substrate.

[0230] Next, as shown in Figure 14E, a sacrificial layer 91 is formed on the semiconductor layer 51. At this time, the sacrificial layer 91 is formed to fill the openings 63. Since the sacrificial layer 91 will be removed in a later step, it is preferable to use a material with a different etching rate from the semiconductor layer 51. Specifically, it is preferable that the etching selectivity ratio of the sacrificial layer 91 to that of the semiconductor layer 51 is large. When an indium oxide film is used as the semiconductor layer 51, for example, a silicon oxide film, an SOC film, or an SOG film can be used as the sacrificial layer 91. Here, if the film formation temperature of the sacrificial layer 91 is too high, the semiconductor layer 51 may crystallize before the formation of the seed layer 57, which will be described later. Therefore, it is preferable to form the sacrificial layer 91 at a temperature that does not cause the semiconductor layer 51 to crystallize.

[0231] Next, as shown in Figure 14F, a portion of the sacrificial layer 91 is removed to expose the upper surface of the semiconductor layer 51, specifically the upper surface in the region overlapping with the insulating layer 62, insulating layer 74a, or insulating layer 74b. The removal of a portion of the sacrificial layer 91 may be performed by CMP processing or by etching. For example, a wet etching method can be used as the etching method. Alternatively, a dry etching method may be used as the etching method. When removing a portion of the sacrificial layer 91 by etching, the removal of a portion of the semiconductor layer 51 can be suppressed by processing the sacrificial layer 91 under conditions where the etching selectivity ratio of the sacrificial layer 91 to the semiconductor layer 51 is large. Note that in Figure 14F, an example is shown where the height of the upper surface of the sacrificial layer 91 from the reference plane matches the height of the upper surface of the semiconductor layer 51 from the reference plane, but the height of the upper surface of the sacrificial layer 91 from the reference plane may be lower than the height of the upper surface of the semiconductor layer 51 from the reference plane. For example, when the sacrificial layer 91 is processed by etching, the height of the upper surface of the sacrificial layer 91 from the reference plane may be lower than the height of the upper surface of the semiconductor layer 51 from the reference plane.

[0232] Here, a portion of the sacrificial layer 91 may be removed using multiple methods. For example, the upper surface of the sacrificial layer 91 may be flattened by performing a CMP treatment on the sacrificial layer 91, and then an etching treatment, specifically a wet etching treatment, may be performed until the upper surface of the semiconductor layer 51 is exposed. By ending the CMP treatment before the upper surface of the semiconductor layer 51 is exposed, and then performing a wet etching treatment on the sacrificial layer 91 under conditions where the etching selectivity ratio of the sacrificial layer 91 to the semiconductor layer 51 is large, the removal of a portion of the semiconductor layer 51 can be suppressed compared to when the CMP treatment is performed until the upper surface of the semiconductor layer 51 is exposed. On the other hand, the amount of sacrificial layer 91 removed per unit time by the CMP treatment can be made larger than the amount of sacrificial layer 91 removed per unit time by the etching treatment. Therefore, by performing a CMP treatment before the etching treatment, a portion of the sacrificial layer 91 can be removed in a shorter time than when only the etching treatment is used to remove a portion of the sacrificial layer 91. Thus, the productivity of semiconductor devices can be increased.

[0233] Next, as shown in Figure 14G, a seed layer 57 is formed on the semiconductor layer 51 and the sacrificial layer 91. The seed layer 57 can be formed such that it has a region in contact with the upper surface of the semiconductor layer 51 and a region in contact with the upper surface of the sacrificial layer 91. The seed layer 57 functions as a seed or nucleus for crystal growth of the semiconductor layer 51. Forming the seed layer 57 using a sputtering method can increase the crystallinity of the seed layer 57. This is preferable as it promotes crystal growth of the semiconductor layer 51 in subsequent processes. It is preferable that the deposition temperature of the seed layer 57 be set to a temperature that prevents the semiconductor layer 51 from crystallizing. This suppresses the crystallization of the semiconductor layer 51 before the formation of the seed layer 57.

[0234] When indium oxide is used as the semiconductor layer 51, the seed layer 57 can be an oxide containing indium (typically indium oxide), an oxide containing one or both of yttrium and zirconium, or erbium oxide. Examples of oxides containing one or both of yttrium and zirconium include yttrium oxide, zirconium oxide, and oxides containing both yttrium and zirconium. These oxides can adopt a cubic crystal structure. Since the crystal structure of indium oxide is cubic, using these oxides as the seed layer 57 can promote epitaxial growth and accelerate the crystallization of the semiconductor layer 51.

[0235] Furthermore, an oxide having a hexagonal or trigonal crystal structure can also be used as the seed layer 57. Examples of oxides having a hexagonal or trigonal crystal structure include zinc oxide, In-Ga oxide, gallium zinc oxide (also written as Ga-Zn oxide or GZO), Al-Zn oxide, In-Ga-Zn oxide, In-Al-Zn oxide, and In-Sn-Zn oxide. It is preferable to use In-Ga-Zn oxide as the seed layer 57. In this case, the seed layer 57 contains indium, gallium, zinc, and oxygen. More specifically, it is preferable to have a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or close to that, or a composition of In:Ga:Zn = 1:3:2 [atomic ratio] or close to that.

[0236] In-Ga-Zn oxides and In-Sn-Zn oxides, etc., tend to have a CAAC (C-Axis Aligned Crystalline) structure. When an oxide having a CAAC structure is used for the seed layer 57, the c-axis direction of the seed layer 57 is perpendicular or approximately perpendicular to the reference plane. Therefore, by using an oxide that tends to have a CAAC structure for the seed layer 57, the controllability of the crystal planes in the crystal grains of the semiconductor layer 51 can be improved.

[0237] The thickness of the seed layer 57 is preferably thin, for example, thinner than the thickness of the semiconductor layer 51. Specifically, the seed layer 57 preferably has a region with a thickness of 0.1 nm or more and less than 2 nm, and more preferably has a region with a thickness of 0.5 nm or more and less than 2 nm.

[0238] Next, as shown in Figure 14H, a portion of the seed layer 57 is removed by processing. In the process shown in Figure 14H, at least the region of the seed layer 57 that overlaps with the sacrificial layer 91 is removed. By the processes shown in Figures 14G and 14H, the seed layer 57 is formed to have a region that is in contact with the upper surface of the semiconductor layer 51 and overlaps with the insulating layer 62. The removal of a portion of the seed layer 57 can be carried out by etching, for example, by dry etching or wet etching.

[0239] The shape of the seed layer 57 in plan view can be, for example, island-shaped or striped. Island-shaped or striped seed layers 57 may have tapered sides. The number of seed layers 57 may be one or multiple. The seed layer 57 may be formed to surround the entire opening 63 in plan view. In this case, the shape of the seed layer 57 in plan view can be annular, for example, circular. Furthermore, processing of the seed layer 57 is not required. That is, the process shown in Figure 14H is not required.

[0240] Next, heat treatment is performed. This causes the semiconductor layer 51 to crystallize, using the seed layer 57 as a seed or nucleus. Specifically, the crystal growth of crystal grains that have formed in the semiconductor layer 51 due to the seed layer 57 is accelerated by the heat treatment.

[0241] The heat treatment temperature is preferably 100°C to 450°C, more preferably 100°C to 350°C, more preferably 150°C to 350°C, more preferably 170°C to 350°C, and more preferably 200°C to 350°C. The heat treatment can be carried out in an atmosphere containing at least one of a noble gas, nitrogen, and oxygen. Dry air (CDA: Clean Dry Air) can be used as the nitrogen-containing atmosphere or the oxygen-containing atmosphere. It is preferable that the content of hydrogen, water, etc. in the atmosphere be kept to a minimum. It is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, as the atmosphere. By using an atmosphere with a minimum content of hydrogen, water, etc., it is possible to prevent hydrogen, water, etc. from being incorporated into the insulating layer 62 as much as possible. For example, an oven can be used for the heat treatment.

[0242] If the heat treatment temperature is too high, spontaneous nuclei are more likely to form, and crystal growth of these spontaneous nuclei will also proceed more easily. On the other hand, if the heat treatment temperature is too low, the rate of crystal growth of the crystal grains originating from the seed layer 57 will slow down, which may result in lower productivity of semiconductor devices. By setting the heat treatment temperature within the aforementioned range, it is possible to suppress the formation of spontaneous nuclei and the crystal growth of these spontaneous nuclei, while accelerating the rate of crystal grain growth.

[0243] The heat treatment can be performed using an RTA (Real-Time Atmosphere) apparatus. Using an RTA apparatus shortens the heat treatment time. Also, because the heat treatment time is short, the crystal growth of native nuclei is less likely to progress compared to the crystal growth of crystal grains caused by the seed layer 57. Therefore, when using an RTA apparatus, the heat treatment temperature can be increased. The heat treatment temperature is preferably 100°C to 750°C, more preferably 200°C to 700°C, more preferably 300°C to 700°C, more preferably 400°C to 700°C, and more preferably 500°C to 700°C. The treatment time is preferably 1 minute to 10 minutes, more preferably 3 minutes to 10 minutes, and more preferably 5 minutes to 10 minutes.

[0244] Microwave treatment may be performed after the heat treatment described above. Microwave treatment can reduce the concentration of impurities such as hydrogen or water in the semiconductor layer 51. In addition, the crystallinity of the semiconductor layer 51 may be improved. Details of microwave treatment will be described later.

[0245] Next, as shown in Figure 15A, the seed layer 57 is removed. The seed layer 57 can be removed, for example, by etching, specifically by wet etching. Alternatively, the seed layer 57 may be removed by CMP. Furthermore, it is not necessary to remove the seed layer 57. In other words, the steps shown in Figure 15A may not be performed.

[0246] It is not necessary to form the seed layer 57. That is, the steps shown in Figures 14G to 15A do not need to be performed. Even in this case, the semiconductor layer 51 can be crystallized by performing the heat treatment described above. By not forming the seed layer 57, the number of manufacturing steps for the semiconductor device can be reduced compared to when the seed layer 57 is formed. Also, for example, when removing the seed layer 57, it is possible to prevent a part of the semiconductor layer 51 from being removed. On the other hand, by forming the seed layer 57, it is possible to improve the controllability of the crystal grains on the crystal plane of the semiconductor layer 51 compared to when the seed layer 57 is not formed.

[0247] Next, as shown in Figure 15B, a conductive layer 56 is formed having a region in contact with the upper surface of the semiconductor layer 51 and a region located on the sacrificial layer 91. In forming the conductive layer 56, first, a conductive film that will become the conductive layer 56 is deposited. Next, a resist mask is formed on the conductive film, and the conductive layer 56 in the regions where the resist mask is not formed is removed by etching. Here, the semiconductor layer 51 is processed using the resist mask, that is, the semiconductor layer 51 in the regions where the resist mask is not formed is removed by etching, so that the edges of the conductive layer 56 and the edges of the semiconductor layer 51 can be aligned outside the opening 64, as shown in Figures 1A to 2B and Figure 4B. By processing the semiconductor layer 51 using the resist mask used for processing the conductive layer 56 in this way, the number of masks required to manufacture the semiconductor device can be reduced compared to the case where the resist mask used for processing the semiconductor layer 51 is different from the resist mask used for processing the conductive layer 56, which is preferable. After processing the semiconductor layer 51, the resist mask is removed.

[0248] Figure 15B shows an example in which a conductive layer 56 is formed, consisting of a conductive layer 56_1 and a conductive layer 56_2 on top of conductive layer 56_1. As mentioned above, conductive layer 56_1 can be formed using an oxide conductor such as ITO. Conductive layer 56_2 can be formed using, for example, at least one of tungsten, copper, and aluminum.

[0249] In one embodiment of the present invention, a semiconductor device is fabricated by forming a semiconductor layer 51, performing a heat treatment to crystallize the semiconductor layer 51, and then forming a conductive layer 56. This prevents oxidation of the conductive layer 56 caused by the heat treatment. Specifically, oxygen contained in the semiconductor layer 51 and oxygen contained in the heat treatment atmosphere are absorbed by the conductive layer 56, preventing oxidation of the conductive layer 56. As a result, a transistor exhibiting good electrical characteristics and high reliability can be fabricated. Furthermore, a highly reliable semiconductor device can be fabricated.

[0250] Next, as shown in Figure 15C, an opening 64 is formed in the conductive layer 56. For example, a resist mask is formed in the region other than the region that will become the opening 64, and the conductive layer 56 in the region where the resist mask is not formed is removed by etching. Dry etching or wet etching can be used for this etching process. Dry etching is suitable for microfabrication.

[0251] After the opening 64 is formed, the sacrificial layer 91 is removed. For example, the sacrificial layer 91 can be removed by processing it using the resist mask used to form the opening 64. The processing of the sacrificial layer 91 can be carried out by etching, for example, by dry etching or wet etching. After the removal of the sacrificial layer 91, the resist mask is removed.

[0252] Figure 15C shows an example in which the side surface of the opening 64 in the conductive layer 56 coincides with the side surface of the semiconductor layer 51, but the present invention is not limited to this. As shown in Figure 8, the opening 64 may be formed so that the side surface of the opening 64 in the conductive layer 56 protrudes relative to the side surface of the semiconductor layer 51. In this case, the sacrificial layer 91 has a region that overlaps with the protruding portion of the conductive layer 56. Therefore, when removing the sacrificial layer 91 using a wet etching method, it is preferable to remove the region of the sacrificial layer 91 that overlaps with the conductive layer 56. When removing the sacrificial layer 91 using a wet etching method, the resist mask may be removed after the opening 64 is formed before performing the wet etching process.

[0253] By forming an opening 64 as shown in Figure 8, it is possible to prevent a portion of the semiconductor layer 51 from being removed due to the formation of the opening 64. For example, it is possible to prevent a portion of the semiconductor layer 51 from being removed due to misalignment of the mask pattern. Therefore, the manufacturing yield of semiconductor devices can be increased.

[0254] Next, as shown in Figure 15D, an insulating layer 52 is formed on the semiconductor layer 51 and the conductive layer 56. It is preferable to use the ALD process two or more times when forming the insulating layer 52, which has a laminated structure of multiple insulating films. For example, it is preferable that two or more of the multiple insulating films of the insulating layer 52 are formed using the ALD process. By forming at least two or more insulating films using the ALD process, the coverage and uniformity of the film thickness of the insulating layer 52 can be improved. Furthermore, productivity can be increased by continuously forming, for example, two or more insulating films using the ALD process.

[0255] Next, it is preferable to perform microwave processing in an oxygen-containing atmosphere. Here, microwave processing refers to processing using, for example, a device having a power supply that generates high-density plasma using microwaves. Furthermore, in this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0256] In microwave processing, it is preferable to use a microwave processing apparatus that has a power supply for generating high-density plasma using microwaves. Here, the frequency of the microwave processing apparatus is preferably 300 MHz to 300 GHz, more preferably 2.4 GHz to 2.5 GHz, and can be, for example, 2.45 GHz. By using high-density plasma, high-density oxygen radicals can be generated. Furthermore, the power of the power supply for applying microwaves to the microwave processing apparatus is preferably 1000 W to 10000 W, and preferably 2000 W to 5000 W. The microwave processing apparatus may also have a power supply for applying RF (Radio Frequency) to the substrate side. Furthermore, by applying RF to the substrate side, oxygen ions generated by the high-density plasma can be efficiently guided into the film.

[0257] Microwave treatment is preferably carried out under reduced pressure, with a pressure of 10 Pa to 1000 Pa, and more preferably 300 Pa to 700 Pa. The treatment temperature is preferably room temperature (25°C) to 750°C, more preferably 300°C to 500°C, and even more preferably 400°C to 450°C.

[0258] Furthermore, after microwave treatment or plasma treatment, heat treatment may be performed continuously without exposure to the outside air. The heat treatment temperature is preferably, for example, 100°C to 750°C, more preferably 300°C to 500°C, and even more preferably 400°C to 450°C.

[0259] Microwave processing can be performed, for example, using oxygen gas and argon gas. Here, the oxygen flow rate ratio (O ２ / ( O ２ +Ar)) is preferably greater than 0% and 100% or less, more preferably greater than 0% and 50% or less, more preferably 10% or more and 40% or less, and even more preferably 10% or more and 30% or less.

[0260] When the insulating layer 52 is in a laminated structure, the microwave treatment described above is not necessarily performed after the insulating layer 52 has been deposited. For example, when two or more layers are laminated as the insulating layer 52, the microwave treatment may be performed before depositing the layer in contact with the conductive layer 53, or after depositing the layers in contact with the semiconductor layer 51 and the conductive layer 56, or after depositing the layer to be placed between these layers. Furthermore, the microwave treatment may be performed multiple times (at least two times).

[0261] By performing microwave processing in an oxygen-containing atmosphere, the above oxygen radicals are supplied to the semiconductor layer, and V in the semiconductor layer 51 Ｏ H and oxygen vacancies can be reduced. In particular, by performing microwave treatment after forming a conductive layer 56 on the semiconductor layer 51, the effects of high frequencies such as RF, microwaves, and oxygen plasma are shielded by the conductive layer 56. Therefore, these effects do not extend to the semiconductor layer 51 beneath the conductive layer 56. Consequently, it is possible to prevent the carrier concentration of the semiconductor layer 51 beneath the conductive layer 56, that is, the carrier concentration in the source region and the other drain region of the transistor 50, from decreasing due to microwave treatment.

[0262] Next, as shown in Figure 15E, a conductive layer 53 is formed on the insulating layer 52. The conductive layer 53 can be formed by depositing a conductive film that will become the conductive layer 53, and then processing the conductive film. The conductive layer 53 can be formed to have at least a region located inside the opening 63. From the above, a transistor 50 can be manufactured.

[0263] Next, as shown in Figure 15E, an insulating layer 88 is formed on the insulating layer 52 and the conductive layer 53. Through these steps, the semiconductor device shown in Figures 1A to 5 can be fabricated. Using this fabrication method, a transistor exhibiting good electrical characteristics and high reliability can be manufactured. Furthermore, a highly reliable semiconductor device can be fabricated.

[0264] <Materials for the semiconductor device> The following describes materials that can be used in the semiconductor device of this embodiment. Note that each layer constituting the semiconductor device of this embodiment may be a single-layer structure or a multilayer structure.

[0265] [Insulating Layers] For the insulating layers of a semiconductor device (insulating layer 52, insulating layer 62, insulating layer 65, insulating layer 86, insulating layer 87, insulating layer 88, insulating layer 89, etc.), it is preferable to use inorganic insulating films. Examples of inorganic insulating films include oxide insulating films, nitride insulating films, and oxidative nitride insulating films. Examples of oxide insulating films include silicon oxide films, aluminum oxide films, magnesium oxide films, gallium oxide films, germanium oxide films, yttrium oxide films, zirconium oxide films, lanthanum oxide films, neodymium oxide films, hafnium oxide films, tantalum oxide films, cerium oxide films, gallium zinc oxide films, and oxide films containing aluminum and hafnium. Examples of nitride insulating films include silicon nitride films and aluminum nitride films. Examples of oxidative nitride insulating films include silicon oxidative nitride films, aluminum oxidative nitride films, gallium oxidative nitride films, yttrium oxidative nitride films, and hafnium oxidative nitride films. Organic insulating films may also be used for the insulating layers of a semiconductor device.

[0266] For example, as transistors become smaller and more integrated, thinning of the gate insulating layer can lead to problems such as leakage current. By using a material with a high dielectric constant (high-k) for the gate insulating layer, it is possible to lower the voltage during transistor operation while maintaining the physical film thickness. It also becomes possible to thin the equivalent oxide thickness (EOT) of the gate insulating layer. On the other hand, by using a material with a low dielectric constant for the insulating layer that functions as an interlayer insulating layer, parasitic capacitance between wiring can be reduced. Therefore, it is preferable to select the material according to the function of the insulating layer. It should be noted that materials with a low dielectric constant also have high dielectric strength.

[0267] Examples of materials with a high dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, oxides containing hafnium and zirconium, oxides containing aluminum and hafnium, oxides containing aluminum and hafnium, oxides containing silicon and hafnium, oxides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0268] Examples of materials with low dielectric constant include inorganic insulating materials such as silicon oxide and silicon oxynitride, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with low dielectric constant include, for example, silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Also, for example, silicon oxide having vacancies can be used. These silicon oxides may contain nitrogen.

[0269] Furthermore, a ferroelectric material may be used for the insulating layer of the semiconductor device. Preferably, an oxide containing one or both hafnium and zirconium is used as the ferroelectric material. Examples of such oxides include metal oxides such as hafnium oxide, zirconium oxide, and hafnium-zirconium oxide. Alternatively, a material may be used in which element J1 (where element J1 is one or more selected from the other of hafnium and zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to a metal oxide containing either hafnium or zirconium as the ferroelectric material.

[0270] Furthermore, by adding a Group 3 element from the periodic table to an oxide containing one or both hafnium and zirconium, the oxygen vacancy concentration in the oxide increases, making it easier to form crystals with an orthorhombic crystal structure. This increases the proportion of crystals with an orthorhombic crystal structure, which is preferable because it allows for a larger amount of remanent polarization. On the other hand, if too much Group 3 element is added, the crystallinity of the oxide may decrease, making it difficult to exhibit ferroelectric properties. Therefore, the content of Group 3 elements in an oxide containing one or both hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of Group 3 elements refers to the ratio of the number of Group 3 elements to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0271] Furthermore, a material that may possess ferroelectric properties is a metal nitride having at least one of elements M1 and M2, and nitrogen. Here, element M1 is one or more selected from aluminum, gallium, indium, etc. Element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. Another material that may possess ferroelectric properties is a material in which element M3 is added to the above metal nitride. Element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc.

[0272] Furthermore, SrTaO is an example of a material that may possess ferroelectric properties. ２ N and BaTaO ２ Perovskite-type oxide nitrides such as N, and GaFeO with a κ-alumina structure. ３ Examples include lead titanate (PbTiO2) as a material that can possess ferroelectric properties. Ｘ ), or piezoelectric ceramics having a perovskite structure such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate may be used.

[0273] While the above explanation uses metal oxides and metal nitrides as examples, it is not limited to these. For example, materials obtained by adding nitrogen to the aforementioned metal oxides, or materials obtained by adding oxygen to the aforementioned metal nitrides, may also be used.

[0274] Furthermore, as a material that may possess ferroelectricity, for example, a mixture or compound consisting of multiple materials selected from the materials listed above can be used. Incidentally, since the crystal structure (properties) of the materials listed above may change not only depending on the film deposition conditions but also on various processes, in this specification, materials that exhibit ferroelectricity are not only called ferroelectrics, but also materials that may possess ferroelectricity.

[0275] In this specification, a layered structure of a material capable of ferroelectricity may be referred to as a ferroelectric layer, a metal oxide layer, or a metal nitride film. Furthermore, a device having such a ferroelectric layer, metal oxide layer, or metal nitride film may be referred to as a ferroelectric device in this specification.

[0276] The ferroelectric layer is preferably composed of crystals having an orthorhombic crystal structure, as this exhibits ferroelectric properties. The crystal structure of the crystals included in the ferroelectric layer may be one or more selected from tetragonal, orthorhombic, monoclinic, and hexagonal systems. The ferroelectric layer may also have an amorphous structure. In this case, the ferroelectric layer may have a composite structure comprising both an amorphous and a crystalline structure.

[0277] Metal oxides containing either or both hafnium and zirconium are insulating materials that have the function of capturing or fixing hydrogen. Therefore, by using a metal oxide containing either or both hafnium and zirconium in at least a portion of the gate insulating layer, hydrogen contained in the oxide semiconductor layer can be captured or fixed, thereby reducing the hydrogen concentration in the oxide semiconductor layer. Furthermore, a transistor having this gate insulating layer can function as an FeFET (Ferroelectric Field Effect Transistor).

[0278] Furthermore, transistors using metal oxides can have their electrical characteristics stabilized by surrounding them with an insulating layer that has the function of suppressing the permeation of impurities and oxygen. As an insulating layer that has the function of suppressing the permeation of impurities and oxygen, for example, an insulating layer containing one or more selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used in a single layer or multilayer configuration. Specifically, as the material for the insulating layer that has the function of suppressing the permeation of impurities and oxygen, metal oxides such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, nitrides such as aluminum nitride or silicon nitride, and oxidized nitrides such as silicon oxiditride can be used.

[0279] Specifically, materials for insulating layers that have the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, include metal oxides such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium. Also, nitrides such as aluminum nitride, titanium aluminum nitride, and silicon nitride are mentioned. Furthermore, oxidized nitrides such as silicon oxynitride are mentioned. Additionally, gallium oxide is mentioned as a material for insulating layers that has the function of suppressing oxygen permeation.

[0280] Furthermore, insulating layers that are in contact with the oxide semiconductor layer, such as gate insulating layers, or insulating layers provided near the oxide semiconductor layer, are preferably insulating layers that contain regions containing excess oxygen. For example, by having an insulating layer containing regions containing excess oxygen in contact with or near the oxide semiconductor layer, the oxygen vacancies in the oxide semiconductor layer can be reduced.

[0281] It is preferable to use a hydrogen barrier insulating layer for the insulating layer in contact with the oxide semiconductor layer, or an insulating layer provided near the oxide semiconductor layer. The insulating layer's hydrogen barrier properties suppress the diffusion of hydrogen into the oxide semiconductor layer. A hydrogen barrier insulating layer can also be described as an insulating layer that has the function of suppressing hydrogen diffusion.

[0282] Examples of insulating materials having the function of capturing or fixing hydrogen include metal oxides such as hafnium-containing oxides, magnesium-containing oxides, aluminum-containing oxides, aluminum and hafnium-containing oxides, and hafnium and silicon-containing oxides. Furthermore, these metal oxides may also contain zirconium; for example, examples include oxides containing hafnium and zirconium.

[0283] An insulating layer having the function of capturing or fixing hydrogen preferably has an amorphous structure. In metal oxides having an amorphous structure, some oxygen atoms have dangling bonds, thus having a high ability to capture or fix hydrogen. Therefore, by having an amorphous structure in the insulating layer, the function of capturing or fixing hydrogen can be enhanced.

[0284] By making the insulating layer amorphous, the formation of grain boundaries can be suppressed. Suppressing the formation of grain boundaries improves the flatness of the insulating layer. This makes the thickness distribution of the insulating layer more uniform, reducing areas with extremely thin thickness, and thus improving the dielectric strength of the insulating layer. Furthermore, the thickness distribution of the film provided on the insulating layer can be made more uniform. In addition, suppressing the formation of grain boundaries in the insulating layer reduces leakage current caused by defect levels at the grain boundaries. Therefore, the insulating layer can function as an insulating film with low leakage current.

[0285] Furthermore, the function of capturing or fixing a corresponding substance can also be described as the property of making the corresponding substance difficult to diffuse. Therefore, the function of capturing or fixing a corresponding substance can be rephrased as barrier properties.

[0286] In this specification, the term "barrier insulating layer" refers to an insulating layer that has barrier properties. Barrier properties refer to the property of making it difficult for the corresponding substance to diffuse (also referred to as the property of making it difficult for the corresponding substance to permeate, the property of having low permeability to the corresponding substance, or the function of suppressing the diffusion of the corresponding substance). When hydrogen is described as a corresponding substance, it refers to at least one of the following: a hydrogen atom, a hydrogen molecule, a water molecule, and a substance bonded to hydrogen such as OH-. When impurities are described as a corresponding substance, unless otherwise specified, they refer to impurities in the channel-forming region or semiconductor layer, such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N). ２ O, NO, NO ２ This refers to at least one of the following: copper atoms, etc. Furthermore, when oxygen is described as a corresponding substance, it refers to at least one of the following: oxygen atoms, oxygen molecules, etc.

[0287] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxides containing hafnium and zirconium, silicon nitride, or silicon oxynitride.

[0288] The inorganic insulating layers listed as having the function of capturing or fixing hydrogen, and the function of suppressing hydrogen diffusion, also possess barrier properties against oxygen. Examples of materials for the oxygen barrier insulating layer include oxides containing one or both of aluminum and hafnium, magnesium oxide, zinc gallium oxide, silicon nitride, silicon oxynitride, etc. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium, oxides containing hafnium and silicon, etc.

[0289] [Conductive Layers] The conductive layers (conductive layer 53, conductive layer 55, conductive layer 56, conductive layer 60, conductive layer 77, etc.) of the semiconductor device are preferably made of metal elements selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, palladium, iridium, strontium, lanthanum, etc., or alloys composed of the aforementioned metal elements, or alloys combining the aforementioned metal elements. As alloys composed of the aforementioned metal elements, nitrides of the alloys or oxides of the alloys may be used. For example, it is preferable to use tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used.

[0290] Furthermore, conductive materials containing nitrogen, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; conductive materials containing oxygen, such as oxides containing ruthenium oxide, strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metallic elements such as titanium, tantalum, or ruthenium are preferred because they are conductive materials that are resistant to oxidation, conductive materials that have the function of suppressing oxygen diffusion, or materials that maintain conductivity even when absorbing oxygen. Examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, ITO, indium tin oxide containing titanium oxide, ITSO, In-Zn oxide, and indium zinc oxide containing tungsten oxide. In this specification, conductive films formed using conductive materials containing oxygen are sometimes referred to as oxide conductive films.

[0291] Furthermore, multiple conductive layers formed from the above materials may be used in a laminated structure. For example, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with a nitrogen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material and a nitrogen-containing conductive material.

[0292] Furthermore, when using a metal oxide for the channel formation region of a transistor, it is preferable to use a laminated structure for the conductive layer that functions as the gate electrode, which combines a material containing the aforementioned metal element with a conductive material containing oxygen. In this case, it is preferable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen detached from the conductive material is more easily supplied to the channel formation region.

[0293] [Substrate] As a substrate for forming a transistor, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there are semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, or conductive resin substrates. Alternatively, there are substrates having metal nitrides, substrates having metal oxides, etc. Furthermore, there are substrates on which a conductor or semiconductor is provided on an insulating substrate, substrates on which a conductor or insulator is provided on a semiconductor substrate, and substrates on which a semiconductor or insulator is provided on a conductive substrate. Alternatively, substrates with elements mounted on them may be used. Examples of elements mounted on the substrate include capacitive elements, resistive elements, switch elements, light-emitting elements, or memory elements.

[0294] The above describes the materials that can be used in the semiconductor device of this embodiment.

[0295] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0296] (Embodiment 2) This embodiment describes an indium oxide film that can be used in the semiconductor layer of a transistor in a semiconductor device according to one aspect of the present invention.

[0297] In this specification, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0298] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0299] The carrier concentration dependence of the hole (Hall) mobility of indium oxide, silicon, and IGZO is described. Figure 16A shows silicon (Si) and indium oxide (InO Ｘ Figure 16B is a schematic diagram of the carrier concentration dependence of hole mobility with respect to IGZO.

[0300] First, as indicated by the arrows in Figure 16B, IGZO tends to exhibit higher hole mobility as the carrier concentration increases. On the other hand, as indicated by the arrows in Figure 16A, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases (see Non-Patent Literature 3). This trend is similar to that of silicon, where the lower the concentration of dopants (impurities) in the material, the less impurity scattering occurs and the higher the hole mobility. In other words, the higher the purity and intrinsic nature of indium oxide, the higher its hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that the properties of indium oxide shown in Figure 16A are assumed to be those of a single crystal. Therefore, when indium oxide is not a single crystal (for example, polycrystalline), the properties may differ from those shown in Figure 16A.

[0301] In Figure 16A, the low carrier concentration range R1 exhibits extremely high hole mobility, making it a suitable carrier concentration range for, for example, the channel formation region of a transistor. For example, in the case of indium oxide, the range R1 has a carrier concentration of 1 × 10⁻⁶. １５ cm −３ This range includes, for example, 1 × 10 １４ cm −３ The above is 1 x 10 １８ cm −３ The range is as follows: By sufficiently reducing the carrier concentration, the hole mobility value can be increased to 270 cm⁻¹. ２ It can be expected to be raised to the level of / (V・s).

[0302] Furthermore, in indium oxide, the region where the carrier concentration is within the range R1 may contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Other elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0303] On the other hand, the range R2 with high carrier concentration has low electrical resistance and can be said to be a suitable range of carrier concentration for applications such as the source and drain regions of a transistor, or for resistors or transparent conductive films. Range R2 is when the carrier concentration value is 1 × 10⁻⁶ ２０ cm −３ This range includes, for example, 1 × 10 １９ cm −３ The above is 1 x 10 ２２ cm −３ The range is as follows: By making the carrier concentration sufficiently high, the resistivity can be increased to 1 × 10⁻⁶. −４ It is expected that the level can be reduced to below Ω·cm.

[0304] In the indium oxide, the region where the carrier concentration is in the range R2 may contain elements that increase the carrier concentration. For example, it is preferable to include elements common to the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use elements whose oxides are conductive or semiconducting. As a method for supplying elements that increase the carrier concentration, methods such as forming a film containing the element and diffusing it, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. In this specification, unless otherwise specified, the presence or absence of mass separation is not limited. For example, in this specification, a method of supplying ions by mass separation is called ion implantation, and a method of supplying ions without mass separation is called ion doping.

[0305] In this way, indium oxide uses regions with low carrier concentrations for the transistor's channel formation region and regions with high carrier concentrations for the transistor's source and drain regions. In other words, indium oxide can be said to be an oxide in which valence electron control is possible. In contrast, with IGZO, strain can form in the source and drain regions due to stress on the electrodes in contact with IGZO, sometimes resulting in the formation of an n-type region. On the other hand, unlike IGZO, indium oxide allows for valence electron control, so it does not require the formation of strain in the film as in IGZO. Less strain in the film is expected to improve reliability. For example, by creating regions with carrier concentrations in the range R1 and range R2 shown in Figure 16A within the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Valence electron control in silicon transistors is generally known. On the other hand, valence electron control in indium oxide transistors is a novel technological concept that would not normally be conceived.

[0306] By applying the above technical concept, the indium oxide transistor described herein has two or more, preferably three or more, more preferably four or more, and most preferably five of the following features (1) to (5): (1) High on-current (in other words, high mobility). (2) Low off-current. (3) Normally off is possible. (4) High reliability. (5) High cutoff frequency (fT). For example, the indium oxide transistor described herein has high mobility, low off-current, and is normally off. This transistor is different from a transistor that is high mobility and normally on.

[0307] In addition, the i-type nature of a semiconductor means that its Fermi level (Ef) and its intrinsic Fermi level (Ei) are the same (Ef = Ei). As shown in Figure 16B, in IGZO, the lower the carrier concentration, the lower the hole mobility. Therefore, when Ef = Ei is reached, there are no carriers left (in other words, the material has properties similar to an insulator), and it may cease to function as a transistor. On the other hand, in indium oxide, as shown in Figure 16A, the lower the carrier concentration, the higher the hole mobility, and when Ef = Ei is reached, the hole mobility is maximized. That is, transistors containing indium oxide can achieve high field-effect mobility by setting Ef = Ei. Furthermore, because transistors containing indium oxide have a low carrier concentration, they tend to be normally off. Therefore, transistors containing indium oxide can be normally off and achieve high field-effect mobility.

[0308] Normally off refers to the state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source voltage is 0V. Normally off can be evaluated using the transistor's threshold voltage (Vth) or shift value (Vsh). Unless otherwise specified, Vth will be calculated using the constant current method. More specifically, Vth is the value of drain current (Id) × channel length (L) ÷ channel width (W) in the transistor's Id-Vg characteristic where the current is 1nA (1 × 10⁻¹⁰). −９ Let Vsh be the gate voltage (Vg) when A) is true. Also, Vsh is the tangent to the maximum slope when the drain current (Id) in the Id-Vg characteristic of the transistor is expressed logarithmically, and Id = 1pA (1 × 10⁻¹⁰). −１２ Vg is the gate voltage (Vg) at the intersection with the line in A), or the Vg at the intersection of the line extrapolated from the two points where the slope of Id is maximized when Id is expressed logarithmically in the transistor's Id-Vg characteristic, and the line where Id = 1 pA. For example, if either or both of Vth and Vsh are zero or positive values, it can be considered a normally-off transistor.

[0309] Furthermore, in transistors containing indium oxide, the film configuration in contact with the indium oxide film is crucial for making the semiconductor i-type, that is, for achieving Ef = Ei. For example, in transistors containing indium oxide, a film configuration can be obtained in which a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in contact with the indium oxide film. By using this film configuration, it is possible to create a semiconductor device that satisfies Ef = Ei and is highly reliable.

[0310] Furthermore, in the above film configuration, oxygen-containing films such as silicon oxide-nitride films, silicon oxide nitride films, aluminum oxide films, and gallium oxide films can be used instead of the silicon oxide film. Also, in the above film configuration, silicon oxide nitride films, silicon oxide nitride films, etc. can be used instead of the silicon nitride film. In addition, the hafnium oxide film located on the indium oxide side of the silicon nitride film functions as a hydrogen gettering site.

[0311] Furthermore, the above film configuration can also be viewed as a layered structure consisting of a film that can supply oxygen to the indium oxide film (e.g., a silicon oxide film), a film that can getter hydrogen (e.g., a hafnium oxide film), and a film that suppresses the intrusion of oxygen and hydrogen (e.g., a silicon nitride film). With this configuration, oxygen deficiencies in the indium oxide film are compensated for by oxygen in the silicon oxide film. Also, hydrogen in the indium oxide film is captured by the hafnium oxide film through heat treatment, etc. In addition, the silicon nitride film is provided to create a film configuration in which oxygen and hydrogen do not easily enter from the outside. In other words, by using the above film configuration, the indium oxide film can be made closer to type i. Therefore, transistors having the above indium oxide film have high field-effect mobility and high reliability.

[0312] Next, we will describe indium oxide films applied to transistors. Indium oxide films are preferably crystalline (i.e., they have crystal grains). Examples of films with crystal grains include single-crystal films, polycrystalline films, or amorphous films containing crystal grains (also called microcrystalline films). In particular, polycrystalline films are preferred for indium oxide films, and single-crystal films are more preferred. Single-crystal films do not have crystal grain boundaries. Impurities that inhibit carrier flow (typically insulating impurities, insulating oxides, etc.) tend to segregate at crystal grain boundaries. By using a single-crystal film, carrier scattering at crystal grain boundaries can be suppressed, enabling the realization of transistors with high field-effect mobility. Furthermore, it offers excellent effects such as suppressing variations in transistor characteristics caused by these crystal grain boundaries.

[0313] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using polycrystalline films, it is preferable to use films with the largest possible grain size and few grain boundaries. In a transistor to which a polycrystalline indium oxide film is applied, if there are no grain boundaries in the channel formation region, or if no grain boundaries are observed, the channel formation region is located within the single-crystal region contained in the polycrystalline film, and therefore it can be considered a transistor to which single-crystal indium oxide is applied.

[0314] The crystallinity of indium oxide can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0315] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel-forming region, a semiconductor layer in which the channel-forming region is contained within a single crystal grain, or a semiconductor layer in which the direction of the crystal axes is the same in at least two regions within the channel-forming region can be called a single crystal film. In addition, a semiconductor layer in which, within a single crystal grain in the channel-forming region, the direction of other crystal axes changes continuously with respect to a certain crystal axis or crystal orientation as the axis of rotation can be called a single crystal film.

[0316] The channel formation region refers to the region within the semiconductor layer that overlaps with (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, grain boundaries, crystal axes, and crystal orientation in the channel formation region can be confirmed by cross-sectional observation including the semiconductor layer, source electrode, and drain electrode.

[0317] The indium oxide film in the channel-forming region is preferable to have a low impurity concentration. Impurities in the indium oxide film in the channel-forming region can act as a scattering source for carriers, and thus can cause a decrease in field-effect mobility. Furthermore, these impurities can also inhibit the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The concentration of these impurities in the indium oxide film is preferably 0.1% or less, and more preferably 0.01% (100 ppm) or less. Note that carbon, hydrogen, and other elements may be present in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in higher concentrations than the above-mentioned impurities.

[0318] Furthermore, the indium oxide film in the channel-forming region may contain elements that can become trivalent cations like indium, as long as their crystals maintain a cubic crystal structure (Bixbite type). Examples include Group 13 elements of the periodic table such as gallium and aluminum, and Group 3 elements of the periodic table. Since these elements mainly exist as trivalent cations in the oxide, the carrier concentration of indium oxide can be kept low.

[0319] Furthermore, the indium oxide film described herein has a high film density. Here, an indium oxide film applicable to one aspect of the present invention (here, In ２ O ３ The membrane density of ) is shown in Table 1.

[0320]

[0321] As shown in Table 1, the film density of the indium oxide film was evaluated at six levels, Sample 1 to Sample 6. In Table 1, Condition 1 is the substrate condition for the indium oxide film, where Sample 1 to Sample 3 are glass, Sample 4 is a SiOx film formed by sputtering, and Sample 5 and Sample 6 are yttria-stabilized zirconia (YSZ). Condition 2 is the film deposition condition for the indium oxide film, where Sample 1 to Sample 3 are deposited by sputtering (SP), and Sample 4 to Sample 6 are deposited by ALD. Furthermore, condition 3 is the heat treatment condition after indium oxide film deposition. Sample 1, Sample 4, and Sample 5 are without heat treatment (as-depo), Sample 2 is baked at 350°C in a CDA atmosphere, Sample 3 is baked at 650°C in a CDA atmosphere, and Sample 6 is baked at 250°C in a vacuum atmosphere.

[0322] In Table 1, CDA stands for Clean Dry Air. It is preferable that the hydrogen and water content in the atmosphere during the heat treatment after indium oxide film formation (corresponding to condition 3) be kept as low as possible. It is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, as this atmosphere.

[0323] As shown in Table 1, the indium oxide film tends to have a higher film density when heat-treated compared to when it is not heat-treated (Sample 1, Sample 4, or Sample 5). This is because the heat treatment causes impurity elements (e.g., carbon, nitrogen, hydrogen, argon, etc.) to be removed from the film, resulting in a higher purity indium oxide film. Furthermore, as shown in Sample 5 and Sample 6, the indium oxide film on YSZ has a film density of 7.00 g / cm³. ３ It exceeds [value]. The theoretical value of the film density of the indium oxide film is 7.18 g / cm³. ３ In this specification, the range of film density for indium oxide films is 6.70 g / cm³. ３ 7.18g / cm or more ３ The following, preferably 6.90 g / cm³ ３ 7.18g / cm or more ３ The following, and more preferably 7.00 g / cm³ ３ 7.18g / cm or more ３ The following applies:

[0324] Furthermore, film density can be evaluated using methods such as Rutherford backscattering (RBS) or X-ray reflectivity (XRR). Differences in film density can sometimes be evaluated using transmission electron microscopy (TEM) images of the cross-section. In TEM observation, a high film density results in a darker (more intense) transmission electron (TE) image, while a low film density results in a fainter (brighter) transmission electron (TE) image.

[0325] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm². ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ It can be set to (V・s) or more.

[0326] One of the characteristics of the indium oxide film is that it has higher oxygen permeability (diffusivity) compared to the IGZO film. As shown in FIG. 16C, the oxygen (O) diffusing into the indium oxide film (denoted as InO Ｘ ) permeates through the indium oxide film and is released as oxygen molecules (O ２ ). In addition, by reacting with hydrogen contained in the film, it may be released as water molecules (H ２ O). Also, when there is oxygen deficiency (V Ｏ ) in the film, the diffusing oxygen atoms fill the oxygen deficiency. Since oxygen diffuses easily in the indium oxide film, it can be said that it is easier to fill oxygen deficiencies compared to the IGZO film.

[0327] Thus, since the indium oxide film is likely to reduce oxygen deficiencies in the film compared to the IGZO film, by applying such an indium oxide film to a transistor, a transistor showing extremely high reliability can be realized.

[0328] Also, as shown in FIG. 16C, the indium oxide film diffuses hydrogen. The hydrogen diffusing from the outside into the indium oxide film permeates through the indium oxide film and is released as hydrogen molecules (H ２ ). Or, by reacting with oxygen contained in the film, it is released as water molecules. Note that the above-mentioned oxygen and hydrogen diffuse through the indium oxide film by heat treatment. The temperature of the heat treatment is 200°C or higher and 700°C or lower, preferably 350°C or higher and 650°C or lower, more preferably 400°C or higher and 500°C or lower.

[0329] A transistor using an indium oxide film is an accumulation-type transistor with electrons as majority carriers. Assuming that the relaxation time of carriers is a constant value, the smaller the effective mass of electrons (carriers), the higher the electron mobility. That is, by using indium oxide with a small effective mass of electrons in a transistor, the on-current or the field-effect mobility of the transistor can be increased.

[0330] In Table 2, single-crystal indium oxide (here, In ２ O ３)( ) and the effective masses of single-crystalline silicon (Si) are shown respectively. As shown in Table 2, indium oxide has the characteristics that the effective mass of electrons is small and the effective mass of holes is large. Also, the effective mass of electrons in indium oxide has the characteristic of hardly depending on the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and a transistor with high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with an extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm channel width is 1 fA (1×10 −１５ A) or less, or 1 aA (1×10 −１８ A) or less at 125°C in an environment, and 1 aA (1×10 −１８ A) or less, or 1 zA (1×10 −２１ A) or less at room temperature (25°C) in an environment. Also, as shown in Table 2, since indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, there is a possibility of realizing a transistor with higher field-effect mobility and lower off-current than a Si transistor.

[0331]

[0332] It is preferable to provide a seed layer so as to contact at least a part of the crystalline indium oxide film. For the seed layer, it is preferable to use a material containing a crystal with a small difference in lattice constant (also called lattice mismatch) from indium oxide. Thereby, the crystallinity of the indium oxide film can be improved. Note that a substrate (for example, a single-crystalline substrate) may be used as one of the layers contacting at least a part of the crystalline indium oxide film.

[0333] As one method for evaluating the degree of lattice mismatch, there is a method using the value of lattice mismatch shown below. The lattice mismatch Δa [%] of the crystal of the formed film (here, the indium oxide film) with respect to the crystal of the seed layer is calculated as Δa = ((L １ −L ２ ) / L ２ )×100. Here, L１ L is the length of the unit cell vector of the crystals in the formed film, or the lattice constant. ２ This is the length of the unit cell vector of the crystal in the seed layer, or the lattice constant.

[0334] The lattice mismatch Δa between the seed layer and the indium oxide film is preferably small in absolute value, and most preferably zero. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0335] Here, the indium oxide crystal has a cubic structure (bixbite type). For example, yttria-stabilized zirconia (YSZ) crystals can have a cubic structure (fluorite type). The lattice mismatch of the indium oxide crystal with respect to the cubic YSZ crystal is in the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

[0336] Furthermore, the crystal structure of the seed layer and the crystal structure of the indium oxide film do not necessarily have to be the same in terms of crystal system or crystal orientation. For example, a film with a hexagonal or trigonal crystal structure can be used beneath an indium oxide film with a cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to crystal orientation necessary for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include wurtzite-type structures and YbFe. ２ O ４ Type structure, Yb ２ Fe ３ O ７ There are molded structures and their modified molded structures, etc. YbFe ２ O ４ Type structure or Yb ２ Fe ３ O ７An example of a crystal with a crystalline structure is IGZO. Indium oxide single crystal films can be formed not only on YSZ substrates but also on insulating films. On the other hand, it is difficult to form silicon single crystal films on insulating films. Silicon crystals have a diamond structure. Thus, in terms of single crystals, indium oxide and silicon have similar properties. However, when comparing indium oxide and silicon from the perspective of whether single crystals can be formed on insulating films, they have different properties.

[0337] Here, we compare transistors with crystalline indium oxide films, transistors with IGZO (In, Ga, Zn compound oxide) films, and transistors with silicon (Si) films. This comparison is shown in Table 3.

[0338]

[0339] In Table 3, transistors with a crystalline indium oxide film are explicitly labeled as "Crystal IO (LSI)" for LSI applications. Hereafter, they may simply be referred to as "Crystal IO". Transistors with an IGZO film are explicitly labeled as "IGZO (Display)" for display applications. Hereafter, they may simply be referred to as "IGZO". Transistors with a Si film may simply be referred to as "Si". In Table 3, ◎ represents +2 points, ○ represents +1 point, △ represents 0 points, and × represents -1 point. Total is the sum of the points for ◎, ○, △, and × shown in Table 3. A higher point value indicates better performance than a lower point value.

[0340] In Table 3, the first comparison item is minimal off-current, in which crystalline IO and IGZO are superior to Si. The second comparison item is on-current (Ion) characteristics, in which crystalline IO and Si are superior to IGZO. The third comparison item is reliability, in which crystalline IO and Si are superior to IGZO. The fourth comparison item is channel length miniaturization, in which crystalline IO and IGZO are superior to Si. In the channel length miniaturization item, VFET represents a vertical transistor, UFET represents a U-shaped transistor, and 3D structure represents a three-dimensional structure. The fifth comparison item is cutoff frequency, in which crystalline IO, Si, and IGZO have the best characteristics in that order. The sixth comparison item is improved integration density, in which Si is superior to crystalline IO and IGZO. Furthermore, the seventh comparison item is threshold voltage controllability (Vth controllability), in which Si is superior to crystalline IO and IGZO. The eighth comparison item is radiation resistance, in which crystalline IO and IGZO are superior to Si. The ninth comparison item is 3D (multi-stage) integrated structure, in which crystalline IO and IGZO are superior to Si. The tenth comparison item is the potential for self-heating, in which crystalline IO and IGZO are superior to Si.

[0341] As shown in Table 3, the total scores are 9 points for crystalline IO (LSI), 4 points for IGZO (Display), and 3 points for Si. Thus, a semiconductor device according to one aspect of the present invention, particularly a semiconductor device having a crystalline indium oxide film, has the potential to replace semiconductor devices using Si.

[0342] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0343] (Embodiment 3) In this embodiment, a storage device according to one aspect of the present invention will be described with reference to Figures 17A to 19. The storage device according to one aspect of the present invention has a memory cell. The memory cell has a transistor and a capacitive element.

[0344] The configuration of a memory device having memory cells will be explained using Figures 17A to 18C. Figure 17A is a plan view of a memory device having memory cells 150. Figure 17B is a cross-sectional view between the dashed lines A1 and A2 shown in Figure 17A. Figure 17C is a cross-sectional view between the dashed lines B1 and B2 shown in Figure 17A.

[0345] The memory device shown in Figures 17A to 17C comprises an insulating layer 140 on a substrate (not shown), a conductive layer 110 on the insulating layer 140, a memory cell 150 on the conductive layer 110, an insulating layer 180 on the conductive layer 110, and an insulating layer 62 on the insulating layer 180. The insulating layer 140 and the insulating layer 180 function as interlayer insulating layers. The conductive layer 110 functions as wiring.

[0346] The memory cell 150 includes a capacitive element 100 on a conductive layer 110 and a transistor 50 on the capacitive element 100.

[0347] The capacitive element 100 has a conductive layer 115 on a conductive layer 110, an insulating layer 130 on the conductive layer 115, and a conductive layer 55 on the insulating layer 130. The conductive layer 55 functions as one of a pair of electrodes (sometimes called the upper electrode), the conductive layer 115 functions as the other of a pair of electrodes (sometimes called the lower electrode), and the insulating layer 130 functions as a dielectric. In other words, the capacitive element 100 constitutes a MIM (Metal-Insulator-Metal) capacitance.

[0348] As shown in Figures 17B and 17C, the insulating layer 180 is provided with an opening 190 that reaches the conductive layer 110. At least a portion of the conductive layer 115 is located inside the opening 190. The conductive layer 115 has a region in contact with the upper surface of the conductive layer 110 at the opening 190 and a region in contact with the side surface of the insulating layer 180 at the opening 190. At least a portion of the insulating layer 130 is located inside the opening 190. At least a portion of the conductive layer 55 is located inside the opening 190. The conductive layer 55 is provided so as to fill the opening 190. A capacitive element 100 having such a configuration may be called a trench-type capacitor or trench capacitor. It is preferable that the films provided in the opening 190 be formed using the ALD method. This results in good coverage of the films. For example, it is preferable that the conductive layer 115, the insulating layer 130, and the conductive layer 55 be formed using the ALD method.

[0349] In the capacitive element 100, the upper electrode and lower electrode face each other with a dielectric in between, not only on the bottom surface but also on the side surface of the opening 190, which allows for a large capacitance per unit area. Therefore, the deeper the opening 190, the larger the capacitance of the capacitive element 100 can be. By increasing the capacitance per unit area of ​​the capacitive element 100 in this way, the read operation of the memory device can be made more stable. Furthermore, miniaturization or high integration of the memory device can be promoted.

[0350] Figures 17B and 17C show an example where the side wall of the opening 190 is perpendicular to the upper surface of the conductive layer 110, and the opening 190 is circular in plan view. This configuration makes it possible to miniaturize or highly integrate the memory device.

[0351] The conductive layer 110 functions as a wiring CAL, as described later, and can be provided in a strip shape, for example. A strip shape refers to a shape having a region extending in a certain direction (for example, the X direction, Y direction, or Z direction).

[0352] The conductive layer 110 can be formed as a single layer or in a laminated form using the conductive material described in the [conductive layer] of Embodiment 1. For example, a highly conductive material such as tungsten can be used as the conductive layer 110. By using a highly conductive material, the conductivity of the conductive layer 110 can be improved, allowing it to function sufficiently as a wiring CAL.

[0353] The conductive layer 115 has a region with a curved corner within the recess of the conductive layer 110. This suppresses electric field concentration on the insulating layer 130 near the region, compared to, for example, when the region has a corner (right angle or acute angle) in cross-sectional view. Therefore, dielectric breakdown of the insulating layer 130 is suppressed, and a highly reliable memory device can be provided.

[0354] The conductive layer 115 is preferably made of a conductive material that is resistant to oxidation, or a conductive material that has the function of suppressing oxygen diffusion, and is used in a single layer or laminate. For example, titanium nitride or ITSO may be used. Alternatively, for example, a structure in which a titanium nitride film is laminated on a tungsten film may be used. Alternatively, for example, a structure in which a tungsten film is laminated on a first titanium nitride film, and a second titanium nitride film is laminated on the tungsten film may be used. By using such a structure, if an oxide is used for the insulating layer 130, oxidation of the conductive layer 110 by the insulating layer 130 can be suppressed. Also, if an oxide is used for the insulating layer 180, oxidation of the conductive layer 110 by the insulating layer 180 can be suppressed.

[0355] The insulating layer 130 is provided so as to be in contact with the upper and side surfaces of the conductive layer 115. In other words, it is preferable that the insulating layer 130 has a structure that covers the side edges of the conductive layer 110. This prevents the conductive layer 115 and the conductive layer 55 from short-circuiting.

[0356] It is preferable to use a high-k material as the insulating layer 130. By using a high-k material as the insulating layer 130, the insulating layer 130 can be made thick enough to suppress leakage current, while also ensuring sufficient capacitance of the capacitive element 100.

[0357] Furthermore, the insulating layer 130 is preferably made by laminating insulating layers made of high-k material, and it is preferable to use a laminated structure of high-k material and a material with a higher dielectric strength than the high-k material. For example, as the insulating layer 130, an insulating film laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide can be used. Alternatively, for example, an insulating film laminated in the order of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide can be used. Alternatively, for example, an insulating film laminated in the order of hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide can be used. By laminating insulating layers with relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic discharge breakdown of the capacitive element 100 can be suppressed.

[0358] Furthermore, a material capable of ferroelectricity may be used as the insulating layer 130. For details on materials capable of ferroelectricity, please refer to the description in Embodiment 1.

[0359] Ferroelectric materials are insulators that exhibit internal polarization when an external electric field is applied, and this polarization remains even when the electric field is removed. Therefore, non-volatile memory elements can be formed using capacitive elements (sometimes referred to as ferroelectric capacitors) that utilize this material as a dielectric. Non-volatile memory elements using ferroelectric capacitors are sometimes called FeRAM (Ferroelectric Random Access Memory), ferroelectric memory, etc. For example, a ferroelectric memory has a transistor and a ferroelectric capacitor, with one of the transistor's sources and drains connected to one terminal of the ferroelectric capacitor. Therefore, when a ferroelectric capacitor is used as the capacitive element 100, the memory device shown in this embodiment functions as a ferroelectric memory.

[0360] The conductive layer 55 is provided in contact with the upper surface of the insulating layer 130. The side edges of the conductive layer 55 can be structured to coincide with the side edges of the insulating layer 130. This structure allows the conductive layer 55 and the insulating layer 130 to be formed using the same mask, simplifying the manufacturing process of the memory device. The side edges of the conductive layer 55 may be positioned inward from the side edges of the insulating layer 130 in either the X or Y direction.

[0361] Since the insulating layer 180 functions as an interlayer insulating layer, it is preferable that it has a low relative permittivity. By using a material with a low relative permittivity as the interlayer insulating layer, parasitic capacitance between wiring can be reduced.

[0362] A detailed explanation of transistor 50 will be omitted as it can be found in the description in Embodiment 1. Furthermore, the transistors in the memory cell 150 are not limited to transistor 50, and various transistors such as transistor 50A and transistor 50B exemplified in Embodiment 1 can be used. In addition, transistors with a planar structure or a GAA (Gate All Around) structure (including a GAA nanosheet structure) can also be used.

[0363] As shown in Figures 17A to 17C, the transistor 50 is provided so as to overlap with the capacitive element 100. Furthermore, the openings 63 and 64, which are part of the structure of the transistor 50, have regions that overlap with the opening 190, which is part of the structure of the capacitive element 100. In particular, the conductive layer 55 has the function of being one of the source electrode and drain electrode of the transistor 50 and the function of being the upper electrode of the capacitive element 100, so the transistor 50 and the capacitive element 100 share a part of their structure. With this configuration, the transistor 50 and the capacitive element 100 can be provided without significantly increasing the occupied area in a plan view. As a result, the occupied area of ​​the memory cell 150 can be reduced, so that the memory cell 150 can be arranged at a high density and the storage capacity of the storage device can be increased. In other words, the storage device can be highly integrated. Figures 17B and 17C show an example in which the width of the opening 190 is smaller than the width of the opening 63. The relative sizes of the widths of the opening 190 and the opening 63 are not particularly limited. From the viewpoint of miniaturization, it is preferable that the width of the opening 190 is the same as or smaller than the width of the opening 63.

[0364] Furthermore, by positioning the transistor 50 above the capacitive element 100, the transistor 50 is not affected by the heat treatment during the manufacturing of the capacitive element 100. Therefore, in the transistor 50, fluctuations in the threshold voltage, deterioration of electrical characteristics such as an increase in parasitic resistance, and an increase in variations in electrical characteristics due to the deterioration of electrical characteristics can be suppressed.

[0365] In the examples shown in Figures 17A to 17C, the conductive layer 53 is provided extending in the X direction, and the conductive layer 56 is provided extending in the Y direction.

[0366] The configuration shown in Figures 17A to 17C functions as a memory cell. The memory cell will be described in detail in a later embodiment.

[0367] The memory cell 150 may also have transistors instead of capacitive elements. In this case, the memory cell 150 has two transistors.

[0368] Figure 18A is a plan view of the memory device. Figure 18B is a cross-sectional view between the dashed lines A1 and A2 shown in Figure 18A. Figure 18C is a cross-sectional view between the dashed lines B1 and B2 shown in Figure 18A.

[0369] The memory device shown in Figures 18A to 18C has a memory cell 150 on an insulating layer 87. The memory cell 150 has a transistor 50a and a transistor 50b on the transistor 50a.

[0370] Detailed explanations of transistors 50a and 50b are omitted as they can be found in the description of transistor 50 in Embodiment 1. The transistors in the memory cell 150 are not limited to the combination of transistors 50a and 50b, and one or more of the transistors exemplified in Embodiment 1 can be used. Furthermore, a planar structure or a GAA structure transistor can be applied to one of transistors 50a and 50b.

[0371] In the memory cell 150 shown in Figures 18A to 18C, the capacitance generated between the conductive layer 55 and the conductive layer 56 of the transistor 50a can be utilized. Therefore, in the memory cell 150 shown in Figures 18A to 18C, data can be stored without separately forming a capacitive element.

[0372] As shown in Figures 18A to 18C, transistor 50b is provided so as to overlap with transistor 50a. Furthermore, the opening 63, through which part of the structure of transistor 50b is provided, has an overlapping region with the opening 63 through which part of the structure of transistor 50a is provided. Similarly, the opening 64 through which part of the structure of transistor 50b is provided has an overlapping region with the opening 64 through which part of the structure of transistor 50a is provided. In particular, since the conductive layer 55 functions as one of the source electrode and drain electrode of transistor 50b and as the gate electrode of transistor 50a, transistors 50b and 50a share a part of their structure. With this configuration, transistors 50b and 50a can be provided without significantly increasing the occupied area in a plan view. As a result, the occupied area of ​​the memory cell 150 can be reduced, allowing for a high-density arrangement of the memory cell 150 and increasing the storage capacity of the memory device. In other words, the memory device can be highly integrated.

[0373] In the examples shown in Figures 18A to 18C, the conductive layer 53 extends in the X direction, and the conductive layer 56 of the transistor 50b extends in the Y direction.

[0374] The configuration shown in Figures 18A to 18C functions as a memory cell. The memory cell will be described in detail in a later embodiment.

[0375] The memory cell 150 shown in this embodiment can be used as a memory cell in a storage device. The transistor 50 is an OS transistor. Because the transistor 50 has a small off-current, using it in a storage device makes it possible to retain the stored contents for a long period of time. In other words, refresh operations are not required, or the frequency of refresh operations is extremely low, so the power consumption of the storage device can be significantly reduced. In addition, because the transistor 50 has a high frequency characteristic, reading and writing to the storage device can be performed at high speed.

[0376] A memory cell array can be constructed by arranging the memory cells 150 in a three-dimensional matrix. By stacking layers containing multiple memory cells (also called memory layers), cells can be integrated and arranged without increasing the occupied area of ​​the memory cell array. In other words, a 3D memory cell array can be constructed.

[0377] Figure 19 shows an example of a cross-sectional configuration of a memory device in which a memory layer is stacked on a layer on which a drive circuit including a sense amplifier is provided.

[0378] In Figure 19, a memory cell 150 is provided above the transistor 300. Transistor 300 is one of the transistors in the sense amplifier. For details on the memory cell 150 shown in Figure 19, please refer to the description of the memory cell 150 mentioned above.

[0379] As shown in Figure 19, by configuring the sense amplifier to overlap with the memory cell 150, the bit line can be shortened. This reduces the bit line capacity and enables high-speed operation of the memory device.

[0380] The memory device shown in Figure 19 can correspond to the semiconductor device 900 described in Embodiment 4. Specifically, transistor 300 corresponds to the transistor in sense amplifier 927 of semiconductor device 900. Also, memory cell 150 corresponds to memory cell 950.

[0381] The transistor 300 is provided on a substrate 311 and includes a conductive layer 316 that functions as a gate, an insulating layer 315 that functions as a gate insulating layer, a semiconductor region 313 that is part of the substrate 311, and low-resistance regions 314a and 314b that function as a source region or drain region. The transistor 300 may be either a p-channel or an n-channel type. The substrate 311 preferably contains a silicon-based semiconductor, and more specifically, it preferably contains single-crystal silicon.

[0382] Furthermore, the substrate 311 can also be a structure in which a single-crystal oxide semiconductor film (typically an indium oxide film) is provided on a stabilized zirconia substrate. The indium oxide film formed on the stabilized zirconia substrate has a single crystal structure. By using a portion of the indium oxide film as a semiconductor region 313, the field-effect mobility of the transistor 300 can be increased. In addition, the reliability of the transistor 300 can be improved.

[0383] In Figure 19, the transistor 300 has a convex shape in the semiconductor region 313 (part of the substrate 311) where the channel is formed. Furthermore, a conductive layer 316 covers the side and top surfaces of the semiconductor region 313 via an insulating layer 315. The conductive layer 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. It may also have an insulating layer in contact with the upper part of the convex portion, functioning as a mask for forming the convex portion. While this example shows the formation of the convex portion by processing a part of the semiconductor substrate, a semiconductor film with a convex shape may also be formed by processing an SOI substrate.

[0384] Between each structure, there may be a wiring layer containing an interlayer insulating layer, wiring, plugs, etc. Furthermore, multiple wiring layers may be provided depending on the design. Here, conductive layers functioning as plugs or wiring may be grouped together and assigned the same reference numeral. Also, in this specification, the wiring and the plug connected to the wiring may be a single integrated unit. That is, there may be cases where a part of the conductive layer functions as wiring, and cases where a part of the conductive layer functions as a plug.

[0385] For example, on the transistor 300, insulating layers 320, 322, 324, and 326 are stacked in order as interlayer insulating layers. In addition, a conductive layer 328 is embedded in insulating layers 320 and 322, and a conductive layer 330 is embedded in insulating layers 324 and 326. Conductive layers 328 and 330 function as plugs or wiring.

[0386] Further, the insulating layer that functions as an interlayer insulating layer may function as a planarization film that covers the uneven shape below it. For example, the upper surface of the insulating layer 322 may be planarized by a planarization process using the CMP method or the like to enhance flatness.

[0387] A wiring layer may be provided on the insulating layer 326 and the conductive layer 330. For example, in FIG. 19, the insulating layer 350, the insulating layer 352, and the insulating layer 354 are sequentially stacked and provided. Further, a conductive layer 356 is formed in the insulating layer 350, the insulating layer 352, and the insulating layer 354. The conductive layer 356 functions as a plug or a wiring.

[0388] As the insulating layers 352, 354, etc. that function as interlayer insulating layers, the insulating layers that can be used in the semiconductor device or the memory device described above can be used.

[0389] As the conductive layer that functions as a plug or a wiring, for example, the conductive layer 328, the conductive layer 330, the conductive layer 356, etc., a conductive material applicable to the conductive layer 56 can be used. It is preferable to use a high melting point material such as tungsten or molybdenum that combines heat resistance and conductivity, and it is preferable to use tungsten. Or, it is preferably formed of a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, the wiring resistance can be lowered.

[0390] The conductive layer 56 included in the transistor 50 is connected to the low-resistance region 314b via the conductive layer 388, the conductive layer 387, the conductive layer 386, the conductive layer 385, the conductive layer 384, the conductive layer 383, the conductive layer 382, the conductive layer 381, the conductive layer 371, the conductive layer 356, the conductive layer 330, and the conductive layer 328.

[0391] The insulating layer 372 is located on the conductive layer 356 and on the insulating layer 354. The memory cell 150 is located on the insulating layer 372. The insulating layer 372 has an opening 391 that reaches the conductive layer 356, and the conductive layer 371 is provided so as to fill the opening 391.

[0392] The conductive layer 381 is located on the conductive layer 371 and on the insulating layer 372. The insulating layer 180 is located on the conductive layer 110, on the conductive layer 381, and on the insulating layer 372. The insulating layer 180 has an opening 392 reaching the conductive layer 381, and a conductive layer 382 is provided so as to fill the opening 392. The conductive layer 383 is located on the conductive layer 382 and on the insulating layer 180. Here, FIG. 19 shows an example in which the conductive layer 383 has a two-layer structure of a conductive layer 383_1 and a conductive layer 383_2 on the conductive layer 383_1.

[0393] The insulating layer 62 is located on the conductive layer 55, on the conductive layer 383, and on the insulating layer 180. The insulating layer 52 is located on the semiconductor layer 51, on the conductive layer 56, and on the insulating layer 62. The conductive layer 383_2, the insulating layer 62, and the insulating layer 52 have an opening 394 reaching the conductive layer 383_1, and a conductive layer 384 is provided so as to fill the opening 394. The conductive layer 385 is located on the conductive layer 384 and on the insulating layer 52.

[0394] The insulating layer 88 is located on the conductive layer 53, on the conductive layer 385, and on the insulating layer 52. The insulating layer 86 is located on the insulating layer 88. The insulating layer 88 and the insulating layer 86 have an opening 396 reaching the conductive layer 385, and a conductive layer 386 is provided so as to fill the opening 396. Also, the insulating layer 52, the insulating layer 88, and the insulating layer 86 have an opening 398 reaching the conductive layer 56, and a conductive layer 388 is provided so as to fill the opening 398. The conductive layer 387 is located on the conductive layer 386, on the conductive layer 388, and on the insulating layer 86. The conductive layer 387 connects the conductive layer 386 and the conductive layer 388.

[0395] The conductive layer 381 can be formed of the same material and in the same process as the conductive layer 110. The conductive layer 383_1 can be formed of the same material and in the same process as the conductive layer 55_1. The conductive layer 383_2 can be formed of the same material and in the same process as the conductive layer 55_2. The conductive layer 385 can be formed of the same material and in the same process as the conductive layer 53.

[0396] By providing openings 394 not only in the insulating layers 62 and 52 but also in the conductive layer 383_2, the conductive layer 384 can come into contact with the conductive layer 383_1. As mentioned above, the conductive layer 383_1 can be made of the same material as the conductive layer 55_1, and the conductive layer 383_2 can be made of the same material as the conductive layer 55_2. Furthermore, the conductivity of the conductive layer 55_1 can be made higher than that of the conductive layer 55_2. As a result, the conductivity of the conductive layer 383_1 can be made higher than that of the conductive layer 383_2. Therefore, the contact resistance between the conductive layer 383 and the conductive layer 384 can be made lower than, for example, if the openings 394 are not provided in the conductive layer 383_2. In addition, by providing openings 394 in the conductive layer 383_2, the conductive layer 384 can come into contact with the side surface of the opening 394 in the conductive layer 383_2. This allows for a larger contact area between the conductive layer 383 and the conductive layer 384 compared to when, for example, the opening 394 is not provided in the conductive layer 383_2. Therefore, the contact resistance between the conductive layer 383 and the conductive layer 384 can be reduced.

[0397] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0398] (Embodiment 4) In this embodiment, a semiconductor device 900 according to one aspect of the present invention will be described. The semiconductor device 900 can function as a storage device.

[0399] Figure 20 shows a block diagram illustrating an example configuration of a semiconductor device 900. The semiconductor device 900 shown in Figure 20 includes a drive circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Figure 20 shows an example in which the memory array 920 has multiple memory cells 950 arranged in a matrix.

[0400] The memory cell 950 can be the same as the memory cell 150 described in Embodiment 3.

[0401] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0402] In the semiconductor device 900, each circuit, each signal, and each voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or other signals may be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are external input signals, and signal RDA is an external output signal. Signal CLK is a clock signal.

[0403] Furthermore, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is the write data signal, and signal RDA is the read data signal. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may be generated by the control circuit 912.

[0404] The control circuit 912 is a logic circuit that has the function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs logical operations on signals CE, GW, and BW to determine the operating mode of the semiconductor device 900 (e.g., write operation, read operation). Alternatively, the control circuit 912 generates control signals for the peripheral circuit 911 so that this operating mode is executed.

[0405] The voltage generation circuit 928 has the function of generating a negative voltage. The signal WAKE has the function of controlling the input of the signal CLK to the voltage generation circuit 928. For example, when a high-level signal is given as the signal WAKE, the signal CLK is input to the voltage generation circuit 928, and the voltage generation circuit 928 generates a negative voltage.

[0406] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cell 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0407] The row decoder 941 and column decoder 942 have the function of decoding the ADDR signal. The row decoder 941 is a circuit for specifying the row to access, and the column decoder 942 is a circuit for specifying the column to access. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cell 950, reading data from the memory cell 950, and holding the read data.

[0408] The input circuit 925 has the function of holding the signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is the data (Din) to be written to the memory cell 950. The data (Dout) read by the column driver 924 from the memory cell 950 is output to the output circuit 926. The output circuit 926 has the function of holding Dout. The output circuit 926 also has the function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is the signal RDA.

[0409] PSW931 provides V to peripheral circuit 915 ＤＤ It has the function of controlling the supply. PSW932 has the function of V to line driver 923 ＨＭ It has a function to control the supply. Here, the high power supply potential of the semiconductor device 900 is V ＤＤ Therefore, the low power supply potential is GND (ground potential). Also, V ＨＭ This is a high power supply potential used to raise the word line to a high level, V ＤＤ It is higher than that. The on / off state of PSW931 is controlled by signal PON1, and the on / off state of PSW932 is controlled by signal PON2. In Figure 20, in peripheral circuit 915, V ＤＤThe number of power domains supplied is set to one, but it can be multiple. In this case, a power switch can be provided for each power domain.

[0410] Using Figures 21A to 21H, other examples of memory cell configurations applicable to the memory cell 950 will be described.

[0411] [DOSRAM] Figure 21A shows an example of the circuit configuration of a memory cell of a DRAM (Dynamic Random Access Memory). In this specification, a DRAM using an OS transistor is called a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 951 has a transistor M1 and a capacitive element CA.

[0412] Transistor M1 may have a front gate (sometimes simply called a gate) and a back gate. In this case, the back gate may be connected to a wire to which a constant potential or signal is supplied, or the front gate and back gate may be connected.

[0413] The first terminal of transistor M1 is connected to the first terminal of capacitive element CA, the second terminal of transistor M1 is connected to wiring BIL, and the gate of transistor M1 is connected to wiring WOL. The second terminal of capacitive element CA is connected to wiring CAL.

[0414] Wiring BIL functions as a bit line, and wiring WOL functions as a word line. Wiring CAL functions as wiring for applying a predetermined potential to the second terminal of the capacitive element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to wiring CAL.

[0415] Data writing and reading are performed by applying a high-level potential to the wiring WOL, turning on transistor M1, and creating a conductive state (a state in which current can flow) between the wiring BIL and the first terminal of the capacitive element CA.

[0416] The memory cell 150 shown in Figures 17A to 17C is an example of the memory cell 951 shown in Figure 21A. For example, transistor M1 corresponds to transistor 50, and capacitive element CA corresponds to capacitive element 100. Also, wiring BIL corresponds to conductive layer 56, wiring WOL corresponds to conductive layer 53, and wiring CAL corresponds to conductive layer 110.

[0417] In Figure 17A, the wiring BIL (conductive layer 56) and the wiring WOL (conductive layer 53) are arranged intersecting each other. The wiring CAL (conductive layer 110) is arranged parallel to the wiring WOL (conductive layer 53). However, the present invention is not limited to this. The wiring CAL (conductive layer 110) may, for example, be arranged parallel to the wiring BIL (conductive layer 56).

[0418] Furthermore, the memory cells that can be used in memory cell 950 are not limited to memory cell 951, and the circuit configuration can be changed. For example, a configuration in which one wiring BIL is provided in common for two or more memory cells may be used. Alternatively, for example, the configuration of memory cell 952 as shown in Figure 21B may be used. Memory cell 952 is an example in which there is no capacitive element CA and wiring CAL. The first terminal of transistor M1 is electrically floating.

[0419] In the memory cell 952, the potential written via transistor M1 is held in the capacitance (also called parasitic capacitance) between the first terminal and the gate, indicated by the dashed line. This configuration significantly simplifies the structure of the memory cell.

[0420] Furthermore, it is preferable to use an OS transistor as transistor M1. OS transistors have the characteristic of having an extremely low off-current. By using an OS transistor as transistor M1, the leakage current of transistor M1 can be made very small. In other words, since the written data can be held by transistor M1 for a long time, the frequency of memory cell refresh can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary. In addition, because the leakage current is very small, multi-level data or analog data can be held in memory cells 951 and 952.

[0421] [NOSRAM] FIG. 21C shows a circuit configuration example of a gain cell type memory cell of a two-transistor one-capacitor element. Memory cell 953 includes transistor M2, transistor M3, and capacitor element CB. In this specification and the like, a storage device having a gain cell type memory cell using transistor M2 as an OS transistor is called a NOSRAM (Nonvolatile Oxide Semiconductor RAM).

[0422] The first terminal of transistor M2 is connected to the first terminal of capacitor element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL. The second terminal of capacitor element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitor element CB.

[0423] Wiring WBL functions as a write bit line, wiring RBL functions as a read bit line, and wiring WOL functions as a word line. Wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of capacitor element CB. It is preferable to apply a low-level potential (sometimes referred to as a reference potential) to wiring CAL during data writing, during data retention, and during data reading.

[0424] Data writing is performed by applying a high-level potential to wiring WOL to turn on transistor M2 and making wiring WBL and the first terminal of capacitor element CB conductive. Specifically, when transistor M2 is on, a potential corresponding to the information to be recorded on wiring WBL is applied, and this potential is written to the first terminal of capacitor element CB and the gate of transistor M3. Then, by applying a low-level potential to wiring WOL to turn off transistor M2, the potential of the first terminal of capacitor element CB and the potential of the gate of transistor M3 are held.

[0425] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of transistor M3, and the potential of the first terminal of transistor M3, are determined by the potential of the gate and the potential of the second terminal of transistor M3. Therefore, by reading the potential of the wiring RBL connected to the first terminal of transistor M3, the potential held at the first terminal of the capacitive element CB (or the gate of transistor M3) can be read. In other words, the information written to this memory cell can be read from the potential held at the first terminal of the capacitive element CB (or the gate of transistor M3).

[0426] Alternatively, for example, the wiring WBL and wiring RBL may be combined into a single wiring BIL. An example of the circuit configuration of such a memory cell is shown in Figure 21D. Memory cell 954 is configured such that the wiring WBL and wiring RBL of memory cell 953 are combined into a single wiring BIL, and the second terminal of transistor M2 and the first terminal of transistor M3 are connected to the wiring BIL. In other words, memory cell 954 is configured to operate with the write bit line and the read bit line as a single wiring BIL.

[0427] The memory cell 955 shown in Figure 21E is an example where the capacitive element CB and wiring CAL in memory cell 953 are omitted. Similarly, the memory cell 956 shown in Figure 21F is an example where the capacitive element CB and wiring CAL in memory cell 954 are omitted. By using such a configuration, the integration density of memory cells can be increased.

[0428] Furthermore, it is preferable to use an OS transistor for at least transistor M2. In particular, it is preferable to use OS transistors for transistors M2 and M3. By using an OS transistor as transistor M2, the written data can be held by transistor M2 for a long time, thus reducing the frequency of memory cell refresh. Alternatively, it may be possible to eliminate the need for memory cell refresh operations. In addition, because the leakage current is very small, multi-level data or analog data can be held in memory cells 953 to 956.

[0429] Memory cells 953 to 956, which use an OS transistor as transistor M2, represent one form of NOSRAM.

[0430] Furthermore, a Si transistor may be used as transistor M3. Si transistors can increase field-effect mobility and can also be made into p-channel transistors, thus increasing the flexibility of circuit design.

[0431] The memory cell 150 shown in Figures 18A to 18C is an example of the memory cell 955 shown in Figure 21E. For example, transistor M2 corresponds to transistor 50b, and transistor M3 corresponds to transistor 50a. Also, wiring WBL corresponds to the conductive layer 56 of transistor 50b, and wiring WOL corresponds to the conductive layer 53.

[0432] In Figure 18A, the wiring WBL (conductive layer 56 of transistor 50b) and the wiring WOL (conductive layer 53) are arranged to intersect each other.

[0433] Figure 21G also shows a gain cell type memory cell 957 with three transistors and one capacitance element. The memory cell 957 has transistors M4 to M6 and a capacitance element CC.

[0434] The first terminal of transistor M4 is connected to the first terminal of capacitive element CC, the second terminal of transistor M4 is connected to wiring BIL, and the gate of transistor M4 is connected to wiring WOL. The second terminal of capacitive element CC is connected to the first terminal of transistor M5 and to wiring GNDL. The second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of capacitive element CC. The second terminal of transistor M6 is connected to wiring BIL, and the gate of transistor M6 is connected to wiring RWL.

[0435] Wiring BIL functions as a bit line, wiring WOL functions as a write word line, and wiring RWL functions as a read word line. Wiring GNDL is a wire that provides a low level potential.

[0436] Data writing is performed by applying a high-level potential to the wiring WOL, turning on transistor M4, and creating a conductive state between the wiring BIL and the first terminal of the capacitive element CC. Specifically, when transistor M4 is ON, a potential corresponding to the information to be recorded in wiring BIL is applied, and this potential is written to the first terminal of the capacitive element CC and the gate of transistor M5. Subsequently, a low-level potential is applied to the wiring WOL, turning off transistor M4, thereby maintaining the potential of the first terminal of the capacitive element CC and the potential of the gate of transistor M5.

[0437] Data is read by precharging the wiring BIL to a predetermined potential, then electrically freezing the wiring BIL, and applying a high-level potential to the wiring RWL. As the wiring RWL reaches a high-level potential, transistor M6 turns ON, and the wiring BIL and the second terminal of transistor M5 become conductive. At this time, the potential of the wiring BIL is applied to the second terminal of transistor M5, but the potential of the second terminal of transistor M5 and the potential of the wiring BIL change depending on the potential held at the first terminal of the capacitive element CC (or the gate of transistor M5). By reading the potential of the wiring BIL, the potential held at the first terminal of the capacitive element CC (or the gate of transistor M5) can be read. In other words, the information written to this memory cell can be read from the potential held at the first terminal of the capacitive element CC (or the gate of transistor M5).

[0438] Furthermore, it is preferable to use an OS transistor for at least transistor M4.

[0439] Note that Si transistors may be used as transistors M5 and M6. As mentioned above, depending on the crystal state of the silicon used in the semiconductor layer, Si transistors may have a higher field-effect mobility than OS transistors.

[0440] [OS-SRAM] Figure 21H shows an example of SRAM (Static Random Access Memory) using an OS transistor. In this specification, SRAM using an OS transistor is called OS-SRAM (Oxide Semiconductor-SRAM). The memory cell 958 shown in Figure 21H is a memory cell of a backup-capable SRAM.

[0441] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, and capacitive elements CD1 and CD2. Transistors MS1 and MS2 are p-channel transistors, while transistors MS3 and MS4 are n-channel transistors.

[0442] The first terminal of transistor M7 is connected to wiring BIL, and the second terminal of transistor M7 is connected to the first terminal of transistor MS1, the first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and the first terminal of transistor M10. The gate of transistor M7 is connected to wiring WOL. The first terminal of transistor M8 is connected to wiring BILB, and the second terminal of transistor M8 is connected to the first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and the first terminal of transistor M9. The gate of transistor M8 is connected to wiring WOL.

[0443] The second terminal of transistor MS1 is connected to wiring VDL. The second terminal of transistor MS2 is connected to wiring VDL. The second terminal of transistor MS3 is connected to wiring GNDL. The second terminal of transistor MS4 is connected to wiring GNDL.

[0444] The second terminal of transistor M9 is connected to the first terminal of capacitive element CD1, and the gate of transistor M9 is connected to wiring BRL. The second terminal of transistor M10 is connected to the first terminal of capacitive element CD2, and the gate of transistor M10 is connected to wiring BRL.

[0445] The second terminal of capacitive element CD1 is connected to wiring GNDL, and the second terminal of capacitive element CD2 is connected to wiring GNDL.

[0446] Wires BIL and BILB function as bit lines, wire WOL functions as a word line, and wire BRL controls the on and off states of transistors M9 and M10.

[0447] Wiring VDL is a wiring that provides a high-level potential, and wiring GNDL is a wiring that provides a low-level potential.

[0448] Data is written by applying a high-level potential to the wiring WOL and also to the wiring BRL. Specifically, when transistor M10 is ON, a potential corresponding to the information to be recorded in wiring BIL is applied, and this potential is written to the second terminal side of transistor M10.

[0449] Incidentally, since the memory cell 958 is configured in an inverter loop by transistors MS1 to MS2, an inverted signal of the data signal corresponding to the potential is input to the second terminal side of transistor M8. Because transistor M8 is ON, the potential applied to wiring BIL, i.e., the inverted signal of the signal input to wiring BIL, is output to wiring BILB. Also, because transistors M9 and M10 are ON, the potential of the second terminal of transistor M7 and the potential of the second terminal of transistor M8 are held at the first terminal of capacitive element CD2 and the first terminal of capacitive element CD1, respectively. Subsequently, by applying a low-level potential to wiring WOL and wiring BRL, and turning off transistors M7 to M10, the potentials of the first terminal of capacitive element CD1 and the first terminal of capacitive element CD2 are maintained.

[0450] Data is read by first precharging wiring BIL and wiring BILB to a predetermined potential, then applying a high-level potential to wiring WOL and wiring BRL, thereby refreshing the potential of the first terminal of capacitive element CD1 by the inverter loop of memory cell 958 and outputting it to wiring BILB. Similarly, the potential of the first terminal of capacitive element CD2 is also refreshed by the inverter loop of memory cell 958 and outputting it to wiring BIL. In wiring BIL and wiring BILB, the potential changes from the precharged potential to the potential of the first terminal of capacitive element CD2 and the potential of the first terminal of capacitive element CD1, respectively, so the potential held in the memory cell can be read from the potential of wiring BIL or wiring BILB.

[0451] Furthermore, it is preferable to use OS transistors as transistors M7 to M10. This allows the written data to be retained for a long time by transistors M7 to M10, thereby reducing the frequency of memory cell refreshes, or even eliminating the need for memory cell refresh operations.

[0452] Furthermore, Si transistors may be used as transistors MS1 to MS4.

[0453] The drive circuit 910 and memory array 920 of the semiconductor device 900 may be provided on the same plane. Alternatively, as shown in Figure 22A, the drive circuit 910 and memory array 920 may be stacked on top of each other. By stacking the drive circuit 910 and memory array 920, the signal propagation distance can be shortened. Furthermore, as shown in Figure 22B, multiple memory arrays 920 may be stacked on top of the drive circuit 910.

[0454] Next, an example of a processing unit that can be equipped with the above-mentioned memory device and other semiconductor devices will be described.

[0455] Figure 23 shows a block diagram of the arithmetic unit 960. The arithmetic unit 960 shown in Figure 23 can be applied to a CPU, for example. The arithmetic unit 960 can also be applied to processors such as GPUs (Graphics Processing Units), TPUs (Tensor Processing Units), and NPUs (Neural Processing Units) that have a large number of processor cores (tens to hundreds) capable of parallel processing, more so than a CPU.

[0456] The arithmetic unit 960 shown in Figure 23 has an ALU 962 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 962c, an instruction decoder 963, an interrupt controller 964, a timing controller 965, a register 966, a register controller 967, a bus interface 968, a cache 969, and a cache interface 969i on a substrate 961. The substrate 961 can be a semiconductor substrate, an SOI substrate, a glass substrate, etc. It may also have a rewritable ROM and a ROM interface. In addition, the cache 969 and the cache interface 969i may be provided on a separate chip.

[0457] The cache 969 is connected to the main memory, which is located on a separate chip, via a cache interface 969i. The cache interface 969i has the function of supplying a portion of the data held in the main memory to the cache 969. The cache interface 969i also has the function of outputting a portion of the data held in the cache 969 to the ALU 962 or register 966, etc., via the bus interface 968.

[0458] As will be described later, a memory array 920 can be stacked on the arithmetic unit 960. The memory array 920 can be used as a cache. In this case, the cache interface 969i may have the function of supplying data held in the memory array 920 to the cache 969. In this case, it is preferable that a drive circuit 910 is included in part of the cache interface 969i.

[0459] Alternatively, the cache 969 can be omitted, and only the memory array 920 can be used as the cache.

[0460] The arithmetic unit 960 shown in Figure 23 is merely one example of a simplified configuration, and actual arithmetic units 960 have a wide variety of configurations depending on their application. For example, it is preferable to have a so-called multi-core configuration in which the configuration including the arithmetic unit 960 shown in Figure 23 is considered one core, and multiple such cores are included, with each core operating in parallel. The more cores there are, the higher the computational performance can be. While a larger number of cores is preferable, it is preferable to have, for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more cores. Furthermore, in cases where very high computational performance is required, such as for server applications, it is preferable to have a multi-core configuration with 16 or more, preferably 32 or more, and even more preferably 64 or more cores. In addition, the number of bits that the arithmetic unit 960 can handle in its internal arithmetic circuitry, data bus, etc., can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0461] Instructions input to the arithmetic unit 960 via the bus interface 968 are input to the instruction decoder 963, decoded, and then input to the ALU controller 962c, interrupt controller 964, register controller 967, and timing controller 965.

[0462] The ALU controller 962c, interrupt controller 964, register controller 967, and timing controller 965 perform various controls based on the decoded instructions. Specifically, the ALU controller 962c generates signals to control the operation of the ALU 962. The interrupt controller 964 processes interrupt requests from external input / output devices, peripheral circuits, etc., during program execution of the arithmetic unit 960, based on their priority, mask state, etc. The register controller 967 generates the address of register 966 and reads and writes to register 966 according to the state of the arithmetic unit 960.

[0463] Furthermore, the timing controller 965 generates signals that control the timing of the operation of the ALU 962, ALU controller 962c, instruction decoder 963, interrupt controller 964, and register controller 967. For example, the timing controller 965 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits mentioned above.

[0464] In the arithmetic unit 960 shown in Figure 23, the register controller 967 selects a data retention operation in register 966 according to instructions from ALU 962. That is, it selects whether to retain data in the memory cell of register 966 using a flip-flop or using a capacitive element. If data retention using a flip-flop is selected, power potential is supplied to the memory cell in register 966. If data retention using a capacitive element is selected, data is rewritten to the capacitive element, and the supply of power potential to the memory cell in register 966 can be stopped.

[0465] The memory array 920 and the arithmetic unit 960 can be installed on top of each other. Figures 24A and 24B show perspective views of the semiconductor device 970A. The semiconductor device 970A has a layer 930 on which memory arrays are provided on the arithmetic unit 960. The layer 930 is provided with memory arrays 920L1, 920L2, and 920L3. The arithmetic unit 960 and each memory array have overlapping regions. To make the configuration of the semiconductor device 970A easier to understand, Figure 24B shows the arithmetic unit 960 and layer 930 separately.

[0466] By stacking the layer 930 containing the memory array and the arithmetic unit 960, the connection distance between them can be shortened. Therefore, the communication speed between them can be increased. In addition, power consumption can be reduced due to the short connection distance.

[0467] As a method for stacking the layer 930 having the memory array and the arithmetic unit 960, one may use a method in which the layer 930 having the memory array is directly stacked on the arithmetic unit 960 (also called monolithic stacking), or one may use a method in which the arithmetic unit 960 and the layer 930 are formed on different substrates, the two substrates are bonded together, and they are connected using through-via or conductive film bonding technology (such as Cu-Cu bonding). The former does not require consideration of positional misalignment during bonding, so not only can the chip size be reduced, but manufacturing costs can also be reduced.

[0468] Here, the arithmetic unit 960 does not have a cache 969, and the memory arrays 920L1, 920L2, and 920L3 provided in layer 930 can each be used as caches. In this case, for example, memory array 920L1 can be used as an L1 cache (also called a level 1 cache), memory array 920L2 can be used as an L2 cache (also called a level 2 cache), and memory array 920L3 can be used as an L3 cache (also called a level 3 cache). Of the three memory arrays, memory array 920L3 has the largest capacity and the lowest access frequency. Also, memory array 920L1 has the smallest capacity and the highest access frequency.

[0469] Furthermore, when the cache 969 provided in the arithmetic unit 960 is used as the L1 cache, each memory array provided in layer 930 can be used as a lower-level cache or main memory, respectively. Main memory has a larger capacity than cache and is accessed less frequently.

[0470] Furthermore, as shown in Figure 24B, drive circuits 910L1, 910L2, and 910L3 are provided. Drive circuit 910L1 is connected to memory array 920L1 via connecting electrode 940L1. Similarly, drive circuit 910L2 is connected to memory array 920L2 via connecting electrode 940L2, and drive circuit 910L3 is connected to memory array 920L3 via connecting electrode 940L3.

[0471] Note that while this example shows three memory arrays functioning as a cache, it may also use one, two, or four or more arrays.

[0472] When the memory array 920L1 is used as a cache, the drive circuit 910L1 may function as part of the cache interface 969i, or the drive circuit 910L1 may be configured to be connected to the cache interface 969i. Similarly, the drive circuits 910L2 and 910L3 may also function as part of the cache interface 969i, or be configured to be connected to it.

[0473] Whether the memory array 920 functions as a cache or as main memory is determined by the control circuit 912 of each drive circuit 910. Based on signals supplied from the arithmetic unit 960, the control circuit 912 can make some of the multiple memory cells 950 of the semiconductor device 900 function as RAM.

[0474] The semiconductor device 900 can have some of its multiple memory cells 950 function as a cache and the other part function as main memory. In other words, the semiconductor device 900 can have both cache and main memory functions. A semiconductor device 900 according to one aspect of the present invention can function as a universal memory, for example.

[0475] Alternatively, a layer 930 having a single memory array 920 may be superimposed on the arithmetic unit 960. Figure 25A shows a perspective view of the semiconductor device 970B.

[0476] In the semiconductor device 970B, a single memory array 920 can be divided into multiple areas, each used for a different function. Figure 25A shows an example where area L1 is used as the L1 cache, area L2 as the L2 cache, and area L3 as the L3 cache.

[0477] Furthermore, in the semiconductor device 970B, the capacities of each of the regions L1 to L3 can be changed according to the situation. For example, if it is desired to increase the capacity of the L1 cache, this can be achieved by increasing the area of ​​region L1. By adopting such a configuration, the efficiency of arithmetic processing can be improved, and the processing speed can be increased.

[0478] Furthermore, multiple memory arrays may be stacked. Figure 25B shows a perspective view of the semiconductor device 970C.

[0479] The semiconductor device 970C has a layer 930L1 with a memory array 920L1, a layer 930L2 with a memory array 920L2 on top of it, and a layer 930L3 with a memory array 920L3 on top of that. The memory array 920L1, which is physically closest to the arithmetic unit 960, can be used as the upper cache, and the memory array 920L3, which is furthest away, can be used as the lower cache or main memory. By using this configuration, the capacity of each memory array can be increased, thereby improving processing power.

[0480] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0481] (Embodiment 5) In this embodiment, an example of a CMOS type circuit configuration using a Si transistor and an OS transistor according to one aspect of the present invention will be described.

[0482] Si transistors have higher field-effect mobility and faster operating speeds than OS transistors. Furthermore, OS transistors have significantly lower off-currents than Si transistors. In particular, OS transistors using indium oxide in the semiconductor layer where the channel is formed achieve extremely low off-currents and high field-effect mobility comparable to Si transistors. By combining OS and Si transistors, a low-power, high-speed CMOS-type circuit can be realized.

[0483] In this embodiment, as an example of a circuit using Si transistors and OS transistors, configuration examples of logic circuits such as NOT circuits, NOR circuits, and NAND circuits will be described. In addition, a DFF circuit (DFF: Delay Flip Flop) and configuration examples of a shift register circuit using a DFF circuit will be described.

[0484] [NOT Circuit] Figure 26A is a circuit diagram showing an example of a NOT circuit (NOT). A NOT circuit is also called an inverting circuit or inverter circuit. Figure 26B shows the circuit symbol for a NOT circuit. Figure 26C is a timing chart explaining the operation of a NOT circuit.

[0485] The NOT gate shown in Figure 26A has transistors Tr11 and Tr12. Transistor Tr11 is a Si transistor that functions as a p-type transistor, and transistor Tr12 is an OS transistor that functions as an n-type transistor. A potential H (e.g., high power supply potential VDD) is supplied to either the source or drain of transistor Tr11. The other source or drain of transistor Tr11 is connected to either the source or drain of transistor Tr12 and to terminal Y. A potential L (e.g., low power supply potential VSS) is supplied to the other source or drain of transistor Tr12. The gates of transistor Tr11 and transistor Tr12 are connected to terminal A.

[0486] In the NOT gate shown in Figure 26A, terminal A functions as the input terminal and terminal Y functions as the output terminal. When a potential H is input to terminal A, a potential L is output from terminal Y, and when a potential L is input to terminal A, a potential H is output from terminal Y (see Figure 26C).

[0487] Furthermore, as shown in Figure 26C, the NOT gate has the function of correcting an input signal that has been degraded by wiring resistance, parasitic capacitance, noise, etc., into a signal that is undegraded or has reduced degradation, and outputting it. The NOT gate also has the function of amplifying the voltage amplitude of the input signal and outputting it. The output of the NOT gate is supplied to a load such as a capacitive element Cx or a transistor Trx.

[0488] Here, an example of the structure of a NOT gate will be explained using Figure 27. As shown in Figure 27, transistor Tr12 is provided above transistor Tr11.

[0489] Transistor Tr11 is a modified version of transistor 300 shown in Figure 19, and has a so-called planar configuration. Components of transistor Tr11 that are the same as those of transistor 300 shown in Figure 19 are denoted by the same reference numerals. For details of transistor Tr11, please refer to the description of transistor 300.

[0490] A detailed explanation of transistor Tr12 is omitted as it can be described by referring to the explanation of transistor 50 in Embodiment 1. Note that transistor Tr12 is not limited to transistor 50, and any of the transistors exemplified in Embodiment 1, such as transistor 50A and transistor 50B, can be used. Furthermore, a planar structure or a GAA structure transistor can also be used.

[0491] In the semiconductor device shown in Figure 27, an insulating layer 320 is provided on an insulating layer 315 that functions as a gate insulating layer for transistor Tr11. A conductive layer 316 that functions as a gate electrode for transistor Tr11 is provided so as to fill the openings in the insulating layer 320. An insulating layer 87 is provided on the conductive layer 316 and on the insulating layer 320. Transistor Tr12 is provided on the insulating layer 87.

[0492] The insulating layer 315, insulating layer 320, and insulating layer 87 are provided with openings that reach the low-resistance region 314a, and a conductive layer 331a is provided to fill these openings. Furthermore, the insulating layer 315, insulating layer 320, and insulating layer 87 are provided with openings that reach the low-resistance region 314b, and a conductive layer 331b is provided to fill these openings. In addition, the insulating layer 87 is provided with openings that reach the conductive layer 316, and a conductive layer 331c is provided to fill these openings.

[0493] A conductive layer 255 is provided on the conductive layer 331a and on the insulating layer 87. A conductive layer 55 is provided on the conductive layer 331b and on the insulating layer 87. A conductive layer 256 is provided on the conductive layer 331c and on the insulating layer 87. An insulating layer 62 is provided on the conductive layer 55, conductive layer 255, conductive layer 256, and insulating layer 87.

[0494] Figure 27 shows an example where the conductive layer 255 has a two-layer structure consisting of conductive layer 255_1 and conductive layer 255_2 on top of conductive layer 255_1. Also, Figure 27 shows an example where the conductive layer 256 has a two-layer structure consisting of conductive layer 256_1 and conductive layer 256_2 on top of conductive layer 256_1. Conductive layers 255_1 and conductive layer 256_1 can be formed from the same material and using the same process as conductive layer 55_1. Conductive layers 255_2 and conductive layer 256_2 can be formed from the same material and using the same process as conductive layer 55_2.

[0495] An insulating layer 88 is provided on the conductive layer 53 and the insulating layer 52 of the transistor Tr12. An insulating layer 86 is provided on the insulating layer 88, and a wiring layer 287 is provided on the insulating layer 86. An insulating layer 288 is provided on the wiring layer 287, and conductive layers 248a, 248b, 248c, and 248d are provided to fill the openings provided in the insulating layer 288. Conductive layers 248a, 248b, 248c, and 248d function as wiring.

[0496] The insulating layer 288 functions as an interlayer insulating layer. Therefore, it is preferable to use a material with a low dielectric constant, as shown in Embodiment 1, for the insulating layer 288. For example, a material that can be used for the insulating layer 86 can be used for the insulating layer 288.

[0497] The conductive layer 255_2, insulating layer 62, insulating layer 52, insulating layer 88, and insulating layer 86 each have an opening 249a that reaches the conductive layer 255_1, and the conductive layer 247a is provided to fill the opening 249a. The conductive layer 248a is located on the conductive layer 247a and the insulating layer 86. The conductive layer 248a is connected to the low-resistance region 314a via the conductive layer 247a, the conductive layer 255, and the conductive layer 331a.

[0498] The conductive layer 55_2, insulating layer 62, insulating layer 52, insulating layer 88, and insulating layer 86 have openings 249b that reach the conductive layer 55_1, and the conductive layer 247b is provided so as to fill the openings 249b. The conductive layer 248b is located on the conductive layer 247b and on the insulating layer 86. The conductive layer 248b is connected to the low-resistance region 314b via the conductive layer 247b, conductive layer 55, and conductive layer 331b.

[0499] The insulating layer 52, insulating layer 88, and insulating layer 86 have openings 249c that reach the conductive layer 56, and the conductive layer 247c is provided so as to fill the openings 249c. The conductive layer 248c is located on the conductive layer 247c and on the insulating layer 86. The conductive layer 248c is connected to the conductive layer 56 via the conductive layer 247c.

[0500] The conductive layer 256_2, insulating layer 62, insulating layer 52, insulating layer 88, and insulating layer 86 each have an opening 249d that reaches the conductive layer 256_1, and a conductive layer 247d is provided to fill the opening 249d. The insulating layer 88 and insulating layer 86 each have an opening 249e that reaches the conductive layer 53, and a conductive layer 247e is provided to fill the opening 249e. The conductive layer 248d is located on the conductive layer 247d, the conductive layer 247e, and the insulating layer 86. The conductive layer 316, which functions as the gate electrode of transistor Tr11, and the conductive layer 53, which functions as the gate electrode of transistor Tr12, are connected via the conductive layer 331c, the conductive layer 256, the conductive layer 247d, the conductive layer 248d, and the conductive layer 247e.

[0501] The conductivity of conductive layer 55_1, conductive layer 255_1, and conductive layer 256_1 can be made higher than the conductivity of conductive layer 55_2, conductive layer 255_2, and conductive layer 256_2, respectively. Therefore, by providing an opening 249a in conductive layer 255_2, the contact resistance between conductive layer 255 and conductive layer 247a can be lowered compared to the case where there is no opening 249a in conductive layer 255_2. Furthermore, by providing an opening 249b in conductive layer 55_2, the contact resistance between conductive layer 55 and conductive layer 247b can be lowered compared to the case where there is no opening 249b in conductive layer 55_2. In addition, by providing an opening 249d in conductive layer 256_2, the contact resistance between conductive layer 256 and conductive layer 247d can be lowered compared to the case where there is no opening 249d in conductive layer 256_2.

[0502] A potential H is supplied to the conductive layer 248a. The conductive layer 248b functions as terminal Y. A potential L is supplied to the conductive layer 248c. The conductive layer 248d functions as terminal A.

[0503] By making all the transistors Tr11 formed on the substrate 311 p-type transistors and all the transistors Tr12 formed above them n-type transistors, a NOT-type circuit can be constructed, simplifying complex processes such as the formation of element isolation layers, and improving the productivity of semiconductor devices including the circuit.

[0504] [NOR Circuit] Figure 28A is a circuit diagram showing an example configuration of a 2-input 1-output NOR circuit (NOR). Figure 28B shows the circuit symbol for the NOR circuit. The NOR circuit shown in Figure 28A has transistors Tr21, Tr22, Tr23, and Tr24. Si transistors functioning as p-type transistors can be used for transistors Tr21 and Tr22, and OS transistors functioning as n-type transistors can be used for transistors Tr23 and Tr24.

[0505] In Figure 28A, a potential H is supplied to either the source or drain of transistor Tr21. The other source or drain of transistor Tr21 is connected to either the source or drain of transistor Tr22. The other source or drain of transistor Tr22 is connected to either the source or drain of transistor Tr23, either the source or drain of transistor Tr24, and terminal Y. A potential L is supplied to either the source or drain of transistor Tr23 and the other source or drain of transistor Tr24.

[0506] Furthermore, the gate of transistor Tr21 is connected to the gate and terminal A of transistor Tr23. Also, the gate of transistor Tr22 is connected to the gate and terminal B of transistor Tr24.

[0507] The NOR circuit shown in Figures 28A and 28B has the function of outputting a potential H from terminal Y when a potential L is input to both terminals A and B. It also has the function of outputting a potential L from terminal Y when a potential H is input to one or both terminals A and B.

[0508] Furthermore, as shown in Figure 28C, an OR gate can be realized by connecting the input of a NOT gate to the output of a NOR gate.

[0509] [NAND Circuit] Figure 28D is a circuit diagram showing an example configuration of a 2-input, 1-output NAND circuit (NAND). Figure 28E shows the circuit symbol for the NAND circuit. The NAND circuit shown in Figure 28D has transistors Tr31, Tr32, Tr33, and Tr34. Transistors Tr31 and Tr32 are Si transistors that function as p-type transistors, and transistors Tr33 and Tr34 are OS transistors that function as n-type transistors.

[0510] In Figure 28D, a potential H is supplied to one of the sources or drains of transistor Tr31 and one of the sources or drains of transistor Tr32. The other source or drain of transistor Tr31 and the other source or drain of transistor Tr32 are connected to one of the sources or drains of transistor Tr33 and terminal Y. The other source or drain of transistor Tr33 is connected to one of the sources or drains of transistor Tr34. A potential L is supplied to the other source or drain of transistor Tr34.

[0511] The gate of transistor Tr31 is connected to the gate and terminal B of transistor Tr34. The gate of transistor Tr32 is connected to the gate and terminal A of transistor Tr33.

[0512] The NAND circuits shown in Figures 28D and 28E have the function of outputting a potential L from terminal Y when a potential H is input to both terminals A and B. Furthermore, they have the function of outputting a potential H from terminal Y when a potential L is input to either or both terminals A and B.

[0513] Furthermore, as shown in Figure 28F, an AND circuit can be realized by combining a NOT circuit with a NAND circuit.

[0514] [DFF Circuit] Figure 29A is a circuit diagram showing an example configuration of a D flip-flop circuit (DFF). Figure 29B shows the circuit symbol for a D flip-flop circuit. A DFF has a clock signal input terminal CK, an input terminal D, and an output terminal Q.

[0515] The D flip-flop circuit shown in Figure 29A has transistors Tr41 to Tr49, Tr51 to Tr59, Tr61, Tr62, Tr71, and Tr72. Si transistors functioning as p-type transistors can be used for transistors Tr41 to Tr49, Tr61, and Tr62, and OS transistors functioning as n-type transistors can be used for transistors Tr51 to Tr59, Tr71, and Tr72.

[0516] A potential of H is supplied to either the source or drain of transistor Tr41, either the source or drain of transistor Tr42, either the source or drain of transistor Tr44, either the source or drain of transistor Tr46, either the source or drain of transistor Tr48, either the source or drain of transistor Tr61, and either the source or drain of transistor Tr62.

[0517] The source or drain of transistor Tr41 is connected to either the source or drain of transistor Tr51, the gate of transistor Tr44, the gate of transistor Tr46, the gate of transistor Tr53, and the gate of transistor Tr59. The gate of transistor Tr41 is connected to the clock signal input terminal CK, the gate of transistor Tr51, the gate of transistor Tr42, the gate of transistor Tr48, the gate of transistor Tr55, and the gate of transistor Tr57.

[0518] The other source or drain of transistor Tr42 is connected to one source or drain of transistor Tr43. The other source or drain of transistor Tr44 is connected to one source or drain of transistor Tr45. The other source or drain of transistor Tr43 is connected to the other source or drain of transistor Tr45, one source or drain of transistor Tr52, one source or drain of transistor Tr54, the gate of transistor Tr61, and the gate of transistor Tr71. The gate of transistor Tr43 is connected to the gate of transistor Tr52 and input terminal D.

[0519] The other source or drain of transistor Tr52 is connected to one source or drain of transistor Tr53. The other source or drain of transistor Tr54 is connected to one source or drain of transistor Tr55. The gate of transistor Tr45 is connected to the gate of transistor Tr54, the other source or drain of transistor Tr61, one source or drain of transistor Tr71, the gate of transistor Tr47, and the gate of transistor Tr56. The other source or drain of transistor Tr46 is connected to one source or drain of transistor Tr47. The other source or drain of transistor Tr48 is connected to one source or drain of transistor Tr49.

[0520] The other source or drain of transistor Tr47 is connected to one source or drain of transistor Tr56, the other source or drain of transistor Tr49, one source or drain of transistor Tr58, the gate of transistor Tr62, and the gate of transistor Tr72. The other source or drain of transistor Tr62 is connected to one source or drain of transistor Tr72, the gate of transistor Tr49, the gate of transistor Tr58, and the output terminal Q.

[0521] The other source or drain of transistor Tr56 is connected to one source or drain of transistor Tr57. The other source or drain of transistor Tr58 is connected to one source or drain of transistor Tr59. A potential L is supplied to the other source or drain of transistor Tr51, the other source or drain of transistor Tr53, the other source or drain of transistor Tr55, the other source or drain of transistor Tr71, the other source or drain of transistor Tr57, the other source or drain of transistor Tr59, and the other source or drain of transistor Tr72.

[0522] The DFF shown in Figures 29A and 29B has the function of writing information (potential) supplied to input terminal D to the DFF while a potential H is input to the clock signal input terminal CK, and when the signal input to the clock signal input terminal CK changes from potential H to potential L, it holds this information until a potential H is input to the clock signal input terminal CK again. In addition, a signal (potential H or potential L) based on the information held by the DFF is always output from output terminal Q.

[0523] Figure 30A is a block diagram showing an example configuration of a shift register circuit (SR). The SR includes multiple DFFs. In this specification, the first stage (first) DFF is indicated as "DFF[1]", and the potential (data) output from the output terminal Q of DFF[1] is indicated as "Data OUT[1]". Figure 30A shows a block diagram of an SR including four stages (four) DFFs (DFF[1] to DFF[4]). In Figure 30A, the data output from the output terminal Q of each of DFF[1] to DFF[4] is indicated as Data OUT[1] to Data OUT[4].

[0524] Figure 30B is a timing chart illustrating the operation of the SR. The clock signal input terminal CK of the odd-numbered stage DFF is input with the signal CLK. The clock signal input terminal CK of the even-numbered stage DFF is input with the inverted signal of signal CLK.

[0525] The input terminal D of DFF[1] receives the pulse signal SPL. DFF[1] holds a signal corresponding to the input signal SPL in synchronization with the signal CLK and outputs it as dataOUT[1]. The value of dataOUT[1] will be a value corresponding to the data held by DFF[1].

[0526] Furthermore, data OUT[1] is input to input terminal D of DFF[2]. DFF[2] holds a signal corresponding to the input data OUT[1] in synchronization with the signal CLK and outputs it as data OUT[2]. Similarly, data OUT[2] is input to input terminal D of DFF[3], and data OUT[3] is input to input terminal D of DFF[4].

[0527] Thus, the SR has the function of sequentially transferring the input signal SPL to the subsequent DFF in synchronization with the signal CLK. In addition, the SR has the function of sequentially switching the potential of the data OUT output from multiple DFFs in synchronization with the signal CLK.

[0528] Furthermore, it is preferable to stack the Si transistor and the OS transistor. Stacking the Si transistor and the OS transistor allows for the realization of a circuit with a small footprint. In addition, the OS transistor operates stably even in high-temperature environments and exhibits minimal characteristic fluctuations. Therefore, the OS transistor is less affected by the heat generated by the Si transistor and can operate stably. Moreover, stacking the Si transistor and the OS transistor allows for extremely short connection distances between them. As a result, wiring resistance and parasitic capacitance are reduced, enabling high-speed operation of the circuit. In addition, the power consumption of the circuit is reduced.

[0529] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0530] (Embodiment 6) In this embodiment, an application example of a semiconductor device according to one aspect of the present invention will be described with reference to Figures 31A to 32E.

[0531] A semiconductor device according to one aspect of the present invention can be used, for example, in electronic components, large computers, space equipment, data centers (also referred to as DCs), and various electronic devices. By using a semiconductor device according to one aspect of the present invention, lower power consumption and higher performance can be achieved in electronic components, large computers, space equipment, data centers, and various electronic devices.

[0532] The electronic device of this embodiment may have sensors (including functions for detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation).

[0533] The electronic device of this embodiment can have a variety of functions. For example, it can have a function to display various information (still images, videos, or text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, or time, a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, and so on.

[0534] [Electronic Components] Figure 31A shows a perspective view of a substrate (mounted substrate 819) on which electronic components 810 are mounted. The electronic component 810 shown in Figure 31A has a semiconductor device 811 inside a mold 814. Some details are omitted in Figure 31A to show the inside of the electronic component 810. The electronic component 810 has a land 815 on the outside of the mold 814. The land 815 is connected to an electrode pad 816, and the electrode pad 816 is connected to the semiconductor device 811 via a wire 817. The electronic component 810 is mounted on a printed circuit board 818, for example. Multiple such electronic components are combined and connected on the printed circuit board 818 to complete the mounted substrate 819.

[0535] Furthermore, the semiconductor device 811 includes a drive circuit layer 812 and a storage layer 813. The storage layer 813 has a configuration in which multiple memory cell arrays are stacked. The configuration in which the drive circuit layer 812 and the storage layer 813 are stacked can be a monolithic stack configuration. In a monolithic stack configuration, the layers can be connected without using through-electrode technologies such as TSV (Through Silicon Via) and bonding technologies such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 812 and the storage layer 813, for example, a so-called on-chip memory configuration can be achieved in which memory is directly formed on the processor. By using an on-chip memory configuration, it is possible to speed up the operation of the interface portion between the processor and the memory.

[0536] Furthermore, by using an on-chip memory configuration, the size of connection wiring can be reduced compared to technologies using through-hole electrodes such as TSVs, making it possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which in turn improves the memory bandwidth (also called memory bandwidth).

[0537] Furthermore, it is preferable to form the multiple memory cell arrays of the memory layer 813 using OS transistors and to stack these multiple memory cell arrays monolithically. By configuring the multiple memory cell arrays in a monolithic stack, it is possible to improve either or both of the memory bandwidth and / or memory access latency. Bandwidth is the amount of data transferred per unit time, and access latency is the time from access to the start of data exchange. In the case of a configuration using Si transistors in the memory layer 813, it is difficult to create a monolithic stack configuration compared to OS transistors. Therefore, in a monolithic stack configuration, OS transistors can be said to have a superior structure compared to Si transistors.

[0538] The semiconductor device 811 may also be referred to as a die. In this specification, a die refers to a chip piece obtained in the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disc-shaped substrate (also called a wafer) and cutting it into cubes. Examples of semiconductor materials that can be used for dies include silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) is sometimes called a silicon die.

[0539] Next, a perspective view of the electronic component 820 is shown in Figure 31B. The electronic component 820 is an example of a SiP (System in Package) or MCM (Multi-Chip Module). The electronic component 820 has an interposer 821 provided on a package substrate 822 (printed circuit board), and a semiconductor device 824 and a plurality of semiconductor devices 811 are provided on the interposer 821.

[0540] Electronic component 820 shows an example where semiconductor device 811 is used as a high-bandwidth memory (HBM). Furthermore, semiconductor device 824 can be used in integrated circuits such as CPUs, GPUs, or FPGAs (Field Programmable Gate Arrays).

[0541] The package substrate 822 can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 821 can be, for example, a silicon interposer or a resin interposer.

[0542] The interposer 821 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 821 also has the function of connecting integrated circuits provided on the interposer 821 to electrodes provided on the package substrate 822. For these reasons, the interposer is sometimes called a "redistribution board" or "intermediate board". In addition, through electrodes may be provided on the interposer 821, and these through electrodes may be used to connect the integrated circuits and the package substrate 822. Furthermore, in silicon interposers, TSVs can also be used as through electrodes.

[0543] In HBMs, many connections are necessary to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted requires fine and high-density wiring. For this reason, it is preferable to use a silicon interposer for mounting the HBM.

[0544] Furthermore, in SiP and MCM using silicon interposers, reliability degradation due to differences in expansion coefficients between the integrated circuit and the interposer is less likely to occur. In addition, because silicon interposers have high surface flatness, connection failures between the integrated circuit and the silicon interposer are less likely to occur. In particular, in 2.5D packages (2.5-dimensional packaging) where multiple integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0545] On the other hand, when connecting multiple integrated circuits with different terminal pitches using silicon interposers, TSVs, etc., space such as the width of the terminal pitch is required. Therefore, when trying to reduce the size of the electronic component 820, the width of the terminal pitch becomes a problem, and it may become difficult to provide the many wires necessary to achieve a wide memory bandwidth. For this reason, as mentioned above, a monolithic stacked configuration using OS transistors is preferable. A composite structure combining a memory cell array stacked using TSVs and a monolithic stacked memory cell array may also be used.

[0546] Alternatively, a heat sink (heat dissipation plate) may be provided on top of the electronic component 820. If a heat sink is provided, it is preferable to align the heights of the integrated circuits provided on the interposer 821. For example, in the electronic component 820 shown in this embodiment, it is preferable to align the heights of the semiconductor device 811 and the semiconductor device 824.

[0547] To mount the electronic component 820 onto another substrate, electrodes 823 may be provided at the bottom of the package substrate 822. Figure 31B shows an example in which the electrodes 823 are formed with solder balls. By providing solder balls in a matrix at the bottom of the package substrate 822, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrodes 823 may be formed with conductive pins. By providing conductive pins in a matrix at the bottom of the package substrate 822, PGA (Pin Grid Array) mounting can be achieved.

[0548] The electronic component 820 can be mounted on other boards using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0549] [Large-scale computer] Next, a perspective view of the large-scale computer 830 is shown in Figure 32A. The large-scale computer 830 shown in Figure 32A has multiple rack-mount type computers 832 housed in rack 831. The large-scale computer 830 may also be called a supercomputer.

[0550] The computer 832 can have the configuration shown in the perspective view in Figure 32B, for example. In Figure 32B, the computer 832 has a motherboard 842, which has multiple slots 843 and multiple connection terminals. A PC card 833 is inserted into a slot 843. In addition, the PC card 833 has connection terminals 835, 836, and 837, which are each connected to the motherboard 842.

[0551] The PC card 833 shown in Figure 32C is an example of a processing board equipped with a CPU, GPU, storage device, etc. The PC card 833 has a board 834. The board 834 also has connection terminals 835, 836, 837, semiconductor device 838, semiconductor device 839, semiconductor device 840, and connection terminal 841. Although Figure 32C shows semiconductor devices other than semiconductor devices 838, 839, and 840, you can refer to the descriptions of semiconductor devices 838, 839, and 840 below for details on these semiconductor devices.

[0552] The connector 841 has a shape that allows it to be inserted into the slot 843 of the motherboard 842, and functions as an interface for connecting the PC card 833 and the motherboard 842. Examples of standards for the connector 841 include PCIe.

[0553] Terminals 835, 836, and 837 can serve as interfaces for, for example, supplying power and inputting signals to the PC card 833. They can also serve as interfaces for, for example, outputting signals calculated by the PC card 833. Examples of standards for terminals 835, 836, and 837 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). When outputting video signals from terminals 835, 836, and 837, examples of standards include HDMI (registered trademark).

[0554] The semiconductor device 838 has terminals (not shown) for inputting and outputting signals, and the semiconductor device 838 and board 834 can be connected by inserting these terminals into sockets (not shown) provided on board 834.

[0555] The semiconductor device 839 has multiple terminals, and the semiconductor device 839 and the board 834 can be connected by soldering these terminals to the wiring provided on the board 834, for example, using a reflow soldering method. Examples of semiconductor devices 839 include FPGAs, GPUs, CPUs, etc. For example, an electronic component 820 can be used as the semiconductor device 839.

[0556] The semiconductor device 840 has multiple terminals, and the semiconductor device 840 and the board 834 can be connected by soldering these terminals to the wiring on the board 834, for example, using a reflow soldering method. Examples of the semiconductor device 840 include a memory device. For example, an electronic component 820 can be used as the semiconductor device 840.

[0557] The mainframe computer 830 can also function as a parallel computer. By using the mainframe computer 830 as a parallel computer, it is possible to perform large-scale calculations necessary for, for example, artificial intelligence training and inference.

[0558] [Space Equipment] A semiconductor device according to one aspect of the present invention can be suitably used in space equipment.

[0559] One embodiment of the present invention includes an OS transistor. Compared to Si transistors, OS transistors exhibit smaller fluctuations in electrical properties due to radiation exposure. In other words, they have high resistance to radiation, making them highly reliable and suitable for use in environments where radiation may be incident. For example, OS transistors are suitable for use in outer space. Specifically, OS transistors can be used in transistors constituting semiconductor devices installed in space shuttles, artificial satellites, or space probes. Examples of radiation include X-rays and neutrons. Outer space refers, for example, to an altitude of 100 km or higher, but outer space as described herein may include one or more of the thermosphere, mesosphere, and stratosphere.

[0560] Figure 32D shows an example of space equipment, specifically a satellite 850. The satellite 850 comprises a body 851, solar panels 852, an antenna 853, a secondary battery 855, and a control device 856. In Figure 32D, a planet 854 is shown as an example in outer space.

[0561] Furthermore, although not shown in Figure 32D, a battery management system (also known as a BMS) or a battery control circuit may be provided with the secondary battery 855. Using an OS transistor in the aforementioned battery management system or battery control circuit is preferable because it consumes little power and has high reliability even in outer space.

[0562] Furthermore, outer space is an environment with radiation levels more than 100 times higher than those on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutrons, protons, heavy ions, and mesons.

[0563] When sunlight shines on the solar panel 852, the power necessary for the satellite 850 to operate is generated. However, if, for example, sunlight does not shine on the solar panel, or if the amount of sunlight shining on the solar panel is low, the amount of power generated will decrease. Therefore, there is a possibility that the power necessary for the satellite 850 to operate will not be generated. To operate the satellite 850 even under conditions where the amount of power generated is low, it is advisable to equip the satellite 850 with a secondary battery 855. Note that solar panels are sometimes called solar cell modules.

[0564] The artificial satellite 850 can generate a signal. This signal is transmitted via the antenna 853, and can be received by, for example, a receiver on the ground or another artificial satellite. By receiving the signal transmitted by the artificial satellite 850, the position of the receiver that received the signal can be measured. Thus, the artificial satellite 850 can constitute a satellite positioning system.

[0565] Furthermore, the control device 856 has the function of controlling the artificial satellite 850. The control device 856 is configured using, for example, one or more selected from a CPU, a GPU, and a memory device. It is preferable to use a semiconductor device including an OS transistor, which is one embodiment of the present invention, for the control device 856.

[0566] Furthermore, the satellite 850 can be configured to include sensors. For example, by configuring it to include a visible light sensor, the satellite 850 can have the function of detecting sunlight reflected after hitting an object on the ground. Alternatively, by configuring it to include a thermal infrared sensor, the satellite 850 can have the function of detecting thermal infrared radiation emitted from the Earth's surface. Thus, the satellite 850 can function, for example, as an Earth observation satellite.

[0567] In this embodiment, an artificial satellite was used as an example of spa...

Claims

It comprises a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, a second insulating layer, a third insulating layer, and a semiconductor layer. The first insulating layer has a region located on the first conductive layer, The first insulating layer has a first opening that overlaps with the first conductive layer, The second insulating layer has a region located inside the first opening, The semiconductor layer has a region in contact with the first conductive layer, a region in contact with the side surface of the second insulating layer within the first opening, a region located on the first insulating layer, and a region located on the second insulating layer. The second conductive layer is located on the first insulating layer and has a region in contact with the upper surface of the semiconductor layer. The second conductive layer has a second opening that overlaps with the first opening, The third insulating layer has a region located inside the first opening, a region located inside the second opening, and a region located on the second conductive layer. The third conductive layer is provided on the third insulating layer such that it has a region located inside the first opening. The semiconductor layer has indium oxide, The semiconductor layer has crystalline grains, and is a semiconductor device. 　 In claim 1, A semiconductor device wherein the side surface of the second conductive layer at the second opening protrudes from the side surface of the semiconductor layer opposite to the side surface in contact with the second insulating layer. 　 In claim 1 or claim 2, The semiconductor device wherein the second insulating layer comprises gallium and oxygen. 　 In claim 3, It has a fourth insulating layer, The fourth insulating layer is provided inside the first opening so as to cover the side of the second insulating layer opposite to the semiconductor layer and its lower end. The semiconductor layer has a region located on the fourth insulating layer, The semiconductor device comprises a fourth insulating layer made of hafnium and oxygen. 　 In claim 1 or 2, The second conductive layer comprises a first layer having a region in contact with the upper surface of the semiconductor layer, and a second layer on the first layer. The first layer has an oxide conductor, The semiconductor device wherein the second layer is made of a material with higher conductivity than the oxide conductor. 　 In claim 5, The first layer comprises at least one of indium tin oxide, silicon-containing indium tin oxide, indium zinc oxide, and indium titanium oxide. The second layer comprises at least one of tungsten, copper, and aluminum, in a semiconductor device. 　 A first conductive layer is formed, A first insulating layer is formed so as to cover the first conductive layer. A first opening is formed in the first insulating layer, which reaches the first conductive layer. A second insulating layer is formed inside the first opening. A semiconductor layer is formed having a region in contact with the first conductive layer, a region in contact with the side surface of the second insulating layer, a region located on the first insulating layer, and a region located on the second insulating layer. A sacrificial layer is formed to fill the first opening, Heat treatment is performed, A second conductive layer is formed having a region in contact with the upper surface of the semiconductor layer and a region located on the sacrificial layer. A second opening is formed in the second conductive layer, which overlaps with the first opening. Remove the aforementioned sacrificial layer, A third insulating layer is formed on the semiconductor layer and the second conductive layer. A method for manufacturing a semiconductor device, comprising forming a third conductive layer such that it has a region located inside the first opening. 　 In claim 7, After the formation of the sacrificial layer, a seed layer is formed so as to be in contact with the upper surface of the semiconductor layer and to have a region that overlaps with the first insulating layer. After the seed layer is formed, the heat treatment is performed. A method for manufacturing a semiconductor device, comprising removing the seed layer after the heat treatment.

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