Display device and method of driving same

Abstract

The present application discloses an internal-compensation current-driven display device in which an initialization operation for a gate voltage of a driving transistor is accelerated while suppressing an increase in the number of elements in a pixel circuit. In a pixel circuit of an organic EL display device according to the present invention, a gate voltage of a driving transistor is initialized before a voltage of a data signal line is written to a storage capacitor via the driving transistor in a diode-connected state. At this time, a current path is formed from a node including the gate terminal of the driving transistor to an initialization voltage line Vini via a threshold compensation transistor and an initialization transistor, and the gate voltage Vg of the driving transistor T4 is initialized by charging a storage capacitor Cst through this current path.

Description

Display device and driving method thereof

[0001] The present disclosure relates to a display device, and more particularly, to a current-driven display device including a display element driven by current, such as an organic EL (Electro Luminescence) display device, and a driving method thereof.

[0002] In recent years, an organic EL display device (also referred to as an "OLED display device") including a pixel circuit including an organic EL element (also referred to as an organic light emitting diode (Organic Light Emitting Diode: OLED)) has been put into practical use. The pixel circuit of the organic EL display device includes, in addition to the organic EL element, a driving transistor, a write control transistor, a holding capacitor, and the like. A thin film transistor (Thin Film Transistor) is used for the driving transistor and the write control transistor, a holding capacitor is connected to the gate terminal of the driving transistor, and a voltage corresponding to a video signal representing an image to be displayed (more specifically, a voltage indicating the gradation value of the pixel to be formed in the pixel circuit, hereinafter referred to as "data voltage") is applied to this holding capacitor via a data signal line from a driving circuit. The organic EL element is a self-emitting display element that emits light with a luminance corresponding to the current flowing through it. The driving transistor is provided in series with the organic EL element and controls the current flowing through the organic EL element according to the voltage held in the holding capacitor.

[0003] Variations and fluctuations occur in the characteristics of organic EL elements and driving transistors. Therefore, in order to achieve high-quality display in organic EL display devices, it is necessary to compensate for these variations and fluctuations in the characteristics of these elements. For organic EL display devices, two methods are known for compensating for element characteristics: one that is done inside the pixel circuit and another that is done outside the pixel circuit. As a pixel circuit corresponding to the former method, a pixel circuit is known that is configured to initialize the voltage at the gate terminal of the driving transistor, i.e., the voltage held in the holding capacitor, and then charge the holding capacitor with the data voltage via the diode-connected driving transistor. In such a pixel circuit, variations and fluctuations in the threshold voltage of the driving transistor are compensated internally (hereinafter, this compensation for variations and fluctuations in the threshold voltage is referred to as "threshold compensation").

[0004] As described above, matters related to organic EL display devices (OLED display devices) that perform threshold compensation within the pixel circuit (hereinafter referred to as the "internal compensation method") are described, for example, in U.S. Patent Application Publication No. 2010 / 0164847 (Patent Document 1). In the pixel circuit of such an organic EL display device with internal compensation (hereinafter referred to as the "internal compensation type pixel circuit"), in addition to the transistor for threshold compensation, a transistor for initializing the voltage of the gate terminal of the drive transistor (hereinafter simply referred to as the "gate voltage") (hereinafter referred to as the "gate voltage initialization transistor") is usually provided, resulting in a large number of elements and a high layout density. As a result, it is difficult to increase the resolution of the displayed image, and if one tries to accommodate high resolution, the yield in the manufacturing of the display panel tends to deteriorate.

[0005] In contrast, internally compensated pixel circuits are known in which, instead of providing a gate voltage initialization transistor, a transistor that performs other functions within the pixel circuit is also used for gate voltage initialization. For example, in the pixel circuit shown in Figure 12 of U.S. Patent Application Publication No. 2010 / 0164847 (Patent Document 1), the switching transistor Qs3 for threshold compensation, the switching transistor Qs5 for light emission control, and the switching transistor Qs6 for anode voltage initialization are all used for gate voltage initialization (voltage at node N1). Furthermore, similar internally compensated pixel circuits are disclosed in Figure 8A of U.S. Patent Application Publication No. 2012 / 0001896 (Patent Document 2) and in Figure 5 of International Publication No. 2022 / 264359 (Patent Document 3).

[0006] U.S. Patent Application Publication No. 2010 / 0164847 Specification U.S. Patent Application Publication No. 2012 / 0001896 Specification International Publication No. 2022 / 264359 Brochure

[0007] In the internally compensated pixel circuit described above (hereinafter referred to as the "conventional internally compensated pixel circuit"), three transistors are included in the current path for initializing the gate voltage of the drive transistor, and the current for initializing the gate voltage flows through these three transistors. As a result, it takes time to charge the gate voltage for initialization, and it is difficult for the gate voltage to reach the target initialization voltage during the initialization period. Consequently, variations in the luminescence brightness of the pixel circuit may occur.

[0008] Therefore, in internally compensated pixel circuits for current-driven display devices such as organic EL displays, it is desirable to speed up the initialization operation of the gate voltage of the drive transistor while suppressing the increase in the number of elements.

[0009] A display device according to several embodiments of the present invention comprises a display unit including a plurality of pixel circuits, a plurality of data signal lines, and an initialization voltage line, and a drive circuit for driving the plurality of pixel circuits, each of the plurality of pixel circuits including a display element driven by current, a drive transistor, a holding capacitor, a write control switching element, a threshold compensation switching element, a light emission control switching element, and an initialization switching element, the drive transistor having a first conductive terminal connected to one of the plurality of data signal lines via the write control switching element, a second conductive terminal connected to the display element via the light emission control switching element and connected to the initialization voltage line via the initialization switching element, and a control terminal connected to a fixed voltage line via the holding capacitor and connected to the second conductive terminal via the threshold compensation switching element. Each of the plurality of pixel circuits is provided with a light emission period for emitting light from the display element in accordance with the voltage held by the holding capacitor, a write period for writing the voltage of one data signal line to the holding capacitor as a data voltage during periods other than the light emission period, a write voltage initialization period for initializing the voltage of the control terminal of the drive transistor before the write period during periods other than the light emission period, and a display element initialization period for initializing the display element during periods other than the light emission period. The drive circuit drives the plurality of pixel circuits such that during the display element initialization period a current path is formed from the display element to the initialization voltage line via the light emission control switching element and the initialization switching element, during the write voltage initialization period a current path is formed from the control terminal of the drive transistor to the initialization voltage line via the threshold compensation switching element and the initialization switching element, and during the write period the voltage of one data signal line is written to the holding capacitor via the write control switching element, the drive transistor, and the threshold compensation switching element.

[0010] A driving method according to several embodiments of the present invention is a driving method for a display device using a display element driven by an electric current, wherein the display device comprises a display unit including a plurality of pixel circuits, a plurality of data signal lines, and an initialization voltage line, each of the plurality of pixel circuits includes a display element driven by an electric current, a driving transistor, a holding capacitor, a write control switching element, a threshold compensation switching element, a light emission control switching element, and an initialization switching element, wherein the driving transistor has a first conductive terminal connected to one of the plurality of data signal lines via the write control switching element, a second conductive terminal connected to the display element via the light emission control switching element and connected to the initialization voltage line via the initialization switching element, and a control terminal connected to a fixed voltage line via the holding capacitor and connected to the second conductive terminal via the threshold compensation switching element. Each of the plurality of pixel circuits is provided with a light emission period for emitting light in accordance with the voltage held by the holding capacitor, a write period for writing the voltage of one data signal line to the holding capacitor as a data voltage during periods other than the light emission period, a write voltage initialization period for initializing the voltage of the control terminal of the drive transistor before the write period during periods other than the light emission period, and a display element initialization period for initializing the display element during periods other than the light emission period, the driving method includes the steps of: driving the plurality of pixel circuits during the display element initialization period such that a current path is formed from the display element to the initialization voltage line via the light emission control switching element and the initialization switching element; and driving the plurality of pixel circuits during the write voltage initialization period such that a current path is formed from the control terminal of the drive transistor to the initialization voltage line via the threshold compensation switching element and the initialization switching element.The method includes the step of driving the plurality of pixel circuits such that, during the writing period, the voltage of one data signal line is written as a data voltage to the holding capacitor via the write control switching element, the drive transistor, and the threshold compensation switching element.

[0011] In each pixel circuit of the above-described embodiments of the present invention, the first conductive terminal of the drive transistor is connected to one of the plurality of data signal lines in the display unit via a write control switching element, the control terminal of the drive transistor is connected to a fixed voltage line via a holding capacitor and to a second conductive terminal of the drive transistor via a threshold compensation switching element, and this second conductive terminal is connected to a display element via a light emission control switching element and to an initialization voltage line via an initialization switching element. For each such pixel circuit, there is a light emission period for illuminating the display element according to the voltage held in the holding capacitor, a write period for writing the voltage of the one data signal line as a data voltage to the holding capacitor during periods other than the light emission period, a write voltage initialization period for initializing the voltage of the control terminal of the drive transistor before the write period during periods other than the light emission period, and a display element initialization period for initializing the display element during periods other than the light emission period. During these periods, a current path is formed from the display element through the light emission control switching element and the initialization switching element to the initialization voltage line during the display element initialization period. During the write voltage initialization period, a current path is formed from the control terminal of the drive transistor through the threshold compensation switching element and the initialization switching element to the initialization voltage line. During the write period, the voltage of one of the data signal lines is written to the holding capacitor via the write control switching element, the drive transistor, and the threshold compensation switching element. As a result, threshold compensation of the drive transistor is performed when writing the data voltage within each pixel circuit. Prior to the writing of such data voltage, the voltage at the gate terminal of the drive transistor is initialized, i.e., the write voltage held in the holding capacitor is initialized, by the current path from the control terminal of the drive transistor through the threshold compensation switching element and the initialization switching element to the initialization voltage line. The initialization transistor used to form this current path is also used to form the current path for the initialization of the display element.Therefore, in a pixel circuit equipped with such threshold compensation functionality, a dedicated switching element for initializing the write voltage held in the holding capacitor is unnecessary, and the pixel circuit can be realized with a small number of elements. Moreover, since the current path for initializing the write voltage held in the holding capacitor is formed by two switching elements (a threshold compensation switching element and an initialization switching element), brightness variations caused by insufficient charging of the holding capacitor during the write voltage initialization period are improved compared to conventional internally compensated pixel circuits where the current path is formed by three transistors. Therefore, according to some of the above embodiments, it is possible to provide a high-definition internally compensated display device that improves brightness variations while suppressing a decrease in yield.

[0012] This is a block diagram showing the overall configuration of the display device according to the first embodiment. This is a timing chart for explaining the general operation of the display device according to the first embodiment. This is a circuit diagram showing the configuration of a pixel circuit in a conventional display device. This is a timing chart for explaining the operation of a pixel circuit in the conventional display device. This is a circuit diagram showing the configuration of a pixel circuit in a display device according to a comparative example to the first embodiment. This is a timing chart for explaining the operation of a pixel circuit in the comparative example. This is a circuit diagram showing the configuration of a pixel circuit in the first embodiment. This is a timing chart for explaining the operation of a pixel circuit in the first embodiment. This is a circuit diagram for explaining the anode initialization operation in the pixel circuit in the first embodiment. This is a circuit diagram for explaining the gate voltage initialization operation in the pixel circuit in the first embodiment. This is a circuit diagram for explaining the data voltage writing operation in the pixel circuit in the first embodiment. This is a circuit diagram for explaining the light emission operation in the pixel circuit in the first embodiment. This is a circuit diagram showing the configuration of a pixel circuit in the display device according to the second embodiment. This is a timing chart for explaining the operation of a pixel circuit in the second embodiment. This is a circuit diagram for explaining the anode initialization operation in the pixel circuit in the second embodiment. This is a circuit diagram for explaining the gate voltage initialization operation in the pixel circuit in the second embodiment. This is a circuit diagram illustrating the data voltage writing operation in the pixel circuit according to the second embodiment described above. This is a circuit diagram illustrating the light emission operation in the pixel circuit according to the second embodiment described above. This is a block diagram illustrating the overall configuration of the display device according to the third embodiment described above. This is a timing chart illustrating the general operation of the display device according to the third embodiment described above. This is a circuit diagram showing the configuration of the pixel circuit according to the third embodiment described above. This is a timing chart illustrating the operation of the pixel circuit according to the third embodiment described above. This is a circuit diagram illustrating the anode initialization operation during the drive period in the pixel circuit according to the third embodiment described above. This is a circuit diagram illustrating the gate voltage initialization operation during the drive period in the pixel circuit according to the third embodiment described above.This is a circuit diagram illustrating the anode initialization pressure operation during the pause period in the pixel circuit according to the third embodiment described above. This is a circuit diagram illustrating the on-bias voltage application operation during the pause period in the pixel circuit according to the third embodiment described above. This is a block diagram illustrating the overall configuration of the display device according to the fourth embodiment described above. This is a timing chart illustrating the general operation of the display device according to the fourth embodiment described above. This is a circuit diagram showing the configuration of the pixel circuit according to the fourth embodiment described above. This is a timing chart illustrating the operation of the pixel circuit according to the fourth embodiment described above. This is a circuit diagram illustrating the anode initialization operation during the pause period in the pixel circuit according to the fourth embodiment described above. This is a circuit diagram illustrating the on-bias voltage application operation during the pause period in the pixel circuit according to the fourth embodiment described above. This is a circuit diagram showing the configuration of the pixel circuit in the display device according to the fifth embodiment described above. This is a timing chart illustrating the operation of the pixel circuit according to the fifth embodiment described above.

[0013] The embodiments will be described below with reference to the attached drawings. In each transistor mentioned below, the gate terminal corresponds to the control terminal, one of the drain terminal and the source terminal corresponds to the first conduction terminal, and the other corresponds to the second conduction terminal. Furthermore, the transistors in each embodiment are, for example, thin-film transistors, but the present invention is not limited thereto. Moreover, in this specification, "connection" means "electrical connection" unless otherwise specified, and to the extent that it does not depart from the gist of the present invention, it includes not only direct connections but also indirect connections via other elements.

[0014] <1. First Embodiment> <1.1 Overall Configuration> Figure 1 is a block diagram showing the overall configuration of the display device 10 according to the first embodiment. This display device 10 is an internally compensated organic EL display device. That is, in this display device 10, when writing pixel data to each pixel circuit, the retention capacitor is charged with the voltage of the data signal (data voltage) via a diode-connected drive transistor within the pixel circuit, thereby compensating for variations and fluctuations in the threshold voltage of the drive transistor (details will be described later).

[0015] As shown in Figure 1, the display device 10 comprises a display unit 11, a display control circuit 20, a data-side drive circuit 30, a scanning-side drive circuit 40, and a power supply circuit 50. The data-side drive circuit 30 functions as a data signal line drive circuit (also called a "data driver"). The scanning-side drive circuit 40 functions as a scanning signal line drive circuit (also called a "gate driver") and an emission control circuit (also called an "emission driver"). In the configuration shown in Figure 1, these two scanning-side circuits are realized as a single scanning-side drive circuit 40, but these two circuits may be configured to be appropriately separated, or these two circuits may be configured to be separated and arranged on one side and the other side of the display unit 11. Furthermore, at least a part of the scanning-side drive circuit 40 and the data-side drive circuit 30 may be integrally formed with the display unit 11. These points are also the same in other embodiments described later. The power supply circuit 50 generates the high-level power supply voltage ELVDD, the low-level power supply voltage ELVSS, and the initialization voltage Vini to be supplied to the display unit 11, as well as a power supply voltage (not shown) to be supplied to the display control circuit 20, the data-side drive circuit 30, and the scanning-side drive circuit 40.

[0016] The display unit 11 is equipped with m data signal lines D1, D2, ..., Dm (where m is an integer of 2 or more), n first scan signal lines PS1, PS2, ..., PSn intersecting these, and n+2 second scan signal lines NS-1, NS0, NS1, NS2, ..., NSn (where n is an integer of 2 or more). N light emission control lines (emission lines) EM1 to EMn are arranged along each of the n first scan signal lines PS1 to PSn. Furthermore, the display unit 11 is provided with n × m pixel circuits 15 arranged in a matrix along m data signal lines D1 to Dm and n first scan signal lines PS1 to PSn. Each pixel circuit 15 corresponds to one of the m data signal lines D1 to Dm and one of the n first scan signal lines PS1 to PSn (hereinafter, when distinguishing each pixel circuit 15, the pixel circuit corresponding to the i-th first scan signal line PSi and the j-th data signal line Dj will be referred to as the "i-th row, j-th column pixel circuit" and will be denoted by the symbol "Pix(i,j)"). Each pixel circuit 15 also corresponds to one of the n second scan signal lines NS1 to NSn and one of the n light emission control lines EM1 to EMn.

[0017] The display unit 11 is also provided with power lines (not shown) common to each pixel circuit 15. Specifically, it is provided with a first power line (hereinafter referred to as the "high-level power line," and denoted by the same symbol "ELVDD" as the high-level power supply voltage) for supplying a high-level power supply voltage ELVDD for driving the organic EL elements described later, and a second power line (hereinafter referred to as the "low-level power line," and denoted by the same symbol "ELVSS" as the low-level power supply voltage) for supplying a low-level power supply voltage ELVSS for driving the organic EL elements. Furthermore, the display unit 11 is also provided with an initialization voltage line (not shown), denoted by the same symbol "Vini" as the initialization voltage, for supplying an initialization voltage Vini used for a reset operation (also called the "initialization operation") for initializing each pixel circuit 15. The high-level power supply voltage ELVDD, the low-level power supply voltage ELVSS, and the initialization voltage Vini are supplied from the power supply circuit 50.

[0018] The display control circuit 20 receives an input signal Sin from outside the display device 10, which includes image information representing the image to be displayed and timing control information for image display. Based on this input signal Sin, it generates a data-side control signal Scd and a scanning-side control signal Scs, and outputs the data-side control signal Scd to the data-side drive circuit (data signal line drive circuit) 30 and the scanning-side control signal Scs to the scanning-side drive circuit (scanning signal line drive / light emission control circuit) 40. As can be seen from the explanation below, the data-side drive circuit 30 and the scanning-side drive circuit 40 constitute a drive circuit that drives the pixel circuits Pix(1,1) to Pix(n,m).

[0019] The data-side drive circuit 30 drives the data signal lines D1 to Dm based on the data-side control signal Scd from the display control circuit 20. That is, based on the data-side control signal Scd, the data-side drive circuit 30 outputs m data signals D(1) to D(m) representing the image to be displayed in parallel and applies them to the data signal lines D1 to Dm, respectively.

[0020] The scanning-side drive circuit 40 functions as a scanning signal line drive circuit that drives n first scanning signal lines PS1 to PSn and n+2 second scanning signal lines NS-1 to NSn based on the scanning-side control signal Scs from the display control circuit 20, and also functions as a light emission control circuit that drives light emission control lines EM1 to EMn.

[0021] More specifically, the scanning drive circuit 40, as a scanning signal line drive circuit, in each frame period, based on the scanning control signal Scs, sequentially selects n first scanning signal lines PS1 to PSn for predetermined periods corresponding to one horizontal period, and sequentially selects n+2 second scanning signal lines NS-1 to NSn for predetermined periods corresponding to one horizontal period, applies an active signal to the selected first scanning signal line PSk (where k is an integer such that 1 ≤ k ≤ n), applies an active signal to the selected second scanning signal line NSk (where k is an integer such that -1 ≤ k ≤ n), applies an inactive signal to the unselected first scanning signal line PSi, and applies an inactive signal to the unselected second scanning signal line NSi. As a result, m pixel circuits Pix(k,1) to Pix(k,m) corresponding to the selected first scanning signal line PSk are selected collectively. As a result, during the selection period of the first scan signal line PSk (hereinafter referred to as the "kth scan selection period"), the voltages of m data signals D(1) to D(m) applied from the data-side drive circuit 30 to the data signal lines D1 to Dm (hereinafter, these voltages may be simply referred to as "data voltages" without distinction) are written as pixel data to the pixel circuits Pix(k,1) to Pix(k,m), respectively. In this embodiment, as shown in Figure 7 described later, the first scan signal line PSi1 is connected to the gate terminal of a predetermined P-channel type (hereinafter also referred to as "P-type") transistor in the pixel circuit 15 (i1 = 1 to n), and the second scan signal line NSi2 is connected to the gate terminal of a predetermined N-channel type (hereinafter also referred to as "N-type") transistor in the pixel circuit 15 (i2 = -1 to n). Therefore, a low-level voltage is applied as an active signal to the selected first scan signal line PSi1, and a high-level voltage is applied as an active signal to the selected second scan signal line NSi2.

[0022] Furthermore, the scanning drive circuit 40 drives the light emission control lines EM1 to EMn in each frame period so that they are selectively deactivated in conjunction with the above-mentioned driving of the first scanning signal lines PS1 to PSn and the second scanning signal lines NS-1 to NSn. That is, the scanning drive circuit 40, as a light emission control circuit, applies a light emission control signal (high-level voltage) indicating no light emission to the i-th light emission control line EMI for a predetermined period including the i-th horizontal period, based on the scanning control signal Scs, and applies a light emission control signal (low-level voltage) indicating light emission for the other periods (i = 1 to n). The organic EL elements in the pixel circuits Pix(i,1) to Pix(i,m) corresponding to the i-th first scanning signal line PSi (hereinafter also referred to as "i-th row pixel circuits") emit light with a brightness corresponding to the data voltage written to each of the i-th row pixel circuits Pix(i,1) to Pix(i,m) while the voltage of the light emission control line EMI is at a low level.

[0023] <1.2 Outline Operation> Figure 2 is a timing chart for illustrating the outline operation of the display device 10 according to this embodiment. The scanning control signal Scs provided from the display control circuit 20 to the scanning drive circuit 40 includes a two-phase clock signal consisting of first and second clock signals with different phases. Hereinafter, this first clock signal will be referred to as the "first gate clock signal" and denoted by the symbol "GCK1", and this second clock signal will be referred to as the "second gate clock signal" and denoted by the symbol "GCK2". Based on this two-phase clock signal, the scanning drive circuit 40 generates first scanning signals PS(1) to PS(n) and second scanning signals NS(-1) to NS(n) as shown in Figure 2, applies the first scanning signals PS(1) to PS(n) to the first scanning signal lines PS1 to PSn, respectively, and applies the second scanning signals NS(-1) to NS(n) to the second scanning signal lines NS-1 to NSn, respectively. Furthermore, the scanning drive circuit 40 generates light emission control signals EM(1) to EM(n) as shown in Figure 2 based on the two-phase clock signals (first and second gate clock signals GCK1 and GCK2) and applies them to the light emission control lines EM1 to EMn, respectively. On the other hand, the data drive circuit 30 generates data signals D(1) to D(m) as shown in Figure 2, which change in conjunction with the first scanning signals PS(1) to PS(n), based on the data-side control signal Scd from the display control circuit 20, and applies them to the data signal lines D1 to Dm, respectively. In this way, the first scanning signal lines PS1 to PSn, the second scanning signal lines NS-1 to NSn, the light emission control lines EM1 to EMn, and the data signal lines D1 to Dm in the display unit 11 are driven, so that during the non-light emission period, initialization and data voltage writing are performed on each pixel circuit Pix(i,j), and during the light emission period, each pixel circuit emits light with a brightness corresponding to the written data voltage. In addition, the display devices according to other embodiments also basically operate as shown in Figure 2. However, the operation during the pause period when pause driving is performed differs from the operation shown in Figure 2 (details will be described later). Furthermore, in this embodiment, the scanning drive circuit 40 is configured to operate with a two-phase clock signal consisting of first and second gate clock signals GCK1 and GCK2, but it may also be configured to operate with a multi-phase clock signal of three or more phases (the same applies to other embodiments described later).

[0024] In this embodiment, the first scan signal lines PS1 to PSn, the second scan signal lines NS-1 to NSn, the light emission control lines EM1 to EMn, and the data signal lines D1 to Dm are driven as described above by the various signals shown in Figure 2. This allows for a refresh frame period in which the first scan signal lines PS1 to PSn are sequentially selected and the second scan signal lines NS-1 to NSn are sequentially selected to write image data to the display unit 11 (specifically, the pixel circuits Pix(1,1) to Pix(n,m)).

[0025] <1.3 Configuration and Operation of Pixel Circuits in Conventional Display Devices> Before describing the configuration and operation of the pixel circuit 15 in this embodiment, the configuration and operation of the pixel circuit 14a in a conventional display device using an internal compensation method (hereinafter referred to as "conventional example") will be described with reference to Figures 3 and 4.

[0026] Figure 3 is a circuit diagram showing the configuration of the pixel circuit 14a in the conventional example described above, or more specifically, the configuration of the pixel circuit 14a corresponding to the i-th first scan signal line PSi and the j-th data signal line Dj, i.e., the i-th row and j-th column pixel circuit Pix(i,j) (1≦i≦n, 1≦j≦m). As shown in Figure 3, the pixel circuit 14a includes one organic EL element (organic light-emitting diode) OL as a display element, seven transistors T1 to T7 (hereinafter referred to as "first initialization transistor T1", "threshold compensation transistor T2", "write control transistor T3", "drive transistor T4", "power supply control transistor T5", "light emission control transistor T6", and "second initialization transistor T7"), and one retaining capacitor Cst. The retaining capacitor Cst is a capacitive element consisting of two electrodes (first electrode and second electrode). As shown in Figure 3, the first electrode and second electrode of the retaining capacitor Cst are connected to the high-level power line ELVDD and the gate terminal of the drive transistor T4, respectively. In the pixel circuit 14a, transistors T1 to T3 and T5 to T7, other than the drive transistor T4, function as switching elements.

[0027] In the above conventional example, the pixel circuit Pix(i,j) is connected to the following lines: the corresponding first scan signal line (hereinafter also referred to as the "corresponding first scan signal line" in the explanation focusing on the pixel circuit) PSi, the corresponding second scan signal line (hereinafter also referred to as the "corresponding second scan signal line" in the explanation focusing on the pixel circuit) NSi, the second scan signal line two positions prior to the second scan signal line NSi (the scan signal line two positions prior in the scanning order of the second scan signal lines NS-1 to NSn, and hereinafter simply referred to as the "preceding second scan signal line" in the explanation focusing on the pixel circuit) NSi-2, the corresponding light emission control line (hereinafter also referred to as the "corresponding light emission control line" in the explanation focusing on the pixel circuit) EMI, the corresponding data signal line (hereinafter also referred to as the "corresponding data signal line" in the explanation focusing on the pixel circuit) Dj, the initialization voltage line Vini, the high-level power supply line ELVDD, and the low-level power supply line ELVSS.

[0028] As shown in Figure 5, in the pixel circuit 14a, the source terminal of the drive transistor T4 is connected to the corresponding data signal line Dj via the write control transistor T3, and is also connected to the high-level power line ELVDD via the power supply control transistor T5. The drain terminal of the drive transistor T4 is connected to the anode electrode, which is the first terminal of the organic EL element OL, via the light emission control transistor T6. The gate terminal of the drive transistor T4 is connected to the high-level power line ELVDD, which is the fixed voltage line, via the holding capacitor Cst, and is also connected to the drain terminal of the drive transistor T4 via the threshold compensation transistor T2, and is also connected to the initialization voltage line Vini via the first initialization transistor T1. The anode electrode of the organic EL element OL is connected to the initialization voltage line Vini via the second initialization transistor T7, and the cathode electrode of the organic EL element OL is connected to the low-level power line ELVSS. Furthermore, the gate terminals of the write control transistor T3 and the threshold compensation transistor T2 are connected to the corresponding first scan signal line PSi and the corresponding second scan signal line NSi, respectively. The gate terminals of the power supply control transistor T5, the light emission control transistor T6, and the second initialization transistor T7 are all connected to the corresponding light emission control line EMI, and the gate terminal of the first initialization transistor T1 is connected to the preceding second scan signal line NSi-2.

[0029] Next, the operation of the pixel circuit 14a shown in Figure 3, that is, the pixel circuit Pix(i,j) in the i row and j column in the conventional example, will be explained with reference to Figure 4 as well as Figure 3. Figure 4 is a timing chart for explaining the operation of the pixel circuit Pix(i,j).

[0030] When the light emission control signal EM(i), which is supplied to the pixel circuit Pix(i,j) in Figure 3 via the corresponding light emission control line EMI, changes from L level to H level at time t1, the P-type power supply control transistor T5 and the light emission control transistor T6 change from the ON state to the OFF state and remain in the OFF state while the light emission control signal EM(i) is at the H level. Therefore, during the period t1 to t8 when the light emission control signal EM(i) is at the H level, no current flows to the organic EL element OL and the pixel circuit Pix(i,j) is in a non-light-emitting state. Also, during the period t1 to t8 when the pixel circuit Pix(i,j) is in a non-light-emitting state (non-light-emitting period), the N-type second initialization transistor T7 turns ON, and the voltage Va of the anode electrode of the organic EL element OL (hereinafter referred to as "anode voltage") is initialized.

[0031] During the non-emitting period t1 to t8, the preceding second scan signal NS(i-2), which is supplied to the pixel circuit Pix(i,j) via the preceding second scan signal line NSi-2, changes from L level to H level at time t2. This causes the N-type first initialization transistor T1 to change from the off state to the on state, and it remains on while the second scan signal NS(i-2) is at the H level. During the period t2 to t3 when the first initialization transistor T1 is on (hereinafter referred to as the "initialization period"), the holding capacitor Cst is initialized, and the voltage Vg at the gate terminal of the drive transistor T4 (hereinafter referred to as the "gate voltage") becomes the initialization voltage Vini.

[0032] During the non-emitting period t1 to t8 of the pixel circuit Pix(i,j) in Figure 5, the preceding second scanning signal NS(i-2) changes to an L level at time t3, and then the corresponding second scanning signal NS(i), which is provided via the corresponding second scanning signal line NSi, changes from an L level to an H level at time t4. As a result, the N-type threshold compensation transistor T2 changes from the off state to the on state and remains on while the corresponding second scanning signal NS(i) is at an H level, and the drive transistor T4 is in a diode connection state.

[0033] During the period t4 to t7 when the threshold compensation transistor T2 is ON, the corresponding first scan signal PS(i), which is the first scan signal supplied to the pixel circuit Pix(i,j) via the corresponding first scan signal line PSi, changes from H level to L level at time t5. As a result, the P-type write control transistor T3 changes from the OFF state to the ON state and remains ON while the first scan signal PS(i) is at the L level. During the period t5 to t6 when the write control transistor T3 is ON (hereinafter referred to as the "data writing period"), the voltage of the data signal D(j), which is supplied to the pixel circuit Pix(i,j) via the corresponding data signal line Dj, is supplied as the data voltage Vdata to the holding capacitor Cst via the diode-connected drive transistor T4. As a result, the threshold-compensated data voltage is written to and held in the holding capacitor Cst, and the gate voltage Vg of the drive transistor T4 is maintained at the voltage of the second electrode of the holding capacitor Cst. At this time, the gate voltage Vg is given by the following equation, where Vth (<0) is the threshold value of the drive transistor T4: Vg = Vdata + Vth ... (1) In this way, during the data writing period t5 to t6, data voltages with threshold compensation are written.

[0034] At time t7, after the data writing period t5-t6, the second scanning signal NS(i) changes from high level to low level, and the threshold compensation transistor T2 turns off. Subsequently, at time t8, the light emission control signal EM(i) changes from high level to low level, which turns on the corresponding power supply control transistor T5 and light emission control transistor T6, and the light emission period begins. During this light emission period, a current I1 corresponding to the voltage held in the holding capacitor Cst (the voltage written during the data writing period t5-t6) flows from the high-level power line ELVDD through the power supply control transistor T5, the drive transistor T4, the light emission control transistor T6, and the organic EL element OL to the low-level power line ELVSS.

[0035] During this light-emitting period, the drive transistor T4 operates in the saturation region, and the current I1 flowing through the organic EL element OL is given by equation (2). The gain β of the drive transistor T4 included in equation (2) is given by equation (3) below. I1 = (β / 2)(|Vgs| - |Vth|) 2 = (β / 2) (|Vg-ELVDD|-|Vth|) 2 …(2) β = μ × (W / L) × Cox …(3) In equations (2) and (3) above, Vth, μ, W, L, and Cox represent the threshold voltage, mobility, gate width, gate length, and gate dielectric capacitance per unit area of ​​the drive transistor T4, respectively. Here, the drive transistor T4 is of type P, and Vth < 0, Vg < ELVDD, so I1 = (β / 2)(ELVDD - Vg + Vth) 2 Furthermore, substituting equation (1) mentioned earlier into this equation, we get I1 = (β / 2)(ELVDD - Vdata) 2 ...(4) As can be seen from equation (4) above, during the light emission period from time t8 onwards, the organic EL element OL emits light with a brightness corresponding to the data voltage Vdata, which is the voltage of the corresponding data signal line Dj, regardless of the threshold voltage Vth of the drive transistor T4.

[0036] <1.4 Configuration and Operation of Pixel Circuit in Comparative Example> Next, the configuration and operation of the pixel circuit 14b in a display device according to a comparative example with respect to the pixel circuit in this embodiment will be described with reference to Figures 5 and 6. Figure 5 is a circuit diagram showing the configuration of the pixel circuit 14b in this comparative example, and this pixel circuit 14b corresponds to the pixel circuit 15 shown in Figure 5 of International Publication No. 2022 / 264359 (Patent Document 3).

[0037] Figure 5 is a circuit diagram showing the configuration of the pixel circuit 14b, i.e., the i-th row, j-th column pixel circuit Pix(i,j), corresponding to the i-th first scan signal line PSi and the j-th data signal line Dj in this comparative example (1 ≤ i ≤ n, 1 ≤ j ≤ m). This pixel circuit 14b includes a display element initialization transistor T7, which corresponds to the second initialization transistor described above, similar to the pixel circuit 14a (Figure 3) in the conventional example, but differs from the pixel circuit 14a (Figure 3) in that it does not include the first initialization transistor T1. The configuration and operation of the pixel circuit 14b in this comparative example that are not newly described below are the same as those of the pixel circuit 14a in the conventional example.

[0038] As shown in Figure 5, in this comparative example, the pixel circuit Pix(i,j) in the i row and j column is connected to NSi+2, which is two steps after the corresponding second scan signal line NSi (the second scan signal line two steps after the scanning order of second scan signal lines NS1 to NSn, and will hereafter be simply referred to as the "successor second scan signal line" in the explanation focusing on the pixel circuit), and the preceding second scan signal line NSi-2 is not connected. In the pixel circuit 14b in this comparative example, unlike the pixel circuit 14a in the modified example (Figure 3), the gate terminal of the light emission control transistor T6 is connected to the successor second scan signal line NSi+2 instead of the corresponding light emission control line EMI.

[0039] Next, the operation of the pixel circuit 14b shown in Figure 5, that is, the i-th row, j-th column pixel circuit Pix(i,j) in this comparative example, will be explained with reference to Figure 5 and Figure 6. Figure 6 is a timing chart for explaining the operation of the pixel circuit Pix(i,j). In this comparative example, the first scan signal line PSi, the second scan signal line NSi, the light emission control line EMI, and the data signal line Dj are driven as shown in Figure 6, and as a result, the i-th row, j-th column pixel circuit 14b, that is, Pix(i,j), in this comparative example operates as follows.

[0040] In this comparative example, for the pixel circuit Pix(i,j), the selection period of the subsequent second scan signal line NSi+2 connected to the gate terminal of the light emission control transistor T6 partially overlaps with the selection period of the corresponding second scan signal line NSi. Therefore, as shown in Figure 6, the corresponding second scan signal NS(i), which is the second scan signal of the corresponding second scan signal line NSi, and the subsequent corresponding second scan signal NS(i+2), which is the second scan signal of the subsequent second scan signal line NSi+2, are at the H level from time t3 to time t6. During the non-light emission period t1 to t8, when the light emission control signal EM(i) of the corresponding light emission control line EMI is at the H level, the corresponding second scan signal NS(i) is at the H level and the subsequent second scan signal NS(i+2) is at the L level from time t2 to time t3. Therefore, during this period t2 to t3, the threshold compensation transistor T2, the light emission control transistor T6, and the display element initialization transistor T7 are all in the ON state. This creates a current path from the node including the gate terminal of the drive transistor T4 to the initialization voltage line Vini via the threshold compensation transistor T2, the light emission control transistor T6, and the display element initialization transistor T7. This period t2 to t3 is the initialization period for this pixel circuit Pix(i,j), and the gate voltage of the drive transistor T4 is initialized by this current path.

[0041] As shown in Figure 6, the first scan signal PS(i) is at a low level during the period t4 to t5, when the corresponding second scan signal NS(i) and the subsequent second scan signal NS(i+1) are both at a high level during the period t3 to t6, and the write control transistor T3 is in the ON state. During other periods, the first scan signal PS(i) is at a high level and the write control transistor T3 is in the OFF state. The period t4 to t5, when the first scan signal PS(i) is at a low level, is the data writing period for this pixel circuit Pix(i,j). During this data writing period t4 to t5, the voltage of the corresponding data signal line Dj, i.e., the voltage of the data signal D(j), is supplied as the data voltage to the gate terminal of the drive transistor T4 via the write control transistor T3, the drive transistor T4, and the threshold compensation transistor T2. As a result, the threshold-compensated data voltage is written to and held in the holding capacitor Cst.

[0042] As described above, in the pixel circuit 14b in this comparative example as well, similar to the pixel circuit 14a in the above conventional example, after the gate voltage Vg is initialized, writing of a data voltage with threshold compensation is performed. Therefore, according to this comparative example, an organic EL display device with an internal compensation method is realized with a configuration having one less transistor in the pixel circuit than in the above conventional example.

[0043] <1.5 Configuration and Operation of Pixel Circuit in First Embodiment> FIG. 7 is a circuit diagram showing the configuration of the pixel circuit 15 corresponding to the i-th first scanning signal line PSi and the j-th data signal line Dj in the first embodiment, that is, the pixel circuit Pix(i, j) at the i-th row and j-th column (1 ≤ i ≤ n, 1 ≤ j ≤ m). This pixel circuit 15, similar to the pixel circuit 14b (FIG. 5) in the above comparative example, includes an organic EL element OL as a display element, a driving transistor T4, a writing control transistor T3, a threshold compensation transistor T2, a power supply control transistor T5, a light emission control transistor T6, an initialization transistor T7, and a holding capacitor Cst, but does not include the first initialization transistor T1 in the pixel circuit 14a of the conventional example. Note that the transistors T2 and T7 are N-type transistors, for example, thin film transistors (hereinafter referred to as "IGZO-TFTs") in which the channel layer is formed of indium gallium zinc oxide (InGaZnO) as an oxide semiconductor. The transistors T3 to T6 are P-type transistors, for example, thin film transistors (hereinafter referred to as "LTPS-TFTs") in which the channel layer is formed of low-temperature polysilicon. However, it is not limited to these. In this pixel circuit 15, the transistors T2, T3, T5 to T7 other than the driving transistor T4 function as switching elements. Note that, for the configurations and operations that are not newly described below for the pixel circuit 15 in this embodiment, they are the same as those of the pixel circuit 14b in the above comparative example.

[0044] As shown in Figure 7, in the pixel circuit 15 of this embodiment, the source terminal of the initialization transistor T7 is connected to the initialization voltage line Vini, similar to the pixel circuit 14b (Figure 5) in the comparative example. However, in the pixel circuit 15 of this embodiment, unlike the pixel circuit 14b (Figure 5) in the comparative example, the drain terminal of the initialization transistor T7 is connected to the drain terminal of the drive transistor T4 instead of the anode electrode of the organic EL element OL. Also, in the i-th row, j-th column pixel circuit Pix(i,j) of this embodiment, unlike the pixel circuit 14b (Figure 5) in the comparative example, the gate terminal of the light emission control transistor T6 is connected to the corresponding second scan signal line NSi instead of the subsequent second scan signal line NSi+2, and the gate terminal of the initialization transistor T7 is connected to the second scan signal line NSi-X that precedes the corresponding second scan signal line NSi instead of the corresponding light emission control line EMI (hereinafter, in the description focusing on the pixel circuit, this second scan signal line NSi-X will be referred to as the "preceding second scan signal line NSi-X"). Here, X is a positive integer, and is selected such that the selection period of the preceding second scan signal line NSi-X partially overlaps with the selection period of the corresponding second scan signal line NSi. X is preferably 1 or 2, and in the example shown in Figure 1, X = 2.

[0045] Next, the operation of the pixel circuit 15 shown in Figure 7, that is, the i-th row, j-th column pixel circuit Pix(i,j) in this embodiment, will be explained with reference to Figures 9A to 9D along with Figure 8. Figure 8 is a timing chart for explaining the operation of the pixel circuit Pix(i,j), and shows the change in the drive signal during the period in which data writing is performed in this pixel circuit Pix(i,j) and the periods before and after. In this embodiment, for each pixel circuit Pix(i,j), an anode initialization period TAini as a display element initialization period, a gate voltage initialization period TGini as a write voltage initialization period, a write period Twr, and an illumination period Temp are provided in order for each frame period. In the write period Twr, threshold compensation is performed in the pixel circuit Pix(i,j) along with the writing of the data voltage, as in the conventional example and comparative example described above (see equations (1) to (4) described above). For this reason, this write period Twr is also a compensation period Tcmp in which threshold compensation is performed by an internal compensation method.

[0046] FIG. 9A is a circuit diagram for explaining the anode initialization operation in the pixel circuit Pix(i, j), and shows the circuit state such as the on / off state of each transistor as a switching element in the pixel circuit Pix(i, j) during the anode initialization period TAini. FIG. 9B is a circuit diagram for explaining the gate voltage initialization operation in the pixel circuit Pix(i, j), and shows the circuit state such as the on / off state of each transistor as a switching in the pixel circuit Pix(i, j) during the gate voltage initialization period TGini. FIG. 9C is a circuit diagram for explaining the data writing operation in the pixel circuit Pix(i, j), and shows the circuit state such as the on / off state of each transistor as a switching in the pixel circuit Pix(i, j) during the writing period Twr. FIG. 9D is a circuit diagram for explaining the light emitting operation in the pixel circuit Pix(i, j), and shows the circuit state such as the on / off state of each transistor as a switching in the pixel circuit Pix(i, j) during the light emitting period Tem. In FIGS. 9A to 9D, a dotted circle indicates that the transistor therein is in the on state, and a dotted cross mark indicates that the transistor to which it is attached is in the off state. For example, FIG. 9B shows that the threshold compensation transistor T2 and the initialization transistor T7 are in the on state, and the write control transistor T3, the power supply control transistor T5, and the light emitting control transistor T6 are in the off state. Such an expression method is also adopted in FIGS. 12A to 12D, FIGS. 17A to 17D, and FIGS. 22A to 22B described later.

[0047] In this embodiment, the first scanning signal line PSi, the second scanning signal line NSi, and the light emitting control line EMi are driven as shown in FIG. 8.

[0048] As shown in Figure 8, immediately before time t1, the corresponding first scan signal PS(i), which is the first scan signal provided via the corresponding first scan signal line PSi, is at a high level (H level), the corresponding light emission control signal EM(i), which is the light emission control signal provided via the corresponding light emission control line EMI, the corresponding second scan signal NS(i), which is the second scan signal provided via the corresponding second scan signal line NSi, and the preceding second scan signal NS(i-X), which is the second scan signal provided via the preceding second scan signal line NSi-X, are all at a low level (L level), and the pixel circuit Pix(i,j) is in a light emission state.

[0049] At time t1, the corresponding light emission control signal EM(i) changes from L level to H level, maintains the H level until time t8, and then changes back to L level. As a result, the P-type power supply control transistor T5 changes from the ON state to the OFF state at time t1 and remains in the OFF state while the corresponding light emission control signal EM(i) is at the H level. Therefore, during the period t1 to t8 when the corresponding light emission control signal EM(i) is at the H level, no current flows to the organic EL element OL and the pixel circuit Pix(i,j) is in a non-light-emitting state.

[0050] During the period t1 to t8 when the corresponding light emission control signal EM(i) is at the H level (hereinafter referred to as the "non-light emission period"), as shown in Figure 8, the preceding second scan signal NS(i-X) changes from the L level to the H level at time t2, maintains the H level until time t4, and then changes to the L level. The corresponding second scan signal NS(i) changes from the L level to the H level at time t3, maintains the H level until time t7, and then changes to the L level. The selection period t3 to t7 for this corresponding second scan signal line NSi partially overlaps with the selection period t2 to t4 for the preceding second scan signal, and during the period from time t3 to time t4, both the preceding second scan signal NS(i-X) and the corresponding second scan signal NS(i) are at the H level. On the other hand, the corresponding first scan signal PS(i) changes from the H level to the L level at time t5, maintains the L level until time t6, and then changes to the H level. In other words, the corresponding first scan signal PS(i) is at an L level from time t5 to time t6 during the period t4 to t7 when the preceding second scan signal NS(i-X) is at an L level and the corresponding second scan signal NS(i) is at an H level. Furthermore, from time t8 onward, when the corresponding light emission control signal EM(i) changes from an H level to an L level, the period during which the light emission control signal EM(i) remains at an L level is the light emission period Tem of the pixel circuit Pix(i,j).

[0051] The pixel circuit Pix(i,j) in this embodiment, driven by the corresponding light emission control signal EM(i), corresponding second scan signal NS(i), preceding second scan signal NS(i-X), and corresponding first scan signal PS(i) as shown in Figure 8, operates as follows during the anode initialization period TAini, the gate voltage initialization period TGini, the write period Twr, and the light emission period Temp after the write period Twr.

[0052] The period from time t2 to time t3 is the anode initialization period TAini of the pixel circuit Pix(i,j). During this anode initialization period TAini, as shown in Figure 8, the corresponding light emission control signal EM(i), the preceding second scan signal NS(i-X), and the corresponding first scan signal PS(i) are at the H level, while the corresponding second scan signal NS(i) is at the L level. As a result, the pixel circuit Pix(i,j) enters the circuit state shown in Figure 9A, and a current path is formed from the anode electrode of the organic EL element OL through the light emission control transistor T6 and the initialization transistor T7 to the initialization voltage line Vini. This current path discharges the charge accumulated in the parasitic capacitance of the organic EL element OL, and the voltage at the anode electrode of the organic EL element OL (anode voltage) Va is initialized to the initialization voltage Vini (hereinafter this initialization is referred to as "anode initialization").

[0053] The period from time t3 to time t4 is the gate voltage initialization period TGini of the pixel circuit Pix(i,j). During this gate voltage initialization period TGini, as shown in Figure 8, the corresponding light emission control signal EM(i), the corresponding first scan signal PS(i), the corresponding second scan signal NS(i), and the preceding second scan signal NS(i-X) are all at the H level. As a result, the pixel circuit Pix(i,j) enters the circuit state shown in Figure 9B, and a current path is formed from the node including the gate terminal of the drive transistor T4 to the initialization voltage line Vini via the threshold compensation transistor T2 and the initialization transistor T7. This current path initializes the gate voltage Vg of the drive transistor T4 to the initialization voltage Vini (hereinafter, this initialization is referred to as "gate voltage initialization"), and a voltage (ELVDD-Vini) for maintaining the gate voltage Vg at the initialization voltage Vini is held in the holding capacitor Cst. Furthermore, this current path contains two transistors (threshold compensation transistor T2 and initialization transistor T7), which is one less than the number of transistors (threshold compensation transistor T2, light emission control transistor T6, and initialization transistor T7) included in the current path formed for initializing the gate voltage Vg in the pixel circuit 14b (Figure 5) in the comparative example above.

[0054] The period from time t5 to time t6 is the write period Twr for the pixel circuit Pix(i,j). During this write period Twr, as shown in Figure 8, the corresponding first scan signal PS(i) and the preceding second scan signal NS(i-X) are at the L level, and the corresponding light emission control signal EM(i) and the corresponding second scan signal NS(i) are at the H level. As a result, the pixel circuit Pix(i,j) enters the circuit state shown in Figure 9C, and the voltage of the data signal line Dj, i.e., the voltage of the data signal D(j), is applied as the data voltage Vdata to the node including the gate terminal of the drive transistor T4 via the write control transistor T3, the drive transistor T4, and the threshold compensation transistor T2. As a result, the threshold-compensated data voltage Vdata is written to the holding capacitor Cst (see equation (1) described above).

[0055] After the end of the above-mentioned writing period Twr, the corresponding light emission control signal EM(i) changes from H level to L level at time t8, and a new light emission period Term begins. During this light emission period Term, as shown in Figure 8, the corresponding light emission control signal EM(i), the corresponding second scan signal NS(i), and the preceding second scan signal NS(i-X) are at L level, and the corresponding first scan signal PS(i) is at H level. As a result, the pixel circuit Pix(i,j) enters the circuit state shown in Figure 9D, and a current I1 corresponding to the voltage held in the holding capacitor Cst flows from the high-level power line ELVDD through the power supply control transistor T5, the drive transistor T4, the light emission control transistor T6, and the organic EL element OL to the low-level power line ELVSS. At this time, the current I1 flowing through the organic EL element OL is given by the previously described equation (4) and does not depend on the threshold voltage Vth of the drive transistor T4. Therefore, during the light emission period Tem after time t8, the organic EL element OL emits light with a brightness corresponding to the data voltage Vdata, which is the voltage of the corresponding data signal line Dj during the writing period Twr, regardless of the threshold voltage Vth of the drive transistor T4.

[0056] <1.6 Effects> According to this embodiment as described above, in the pixel circuit 15 (Figure 7), the first initialization transistor T1, which was used to initialize the gate voltage Vg of the drive transistor T4 in the conventional pixel circuit 14a (Figure 3), is removed, and the gate voltage Vg of the drive transistor T4 is initialized by a current path including the threshold compensation transistor T2 and the initialization transistor T7 (see Figure 9B). The initialization transistor T7 used to form this current path is also used to form a current path for anode initialization (see Figure 9A). As a result, an internally compensated display device is realized using a pixel circuit 15 containing fewer transistors than in the conventional model. Therefore, it is possible to provide a high-definition internally compensated display device while suppressing a decrease in yield.

[0057] The number of transistors (more generally, the number of elements) included in the pixel circuit 14b (Figure 5) in the above comparative example is the same as the number of transistors included in the pixel circuit 15 in this embodiment. However, the number of transistors included in the current path for gate voltage initialization formed in the pixel circuit 15 in this embodiment is 2, which is one less than the number of transistors included in the current path for gate voltage initialization formed in the pixel circuit 14b in the above comparative example. Therefore, according to this embodiment, the charging speed of the holding capacitor Cst for gate voltage initialization in the pixel circuit 15 is improved compared to the pixel circuit 14b in the above comparative example. As a result, according to this embodiment, the brightness variation caused by the difficulty of the gate voltage Vg of the drive transistor T4 reaching the initialization voltage Vini during the gate voltage initialization period TGini is improved.

[0058] <2. Second Embodiment> Next, a display device according to the second embodiment will be described. The display device according to this embodiment is also an internally compensated organic EL display device, and uses a pixel circuit 16 configured as shown in Figure 10. Unlike the pixel circuit 15 in the first embodiment (Figure 7), the second scanning signal line NSi is not used to drive this pixel circuit 16. To drive this pixel circuit 16 (Pix(i,j)), in addition to the corresponding light emission control line EMI, which is the light emission control line corresponding to this pixel circuit Pix(i,j), a preceding light emission control line EMI-X, which is the light emission control line preceding the corresponding light emission control line EMI, is used. Here, X is a positive integer, and is selected so that the deactivation period of the preceding light emission control line EMI-X partially overlaps with the deactivation period of the corresponding light emission control line EMI. X is preferably 1 or 2.

[0059] As described above, the overall configuration of this embodiment differs from the overall configuration of the first embodiment (see Figure 1). The display unit 11 does not have second scanning signal lines NS-1, NS0, NS1 to NSn, and instead of n light emission control lines EM1 to EMn, it has n+2 light emission control lines EM-1, EM0, EM1 to EMn. Therefore, the scanning drive circuit 40 in this embodiment drives n first scanning signal lines PS1 to PSn and n+2 light emission control lines EM-1 to EMn. Configurations and operations that are not newly described in this embodiment are the same as in the first embodiment. In the following description, parts of the configuration in this embodiment that are the same as or correspond to the configuration in the first embodiment will be denoted by the same reference numerals.

[0060] <2.1 Pixel Circuit Configuration and Operation> Figure 10 is a circuit diagram showing the configuration of the pixel circuit 16, i.e., the i-th row, j-th column pixel circuit Pix(i,j), corresponding to the i-th first scanning signal line PSi and the j-th data signal line Dj in this embodiment (1 ≤ i ≤ n, 1 ≤ j ≤ m). As can be seen by comparing Figure 10 with Figure 7, the pixel circuit 16 in this embodiment differs from the pixel circuit 15 in the first embodiment above in that it includes two P-type transistors as switching elements: a first power supply control transistor T5a corresponding to the power supply control transistor T5, and a second power supply control transistor T5b connected in series therewith. The other configurations of the pixel circuit 16 in this embodiment are the same as those of the pixel circuit 15 in the first embodiment above, except for the signal lines for driving the pixel circuit 16.

[0061] As shown in Figure 10, in the i-th row, j-th column pixel circuit Pix(i,j) in this embodiment, the source terminal of the drive transistor T4 is connected to the high-level power line ELVDD via the first power supply control transistor T5a and the second power supply control transistor T5b in sequence. The gate terminals of the first power supply control transistor T5a and the initialization transistor T7 are connected to the preceding light emission control line EMi-X, the gate terminals of the second power supply control transistor T5b, the threshold compensation transistor and the light emission control transistor T6 are connected to the corresponding light emission control line EMi, and the gate terminal of the write control transistor T3 is connected to the corresponding first scan signal line PSi.

[0062] Next, the operation of the pixel circuit 16 shown in Figure 10, that is, the i-th row, j-th column pixel circuit Pix(i,j) in this embodiment, will be explained with reference to Figures 11 and 12A to 12D. Figure 11 is a timing chart for explaining the operation of the pixel circuit Pix(i,j), showing the changes in the drive signal during the period in which data writing is performed in this pixel circuit Pix(i,j) and the periods before and after. In this embodiment as well, for each pixel circuit Pix(i,j), an anode initialization period TAini, a gate voltage initialization period TGini, a writing period Twr, and an emission period Temp are provided in order for each frame period. During the writing period Twr, threshold compensation is performed in the pixel circuit Pix(i,j) along with the writing of the data voltage, as in the conventional example and comparative example described above.

[0063] Figure 12A is a circuit diagram illustrating the anode initialization operation in the pixel circuit Pix(i,j), showing the circuit state of the pixel circuit Pix(i,j) during the anode initialization period TAini (on / off state of each transistor functioning as a switch, etc.). Figure 12B is a circuit diagram illustrating the gate voltage initialization operation in the pixel circuit Pix(i,j), showing the circuit state of the pixel circuit Pix(i,j) during the gate voltage initialization period TGini. Figure 12C is a circuit diagram illustrating the data writing operation in the pixel circuit Pix(i,j), showing the circuit state of the pixel circuit Pix(i,j) during the writing period Twr. Figure 12D is a circuit diagram illustrating the light emission operation in the pixel circuit Pix(i,j), showing the circuit state of the pixel circuit Pix(i,j) during the light emission period Temp.

[0064] In this embodiment, the first scanning signal line PSi and the light emission control line EMI are driven as shown in Figure 11.

[0065] As shown in Figure 11, the leading light emission control signal EM(i-X), which is a light emission control signal applied to the pixel circuit Pix(i,j) via the leading light emission control line EMi-X, changes from L level to H level at time t1, maintains the H level until time t3, and then changes to L level. As a result, the first power supply control transistor T5a changes from the ON state to the OFF state at time t1 and maintains the OFF state until time t3. Also, the corresponding light emission control signal EM(i) changes from L level to H level at time t2, maintains the H level until time t6, and then changes to L level. As a result, the second power supply control transistor T5b and the light emission control transistor T6 change from the ON state to the OFF state at time t2 and maintain the OFF state until time t6. Therefore, during the period t1 to t6 when either the leading light emission control signal EM(i-X) or the corresponding light emission control signal EM(i) is at the H level, no current flows to the organic EL element OL and the pixel circuit Pix(i,j) is in a non-light emission state.

[0066] The corresponding first scanning signal PS(i) maintains an L level from before time t1. During the period t3 to t6, when the corresponding light emission control signal EM(i) is at an H level and the preceding light emission control signal EM(i-X) is at an L level, PS(i) changes from an H level to an L level at time t4, maintains an L level until time t5, and then changes back to an H level. After time t6, both the corresponding light emission control signal EM(i) and the preceding light emission control signal EM(i-X) are at an L level. As a result, the first power supply control transistor T5a, the second power supply control transistor T5b, and the light emission control transistor T6 are all in the ON state. Therefore, the period after time t6 when both the corresponding light emission control signal EM(i) and the preceding light emission control signal EM(i-X) maintain an L level is the light emission period TEM of the pixel circuit Pix(i,j).

[0067] As shown in Figure 11, the corresponding light emission control signal EM(i), the preceding light emission control signal EM(i-X), and the corresponding first scan signal PS(i) allow the pixel circuit Pix(i,j) in this embodiment to operate as follows during the anode initialization period TAini, the gate voltage initialization period TGini, the write period Twr, and the light emission period Temp after the write period Twr.

[0068] The period from time t1 to time t2 is the anode initialization period TAini of the pixel circuit Pix(i,j). During this anode initialization period TAini, as shown in Figure 11, the corresponding light emission control signal EM(i) is at the L level, and the preceding light emission control signal EM(i-X) and the corresponding first scan signal PS(i) are at the H level. As a result, the pixel circuit Pix(i,j) enters the circuit state shown in Figure 12A, forming a current path from the anode electrode of the organic EL element OL through the light emission control transistor T6 and the initialization transistor T7 to the initialization voltage line Vini. This current path performs anode initialization in the same manner as in the first embodiment. That is, the accumulated charge of the parasitic capacitance in the organic EL element OL is discharged, and the anode voltage Va is initialized.

[0069] The period from time t2 to time t3 is the gate voltage initialization period TGini of the pixel circuit Pix(i,j). During this gate voltage initialization period TGini, as shown in Figure 11, the corresponding light emission control signal EM(i), the preceding light emission control signal EM(i-X), and the corresponding first scan signal PS(i) are all at the H level. As a result, the pixel circuit Pix(i,j) enters the circuit state shown in Figure 12B, and a current path is formed from the node including the gate terminal of the drive transistor T4 to the initialization voltage line Vini via the threshold compensation transistor T2 and the initialization transistor T7, and gate voltage initialization is performed in the same manner as in the first embodiment. That is, the gate voltage Vg of the drive transistor T4 is initialized to the initialization voltage Vini, and a voltage (ELVDD-Vini) for maintaining the gate voltage Vg at the initialization voltage Vini is held in the holding capacitor Cst. In this embodiment as well, the number of transistors included in the current path for gate voltage initialization is 2, which is one less than the number of transistors included in the current path for gate voltage initialization in the comparative example above.

[0070] The period from time t4 to time t5 is the write period Twr for the pixel circuit Pix(i,j). During this write period Twr, the corresponding light emission control signal EM(i) is at the H level, and the preceding light emission control signal EM(i-X) and the corresponding first scan signal PS(i) are at the L level. As a result, the pixel circuit Pix(i,j) is in the circuit state shown in Figure 12C, and the voltage of the data signal line Dj is applied as the data voltage Vdata to the node including the gate terminal of the drive transistor T4 via the write control transistor T3, the drive transistor T4, and the threshold compensation transistor T2. Consequently, the threshold-compensated data voltage Vdata is written to the holding capacitor Cst.

[0071] After the end of the above-mentioned write period Twr, the corresponding light emission control signal EM(i) changes from H level to L level at time t6, and a new light emission period Tem begins. During this light emission period Tem, as shown in Figure 11, the corresponding light emission control signal EM(i) and the preceding light emission control signal EM(i-X) are at L level, and the corresponding first scan signal PS(i) is at H level. As a result, the pixel circuit Pix(i,j) enters the circuit state shown in Figure 12D, and a current I1 corresponding to the voltage held in the holding capacitor Cst flows from the high-level power line ELVDD through the second power supply control transistor T5b, the first power supply control transistor T5a, the drive transistor T4, the light emission control transistor T6, and the organic EL element OL to the low-level power line ELVSS. At this time, the current I1 flowing through the organic EL element OL is given by equation (4) described above, as in the first embodiment, and does not depend on the threshold voltage Vth of the drive transistor T4. Therefore, during the light emission period Tem after time t6, the organic EL element OL emits light with a brightness corresponding to the data voltage Vdata, which is the voltage of the corresponding data signal line Dj during the writing period Twr, regardless of the threshold voltage Vth of the drive transistor T4.

[0072] <2.2 Effects> According to this embodiment as described above, similar to the first embodiment (Figure 7), in the pixel circuit 16 (Figure 10), the gate voltage Vg of the drive transistor T4 is initialized by a current path including a threshold compensation transistor T2 and an initialization transistor T7. This eliminates the need for a dedicated initialization transistor T1 (see Figure 3) for gate voltage initialization. Furthermore, the initialization transistor T7 used to form this current path is also used to form a current path for anode initialization (see Figure 12A). This enables the realization of an internally compensated display device using a pixel circuit 15 containing fewer transistors than conventional devices. Therefore, it is possible to provide a high-definition internally compensated display device while suppressing a decrease in manufacturing yield. In addition, according to this embodiment, similar to the first embodiment, the number of transistors included in the current path for gate voltage initialization is 2, which is one less than the number of transistors included in the current path for gate voltage initialization in the pixel circuit 14b in the comparative example, so the charging speed for gate voltage initialization is improved compared to the comparative example. As a result, brightness variations caused by insufficient charging during the gate voltage initialization period TGini are improved.

[0073] As described above, this embodiment provides the same effects as the first embodiment, but as can be seen from Figures 10 and 11, the first scanning signal line NSi used in the first embodiment is unnecessary. Therefore, this embodiment reduces the size of the scanning drive circuit 40 compared to the first embodiment, which is advantageous for narrowing the bezel of the display device. In addition, in this embodiment, the scanning signals for driving each pixel circuit 16 consist only of the first scanning signal PS(i) and the light emission control signal EM(i), which is one less than the scanning signals for driving the pixel circuits in the first embodiment. This contributes to higher resolution displays and improved yield during manufacturing.

[0074] <3. Third Embodiment> A display device that performs sleep drive is known as a low-power display device. Sleep drive is a driving method in which a driving period (refresh period) and a sleep period (non-refresh period) are set when displaying the same image continuously, and the driving circuit is operated during the driving period and the operation of the driving circuit is stopped during the sleep period, and is also called "intermittent drive" or "low-frequency drive". In an organic EL display device that performs such sleep drive, in order to suppress the occurrence of flicker caused by the hysteresis characteristics of the driving transistor T4, a configuration is known in which a bias stress voltage (also called "on-bias voltage") is applied to the driving transistor T4 via the data signal line Dj during the sleep period. Below, as in the first and second embodiments described above, an organic EL display device that performs sleep drive while applying an on-bias voltage to the driving transistor T4 during the sleep period is described as a third embodiment, which performs threshold compensation by an internal compensation method using a pixel circuit in which the gate voltage Vg of the driving transistor T4 is initialized by a current path including a threshold compensation transistor T2 and an initialization transistor T7, and performs sleep drive. Note that the configuration and operation of this embodiment that are not newly described below are the same as in the first embodiment described above. Furthermore, in the following description, parts of the configuration in this embodiment that are the same as or corresponding to the configuration in the first embodiment described above will be denoted by the same reference numerals.

[0075] <3.1 Overall Configuration> Figure 13 is a block diagram showing the overall configuration of the display device 10b according to this embodiment. As shown in Figure 13, unlike the display device in the first embodiment (Figure 1), the display unit 11 in this embodiment is equipped with n second scan signal lines NSa1 to NSaan and n third scan signal lines NSb1 to NSbn instead of n+2 second scan signal lines NS-1 to NSn+2, and n+2 light emission control lines EM1 to EMn are equipped with n+2 light emission control lines EM1 to EMn+2 instead of n light emission control lines EM1 to EMn.

[0076] Accordingly, the scanning drive circuit 40 in this embodiment, as a scanning signal line drive circuit, in each refresh frame period Trf, sequentially selects n first scanning signal lines PS1 to PSn for predetermined periods corresponding to one horizontal period based on the scanning control signal Scs, sequentially selects n second scanning signal lines NSa1 to NSaan for predetermined periods corresponding to one horizontal period, sequentially selects n third scanning signal lines NSb1 to NSbn for predetermined periods corresponding to one horizontal period, applies an L-level signal as an active signal to the selected first scanning signal line PSk (1 ≤ k ≤ n), and the selected A high-level signal is applied as an active signal to the second scan signal line NSak (1 ≤ k ≤ n), and a high-level signal is applied as an active signal to the selected third scan signal line NSbk (1 ≤ k ≤ n). On the other hand, a high-level signal is applied as an inactive signal to the unselected first scan signal line PSi, a low-level signal is applied as an inactive signal to the unselected second scan signal line NSai, and a low-level signal is applied as an inactive signal to the unselected third scan signal line NSbi (see the signal waveform during the refresh frame period Trf shown in Figure 14 below).

[0077] Furthermore, the scanning drive circuit 40 drives n+2 light emission control lines EM1 to EMn+2 during each refresh frame period Trf so that they are selectively deactivated in conjunction with the above-mentioned driving of the first to third scanning signal lines PS1 to PSn, NSa1 to NSaan, and NSb1 to NSbn. That is, the scanning drive circuit 40, as a light emission control circuit, applies an H-level signal to the i-th light emission control line EMI as a light emission control signal indicating no light emission during a predetermined period including the i-th horizontal period, and applies an L-level signal as a light emission control signal indicating light emission during other periods (i = 1 to n). Furthermore, the scanning drive circuit 40 drives n+2 light emission control lines EM1 to EMn+2 such that the period when light emission control line EMi is inactive (the period when the light emission control signal EM(i) is at the H level) and the period when the subsequent light emission control line EMi+2 is inactive (the period when the light emission control signal EM(i+2) is at the H level) partially overlap (see the waveforms of light emission control signals EM(1) to EM(n+2) shown in Figure 14 below).

[0078] <3.2 General Operation> Figure 14 is a timing chart for illustrating the general operation of the display device 10b according to this embodiment.

[0079] The display device 10b according to this embodiment has two operating modes: a normal drive mode and a pause drive mode. In the normal drive mode, the scanning drive circuit 40 drives the first scanning signal lines PS1 to PSn, the second scanning signal lines NSa1 to NSaan, the third scanning signal lines NSb1 to NSbn, and the light emission control lines EM1 to EMn+2 as described above during each refresh frame period Trf, and the data drive circuit 30 generates data signals D(1) to D(m) that change in conjunction with the first scanning signals PS(1) to PS(n), and applies them to the data signal lines D1 to Dm, respectively. In this manner, the first scan signal lines PS1 to PSn, the second scan signal lines NSa1 to NSaan, the third scan signal lines NSb1 to NSbn, the light emission control lines EM1 to EMn+2, and the data signal lines D1 to Dm in the display unit 11 are driven, and, as in the first embodiment described above, during each refresh frame period Trf, during the non-light emission period, initialization and data voltage writing are performed for each pixel circuit Pix(i,j), and during the light emission period, each pixel circuit emits light with a brightness corresponding to the written data voltage. In the normal drive mode, such a refresh frame period Trf is repeated.

[0080] In contrast, in the idle drive mode, as shown in Figure 14, a drive period TD consisting of a refresh frame period (hereinafter also called the "RF frame" period) Trf in which data writing operations are performed to write data voltages to each pixel circuit Pix(i,j) as described above, and a idle period TP consisting of multiple non-refresh frame periods (hereinafter also called the "NRF frame" period) Tnrf in which such data writing operations are stopped are alternately repeated. In the idle drive mode in this embodiment, during the idle period TP, the driving of the second scanning signal lines NSa1 to NSa by the scanning drive circuit 40 and the application of data signals D(1) to D(n) to the data signal lines D1 to Dm by the data drive circuit 30 are stopped, and the display of image data consisting of data voltages written to each pixel circuit Pix(i,j) in the immediately preceding drive period TD (RF frame period Trf) continues. For this reason, the idle drive mode is effective in reducing the power consumption of the display device when displaying still images. In the example shown in Figure 14, the drive period TD consists of only one RF frame period Trf, but it may consist of two or more RF frame periods Trf (this also applies to the pause drive in other embodiments). In this embodiment, the drive of the first scan signal lines PS1 to PSn, the third scan signal lines NSb1 to NSbn, and the light emission control lines EM1 to EMn+2 continues even during the NRF frame period Tnrf. In addition, during the NRF frame period Tnrf, an on-bias voltage Vob is applied to the data signal lines D1 to Dm in place of the data signals D(1) to D(m).

[0081] The external input signal Sin includes an operation mode signal Sm that indicates which of the above-described normal drive mode and idle drive mode will be used to drive the display unit 11. This operation mode signal Sm is provided to the scanning drive circuit 40 as part of the scanning control signal Scs, and to the data drive circuit 30 as part of the data control signal Scd. The scanning drive circuit 40 drives the second scanning signal lines NSa1 to NSa according to the operation mode indicated by this operation mode signal Sm, and the data drive circuit 30 drives the data signal lines D1 to Dn according to the operation mode indicated by this operation mode signal Sm (see Figure 14). In the following description, the operation of the display device 10b or its pixel circuit 17 in this embodiment will be explained focusing on the operation in idle drive mode.

[0082] <3.3 Pixel Circuit Configuration and Operation> Figure 15 is a circuit diagram showing the configuration of the pixel circuit 17, i.e., the i-th row, j-th column pixel circuit Pix(i,j), corresponding to the i-th first scan signal line PSi and the j-th data signal line Dj in this embodiment (1 ≤ i ≤ n, 1 ≤ j ≤ m). As can be seen by comparing Figure 15 with Figure 7, the configuration of the pixel circuit 17 in this embodiment is the same as the configuration of the pixel circuit 15 in the first embodiment, except for the signal lines for driving this pixel circuit 17.

[0083] As shown in Figure 15, in this embodiment, the pixel circuit Pix(i,j) in the i row and j column differs from the pixel circuit 15 in the first embodiment (Figure 7) in that the gate terminal of the threshold compensation transistor T2 is connected to the corresponding second scan signal line NSai, which is the second scan signal line corresponding to the pixel circuit Pix(i,j); the gate terminal of the initialization transistor T7 is connected to the corresponding third scan signal line NSbi, which is the third scan signal line corresponding to the pixel circuit Pix(i,j); and the gate terminal of the light emission control transistor T6 is connected to the subsequent light emission control line EMi+X, which is the subsequent light emission control line following the light emission control line EMi corresponding to the pixel circuit Pix(i,j). Here, X is a positive integer and is selected such that the deactivation period of the subsequent light emission control line EMi+X partially overlaps with the deactivation period of the corresponding light emission control line EMi (see Figure 16, described later). X is preferably 1 or 2, and in this embodiment, X = 2.

[0084] Next, the operation of the pixel circuit 17 shown in Figure 15, that is, the i-th row, j-th column pixel circuit Pix(i,j) in this embodiment, will be explained with reference to Figures 17A to 17D, along with Figure 16. Figure 16 is a timing chart for explaining the operation of the pixel circuit Pix(i,j), showing the changes in the drive signal during the period in which data writing is performed in this pixel circuit Pix(i,j) and the periods before and after it during the drive period TD (RF frame period Trf), and also showing the changes in the drive signal during the period in which on-bias voltage is applied in this pixel circuit Pix(i,j) and the periods before and after it during the pause period TP (NRF frame period Tnrf). In this embodiment as well, in each frame period within the drive period TD, the RF frame period Trf is provided with the pixel circuit Pix(i,j) in the following order: anode initialization period TAini, gate voltage initialization period TGini, write period Twr, and light emission period Temp. During the write period Twr, threshold compensation is performed within the pixel circuit Pix(i,j) along with the writing of the data voltage, similar to the conventional and comparative examples described above. In this embodiment, during the NRF frame period Tnrf, which is each frame period within the pause period TP, an anode initialization period TAini, an on-bias period Tob, and an emission period Temp are provided in order for the pixel circuit Pix(i,j).

[0085] Figure 17A is a circuit diagram illustrating the anode initialization operation of the pixel circuit Pix(i,j) during the drive period TD, and shows the circuit state of the pixel circuit Pix(i,j) during the anode initialization period TAini in the drive period TD (on / off state of each transistor functioning as a switch, etc.). Figure 17B is a circuit diagram illustrating the gate voltage initialization operation of the pixel circuit Pix(i,j) during the drive period TD, and shows the circuit state of the pixel circuit Pix(i,j) during the gate voltage initialization period TGini in the drive period TD. Figure 17C is a circuit diagram illustrating the anode initialization operation of the pixel circuit Pix(i,j) during the pause period TP, and shows the circuit state of the pixel circuit Pix(i,j) during the anode initialization period TAini in the pause period TP. Figure 17D is a circuit diagram illustrating the on-bias voltage application operation of the pixel circuit Pix(i,j) during the idle period TP, and shows the circuit state of the pixel circuit Pix(i,j) during the on-bias period Tob in the idle period TP.

[0086] In this embodiment, the corresponding light emission control line EMi, corresponding first scan signal line PSi, corresponding second scan signal line NSai, corresponding third scan signal line NSbi, and subsequent light emission control line EMi+X connected to the i-th row and j-th column pixel circuit 17, i.e., Pix(i,j), are driven as shown in Figure 16.

[0087] First, we will explain the driving of signal lines EMI, NSai, NSbi, PSi, and EMI+X during the driving period TD (RF frame period Trf).

[0088] The corresponding light emission control signal EM(i) changes from L level to H level at time t1, maintains the H level until time t8, and then changes to L level. As a result, the power supply control transistor T5 changes from the ON state to the OFF state at time t1 and maintains the OFF state until time t8. Furthermore, the subsequent light emission control signal EM(i+X), which is a light emission control signal given to Pix(i,j) via the subsequent light emission control line EMi+X, partially overlaps with the H level period of the corresponding light emission control signal EM(i), changing from L level to H level after time t1 and changing from H level to L level at time t9 after time t8. The light emission control transistor T6 is in the OFF state while the subsequent light emission control signal EM(i+X) is at the H level. Therefore, during the period t1 to t9 when either the corresponding light emission control signal EM(i) or the subsequent light emission control signal EM(i+X) is at the H level, no current flows to the organic EL element OL and the pixel circuit Pix(i,j) is in a non-light emission state.

[0089] The corresponding third scan signal NSb(i), which is the third scan signal supplied to the pixel circuit Pix(i,j) via the corresponding third scan signal line NSbi, is at an L level from before time t1. During the period when the corresponding light emission control signal EM(i) is at an H level and the subsequent light emission control signal EM(i+X) is at an L level, it is at an H level from time t2 to time t4, and changes to an L level at time t4. The corresponding second scan signal NSa(i), which is the second scan signal supplied to the pixel circuit Pix(i,j) via the corresponding second scan signal line NSai, has a period of being at an H level that partially overlaps with the period of being at an H level of the corresponding third scan signal NSb(i). It changes from an L level to an H level at time t3, maintains an H level until time t7, and then changes to an L level.

[0090] The corresponding first scan signal PS(i) supplied to the pixel circuit Pix(i,j) via the corresponding first scan signal line PSi is at an H level from before time t1, and during the period when the corresponding second scan signal NSa(i) is at an H level, the corresponding third scan signal NSb(i) is at an L level, and both the corresponding light emission control signal EM(i) and the subsequent light emission control signal EM(i+X) are at an H level, the PS(i) is at an L level from time t5 to time t6, and then changes to an H level.

[0091] Next, we will explain the driving of signal lines EMi, NSai, NSbi, PSi, and EMi+X during the pause period TP (NRF frame period Tnrf).

[0092] The corresponding light emission control line EMI and the subsequent light emission control line EMI+X are driven in the same way as during the idle period TP as during the drive period TD. During the period t10 to t16 when either the corresponding light emission control signal EM(i) or the subsequent light emission control signal EM(i+X) is at the H level, no current flows to the organic EL element OL and the pixel circuit Pix(i,j) is in a non-light-emitting state.

[0093] During the pause period TP, the corresponding second scan signal NSa(i) is maintained at an L level, but the corresponding third scan signal line NSbi is driven in the same way as during the drive period TD, and the corresponding third scan signal NSb(i) is at an H level between time t11 and time t12. In addition, the corresponding first scan signal PS(i) is at an L level between time t13 and time t14 during the period when the corresponding third scan signal NSb(i) is at an L level and both the corresponding light emission control signal EM(i) and the subsequent light emission control signal EM(i+X) are at an H level, and then changes to an H level.

[0094] The pixel circuit Pix(i,j) in this embodiment, driven by the corresponding light emission control signal EM(i), corresponding first scan signal PS(i), corresponding second scan signal NSa(i), corresponding third scan signal NSb(i), and subsequent light emission control signal EM(i+X) as shown in Figure 16, operates as follows during the anode initialization period TAini, gate voltage initialization period TGini, write period Twr, and light emission period Temp after the write period Twr, which are provided during the drive period TD.

[0095] The period from time t2 to time t4 is the anode initialization period TAini during the drive period TD of the pixel circuit Pix(i,j). During this anode initialization period TAini, as shown in Figure 16, the corresponding light emission control signal EM(i), the corresponding first scan signal PS(i), and the corresponding third scan signal NSb(i) are at the H level, and the subsequent light emission control signal EM(i+X) is at the L level. As a result, the pixel circuit Pix(i,j) enters the circuit state shown in Figure 17A, and a current path is formed from the anode electrode of the organic EL element OL through the light emission control transistor T6 and the initialization transistor T7 to the initialization voltage line Vini. This current path performs anode initialization in the same manner as in the first embodiment. Furthermore, the corresponding second scanning signal NSa(i) changes from an L level to an H level during the anode initialization period TAini, causing the threshold compensation transistor T2 to change from an off state to an on state and the gate voltage Vg of the drive transistor T4 to decrease. However, this operation of the threshold compensation transistor T2 does not substantially affect the anode initialization operation described above.

[0096] The period from time t3 to time t4 is the gate voltage initialization period TGini during the drive period TD of the pixel circuit Pix(i,j). During this gate voltage initialization period TGini, as shown in Figure 16, the corresponding light emission control signal EM(i), the corresponding first scan signal PS(i), the corresponding second scan signal NSa(i), and the corresponding third scan signal NSb(i) are at the H level, and the subsequent light emission control signal EM(i+X) is at the L level. Therefore, the pixel circuit Pix(i,j) enters the circuit state shown in Figure 17B, and a current path is formed from the node including the gate terminal of the drive transistor T4 to the initialization voltage line Vini via the threshold compensation transistor T2 and the initialization transistor T7, and gate voltage initialization is performed in the same manner as in the first embodiment. In this embodiment as well, the number of transistors included in this current path for gate voltage initialization is 2. In addition, during this gate voltage initialization period TGini, the light emission control transistor T6 is in the ON state, so anode initialization is also performed.

[0097] The period from time t4 to time t5 is the write period Twr during the drive period TD of the pixel circuit Pix(i,j). During this write period Twr, the corresponding light emission control signal EM(i), the subsequent light emission control signal EM(i+X), and the corresponding second scan signal NSa(i) are at the H level, while the corresponding first scan signal PS(i) and the corresponding third scan signal NSb(i) are at the L level. Therefore, the pixel circuit Pix(i,j) is in the same circuit state as the pixel circuit Pix(i,j) during the anode initialization period TAini in the first embodiment, as shown in Figure 9C. As a result, the voltage of the data signal line Dj is applied as the data voltage Vdata to the node including the gate terminal of the drive transistor T4 via the write control transistor T3, the drive transistor T4, and the threshold compensation transistor T2. Consequently, the threshold-compensated data voltage Vdata is written to the holding capacitor Cst.

[0098] After the end of the above-mentioned write period Twr, the subsequent light emission control signal EM(i+X) changes from H level to L level at time t9, and a new light emission period Tem begins. During this light emission period Tem, as shown in Figure 16, the corresponding light emission control signal EM(i), the subsequent light emission control signal EM(i+X), the corresponding second scan signal NSa(i), and the corresponding third scan signal NSb(i) are all at L level, while the corresponding first scan signal PS(i) is at H level. Therefore, this pixel circuit Pix(i,j) is in the same state as the pixel circuit Pix(i,j) in the light emission period Tem in the first embodiment, as shown in Figure 9D. As a result, a current I1 corresponding to the voltage held in the holding capacitor Cst flows from the high-level power line ELVDD through the power supply control transistor T5, the drive transistor T4, the light emission control transistor T6, and the organic EL element OL to the low-level power line ELVSS. In this case, the current I1 flowing through the organic EL element OL is given by equation (4) described above, as in the first embodiment, and does not depend on the threshold voltage Vth of the drive transistor T4. During the light emission period Tem from time t9 onward, the organic EL element OL emits light with a brightness corresponding to this current I1.

[0099] Next, the operation of the pixel circuit Pix(i,j) in this embodiment during the pause period TP will be described. In this embodiment, the pixel circuit Pix(i,j) operates as follows during the anode initialization period TAini, the on-bias period Tob, and the light emission period Temp after the on-bias period Tob, which are provided during the pause period TP.

[0100] The period from time t11 to time t12 is the anode initialization period TAini during the pause period TP of the pixel circuit Pix(i,j). During this anode initialization period TAini, as shown in Figure 16, the corresponding light emission control signal EM(i), the first scan signal PS(i), and the corresponding third scan signal NSb(i) are at the H level, while the corresponding second scan signal NSa(i) and the subsequent light emission control signal EM(i+X) are at the L level. As a result, the pixel circuit Pix(i,j) enters the circuit state shown in Figure 17C, forming a current path from the anode electrode of the organic EL element OL through the light emission control transistor T6 and the initialization transistor T7 to the initialization voltage line Vini. This current path performs anode initialization in the same way as the anode initialization period TAin in the first embodiment (see Figure 9A).

[0101] The period from time t13 to time t14 is the on-bias period Tob during the pause period TP of the pixel circuit Pix(i,j). During this on-bias period Tob, as shown in Figure 16, the corresponding light emission control signal EM(i) and the subsequent light emission control signal EM(i+X) are at the H level, while the corresponding first scan signal PS(i), the corresponding second scan signal NSa(i), and the corresponding third scan signal NSb(i) are at the L level. As a result, the pixel circuit Pix(i,j) is in the circuit state shown in Figure 17D. On the other hand, as previously described, during the pause period TP, the data-side drive circuit 30 applies an on-bias voltage Vob to each data signal line Dj in place of the data signal D(j) (see Figure 14). Therefore, during this on-bias period Tob, the voltage of the data signal line Di is applied as the on-bias voltage Vob to the source terminal, which is the first conductive terminal of the drive transistor T4, via the write control transistor T3.

[0102] After the end of the above-mentioned on-bias period Tob, the subsequent light emission control signal EM(i+X) changes from H level to L level at time t16, and a new light emission period Temp begins. During this light emission period Temp, as shown in Figure 16, similar to the light emission period Temp in the drive period TD, the corresponding light emission control signal EM(i), the subsequent light emission control signal EM(i+X), the corresponding second scan signal NSa(i), and the corresponding third scan signal NSb(i) are at L level, and the corresponding first scan signal PS(i) is at H level. Therefore, this pixel circuit Pix(i,j) is in the same state as the pixel circuit Pix(i,j) in the light emission period Temp in the first embodiment, as shown in Figure 9D. As a result, a current I1 corresponding to the voltage held by the holding capacitor Cst flows to the organic EL element OL, and the organic EL element OL emits light with a brightness corresponding to this current I1.

[0103] <3.4 Effects> According to this embodiment as described above, similar to the first embodiment (Figure 7), in the gate voltage initialization period TGini during the drive period TD, the gate voltage Vg of the drive transistor T4 is initialized in the pixel circuit 17 (Figure 15) by a current path including a threshold compensation transistor T2 and an initialization transistor T7. Here, the initialization transistor T7 is also used to form a current path for anode initialization during the anode initialization period TAini. As a result, the number of transistors included in the current path for gate voltage initialization is reduced by one compared to the comparative example, and the total number of transistors included in the pixel circuit 17 is the same as that of the pixel circuit 14b in the comparative example. Therefore, according to this embodiment, similar to the first embodiment, it is possible to provide a high-definition internal compensation type display device that suppresses a decrease in yield while improving brightness variations caused by insufficient charging during the gate voltage initialization period TGini. Furthermore, according to this embodiment, by performing a pause drive as shown in Figures 14 and 16, the power consumption of the display device can be reduced when displaying still images. Furthermore, in this pause drive, an on-bias voltage Vob is applied to the source terminal of the drive transistor T4 for each NRF frame period Tnrf within the pause period TP (Figures 14, 16, and 17D), thereby suppressing the occurrence of flicker caused by the hysteresis characteristics of the drive transistor T4.

[0104] <4. Fourth Embodiment> Next, a display device according to the fourth embodiment will be described. The display device according to this embodiment is an organic EL display device configured to enable idle operation, based on the display device according to the second embodiment (see Figures 10 to 11, etc.). In this embodiment as well, an internal compensation method is employed for threshold compensation, but the scanning-side signals for driving each pixel circuit 18 are one less than in the third embodiment (see Figures 15 and 16).

[0105] In this embodiment, the driving of each pixel circuit is similar to that of the pixel circuit 16 (pixel circuit Pix(i,j)) in the second embodiment, and in addition to the corresponding light emission control line EMI, which is the light emission control line corresponding to the pixel circuit Pix(i,j), a preceding light emission control line EMI-X, which is the light emission control line preceding the corresponding light emission control line EMI, is used. On the other hand, the second scan signal line NSi is not used to drive the pixel circuit 16 in the second embodiment, but in this embodiment, the second scan signal line NSi is used in addition to the first scan signal line PSi to drive the pixel circuit 18.

[0106] <4.1 Overall Configuration> Figure 18 is a block diagram showing the overall configuration of this embodiment. As described above, the overall configuration of this embodiment differs from that of the second embodiment, in that the display unit 11 is equipped with second scanning signal lines NS1 to NSn and n+2 light emission control lines EM-1, EM0, EM1 to EMn. Other parts of the overall configuration of this embodiment will be clear from the following description of this embodiment and will therefore be omitted. Hereinafter, the same reference numerals will be used for parts of the configuration of this embodiment that are the same as or correspond to the configuration of the second embodiment. Configurations and operations that are not newly described in this embodiment and subsequent descriptions are the same as those of the second embodiment. However, configurations and operations related to the pause drive among the configurations and operations that are not newly described in this embodiment and subsequent descriptions are the same as those of the third embodiment.

[0107] <4.2 General Operation> Figure 19 is a timing chart for illustrating the general operation of the display device 10c according to this embodiment.

[0108] The display device 10c according to this embodiment also has two operating modes, a normal drive mode and a pause drive mode, similar to the third embodiment described above. In the normal drive mode, the scanning drive circuit 40 drives the first scanning signal lines PS1 to PSn, the second scanning signal lines NS1 to NSn, and the light emission control lines EM-1 to EMn with the signals PS(1) to PS(n), NS(1) to NS(n), and EM(-1) to EM(n) shown in Figure 19 during the drive period TD, while the data drive circuit 30 generates data signals D(1) to D(m) that change in conjunction with the first scanning signals PS(1) to PS(n) and applies them to the data signal lines D1 to Dm, respectively. In this manner, when the first scan signal lines PS1 to PSn, the second scan signal lines NS1 to NSn, the light emission control lines EM-1 to EMn, and the data signal lines D1 to Dm in the display unit 11 are driven, similar to the second embodiment described above, during each refresh frame period Trf, initialization and data voltage writing are performed to each pixel circuit Pix(i,j) during the non-light emission period, and during the light emission period, each pixel circuit emits light with a brightness corresponding to the written data voltage. In the normal drive mode, such a refresh frame period Trf is repeated.

[0109] In contrast, in the idle drive mode, as shown in Figure 19, a drive period TD consisting of a refresh frame period (RF frame) Trf in which data writing operations are performed to write data voltages to each pixel circuit 17 as described above, and a idle period TP consisting of a plurality of non-refresh frame periods (NRF frames) Tnrf in which such data writing operations are stopped are alternately repeated. In the idle drive mode in this embodiment, during the idle period TP, the driving of the second scan signal lines NS1 to NSn by the scanning drive circuit 40 and the application of data signals D(1) to D(n) to the data signal lines D1 to Dm by the data drive circuit 30 are stopped, and the display of image data consisting of data voltages written to each pixel circuit 17 in the immediately preceding drive period TD (RF frame period Trf) continues. For this reason, the idle drive mode is effective in reducing the power consumption of the display device when displaying still images. Note that even during the NRF frame period Tnrf, the driving of the first scan signal lines PS1 to PSn and the light emission control lines EM-1 to EMn continues. Furthermore, during the NRF frame period Tnrf, an on-bias voltage Vob is applied to the data signal lines D1 to Dm in place of the data signals D(1) to D(m). Below, the operation of the display device 10c or its pixel circuit 18 in this embodiment will be described focusing on its operation in the idle drive mode.

[0110] <4.3 Pixel Circuit Configuration and Operation> Figure 20 is a circuit diagram showing the configuration of the pixel circuit 18, i.e., the i-th row, j-th column pixel circuit Pix(i,j), corresponding to the i-th first scan signal line PSi and the j-th data signal line Dj in this embodiment (1 ≤ i ≤ n, 1 ≤ j ≤ m). As can be seen by comparing Figure 20 with Figure 10, the configuration of the pixel circuit 18 in this embodiment is the same as the configuration of the pixel circuit 16 in the second embodiment described above, except for the signal lines for driving this pixel circuit 18.

[0111] As shown in Figure 20, in the i-th row, j-th column pixel circuit Pix(i,j) in this embodiment, the gate terminal of the threshold compensation transistor T2 is connected to the corresponding second scan signal line NSi, which is the second scan signal line corresponding to the pixel circuit Pix(i,j), unlike the pixel circuit 16 in the second embodiment (Figure 10). In this embodiment as well, the gate terminals of the second power supply control transistor T5b and the light emission control transistor T6 are connected to the corresponding light emission control signal line EMI, and the gate terminals of the first power supply control transistor T5a and the initialization transistor T7 are connected to the preceding light emission control signal line EMI-X. Here, in this embodiment as well, X is a positive integer and is selected so that the deactivation period of the preceding light emission control line EMI-X partially overlaps with the deactivation period of the corresponding light emission control line EMI (see Figure 21 below). X is preferably 1 or 2, and in this embodiment, X = 2 (see Figure 18).

[0112] Next, the operation of the pixel circuit 18 shown in Figure 20, that is, the i-th row, j-th column pixel circuit Pix(i,j) in this embodiment, will be explained with reference to Figures 21 and 22A to 22B. Figure 21 is a timing chart for explaining the operation of the pixel circuit Pix(i,j), showing the changes in the drive signal during the period in which data writing is performed in this pixel circuit Pix(i,j) and the periods before and after it during the drive period TD (RF frame period Trf), and also showing the changes in the drive signal during the period in which on-bias voltage is applied in this pixel circuit Pix(i,j) and the periods before and after it during the pause period TP (NRF frame period Tnrf). In this embodiment as well, in each frame period within the drive period TD, the RF frame period Trf is provided with the pixel circuit Pix(i,j) in the following order: anode initialization period TAini, gate voltage initialization period TGini, write period Twr, and light emission period Temp. During the write period Twr, threshold compensation is performed along with the writing of the data voltage within the pixel circuit Pix(i,j). In this embodiment, during the NRF frame period Tnrf, which is each frame period within the pause period TP, the pixel circuit Pix(i,j) is sequentially provided with an anode initialization period TAini, an on-bias period Tob, and an emission period Temp.

[0113] Figure 22A is a circuit diagram illustrating the anode initialization operation of the pixel circuit Pix(i,j) during the pause period TP, and shows the circuit state of the pixel circuit Pix(i,j) during the anode initialization period TAini during the pause period TP. Figure 22B is a circuit diagram illustrating the on-bias voltage application operation of the pixel circuit Pix(i,j) during the pause period TP, and shows the circuit state of the pixel circuit Pix(i,j) during the on-bias period Tob during the pause period TP.

[0114] In this embodiment, the corresponding light emission control line EMI, the preceding light emission control line EMI-X, the corresponding first scan signal line PSi, and the corresponding second scan signal line NSi connected to the i-th row and j-th column pixel circuit 18, i.e., Pix(i,j), are driven as shown in Figure 21. Here, the second scan signal NS(i) is a signal with the same waveform as the light emission control signal EM(i) during the drive period TD and is maintained at an L level during the pause period TP, but is not limited to this. The second scan signal NS(i) may have an H level period during the drive period TD that partially overlaps with the H level period of the preceding light emission control signal EM(i-X), remain at an H level while the first scan signal PS(i) is at an L level, and be maintained at an L level during the pause period TP.

[0115] As can be seen by comparing Figure 21 with Figure 11, the operation of the pixel circuit Pix(i,j) during the drive period TD in this embodiment is substantially the same as the operation of the pixel circuit 16 in the second embodiment. Therefore, in this embodiment as well, during the drive period TD, anode initialization, gate voltage initialization, and data writing operations are performed in the same way as the pixel circuit 16 in the second embodiment (see Figures 12A to 12D).

[0116] In this embodiment, during the pause period TP, as shown in Figure 21, the period t7 to t8, when the corresponding light emission control signal EM(i) is at the L level and the preceding light emission control signal EM(i-X) is at the H level, is the anode initialization period TAini. During this anode initialization period TAini, the pixel circuit Pix(i,j) is in the same circuit state as the pixel circuit 17 in the second embodiment during the anode initialization period TAini (Figure 12A), as shown in Figure 22A. As a result, a current path is formed from the anode electrode of the organic EL element OL through the light emission control transistor T6 and the initialization transistor T7 to the initialization voltage line Vini, and anode initialization is performed by this current path in the same manner as in the second embodiment.

[0117] Furthermore, during the pause period TP, the corresponding second scan signal NS(i) is at a low level, so the threshold compensation transistor T2 is kept in the off state. For this reason, during the period t10 to t11 when the corresponding first scan signal PS(i) is at a low level, even if the write control transistor T3 is turned on, no data writing operation is performed, and the voltage of the corresponding data signal line Dj is applied to the source terminal, which is the first conductive terminal of the drive transistor T4. This period t10 to t11 is the on-bias period Tob. Figure 22B shows the circuit state of the pixel circuit Pix(i,j) during this on-bias period Tob. During the pause period TP, an on-bias voltage Vob is applied to each data signal line D1 to Dm by the data-side drive circuit 30, so during this on-bias period Tob, as shown in Figure 22B, the voltage of the corresponding data signal line Dj is applied as the on-bias voltage Vob to the source terminal, which is the first conductive terminal of the drive transistor T4, via the write control transistor T3.

[0118] After the end of the above-mentioned on-bias period Tob, the corresponding light emission control signal EM(i) changes from H level to L level at time t12, and a new light emission period Temp begins. During this light emission period Temp, as shown in Figure 21, similar to the light emission period Temp in the drive period TD, the corresponding light emission control signal EM(i), the preceding light emission control signal EM(i-X), and the corresponding second scan signal NS(i) are at L level, and the corresponding first scan signal PS(i) is at H level. Therefore, this pixel circuit Pix(i,j) is in the same circuit state as the pixel circuit Pix(i,j) in the light emission period Temp in the second embodiment, as shown in Figure 12D. As a result, a current I1 corresponding to the voltage held by the holding capacitor Cst flows to the organic EL element OL, and the organic EL element OL emits light with a brightness corresponding to this current I1.

[0119] <4.4 Effects> According to this embodiment as described above, similar to the third embodiment, by using two transistors in the current path for gate voltage initialization in the pixel circuit 18 that performs internal compensation, brightness variations caused by insufficient charging during the gate voltage initialization period TGini are improved, and the power consumption of the display device is reduced when displaying still images by sleep drive. In addition, by applying an on-bias voltage Vob to the source terminal of the drive transistor T4 for each NRF frame period Tnrf within the sleep period TP in this sleep drive (Figures 19, 21, and 22B), the occurrence of flicker caused by the hysteresis characteristics of the drive transistor T4 is suppressed. Moreover, in this embodiment, the scanning-side drive signals for driving each pixel circuit P(i,j) are the first scanning signal PS(i), the second scanning signal NS(i), and the light emission control signals EM(i) and EM(i-X), which is one less scanning-side drive signal compared to the pixel circuit 17 in the third embodiment (Figure 15). This is advantageous in reducing the size of the scanning drive circuit 40 and narrowing the bezel of the display device, and also contributes to higher resolution displays and improved yield during manufacturing.

[0120] <5. Fifth Embodiment> <5.1 Configuration of Display Device and Pixel Circuit> Next, a display device according to the fifth embodiment will be described. The display device according to this embodiment is also an internally compensated organic EL display device, and uses a pixel circuit 19 configured as shown in Figure 23. The display device according to this embodiment differs from the display device according to the first embodiment (Figures 1 and 3) in that all transistors included in the pixel circuit 19 are P-type, and accordingly, the signal lines for driving the pixel circuit 19 differ somewhat between the two embodiments. However, since the display device according to this embodiment basically has the same configuration as the display device according to the first embodiment, the same or corresponding parts will be denoted by the same reference numerals. Configurations and operations that are not newly described in the following embodiments are the same as those of the first embodiment.

[0121] As can be seen by comparing Figure 23 with Figure 7, in the pixel circuit 15 of the first embodiment, the threshold compensation transistor T2 and the initialization transistor T7 are N-type, whereas in the pixel circuit 19 of this embodiment, both transistors T2 and T7 are P-type. Accordingly, in the i-th row j-th column pixel circuit 19, i.e., Pix(i,j), unlike the pixel circuit 15 of the first embodiment, the gate terminal of the threshold compensation transistor T2 is connected to the second scan signal line PSbi, which transmits the negative logic (active low) second scan signal PSb(i), instead of the second scan signal line NSi, which transmits the positive logic (active high) second scan signal NS(i). Similarly, the gate terminal of the initialization transistor T7 is connected to the preceding second scan signal line PSbi-X, which transmits the negative logic preceding second scan signal PSb(i-X), instead of the preceding second scan signal line NSi-X, which transmits the positive logic preceding second scan signal NS(i-X). Here, X is a positive integer, and is selected such that the selection period of the preceding second scan signal line PSbi-X partially overlaps with the selection period of the corresponding second scan signal line PSbi. X is preferably 1 or 2, and in the example shown in Figure 24, X = 2. In addition, in the pixel circuit Pix(i,j) in this embodiment, the gate terminal of the light emission control transistor T6 is connected to the subsequent light emission control line EMi+Y, which transmits the subsequent light emission control signal EM(i+Y), instead of the second scan signal line NSi, which transmits the second scan signal NS(i). Here, Y is a positive integer such that Y > X, and is selected such that the deactivation period of the subsequent light emission control line EMi+Y partially overlaps with the deactivation period of the corresponding light emission control line EMi and also partially overlaps with the selection period of the corresponding second scan signal line PSbi, for example, Y = 5. In this embodiment, the first scanning signal PSa(i) provided to the gate terminal of the write control transistor T3 via the first scanning signal line PSai in the pixel circuit Pix(i,j) is substantially the same as the first scanning signal PS(i) provided via the first scanning signal line PSai in the pixel circuit 15 in the first embodiment (see Figure 8 and Figure 24 described later).

[0122] In this embodiment, corresponding to the above-mentioned drive signals connected to the pixel circuit Pix(i,j), unlike the display unit 11 in the first embodiment (see Figure 1), the display unit 11 in this embodiment is provided with n first scan signal lines PSa1 to PSan instead of n first scan signal lines PS1 to PSn, n+2 second scan signal lines PSb-1, PSb0, PSb1 to PSbn instead of n+2 second scan signal lines NS-1, NS0, NS1 to PSn, and n+5 light emission control lines EM1 to EMn+5 instead of n light emission control lines EM1 to EMn (X=2, Y=5).

[0123] In this embodiment, the scanning-side drive circuit 40, as a scanning signal line drive circuit, sequentially selects n first scanning signal lines PSa1 to PSan for predetermined periods corresponding to one horizontal period, and sequentially selects n+2 second scanning signal lines PSb-1 to PSbn for predetermined periods corresponding to one horizontal period, based on the scanning-side control signal Scs during each frame period. It applies an L-level signal as an active signal to the selected first scanning signal line PSak (1 ≤ k ≤ n) and an L-level signal as an active signal to the selected second scanning signal line PSbk (-1 ≤ k ≤ n). On the other hand, it applies an H-level signal as an inactive signal to the unselected first scanning signal line PSai and an H-level signal as an inactive signal to the unselected second scanning signal line PSbi.

[0124] Furthermore, the scanning-side drive circuit 40 drives the light emission control lines EM1 to EMn+5 in each frame period so that they are selectively deactivated in conjunction with the driving of the first scanning signal lines PSa1 to PSan and the second scanning signal lines PSb-1 to PSbn. That is, the scanning-side drive circuit 40, as a light emission control circuit, applies an H-level signal to the i-th light emission control line EMI as a light emission control signal indicating no light emission during a predetermined period including the i-th horizontal period, and applies an L-level signal as a light emission control signal indicating light emission during other periods (i = 1 to n+5). The scanning-side drive circuit 40 also drives n+5 light emission control lines EM1 to EMn+5 such that the period during which the light emission control line EMI is inactive and the period during which the subsequent light emission control line EMI+5 is inactive partially overlap (i = 1 to n, Y = 5).

[0125] <5.2 Operation of Pixel Circuits> Next, the operation of the pixel circuit 19 shown in Figure 23, that is, the i-th row, j-th column pixel circuit Pix(i,j) in this embodiment, will be explained with reference to Figure 24. Figure 24 is a timing chart for explaining the operation of the pixel circuit Pix(i,j), and shows the changes in the drive signal during the period in which data writing is performed in this pixel circuit Pix(i,j) and the periods before and after. In this embodiment as well, for each pixel circuit Pix(i,j), an anode initialization period TAini, a gate voltage initialization period TGini, a writing period Twr, and an emission period Temp are provided in order for each frame period. During the writing period Twr, threshold compensation is performed in the pixel circuit Pix(i,j) along with the writing of the data voltage.

[0126] In this embodiment, the pixel circuit 19 in the i-th row and j-th column (Figure 23), also known as the pixel circuit Pix(i,j), differs from the pixel circuit 15 in the first embodiment (Figure 7) in that the threshold compensation transistor T2 and the initialization transistor T7 are of type P. Considering this, as can be seen by comparing Figure 24 with Figure 8, the on / off states of the transistors T2, T3, T5-T7 as switching elements within the pixel circuit during the anode initialization period TAini, the gate voltage initialization period TGini, the write period Twr, and the light emission period Tem are the same as in the first embodiment.

[0127] In other words, in this embodiment as well, during the anode initialization period TAini, the pixel circuit Pix(i,j) is in the circuit state shown in Figure 9A, and a current path is formed from the anode electrode of the organic EL element OL to the initialization voltage line Vini via the light emission control transistor T6 and the initialization transistor T7. Anode initialization is performed by this current path, similar to the first embodiment described above. Furthermore, during the gate voltage initialization period TGini, the pixel circuit Pix(i,j) is in the circuit state shown in Figure 9B, and a current path is formed from the node including the gate terminal of the drive transistor T4 to the initialization voltage line Vini via the threshold compensation transistor T2 and the initialization transistor T7. Gate voltage initialization is performed by this current path, similar to the first embodiment described above. In the subsequent write period Twr, the pixel circuit Pix(i,j) is in the circuit state shown in Figure 9C, and the voltage of the data signal line Dj is supplied as the data voltage Vdata to the node including the gate terminal of the drive transistor T4 via the write control transistor T3, the drive transistor T4, and the threshold compensation transistor T2. As a result, the threshold-compensated data voltage Vdata is written to the holding capacitor Cst. During the subsequent light emission period Temp, the pixel circuit Pix(i,j) enters the circuit state shown in Figure 9D, and a current I1 corresponding to the voltage held in the holding capacitor Cst flows from the high-level power line ELVDD through the power supply control transistor T5, the drive transistor T4, the light emission control transistor T6, and the organic EL element OL to the low-level power line ELVSS. Consequently, during the light emission period Temp after time t9, the organic EL element OL emits light with a brightness corresponding to the data voltage Vdata, which is the voltage of the corresponding data signal line Dj during the writing period Twr, regardless of the threshold voltage Vth of the drive transistor T4.

[0128] <5.3 Effects> According to this embodiment as described above, by configuring all transistors in the pixel circuit to be P-type, an internally compensated display device using a pixel circuit with fewer transistors than conventional devices is realized. By using two transistors in the current path for gate voltage initialization in the pixel circuit, insufficient charging during the gate voltage initialization period TGini is prevented. As a result, similar to the first embodiment, it is possible to provide a high-definition internally compensated display device with improved brightness variation while suppressing a decrease in manufacturing yield.

[0129] <6. Modifications> The present invention is not limited to the embodiments described above, and various modifications can be made without departing from the scope of the present invention.

[0130] For example, in each of the embodiments described above, the gate voltage initialization period TGini is provided after the anode initialization period TAini during the refresh frame period (see Figures 8 and 11, etc.), but the gate voltage initialization period TGini may be provided before the anode initialization period TAini, and part or all of the anode initialization period TAini and the gate voltage initialization period TGini may overlap.

[0131] Furthermore, in each of the above embodiments, the threshold compensation transistor T2 is in the off state during the anode initialization period TAini (see Figures 9A, 12A, etc.). However, assuming that data voltage writing is performed after anode initialization, the threshold compensation transistor T2 may be in the on state during the anode initialization period TAini in the refresh frame period. However, during the anode initialization period TAini in the non-refresh frame period (pause period TP), the threshold compensation transistor T2 must be in the off state so that the gate voltage Vg of the drive transistor T4 is maintained. Also, in each of the above embodiments, the light emission control transistor T6 is in the off state during the gate voltage initialization period TGini, but it may be in the on state.

[0132] Furthermore, any combination of the first to fifth embodiments and their variations can be used, provided that it does not contradict the spirit of the present invention and is not technically inconsistent.

[0133] In the above, each embodiment and its modifications have been described using an organic EL display device as an example. However, the present invention is not limited to organic EL display devices, but can be applied to any display device using an internal compensation method that uses a display element driven by electric current. The display elements that can be used here are display elements whose brightness or transmittance is controlled by electric current. For example, in addition to organic EL elements, i.e., organic light-emitting diodes (OLEDs), inorganic light-emitting diodes and quantum dot light-emitting diodes (QLEDs) can be used.

[0134] 10, 10b, 10c... Organic EL display device 11... Display unit 15, 16, 17, 18, 19... Pixel circuit 20... Display control circuit 30... Data side drive circuit (data signal line drive circuit) 40... Scan side drive circuit (scan signal line drive / light emission control circuit) Pix(i,j)... Pixel circuit (i=1 to n, j=1 to m) Dj... Data signal line (j=1 to m) PSi... First scan signal line (i=1 to n) NSi, NSai... Second scan signal line (i=1 to n) NSbi... Third scan signal line (i=1 to n) EMI... Light emission control line (i=1 to n) ELVDD... High-level power line (first power line), high-level power voltage ELVSS... Low-level power line (second power line), low-level power voltage Vini... Initialization voltage line (initialization voltage) OL ...Organic EL element (display element) Cst...Holding capacitor T2...Threshold compensation transistor (threshold compensation switching element) T3...Write control transistor (write control switching element) T4...Drive transistor T5...Power supply control transistor (power supply control switching element) T6...Light emission control transistor (light emission control switching element) T7...Initialization transistor (initialization switching element) Trf...Refresh frame period (RF frame period) Tnrf...Non-refresh frame period (NRF frame period) TAini...Anode initialization period (display element initialization period) TGini...Gate voltage initialization period (write voltage initialization period) Twr...Write period Tob...On-bias period Temp...Light emission period TD...Drive period TP...Hibernation period Vob...On-bias voltage

Claims

1. A display unit comprising a plurality of pixel circuits, a plurality of data signal lines, and an initialization voltage line, and a drive circuit for driving the plurality of pixel circuits, each of the plurality of pixel circuits comprising a display element driven by current, a drive transistor, a holding capacitor, a write control switching element, a threshold compensation switching element, a light emission control switching element, and an initialization switching element, the drive transistor having a first conductive terminal connected to one of the plurality of data signal lines via the write control switching element, a second conductive terminal connected to the display element via the light emission control switching element and connected to the initialization voltage line via the initialization switching element, and a control terminal connected to a fixed voltage line via the holding capacitor and connected to the second conductive terminal via the threshold compensation switching element, A display device comprising: a light emission period for each of the plurality of pixel circuits in which the display element is made to emit light in accordance with the voltage held in the holding capacitor; a write period for writing the voltage of one data signal line to the holding capacitor as a data voltage during periods other than the light emission period; a write voltage initialization period for initializing the voltage of the control terminal of the drive transistor before the write period during periods other than the light emission period; and a display element initialization period for initializing the display element during periods other than the light emission period, wherein the drive circuit drives the plurality of pixel circuits in such a way that during the display element initialization period a current path is formed from the display element to the initialization voltage line via the light emission control switching element and the initialization switching element; during the write voltage initialization period a current path is formed from the control terminal of the drive transistor to the initialization voltage line via the threshold compensation switching element and the initialization switching element; and during the write period the voltage of one data signal line is written to the holding capacitor via the write control switching element, the drive transistor and the threshold compensation switching element.

2. The display unit further includes a first power line and a second power line, each of the plurality of pixel circuits further includes a first power supply control switching element, the display element has a first terminal connected to the second conductive terminal of the drive transistor via the light emission control switching element, and a second terminal connected to the second power line, the first conductive terminal of the drive transistor is connected to the first power line via the first power supply control switching element, The display device according to claim 1, wherein the drive circuit drives the plurality of pixel circuits such that, during the display element initialization period, the light emission control switching element and the initialization switching element are ON and the write control switching element and the first power supply control switching element are OFF; during the write voltage initialization period, the threshold compensation switching element and the initialization switching element are ON and the write control switching element and the first power supply control switching element are OFF; and during the write period, the write control switching element and the threshold compensation switching element are ON and the first power supply control switching element, the light emission control switching element and the initialization switching element are OFF.

3. The display unit further includes a plurality of first scan signal lines, a plurality of second scan signal lines, and a plurality of light emission control lines; the drive circuit includes a data-side drive circuit that generates a plurality of data signals and applies them to the plurality of data signal lines, and a scan-side drive circuit that selectively drives the plurality of first scan signal lines, selectively drives the plurality of second scan signal lines, and selectively deactivates the plurality of light emission control lines; the threshold compensation switching element and the light emission control switching element are transistors of different conductivity types; the threshold compensation switching element and the initialization switching element are transistors of the same conductivity type; in each of the plurality of pixel circuits, the write control switching element has a control terminal connected to one of the plurality of first scan signal lines; the threshold compensation switching element and the light emission control switching element both have a control terminal connected to one of the plurality of second scan signal lines; and the first power supply control switching element has a control terminal connected to one of the plurality of light emission control lines. The display device according to claim 2, wherein the initialization switching element has a control terminal connected to a preceding second scan signal line whose selection is initiated before the one second scan signal line, and the preceding second scan signal line is a second scan signal line selected from the plurality of second scan signal lines such that its selection is initiated before the one second scan signal line and the selection period of the one second scan signal line and the selection period of the preceding second scan signal line partially overlap.

4. The display unit further includes a plurality of first scanning signal lines and a plurality of light emission control lines, the drive circuit includes a data-side drive circuit that generates a plurality of data signals and applies them to the plurality of data signal lines, and a scanning-side drive circuit that selectively drives the plurality of first scanning signal lines and selectively deactivates the plurality of light emission control lines, each of the plurality of pixel circuits further includes a second power supply control switching element connected in series with the first power supply control switching element, the first power supply control switching element, the second power supply control switching element, and the light emission control switching element are transistors of the same conductivity type, the threshold compensation switching element and the second power supply control switching element are transistors of different conductivity types, the initialization switching element and the first power supply control switching element are transistors of different conductivity types, and in each of the plurality of pixel circuits, the first conductive terminal of the drive transistor is connected to the first power line via the first power supply control switching element and the second power supply control switching element. The display device according to claim 2, wherein the write control switching element has a control terminal connected to one of the plurality of first scan signal lines, the threshold compensation switching element, the second power supply control switching element, and the light emission control switching element each have a control terminal connected to one of the plurality of light emission control lines, the initialization switching element and the first power supply control switching element each have a control terminal connected to a preceding light emission control line which is deactivated before the one light emission control line, and the preceding light emission control line is a light emission control line selected from the plurality of light emission control lines such that it is deactivated before the one light emission control line and the deactivation period of the one light emission control line and the deactivation period of the preceding light emission control line partially overlap.

5. The display unit further includes a plurality of first scan signal lines, a plurality of second scan signal lines, a plurality of third scan signal lines, and a plurality of light emission control lines, the drive circuit includes a data-side drive circuit that generates a plurality of data signals and applies them to the plurality of data signal lines, and a scan-side drive circuit that selectively drives the plurality of first scan signal lines, selectively drives the plurality of second scan signal lines, selectively drives the plurality of third scan signal lines, and selectively deactivates the plurality of light emission control lines, the first power supply control switching element and the light emission control switching element are transistors of the same conductivity type, in each of the plurality of pixel circuits, the write control switching element has a control terminal connected to one of the plurality of first scan signal lines, the threshold compensation switching element has a control terminal connected to one of the plurality of second scan signal lines, and the initialization switching element has a control terminal connected to one of the plurality of third scan signal lines. The display device according to claim 2, wherein the light emission control switching element has a control terminal connected to a subsequent light emission control line which is deactivated after one of the plurality of light emission control lines, the first power supply control switching element has a control terminal connected to the one light emission control line, and the subsequent light emission control line is a light emission control line selected from the plurality of light emission control lines such that it is deactivated after the one light emission control line and the deactivation period of the one light emission control line and the deactivation period of the subsequent light emission control line partially overlap.

6. The display unit further includes a plurality of first scanning signal lines, a plurality of second scanning signal lines, and a plurality of light emission control lines; the drive circuit includes a data-side drive circuit that generates a plurality of data signals and applies them to the plurality of data signal lines, and a scanning-side drive circuit that selectively drives the plurality of first scanning signal lines, selectively drives the plurality of second scanning signal lines, and selectively deactivates the plurality of light emission control lines; each of the plurality of pixel circuits further includes a second power supply control switching element connected in series with the first power supply control switching element; the first power supply control switching element, the second power supply control switching element, and the light emission control switching element are transistors of the same conductivity type; the initialization switching element and the first power supply control switching element are transistors of different conductivity types; and in each of the plurality of pixel circuits, the first conductive terminal of the drive transistor is connected to the first power line via the first power supply control switching element and the second power supply control switching element. The display device according to claim 2, wherein the write control switching element has a control terminal connected to one of the plurality of first scan signal lines, the threshold compensation switching element has a control terminal connected to one of the plurality of second scan signal lines, the light emission control switching element and the second power supply control switching element each have a control terminal connected to one of the plurality of light emission control lines, the initialization switching element and the first power supply control switching element each have a control terminal connected to a preceding light emission control line which is deactivated before the one light emission control line, and the preceding light emission control line is a light emission control line selected from the plurality of light emission control lines such that it is deactivated before the one light emission control line and the deactivation period of the one light emission control line and the deactivation period of the preceding light emission control line partially overlap.

7. A display device according to claim 5 or 6, further comprising a display control circuit that controls the data-side drive circuit and the scanning-side drive circuit so that a drive period consisting of one or more refresh frame periods for writing the voltages of the plurality of data signals as data voltages to the plurality of pixel circuits and a pause period consisting of one or more non-refresh frame periods for stopping the writing of data voltages to the plurality of pixel circuits alternate, wherein the display control circuit controls the data-side drive circuit and the scanning-side drive circuit so that for each of the plurality of pixel circuits, each refresh frame period includes the display element initialization period, the write voltage initialization period, the write period, and the light emission period, and for each of the plurality of pixel circuits, the data-side drive circuit and the scanning-side drive circuit are controlled so that each non-refresh frame period does not include either the write period or the write voltage initialization period, but does include the light emission period, by maintaining one second scan signal line in a non-selected state.

8. The display device according to claim 7, wherein the display control circuit controls the data-side drive circuit and the scanning-side drive circuit for each of the plurality of pixel circuits, such that during each non-refresh frame period, the write control switching element is turned on during periods other than the light emission period, thereby applying the voltage of one data signal line as an on-bias voltage to the first conductive terminal of the drive transistor.

9. The display device according to claim 7 or 8, wherein the display control circuit controls the scanning drive circuit such that the display element initialization period is included in the period other than the light emission period in each non-refresh frame period, and the threshold compensation switching element is in the off state during the display element initialization period in the non-refresh frame period.

10. The display unit further includes a plurality of first scan signal lines, a plurality of second scan signal lines, and a plurality of light emission control lines, the drive circuit includes a data-side drive circuit that generates a plurality of data signals and applies them to the plurality of data signal lines, and a scan-side drive circuit that selectively drives the plurality of first scan signal lines, selectively drives the plurality of second scan signal lines, and selectively deactivates the plurality of light emission control lines, the drive transistor, the write control switching element, the threshold compensation switching element, the first power supply control switching element, the light emission control switching element, and the initialization switching element are all P-channel type transistors, in each of the plurality of pixel circuits, the write control switching element has a control terminal connected to one of the plurality of first scan signal lines, the threshold compensation switching element has a control terminal connected to one of the plurality of second scan signal lines, and the first power supply control switching element has a control terminal connected to one of the plurality of light emission control lines. The display device according to claim 2, wherein the light emission control switching element has a control terminal connected to a subsequent light emission control line whose deactivation starts after the first light emission control line, the initialization switching element has a control terminal connected to a preceding second scan signal line whose selection starts before the first second scan signal line, the subsequent light emission control line is a light emission control line selected from the plurality of light emission control lines such that its deactivation starts after the first light emission control line and the deactivation period of the first light emission control line and the deactivation period of the subsequent light emission control line partially overlap, and the preceding second scan signal line is a second scan signal line selected from the plurality of second scan signal lines such that its selection starts before the first second scan signal line and the selection period of the first second scan signal line and the selection period of the preceding second scan signal line partially overlap.

11. The display device according to any one of claims 2 to 6 and 10, wherein the drive circuit drives the plurality of pixel circuits such that, during the light emission period, the first power supply control switching element and the light emission control switching element are in the ON state and the write control switching element, the threshold compensation switching element and the initialization switching element are in the OFF state.

12. The display device according to any one of claims 1 to 6, wherein the drive transistor is a P-channel type transistor and the threshold compensation switching element is an N-channel type transistor.

13. A display device according to claim 1 or 2, further comprising a display control circuit that controls the drive circuit such that a drive period consisting of one or more refresh frame periods for writing the voltages of a plurality of data signals as data voltages to the plurality of pixel circuits alternates with a pause period consisting of one or more non-refresh frame periods for stopping the writing of data voltages to the plurality of pixel circuits, wherein the display control circuit controls the drive circuit such that for each of the plurality of pixel circuits, each refresh frame period includes the display element initialization period, the write voltage initialization period, the write period, and the light emission period, and for each of the plurality of pixel circuits, the drive circuit is controlled such that each non-refresh frame period does not include the write period or the write voltage initialization period, but does include the light emission period, by keeping the threshold compensation switching element in the off state.

14. The display device according to claim 13, wherein the display control circuit controls the drive circuit for each of the plurality of pixel circuits such that, during each non-refresh frame period, the write control switching element is turned on during periods other than the light emission period, thereby applying the voltage of one data signal line as an on-bias voltage to the first conductive terminal of the drive transistor.

15. The display device according to claim 13 or 14, wherein the display control circuit controls the drive circuit such that the display element initialization period is included in the period other than the light emission period in each non-refresh frame period, and the threshold compensation switching element is in the off state during the display element initialization period in the non-refresh frame period.

16. A method for driving a display device using a display element driven by an electric current, wherein the display device comprises a display unit including a plurality of pixel circuits, a plurality of data signal lines, and an initialization voltage line, each of the plurality of pixel circuits includes a display element driven by an electric current, a drive transistor, a holding capacitor, a write control switching element, a threshold compensation switching element, a light emission control switching element, and an initialization switching element, the drive transistor having a first conductive terminal connected to one of the plurality of data signal lines via the write control switching element, a second conductive terminal connected to the display element via the light emission control switching element and connected to the initialization voltage line via the initialization switching element, and a control terminal connected to a fixed voltage line via the holding capacitor and connected to the second conductive terminal via the threshold compensation switching element. Each of the plurality of pixel circuits is provided with a light emission period for emitting light in accordance with the voltage held by the holding capacitor, a write period for writing the voltage of one data signal line to the holding capacitor as a data voltage during periods other than the light emission period, a write voltage initialization period for initializing the voltage of the control terminal of the drive transistor before the write period during periods other than the light emission period, and a display element initialization period for initializing the display element during periods other than the light emission period, the driving method includes the steps of: driving the plurality of pixel circuits during the display element initialization period such that a current path is formed from the display element to the initialization voltage line via the light emission control switching element and the initialization switching element; and driving the plurality of pixel circuits during the write voltage initialization period such that a current path is formed from the control terminal of the drive transistor to the initialization voltage line via the threshold compensation switching element and the initialization switching element.A driving method comprising the step of driving the plurality of pixel circuits such that, during the writing period, the voltage of one data signal line is written as a data voltage to the holding capacitor via the write control switching element, the drive transistor, and the threshold compensation switching element.

17. The driving method according to claim 16, further comprising a pause driving step of driving the plurality of pixel circuits such that a driving period consisting of one or more refresh frame periods for writing the voltages of a plurality of data signals as data voltages to the plurality of pixel circuits alternates with a pause period consisting of one or more non-refresh frame periods for stopping the writing of data voltages to the plurality of pixel circuits, wherein the pause driving step includes: driving the plurality of pixel circuits such that each refresh frame period includes the display element initialization period, the write voltage initialization period, the write period, and the light emission period; and driving the plurality of pixel circuits such that each non-refresh frame period does not include the write period and the write voltage initialization period, but does include the light emission period, by keeping the threshold compensation switching element in the off state.

18. The driving method according to claim 17, wherein the pause driving step further includes driving each of the plurality of pixel circuits such that, during each non-refresh frame period, the write control switching element is turned on during periods other than the light emission period, thereby applying the voltage of one data signal line as an on-bias voltage to the first conductive terminal of the driving transistor.

19. The driving method according to claim 17 or 18, wherein the pause driving step further includes driving the plurality of pixel circuits such that the display element initialization period is included in each non-refresh frame period other than the light emission period, and the threshold compensation switching element is in the off state during the display element initialization period in the non-refresh frame period.

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