Semiconductor device and method for manufacturing semiconductor device

Abstract

The purpose of the present invention is to provide a feature enabling the reliability of semiconductor devices to be enhanced. This semiconductor device comprises: a substrate on the upper surface of which a metal pattern is provided; a semiconductor element that is electrically connected to the metal pattern; and an electrode that has a protruding portion protruding upward and that is bonded onto the metal pattern. A bonding portion where the metal pattern and the electrode are bonded and a non-bonding portion where the metal pattern and the electrode are not bonded are provided between the metal pattern and the electrode. The non-bonding portion is provided below the protruding portion, and a side end portion of the non-bonding portion has roundness in a cross-sectional view.

Description

Semiconductor device and method for manufacturing a semiconductor device

[0001] This disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device.

[0002] Various technologies have been proposed for bonding semiconductor devices. For example, ultrasonic bonding, which mechanically joins components to be bonded together, is known as a bonding technology for semiconductor devices, as described in Patent Document 1. In ultrasonic bonding, the joint that joins the components to be bonded together is formed from the components themselves without the need for solder or other materials, so ultrasonic bonding is considered an effective bonding method for reducing costs.

[0003] Japanese Patent Publication No. 2003-9507

[0004] However, when stress is generated due to thermal deformation in a joint formed by ultrasonic bonding, sharp, wedge-shaped cracks may form in the joint. In such cases, the crack propagates from the wedge shape, reducing the delamination resistance of the joint and lowering the reliability of the semiconductor device.

[0005] Therefore, this disclosure has been made in view of the above-mentioned problems, and aims to provide a technology that can improve the reliability of semiconductor devices.

[0006] The semiconductor device according to this disclosure comprises a substrate having a metal pattern on its upper surface, a semiconductor element electrically connected to the metal pattern, and an electrode having a protruding portion that protrudes upward and is bonded to the metal pattern, wherein a bonding portion is provided between the metal pattern and the electrode where the metal pattern and the electrode are bonded, and a non-bonding portion is provided between the metal pattern and the electrode where the metal pattern and the electrode are not bonded, the non-bonding portion is provided below the protruding portion, and in cross-sectional view the side end of the non-bonding portion is rounded.

[0007] According to this disclosure, the non-joint portion is provided below the protruding portion, and in cross-sectional view, the side edge of the non-joint portion is rounded. With such a configuration, the reliability of the semiconductor device can be improved.

[0008] The purpose, features, aspects, and advantages of this disclosure will become clearer from the following detailed description and accompanying drawings.

[0009] Figure 1 is a cross-sectional view showing an example of the configuration of a semiconductor device according to Embodiment 1. Figure 2 is an enlarged cross-sectional view showing a part of the configuration of the semiconductor device according to Embodiment 1. Figure 3 is an enlarged cross-sectional view showing a part of the configuration of the semiconductor device according to Embodiment 1. Figure 4 is a diagram showing the relationship between c / d and α.

[0010] The embodiments will be described below with reference to the attached drawings. The features described in each of the embodiments below are illustrative, and not all features are necessarily required. In addition, in the descriptions below, the same or similar reference numerals are used for similar components in multiple embodiments, and the different components are mainly described. Also, in the descriptions below, specific positions and directions such as "top," "bottom," "left," "right," "front," or "back" do not necessarily have to coincide with the positions and directions in actual implementation.

[0011] <Embodiment 1> Figure 1 is a cross-sectional view showing an example of the configuration of a semiconductor device according to this embodiment 1, and Figure 2 is a cross-sectional view showing an enlarged view of the portion enclosed by the dotted line in Figure 1. Figure 3 is a cross-sectional view showing an enlarged view of the area around the side end of the non-jointed portion 12 in Figure 2.

[0012] The semiconductor device shown in Figure 1 constitutes, for example, a motor control device and a power converter used in electric railway trains and automobiles. The semiconductor device shown in Figure 1 comprises an insulating substrate 1 which is a substrate, a base plate 2, solder 3, a semiconductor chip 4 which is a semiconductor element, electrodes 5, wires 6, a case 7, a sealing member 8, and a lid 9.

[0013] As shown in Figure 2, metal patterns 1a and 1b are provided on the upper and lower surfaces of the insulating substrate 1, respectively. The metal patterns 1a and 1b are, for example, copper patterns. The base plate 2 is joined to the metal pattern 1b provided on the lower surface of the insulating substrate 1 with solder 3. Note that in Figure 1, for the sake of simplicity, the metal pattern 1b provided on the lower surface is not shown.

[0014] The semiconductor chip 4 in Figure 1 is electrically connected to a metal pattern 1a provided on the upper surface of the insulating substrate 1. The semiconductor chip 4 may be directly connected to the metal pattern 1a, or it may be connected to the metal pattern 1a via a wire 6 or the like, as long as it is electrically connected to the metal pattern 1a.

[0015] The semiconductor chip 4 includes, for example, at least one of MOSFET (Metal Oxide Semiconductor Field Effect Transistor), IGBT (Insulated Gate Bipolar Transistor), RC-IGBT (Reverse Conducting-IGBT), SBD (Schottky Barrier Diode), and PND (PN junction diode). In this specification, for example, at least one of A, B, C, ..., and Z means any one of all combinations that can be obtained by selecting one or more from the groups A, B, C, ..., and Z.

[0016] The semiconductor chip 4 may be made of ordinary silicon (Si), or silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga ２ O ３ ), or it may be composed of a wide-bandgap semiconductor such as diamond. When the semiconductor chip 4 is composed of a wide-bandgap semiconductor, stable operation at high temperatures and high voltages, and faster switching speeds become possible in the semiconductor chip 4.

[0017] As shown in Figures 1 and 2, the electrode 5 is bonded to the metal pattern 1a. The electrode 5 is, for example, a copper electrode with a nickel coating, and laser bonding is used to bond the metal pattern 1a and the electrode 5. As shown in Figures 1 and 2, the electrode 5 has a protruding portion 5a that extends upward. In the example of Figure 1, the upper part of the protruding portion 5a is bent as appropriate and provided on the outside of the case 7.

[0018] The wire 6 electrically connects the metal patterns 1a to each other, the semiconductor chips 4 to each other, and the metal patterns 1a to the semiconductor chips 4. The case 7 and base plate 2 constitute a housing with an opening at the top. The space inside the housing contains an insulating substrate 1, solder 3, semiconductor chips 4, part of the electrodes 5, the wire 6, and a sealing member 8. The sealing member 8 is made of, for example, gel and seals the space inside the housing. The lid 9 covers the opening provided at the top of the housing.

[0019] Now, as a reliability test for semiconductor devices such as power modules, a temperature cycle test is known in which the ambient temperature of the semiconductor device is alternately changed between high and low temperatures. When such a temperature cycle test is performed on the above semiconductor device, stress is applied to the joint between the metal pattern 1a and the electrode 5, as shown by the arrow in Figure 2. The protrusion 5a makes it difficult for stress to escape, so the joint near the bottom of the protrusion 5a experiences the maximum stress σ ｍａｘ A stress σ is applied. In conventional technology, this stress σ ｍａｘ This resulted in a decrease in the delamination resistance of the bond between the metal pattern 1a and the electrode 5, which led to a problem where the reliability of the semiconductor device, such as its lifespan, was reduced.

[0020] In contrast, this embodiment 1 makes it possible to improve the peel resistance of the bond between the metal pattern 1a and the electrode 5, and the reliability of the semiconductor device. This will be explained below.

[0021] In this embodiment 1, as shown in Figure 3, a joint portion 11 where the metal pattern 1a and the electrode 5 are joined, and a non-joint portion 12 where the metal pattern 1a and the electrode 5 are not joined are provided between the metal pattern 1a and the electrode 5. The joint portion 11 may be a part of the electrode 5, or it may be a reaction portion formed by the reaction when the metal pattern 1a and the electrode 5 are joined.

[0022] As shown in Figure 2, the non-joint portion 12 is located below the protruding portion 5a. As shown in Figure 3, in cross-sectional view, the side end 12a of the non-joint portion 12 is rounded. The rounding of the side end 12a may be formed during the laser bonding of the metal pattern 1a and the electrode 5. In other words, the rounding of the side end 12a may be a trace of the laser bonding of the metal pattern 1a and the electrode 5. In the example of Figure 2, the non-joint portion 12 is the gap between the metal pattern 1a and the electrode 5, but it is not limited to this.

[0023] <Summary of Embodiment 1> In this embodiment 1, a non-jointed portion 12 is provided between the metal pattern 1a below the protruding portion 5a and the electrode 5. With this configuration, the stress σ below the protruding portion 5a ｍａｘ Since this can reduce the peeling resistance of the bond between the metal pattern 1a and the electrode 5, and the reliability of the semiconductor device can be improved.

[0024] Furthermore, in this embodiment 1, the side end portion 12a of the non-jointed portion 12 has a rounded shape rather than a sharp wedge shape when viewed in cross-section. With this configuration, it is possible to suppress the propagation of cracks from the non-jointed portion 12 toward the jointed portion 11, thereby improving the peel resistance of the bond between the metal pattern 1a and the electrode 5, and the reliability of the semiconductor device.

[0025] Furthermore, this improvement in the delamination resistance of the bond between the metal pattern 1a and the electrode 5 is particularly effective in configurations where the semiconductor chip 4 is made of a wide-bandgap semiconductor that can be used at high temperatures.

[0026] Furthermore, if the rounded shape of the side end 12a of the non-joined portion 12 is, for example, a trace of laser bonding between the metal pattern 1a and the electrode 5, the rounded shape of the side end 12a can be easily formed.

[0027] <Modification 1> Figure 3 shows the stress σ applied to the joint at a sufficient distance from the vicinity below the protruding portion 5a. ｎ The arrow height (=c) of the arc forming the rounded side end 12a of the non-jointed portion 12 and the chord length (=2d) of the side end 12a are shown. Here, the stress σ ｍａｘ , σ ｎThere is a relationship expressed by Formula (1) and Formula (2) among the sagitta of the arc (= c), half of the chord length of the arc (= d), and the radius of curvature ρ of the rounding of the side end portion 12a.

[0028]

[0029]

[0030] From Formula (1) and Formula (2), Formula (3) and Formula (4) are derived.

[0031]

[0032]

[0033] FIG. 4 is a diagram showing the relationship between c / d and α in Formula (4). Half of the chord length of the arc (= d) may be larger than the sagitta of the arc (= c). According to such a configuration, c / d can be reduced to reduce α in Formula (3), so that the stress σ ｍａｘ can be reduced. Thereby, the peeling resistance of the joint between the metal pattern 1a and the joint portion 11 of the electrode 5, and the reliability of the semiconductor device can be enhanced.

[0034] <Modification Example 2> In the first embodiment, the substrate is the insulating substrate 1, but it is not limited thereto. For example, the substrate may be a semiconductor substrate. Even in this case, the reliability of the semiconductor device can be enhanced.

[0035] In the English disclosure herein, 'a', 'an' mean one or more. For this reason, 'a', 'an', 'one or more' and 'at least one' can be used with the same meaning.

[0036] Note that it is possible to freely combine each embodiment and each modification example, or to appropriately modify or omit each embodiment and each modification example.

[0037] The above description is illustrative in all aspects and not restrictive. An innumerable number of modification examples not illustrated are understood to be conceivable.

[0038] 1 insulating substrate, 1a metal pattern, 4 semiconductor chip, 5 electrode, 5a protruding portion, 11 joint portion, 12 non-joint portion, 12a side end.

Claims

1. A semiconductor device comprising: a substrate having a metal pattern on its upper surface; a semiconductor element electrically connected to the metal pattern; and an electrode having a protruding portion that projects upward and is bonded to the metal pattern, wherein a bonding portion is provided between the metal pattern and the electrode where the metal pattern and the electrode are bonded, and a non-bonding portion is provided between the metal pattern and the electrode where the metal pattern and the electrode are not bonded, the non-bonding portion is provided below the protruding portion, and in cross-sectional view the side edge of the non-bonding portion is rounded.

2. A semiconductor device according to claim 1, wherein, in a cross-sectional view, half the chord length of the arc forming the curvature of the side end is greater than the arrow height of the arc.

3. A semiconductor device according to claim 1 or claim 2, wherein the substrate is an insulating substrate, the electrode is a copper electrode with a nickel coating, and the metal pattern is a copper pattern.

4. A semiconductor device according to any one of claims 1 to 3, wherein the semiconductor element is made of a wide-bandgap semiconductor.

5. A method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the metal pattern and the electrode are joined by laser bonding, and the rounded edges of the side ends are traces of the laser bonding.

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