Power conversion device

Abstract

The present invention comprises a multilayer wiring board including: a first switching element and a second switching element that are electrically connected in series and constitute a first leg; a positive electrode wiring line electrically connected to the first switching element; a negative electrode wiring line electrically connected to the second switching element; and a first output wiring line that electrically connects the first switching element and the second switching element. The positive electrode wiring line and the negative electrode wiring line include a stacked wiring region stacked in the substrate thickness direction of the multilayer wiring board. The first switching element and the second switching element are disposed so as to overlap each other in the substrate thickness direction with the multilayer wiring board interposed therebetween. When viewed from the substrate thickness direction, a projection region where the first output wiring line is disposed does not overlap a projection region where the positive electrode wiring line and the negative electrode wiring line are disposed.

Description

Power conversion device

[0001] The present invention relates to a power conversion device.

[0002] In Patent Document 1 below, a configuration of a semiconductor device and a DC voltage conversion device capable of reducing self-inductance and mutual inductance in a high-frequency circuit to which a high-speed switching device is applied is disclosed.

[0003] Japanese Patent Application Laid-Open No. 2010-135612

[0004] A power conversion device needs to achieve reduction of switching loss and miniaturization due to a high current change rate, a surge voltage due to parasitic inductance, and a charge / discharge current due to a parasitic capacitance between wirings having different potentials. However, in the technique described in Patent Document 1, there is a problem that the overlapping area between the DC wiring and the AC wiring is large and the effect of reducing the parasitic capacitance cannot be obtained. In view of this, an object of the present invention is to provide a power conversion device that realizes miniaturization, reduction of inductance, and reduction of parasitic capacitance.

[0005] The power conversion device includes a first switching element and a second switching element that are electrically connected in series to form a first leg, a positive electrode wiring electrically connected to the first switching element, a negative electrode wiring electrically connected to the second switching element, and a multilayer wiring board having a first output wiring that electrically connects the first switching element and the second switching element. The positive electrode wiring and the negative electrode wiring have a laminated wiring region laminated in the substrate thickness direction of the multilayer wiring board. The first switching element and the second switching element are arranged so as to overlap in the substrate thickness direction with the multilayer wiring board interposed therebetween. When viewed from the substrate thickness direction, the projection region where the first output wiring is arranged does not overlap with the projection regions where the positive electrode wiring and the negative electrode wiring are arranged.

[0006] A power conversion device that realizes miniaturization, reduction of inductance, and reduction of parasitic capacitance can be provided.

[0007] A circuit diagram of a power converter according to one embodiment of the present invention. A structural diagram of the multilayer wiring board layer used in the power converter of Figure 1 according to one embodiment of the present invention. A cross-sectional view of X-X' in Figure 2. A structural diagram of a power semiconductor element. A circuit diagram of a power converter according to a first modified example of the present invention. A structural diagram of the multilayer wiring board layer used in the power converter of Figure 5 according to a first modified example of the present invention. A cross-sectional view of Y-Y' in Figure 6. A cross-sectional view showing the double-sided cooling structure of the power converter according to a second modified example of the present invention. A structural diagram of the multilayer wiring board layer used in the power converter according to a third modified example of the present invention. A cross-sectional view of Z-Z' in Figure 9. A structural diagram of the wiring board layer according to a fourth modified example of the present invention.

[0008] Embodiments of the present invention will be described below with reference to the drawings. The following description and drawings are illustrative for illustrating the present invention, and have been omitted and simplified as appropriate for clarity of explanation. The present invention can also be carried out in various other forms. Unless otherwise specified, each component may be singular or plural.

[0009] The positions, sizes, shapes, and ranges of the components shown in the drawings may not represent their actual positions, sizes, shapes, and ranges in order to facilitate understanding of the invention. Therefore, the present invention is not necessarily limited to the positions, sizes, shapes, and ranges disclosed in the drawings.

[0010] (One Embodiment and Overall Configuration) (Figure 1) Power semiconductor elements S1 and S2 are composed of power semiconductor elements such as IGBTs, SiC-MOSFETs, and GaN-HEMTs. Power semiconductor elements S1 and S2 are each provided with three terminals: a high-voltage terminal for the main circuit (collector terminal for IGBTs, drain terminal for MOSFETs), a low-voltage terminal for the main circuit (emitter terminal for IGBTs, source terminal for MOSFETs), and a control terminal (gate terminal). Power semiconductor elements S1 and S2 may be electrically connected in multiple parallels depending on the desired output current value. The power converter 1 itself may also be electrically connected in parallel.

[0011] Positive wiring 2 is a DC wiring that is electrically connected to a DC voltage source such as a battery (not shown) or the positive terminal of a smoothing capacitor (not shown). Negative wiring 3 is a DC wiring that is electrically connected to a DC voltage source such as a battery (not shown) or the negative terminal of a smoothing capacitor (not shown). As a result, a DC voltage is supplied to the power converter 1.

[0012] The first switching element, power semiconductor element S1, and the second switching element, power semiconductor element S2, are electrically connected in series to form the first leg. The positive electrode wiring 2 is electrically connected to the high-voltage terminal for the main circuit of power semiconductor element S1. The low-voltage terminal for the main circuit of power semiconductor element S1 is electrically connected to the output wiring AC1 (first output wiring) of the power converter 1 via the midpoint M1. The low-voltage terminal for the main circuit of power semiconductor element S1 is also electrically connected to the high-voltage terminal for the main circuit of power semiconductor element S2. In other words, the output wiring AC1 electrically connects power semiconductor element S1 and power semiconductor element S2. The low-voltage terminal for the main circuit of power semiconductor element S2 is electrically connected to the negative electrode wiring 3.

[0013] The output wiring AC1 of the power converter 1 is electrically connected to a load such as a motor or transformer (not shown). The signal terminals 5a and 5b, which are control terminals provided on the power semiconductor element S1 and power semiconductor element S2, respectively, are electrically connected to a control circuit (not shown) and are turned on or off based on signals input from a higher-level control device such as a microcontroller, thereby outputting AC power to the load such as a motor or transformer via the output terminals on the output wiring AC1.

[0014] The positive electrode wiring 2 and the negative electrode wiring 3 have parasitic inductance LS components due to their wiring length and magnetic coupling. Furthermore, parasitic capacitance components C1 and C2 exist between the positive electrode wiring 2 and the output terminal on the output wiring AC1, and between the negative electrode wiring 3 and the output terminal on the output wiring AC1, due to overlapping wiring areas and material dielectric constants.

[0015] (Figure 2) Figure 2(a) is a diagram illustrating the mounting of the first layer of the multilayer wiring board 6 used in the power conversion device 1 of Figure 1. Figure 2(b) is a diagram illustrating the mounting of the second layer of the multilayer wiring board 6 used in the power conversion device 1 of Figure 1. Figure 2(c) is a diagram illustrating the mounting of the third layer of the multilayer wiring board 6 used in the power conversion device 1 of Figure 1. Figure 2(d) is a diagram illustrating the mounting of the fourth layer of the multilayer wiring board 6 used in the power conversion device 1 of Figure 1. In one embodiment of the present invention and the various modifications described later, a four-layer multilayer wiring board structure is used as an example, but it can be similarly realized even with a multilayer wiring board 6 that does not have a four-layer structure.

[0016] In the multilayer wiring board 6, the first layer is mounted with positive electrode wiring 2, negative electrode wiring 3, power semiconductor element S1, and output wiring AC1. The positive electrode wiring 2 is electrically connected to the high-potential electrode of the power semiconductor element S1. The low-potential electrode of the power semiconductor element S1 is electrically connected to the output wiring AC1. The positive electrode wiring 2 and the negative electrode wiring 3 are mounted on the multilayer wiring board 6 while maintaining an insulating distance from each other.

[0017] In the multilayer wiring board 6, the second layer is equipped with positive electrode wiring 2, negative electrode wiring 3, and output wiring AC1. The positive electrode wiring 2 is electrically connected to the positive electrode wiring 2 of the first layer via through-holes 11. The negative electrode wiring 3 is electrically connected to the negative electrode wiring 3 of the first layer via through-holes 11. The output wiring AC1 is electrically connected to the output wiring AC1 of the first layer via through-holes 11. The positive electrode wiring 2 and the negative electrode wiring 3 are mounted on the multilayer wiring board 6 while maintaining an insulating distance from each other.

[0018] In the multilayer wiring board 6, the third layer is mounted with positive electrode wiring 2, negative electrode wiring 3, and output wiring AC1. The positive electrode wiring 2 is electrically connected to the positive electrode wiring 2 of the second layer via through-holes 11. The negative electrode wiring 3 is electrically connected to the negative electrode wiring 3 of the second layer via through-holes 11. The output wiring AC1 is electrically connected to the output wiring AC1 of the second layer via through-holes 11. A portion of the negative electrode wiring 3 of the third layer is mounted so as to overlap with a portion of the positive electrode wiring 2 of the second layer in the substrate thickness direction. The positive electrode wiring 2 and the negative electrode wiring 3 are mounted on the multilayer wiring board 6 while maintaining an insulating distance from each other.

[0019] In the multilayer wiring board 6, the fourth layer is mounted with positive electrode wiring 2, negative electrode wiring 3, power semiconductor element S2, and output wiring AC1. The positive electrode wiring 2 is electrically connected to the high-potential electrode of the power semiconductor element S1. The low-potential electrode of the power semiconductor element S1 is electrically connected to the output wiring AC1. The positive electrode wiring 2 and the negative electrode wiring 3 are mounted on the multilayer wiring board 6 while maintaining an insulating distance from each other. The positive electrode wiring 2 is electrically connected to the positive electrode wiring 2 of the third layer via a through-hole 11. The negative electrode wiring 3 is electrically connected to the negative electrode wiring 3 of the third layer via a through-hole 11. The output wiring AC1 is electrically connected to the output wiring AC1 of the third layer via a through-hole 11.

[0020] (Figure 3) As described above, the positive electrode wiring 2 and negative electrode wiring 3 formed in the first to fourth layers, respectively, are stacked in the substrate thickness direction of the multilayer wiring substrate 6. This stacked region is referred to as the stacked wiring region 7. Power semiconductor elements S1 and S2 are arranged so as to overlap in the substrate thickness direction with the multilayer wiring substrate 6 in between. The positive electrode wiring 2 is electrically connected to the high-voltage terminal for the main circuit of power semiconductor element S1. The low-voltage terminal for the main circuit of power semiconductor element S1 is electrically connected to the output wiring AC1 via the midpoint M1. As a result, the low-voltage terminal for the main circuit of power semiconductor element S1 is electrically connected to the high-voltage terminal for the main circuit of power semiconductor element S2. The low-voltage terminal for the main circuit of power semiconductor element S2 is electrically connected to the negative electrode wiring 3.

[0021] The positive electrode wiring 2 formed in the first and second layers are electrically connected to each other via through-holes 11 and are stacked. The negative electrode wiring 3 formed in the third and fourth layers are electrically connected to each other via through-holes 11 and are stacked. The output wiring AC1 formed in the first to fourth layers are electrically connected to each other via through-holes 11 and are stacked. Furthermore, when viewed from the substrate thickness direction, the projection region where the output wiring AC1 is located is separated so as not to overlap with the projection region where the positive electrode wiring 2 and negative electrode wiring 3 are located.

[0022] As described above, the power converter 1 has the configuration shown in Figures 1 to 3, which reduces the parasitic inductance of the positive electrode wiring 2 and the negative electrode wiring 3 through magnetic coupling, thereby reducing surge voltage. In addition, the overlap area of ​​the positive electrode wiring 2 and the output wiring AC1 on the multilayer wiring board 6 is reduced, and the overlap area of ​​the negative electrode wiring 3 and the output wiring AC1 on the multilayer wiring board 6 is also reduced. Furthermore, as shown in Figure 2, by limiting the overlap of the positive electrode wiring 2 and the negative electrode wiring 3, which have different potentials, to only a portion and minimizing the overlap as much as possible, the multilayer wiring area 7 of each DC wiring can be expanded, and the parasitic capacitances C1 and C2 (Figure 1) that occur between the positive electrode wiring 2 and the output wiring AC1, or between the negative electrode wiring 3 and the output wiring AC1, can be reduced. As a result, the charge and discharge current due to parasitic capacitance can be suppressed during high-frequency driving, and switching losses can be reduced. Furthermore, by mounting each switching element (power semiconductor element) on both sides of the multilayer wiring board 6, with the high-potential side and the low-potential side respectively, the floor area required for mounting can be reduced while sharing DC wiring, thus contributing to increased efficiency and miniaturization. This also contributes to improved driving range and increased interior space.

[0023] (Figure 4) Figure 4(a) is an overall perspective view of the power semiconductor element 10, Figure 4(b) is a plan view of the power semiconductor element 10 as seen from the front surface 10a side, and Figure 4(c) is a plan view of the power semiconductor element 10 as seen from the back surface 10b side. Note that the power semiconductor element 10 has the same structure as the power semiconductor elements used in the power semiconductor elements S1 and S2 described above, and the power semiconductor elements S3 and S4 described later.

[0024] The surface 10a of the power semiconductor element 10 is provided with a heat dissipation section 10c. The back surface 10b of the power semiconductor element 10 is provided with a high-potential side electrode 10d, a low-potential side electrode 10e, and a signal electrode 10f for applying a drive signal. The structure of the power semiconductor element used in one embodiment of the present invention is not limited to this, and any power semiconductor element having a heat dissipation section, a high-potential side electrode, a low-potential side electrode, and a signal electrode is acceptable.

[0025] (First Modified Example) (Figure 5) The power converter 1 may include power semiconductor elements S1 to S4. The second leg is composed of a third switching element, power semiconductor element S3, and a fourth switching element, power semiconductor element S4. The second leg is electrically connected in parallel with the first leg, which is composed of power semiconductor elements S1 and S2. The configuration of power semiconductor elements S1 and S2 is the same as in Figure 1, so the explanation is omitted below.

[0026] The positive electrode wiring 2 is electrically connected to the high-voltage terminal for the main circuit of the power semiconductor element S3. The low-voltage terminal for the main circuit of the power semiconductor element S3 is electrically connected to the output wiring AC2 of the power converter 1 via the midpoint M2. The low-voltage terminal for the main circuit of the power semiconductor element S3 is electrically connected to the high-voltage terminal for the main circuit of the power semiconductor element S4. The low-voltage terminal for the main circuit of the power semiconductor element S4 is electrically connected to the negative electrode wiring 3.

[0027] Output wiring AC2 is electrically connected to a load such as a motor or transformer (not shown). In the power converter 1, signal terminals 5a to 5d, which are control terminals provided on power semiconductor elements S1 to S4 respectively, are electrically connected to a control circuit (not shown) and are turned on or off based on signals input from a higher-level control device such as a microcontroller, thereby outputting AC power to a load such as a motor or transformer (not shown) via output wiring AC1 and output wiring AC2.

[0028] The positive electrode wiring 2 and the negative electrode wiring 3 have parasitic inductance LS components due to their wiring length and magnetic coupling. Furthermore, parasitic capacitance components C1 to C5 exist between the positive electrode wiring 2 and the output terminals on output wiring AC1 and AC2, between the negative electrode wiring 3 and the output terminals on output wiring AC1 and AC2, and between the output terminals on output wiring AC1 and the output terminals on output wiring AC2, respectively, due to overlapping wiring areas and material dielectric constants.

[0029] (Figure 6) Figure 6(a) is a diagram illustrating the mounting of the first layer of the multilayer wiring board 6 used in the power conversion device shown in Figure 5. Figure 6(b) is a diagram illustrating the mounting of the second layer of the multilayer wiring board 6 used in the power conversion device shown in Figure 5. Figure 6(c) is a diagram illustrating the mounting of the third layer of the multilayer wiring board 6 used in the power conversion device shown in Figure 5. Figure 6(d) is a diagram illustrating the mounting of the fourth layer of the multilayer wiring board 6 used in the power conversion device shown in Figure 5.

[0030] In the multilayer wiring board 6, the first layer is mounted with positive electrode wiring 2, negative electrode wiring 3, power semiconductor element S1, and output wiring AC1. The positive electrode wiring 2 is electrically connected to the high-potential electrode of the power semiconductor element S1. The low-potential electrode of the power semiconductor element S1 is electrically connected to the output wiring AC1. Furthermore, the first layer is mounted with power semiconductor element S3 and output wiring AC2. The positive electrode wiring 2 is electrically connected to the high-potential electrode of the power semiconductor element S3. The low-potential electrode of the power semiconductor element S3 is electrically connected to the output wiring AC2. The positive electrode wiring 2 and negative electrode wiring 3 of the first to fourth layers are mounted on the multilayer wiring board 6 while maintaining an insulating distance from each other.

[0031] In the multilayer wiring board 6, the second layer is equipped with positive electrode wiring 2, negative electrode wiring 3, and output wiring AC1. The positive electrode wiring 2 is electrically connected to the positive electrode wiring 2 of the first layer via through-holes 11. The negative electrode wiring 3 is electrically connected to the negative electrode wiring 3 of the first layer via through-holes 11. The output wiring AC1 is electrically connected to the output wiring AC1 of the first layer via through-holes 11. Furthermore, output wiring AC2 is equipped on the second layer. Output wiring AC2 is electrically connected to the output wiring AC2 of the first layer via through-holes 11.

[0032] In the multilayer wiring board 6, the third layer is equipped with positive electrode wiring 2, negative electrode wiring 3, and output wiring AC1. The positive electrode wiring 2 is electrically connected to the positive electrode wiring 2 of the second layer via through-holes 11. The negative electrode wiring 3 is electrically connected to the negative electrode wiring 3 of the second layer via through-holes 11. The output wiring AC1 is electrically connected to the output wiring AC1 of the second layer via through-holes 11. A portion of the negative electrode wiring 3 of the third layer is mounted so as to overlap with a portion of the positive electrode wiring 2 of the second layer. Furthermore, output wiring AC2 is mounted on the third layer. Output wiring AC2 is electrically connected to the output wiring AC2 of the second layer via through-holes 11.

[0033] In the multilayer wiring board 6, the fourth layer is mounted with positive electrode wiring 2, negative electrode wiring 3, power semiconductor element S2, and output wiring AC1. The negative electrode wiring 3 is electrically connected to the high-potential electrode of the power semiconductor element S1. The low-potential electrode of the power semiconductor element S1 is electrically connected to the output wiring AC1. The positive electrode wiring 2 is electrically connected to the positive electrode wiring 2 of the third layer via a through-hole 11. The negative electrode wiring 3 is electrically connected to the negative electrode wiring 3 of the third layer via a through-hole 11. The output wiring AC1 is electrically connected to the output wiring AC1 of the third layer via a through-hole 11. Furthermore, the fourth layer is mounted with power semiconductor element S4 and output wiring AC2. The negative electrode wiring 3 is electrically connected to the high-potential electrode of the power semiconductor element S4. The low-potential electrode of the power semiconductor element S4 is electrically connected to the output wiring AC2. The output wiring AC2 is electrically connected to the output wiring AC2 of the third layer via a through-hole 11.

[0034] (Figure 7) The positive electrode wiring 2 is electrically connected to the high-voltage terminal for the main circuit of the power semiconductor element S1. The low-voltage terminal for the main circuit of the power semiconductor element S1 is electrically connected to the output wiring AC1 of the power converter 1 via the midpoint M1. The low-voltage terminal for the main circuit of the power semiconductor element S1 is electrically connected to the high-voltage terminal for the main circuit of the power semiconductor element S2. The low-voltage terminal for the main circuit of the power semiconductor element S2 is electrically connected to the negative electrode wiring 3. The positive electrode wiring 2 of the first and second layers is electrically connected to each other via the through-hole 11. The negative electrode wiring 3 of the third and fourth layers is electrically connected to each other via the through-hole 11. The output wiring AC1 of the first to fourth layers is electrically connected to each other via the through-hole 11.

[0035] Furthermore, the positive electrode wiring 2 is electrically connected to the high-voltage terminal for the main circuit of the power semiconductor element S3. The low-voltage terminal for the main circuit of the power semiconductor element S3 is electrically connected to the output wiring AC2 of the power converter 1 via the midpoint M2. The low-voltage terminal for the main circuit of the power semiconductor element S3 is electrically connected to the high-voltage terminal for the main circuit of the power semiconductor element S4. The low-voltage terminal for the main circuit of the power semiconductor element S4 is electrically connected to the negative electrode wiring 3. The positive electrode wiring 2 of the first and second layers is electrically connected to each other via the through-hole 11. The negative electrode wiring 3 of the third and fourth layers is electrically connected via the through-hole 11. The output wiring AC2 of the first to fourth layers is electrically connected to each other via the through-hole 11.

[0036] With the above configuration, the positive electrode wiring 2 and a portion of the negative electrode wiring 3 are arranged to overlap each other in the direction of the substrate thickness, thereby reducing the parasitic inductance of the positive electrode wiring 2 and the negative electrode wiring 3 through magnetic coupling.

[0037] Furthermore, output wiring AC2 is positioned on the opposite side of output wiring AC1, with the multilayer wiring region 7 in between. In other words, the projected region where output wiring AC1 and output wiring AC2 are positioned is separated from the projected region where positive electrode wiring 2 and negative electrode wiring 3 are positioned, as viewed from the thickness direction of the substrate, with power semiconductor elements S1 and S2, or S3 and S4, as the boundary. In this way, the overlapping area of ​​positive electrode wiring 2 and output wiring AC1, or positive electrode wiring 2 and output wiring AC2 on the multilayer wiring substrate 6 is reduced. Also, the overlapping area of ​​negative electrode wiring 3 and output wiring AC1, or negative electrode wiring 3 and output wiring AC2 on the multilayer wiring substrate 6 is reduced. Also, the overlapping area of ​​output wiring AC1 and output wiring AC2 on the multilayer wiring substrate 6 is reduced. Therefore, the parasitic capacitances C1 to C5 (Figure 5) that occur between positive electrode wiring 2 and output wiring AC1, or between negative electrode wiring 3 and output wiring AC1, or between output wiring AC1 and output wiring AC2 can be reduced.

[0038] (Second Modification) (Figure 8) The power converter 1 may also include a first cooling section 12a and a second cooling section 12b, each having a cooling channel 14. The first cooling section 12a cools the power semiconductor elements S1 and S3 by thermally connecting to at least one of the heat dissipation sections (see Figure 4) provided on the surfaces of the power semiconductor elements S1 and S3 via a thermal conductive member 13a (first thermal conductive member). The second cooling section 12b cools the power semiconductor elements S2 and S4 by thermally connecting to at least one of the heat dissipation sections (see Figure 4) provided on the surfaces of the power semiconductor elements S2 and S4 via a thermal conductive member 13b (second thermal conductive member).

[0039] The first cooling section 12a and the second cooling section 12b are mounted facing each other. With this cooling structure, the heat generated when the power semiconductor elements S1, S3 or S2, S4 conduct or switch can be dissipated to the first cooling section 12a and the second cooling section 12b, thereby achieving high heat dissipation.

[0040] (Third Modified Example) (Figure 9) Figure 9(a) is a diagram illustrating the mounting of the first layer of the multilayer wiring board 6 used in the power conversion device according to the third modified example. Figure 9(b) is a diagram illustrating the mounting of the second layer of the multilayer wiring board 6 used in the power conversion device according to the third modified example. Figure 9(c) is a diagram illustrating the mounting of the third layer of the multilayer wiring board 6 used in the power conversion device according to the third modified example. Figure 9(d) is a diagram illustrating the mounting of the fourth layer of the multilayer wiring board 6 used in the power conversion device according to the third modified example.

[0041] The power conversion device according to the third modified example has a configuration comprising power semiconductor elements S1 to S4, and the configuration similar to that in Figure 6 will not be explained. In the multilayer wiring board 6, in the first and third layers, a portion of the negative electrode wiring 3 is provided within the region where the positive electrode wiring 2 is formed, with a predetermined insulation distance between them. In addition, in the second and fourth layers, a portion of the positive electrode wiring 2 is provided within the region where the negative electrode wiring 3 is formed, with a predetermined insulation distance between them.

[0042] (Figure 10) The positive electrode wiring 2 is electrically connected to the high-voltage terminal for the main circuit of the power semiconductor element S1. The low-voltage terminal for the main circuit of the power semiconductor element S1 is electrically connected to the output wiring AC1 of the power converter 1 via the midpoint M1. The low-voltage terminal for the main circuit of the power semiconductor element S1 is electrically connected to the high-voltage terminal for the main circuit of the power semiconductor element S2. The low-voltage terminal for the main circuit of the power semiconductor element S2 is electrically connected to the negative electrode wiring 3. The positive electrode wiring 2 of the first to fourth layers is electrically connected to each other via the through-hole 11. The negative electrode wiring 3 of the first to fourth layers is electrically connected to each other via the through-hole 11.

[0043] Further, the positive electrode wiring 2 is electrically connected to the high-voltage side terminal for the main circuit of the power semiconductor device S3. The low-voltage side terminal for the main circuit of the power semiconductor device S3 is electrically connected to the output wiring AC2 of the power conversion device 1 via the midpoint M2. The low-voltage side terminal for the main circuit of the power semiconductor device S3 is electrically connected to the high-voltage side terminal for the main circuit of the power semiconductor device S4. The low-voltage side terminal for the main circuit of the power semiconductor device S4 is electrically connected to the negative electrode wiring 3. The output wirings AC2 of the first layer to the fourth layer are electrically connected to each other via the through holes 11.

[0044] With the above configuration, the positive electrode wiring 2 and the negative electrode wiring 3 are arranged so as to alternately overlap between the first layer and the fourth layer in the substrate thickness direction. Therefore, the parasitic inductance of the positive electrode wiring 2 and the negative electrode wiring 3 is further reduced by magnetic coupling.

[0045] Further, the projection area where the output wiring AC1 and the output wiring AC2 are arranged is separated from and does not overlap with the projection area where the positive electrode wiring 2 and the negative electrode wiring 3 are arranged when viewed from the thickness direction of the multilayer wiring substrate 6 with the power semiconductor device S1 and the power semiconductor device S2, or the power semiconductor device S3 and the power semiconductor device S4 as boundaries. Thereby, the overlapping area of the positive electrode wiring 2 and the output wiring AC1, or the positive electrode wiring 2 and the output wiring AC2 in the multilayer wiring substrate 6 is reduced. Also, the overlapping area of the negative electrode wiring 3 and the output wiring AC1, or the negative electrode wiring 3 and the output wiring AC2 in the multilayer wiring substrate 6 is reduced. Also, the overlapping area of the output wiring AC1 and the output wiring AC2 in the multilayer wiring substrate 6 is reduced. Therefore, the parasitic capacitance generated between the positive electrode wiring 2 and the output wiring AC1, or between the negative electrode wiring 3 and the output wiring AC1, or between the output wiring AC1 and the output wiring AC2 can be reduced.

[0046] (Fourth Modified Example) (FIG. 11) The multilayer wiring board 6 in the power conversion device 1 may have a mounting configuration in which a plurality of power semiconductor elements are electrically connected in parallel. For example, a plurality of power semiconductor elements S1 and S2 constituting the first leg are provided respectively, and the power semiconductor elements S1 and S2 are mounted along the direction in which the output wiring AC1 is mounted on the multilayer wiring board 6. Also, a plurality of power semiconductor elements S3 and S4 constituting the second leg are provided respectively, and the power semiconductor elements S3 and S4 are mounted along the direction in which the output wiring AC2 is mounted on the multilayer wiring board 6. Further, as illustrated in FIGS. 6 and 9, in the multilayer wiring board 6, the mounting direction of the output wiring AC1 is different from the mounting direction of the positive electrode wiring 2, and the mounting direction of the output wiring AC2 is different from the mounting direction of the negative electrode wiring 3. In such a full-bridge circuit, by switching the second leg connected in parallel with the first leg together with the first leg, a current twice that of the configuration with only one leg can be output, so the output can be increased.

[0047] Hereinafter, the mounting on each layer of the multilayer wiring board 6 will be described, but the description of the configuration similar to that in FIG. 6 will be omitted. In the first layer, the positive electrode wiring 2 is electrically connected to the high-potential electrodes of the power semiconductor elements S1a and S1b respectively. The low-potential electrodes of the power semiconductor elements S1a and S1b are electrically connected to the output wiring AC1. Also, the positive electrode wiring 2 is electrically connected to the high-potential electrodes of the power semiconductor elements S3a and S3b respectively. The low-potential electrodes of the power semiconductor elements S3a and S3b are electrically connected to the output wiring AC2.

[0048] In the positive electrode wiring 2 and the negative electrode wiring 3 of the second and third layers, they are mounted corresponding to the mounting configuration in which the power semiconductor elements S1a and S1b are electrically connected in parallel in the first layer.

[0049] In the fourth layer, the negative electrode wiring 3 is electrically connected to the high-potential electrodes of the power semiconductor elements S2a and S2b, respectively. The low-potential electrodes of the power semiconductor elements S2a and S2b are electrically connected to the output wiring AC1. Furthermore, the negative electrode wiring 3 is connected to the high-potential electrodes of the power semiconductor elements S4a and S4b, respectively. The low-potential electrodes of the power semiconductor elements S4a and S4b are connected to the output wiring AC2. This configuration allows for the same effects as those of the previously described embodiment to be achieved.

[0050] According to the embodiments of the present invention described above, the following effects and advantages are achieved.

[0051] (1) The power converter 1 comprises a multilayer wiring board 6 having a first switching element S1 and a second switching element S2 electrically connected in series to constitute a first leg, a positive electrode wiring 2 electrically connected to the first switching element S1, a negative electrode wiring 3 electrically connected to the second switching element S2, and a first output wiring AC1 electrically connecting the first switching element S1 and the second switching element S2. The positive electrode wiring 2 and the negative electrode wiring 3 have a stacked wiring region 7 stacked in the substrate thickness direction of the multilayer wiring board 6. The first switching element S1 and the second switching element S2 are arranged to overlap in the substrate thickness direction with the multilayer wiring board 6 in between. When viewed from the substrate thickness direction, the projected region where the first output wiring AC1 is located does not overlap with the projected region where the positive electrode wiring 2 and the negative electrode wiring 3 are located. In this way, a power converter 1 can be provided that is miniaturized, has low inductance, and has reduced parasitic capacitance.

[0052] (2) The power converter 1 comprises a third switching element S3 and a fourth switching element S4 which constitute a second leg electrically connected in parallel with the first leg, and a second output wiring AC2 which electrically connects the third switching element S3 and the fourth switching element S4, wherein the second output wiring AC2 is located on the opposite side from the first output wiring AC1 with the stacked wiring region 7 in between. This configuration makes it possible to increase the output power of the power converter 1.

[0053] (3) Multiple first switching elements S1 and second switching elements S2 constituting the first leg are provided, and the multiple first switching elements S1 and second switching elements S2 are mounted on the multilayer wiring board 6 in the direction in which the first output wiring AC1 is mounted. Multiple third switching elements S3 and fourth switching elements S4 constituting the second leg are provided, and the multiple third switching elements S3 and fourth switching elements S4 are mounted on the multilayer wiring board 6 in the direction in which the second output wiring AC2 is mounted. On the multilayer wiring board 6, the mounting direction of the first output wiring AC1 is different from the mounting direction of the positive electrode wiring 2, and the mounting direction of the second output wiring AC2 is different from the mounting direction of the negative electrode wiring 3. In this way, the power output of the power converter 1 can be increased.

[0054] (4) The power converter 1 has a first cooling structure 12a for cooling the first switching element S1 and the third switching element S3, a first heat conductive member 13a that thermally connects the first switching element S1 or the third switching element S3 and the first cooling structure 12a, a second cooling structure 12b for cooling the second switching element S2 and the fourth switching element S4, and a second heat conductive member 13b that thermally connects the second switching element S2 or the fourth switching element S4 and the second cooling structure 12b, with the first cooling structure 12a and the second cooling structure 12b being mounted facing each other. This makes it possible to achieve high heat dissipation of the power converter 1.

[0055] It should be noted that the present invention is not limited to the embodiments described above, and various modifications and combinations of other configurations can be made without departing from the spirit of the invention. Furthermore, the present invention is not limited to having all the configurations described in the embodiments described above, and may also include configurations in which some of those configurations are omitted.

[0056] 1 Power converter 2 Positive electrode wiring 3 Negative electrode wiring 4 Smoothing capacitor 5 Signal terminal 6 Multilayer wiring board 7 Multilayer wiring area 10, S1-S4 Power semiconductor element 10a Front surface 10b Back surface 10c Heat dissipation area 10d High potential side electrode 10e Low potential side electrode 10f Signal electrode 11 Through hole 12 Cooling area 12a First cooling area 12b Second cooling area 13 Thermal conductive material 14 Flow path AC1, AC2 Output wiring C1-C4 Parasitic capacitance LS Parasitic inductance M1, M2 Midpoint

Claims

1. A power conversion device comprising: a multilayer wiring board having a first switching element and a second switching element electrically connected in series to constitute a first leg; a positive electrode wiring electrically connected to the first switching element; a negative electrode wiring electrically connected to the second switching element; and a first output wiring electrically connecting the first switching element and the second switching element, wherein the positive electrode wiring and the negative electrode wiring have a stacked wiring region stacked in the substrate thickness direction of the multilayer wiring board; the first switching element and the second switching element are arranged to overlap in the substrate thickness direction with the multilayer wiring board in between; and when viewed from the substrate thickness direction, the projected region where the first output wiring is arranged does not overlap with the projected region where the positive electrode wiring and the negative electrode wiring are arranged.

2. A power conversion device according to claim 1, comprising: a third switching element and a fourth switching element constituting a second leg electrically connected in parallel with the first leg; and a second output wiring electrically connecting the third switching element and the fourth switching element, wherein the second output wiring is arranged on the opposite side from the first output wiring with the stacked wiring region in between.

3. A power conversion device according to claim 2, wherein a plurality of first switching elements and second switching elements constituting the first leg are provided, and the plurality of first switching elements and second switching elements are each mounted on the multilayer wiring board in the direction in which the first output wiring is mounted; a plurality of third switching elements and fourth switching elements constituting the second leg are provided, and the plurality of third switching elements and fourth switching elements are each mounted on the multilayer wiring board in the direction in which the second output wiring is mounted; and on the multilayer wiring board, the mounting direction of the first output wiring is different from the mounting direction of the positive electrode wiring, and the mounting direction of the second output wiring is different from the mounting direction of the negative electrode wiring.

4. A power conversion device according to any one of claims 2 or 3, comprising: a first cooling structure for cooling the first switching element and the third switching element; a first heat conductive member for thermally connecting the first switching element or the third switching element and the first cooling structure; a second cooling structure for cooling the second switching element and the fourth switching element; and a second heat conductive member for thermally connecting the second switching element or the fourth switching element and the second cooling structure, wherein the first cooling structure and the second cooling structure are mounted facing each other.

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