Integrated asymetric metasurface for low loss coupling and back reflection suppression in multi mode waveguide

Abstract

An integrated asymmetric metasurface that simultaneously achieves broadband, low-loss forward power transmission, and back reflection suppression in a tapered multi-mode waveguide. The geometric asymmetry between the bilayers leads to low-loss conversion from the fundamental to high-order modes. Enhanced by a double-flipped structure, a thin metasurface can simultaneously achieve high conversion efficiency (>80%), and back-reflection efficiency of 90% over a 200 nm wavelength range.

Description

[0001] 2101715-001300

[0002] -1-

[0003] INTEGRATED ASYMETRIC METASURFACE FOR LOW LOSS COUPLING AND BACK REFLECTION SUPPRESSION IN MULTI MODE WAVEGUIDE STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH

[0004] This invention was made with government support under Grant No.

[0005] N660012302034 awarded by the Defense Advanced Research Projects Agency (DARPA). The government has certain rights in the invention.

[0006] CROSS REFERENCE TO RELATED APPLICATIONS

[0007] This application claims priority from U. S. Provisional Application Ser. No.

[0008] 63 / 638,592, titled ‘INTEGRATED METALENS FOR LOW LOSS COUPLING AND BACK REFLECTION SUPPRESSION,” filed April 25, 2024, and U. S. Provisional Application Ser. No. 63 / 792,039, titled “BROADBAND LOW-LOSS UNIDIRECTIONAL REFLECTION WITH ASYMMETRIC DIELECTRIC METASURFACE ON A CHIP,” filed April 21, 2025, the entireties of both of which are incorporated herein by reference for all purposes.

[0009] BACKGROUND OF THE INVENTION

[0010] Conventional photonic semiconductor chips can include optical couplers on the edges or surfaces thereof. One group of optical couplers, such as free-space optical couplers, for example, work by transmitting propagating light waves from waveguides on the semiconductor chip into free-space, and vice versa. These types of couplers may be limited by a narrow field of view in which they are able to efficiently couple free-space optical signals, resulting in lower overall coupling efficiency or insertion loss. To improve coupling efficiency of surface optical couplers, optical elements, such as prisms and / or lenses, for example, may be used to redirect, collimate, or focus inbound or outbound light. Broadband, low-loss, and single-side reflectors can be enabling components of gain-integrated adaptive optics on chips. However, these additional structures complicate the design or manufacture of optical coupling systems, consume a lot of power, are difficult to integrate, and cany’ high insertion loss, resulting in increased costs and power consumption, and / or decreased reliability or yield. 2101715-001300

[0011] - 2 -

[0012] SUMMARY OF THE INVENTION

[0013] Aspects of the present invention are directed to semiconductor chips incorporating an asymmetric metasurface, and methods for forming an asymmetric metasurface.

[0014] In one aspect, an asymmetric metasurface comprises a multilayer substrate comprising at least a high-refractive index dielectric layer disposed over a core layer; and a plurality of meta-unit cells, each of the plurality of meta-unit cells being defined as a void in the core layer and including at least one first slot having a first slot taper facing a first direction on one side of the at least one first slot.

[0015] In embodiments, the plurality of meta-unit cells comprise a plurality of double-flipped taper slots (DFTS) meta-unit cells, each of the plurality of DFTS meta-unit cells including the at least one first slot having the first slot taper facing the first direction on one side of the at least one first slot; and at least two second slots each having a trapezoidal shape with an apex facing a second direction opposite the first direction, the at least two second slots disposed on opposite sides of the first slot taper of the at least one first slot.

[0016] In embodiments, the apex of each of the at least two second slots faces two first slot tapers of at least two first slots of the at least one first slot.

[0017] In embodiments, each of the at least two second slots includes a second slot taper on one side of the second slot.

[0018] In embodiments, each of the at least two second slots has a base width of 0.3 μm and a second slot taper width of 0.15 μm.

[0019] In embodiments, an inter-taper gap between a start point of each first slot taper of the at least one first slot and each apex of the each of the at least two second slots is 0.46 μm.

[0020] In embodiments, the plurality of meta-unit cells are arranged to define a metalens. In embodiments, the metasurface is arranged on a silicon-on-insulator (SOI) substrate with a silicon thickness of 250 nm and a lattice constant of 800 nm.

[0021] In embodiments, each of the plurality of meta-unit cells comprises a silicon dioxide-based double-flipped slot taper slot structure arranged on a 250 nm thick silicon (Si) layer in oxide. 2101715-001300

[0022] In embodiments, the high-refractive index dielectric layer comprises a silicon layer or a silicon nitride layer.

[0023] In embodiments, the core layer comprises a silicon dioxide layer.

[0024] In embodiments, the metasurface is configured to simultaneously achieve a conversion efficiency of over 80% and a back-reflection efficiency of 90% over a 200 nm wavelength range.

[0025] In embodiments, the metasurface is integrated into a tapered multi-mode waveguide arranged on a silicon-on-insulator (SOI) substrate.

[0026] In embodiments, the tapered waveguide is tapered from a width of 11 μm to 0.5 μm over a waveguide taper footprint length Lwtin a range of 20 μm to 40 μm.

[0027] In embodiments, the metasurface has a metasurface footprint length Lmof 2.5 μm. In another aspect, a semiconductor chip comprises at least one optical coupler formed on a surface of the semiconductor chip; and an asymmetric dielectric metasurface connected to the at least one optical coupler. The asymmetric metasurface comprises a multilayer substrate comprising at least a high-refractive index dielectric layer disposed over a core layer; and a plurality of meta-unit cells, each of the plurality of meta-unit cells being defined as a void in the core layer and including at least one first slot having a first slot taper facing a first direction on one side of the at least one first slot.

[0028] In embodiments, the at least one optical coupler is a grating coupler.

[0029] In embodiments, the asymmetric dielectric metasurface is embedded between the grating coupler and a waveguide arranged on a silicon-on-insulator (SOI) substrate.

[0030] In another aspect, a method of designing an asymmetric metasurface comprises the steps of: a) depositing a layer of photoresist onto a substrate comprising a high-refractive index dielectric layer disposed over a core layer; b) exposing the layer of photoresist using electron beam li thography in accordance with a pattern corresponding to features of the asymmetric metasurface, the pattern defining at least one first slot having a first slot taper facing a first direction on one side of the at least one first slot; c) developing the patterned photoresist to define openings in the photoresist corresponding to the pattern; d) performing a dry etching step to define openings in the high -refractive index dielectric layer corresponding to the openings in the photoresist; e) stripping the photoresist; and f) 2101715-001300

[0031] - 4 -

[0032] depositing a cladding layer over the high -refractive index dielectric layer and filling the openings therein.

[0033] In embodiments, the pattern corresponding to features of the asymmetric metasurface further comprises a plurality of second slots, each second slot having a trapezoidal shape with an apex facing a second direction opposite the first direction, the plurality of second slots disposed on opposite sides of the first slot taper of at least one first slot of the plurality of first slots, each combination of a first slot and two second slots defining a double-flipped taper slots (DFTS) meta-unit cell.

[0034] In embodiments, the asymmetric metasurface is a component of a waveguide, and the method further comprises tuning dimensions of the DFTS meta-unit cells to optimize transmission contrast for suppression of back excited light contrast for a predetermined wavelength range.

[0035] In embodiments, the method of designing an asymmetric metasurface further comprises integrating the waveguide containing the asymmetric metasurface on a Silicon Nitride (SiN) wafer using Deep ultraviolet (DUV) lithography.

[0036] In embodiments, the tapered multi-mode waveguide is arranged on a silicon-on-insulator (SOI) substrate.

[0037] In embodiments, tuning the dimensions of the DFTS meta-unit cells further comprises defining parameters including a first slot apex length L2, a second slot apex length L1, and a gap length G for each DTFS meta-unit cell.

[0038] In embodiments, an optical isolator comprising the metalens defined by a plurality of meta-unit cells.

[0039] In embodiments, the optical isolator comprises a back -reflection suppressor.

[0040] In embodiments, each DTFS meta-unit cell is defined by parameters including a first slot apex length L2, a second slot apex length L1, and a gap length G, wherein the parameters are selected to optimize transmission contrast for a predetermined wavelength range.

[0041] In embodiments, a photonic platform comprises one or more lasers configured to emit a laser signal; one or more photonic integrated circuits positioned to receive the laser 2101715-001300

[0042] - 5 -

[0043] signal; and a back -reflection suppressor disposed between the one or more lasers and the one or more photonic integrated circuits.

[0044] In embodiments, the metalens comprises an asymmetric metalens integrated into a grating coupler.

[0045] BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Aspects of the invention may be best understood from the following detailed description when read in connection with the accompanying drawings, with like elements having the same reference numerals. When a plurality of similar elements are present, a single reference numeral may be assigned to the plurality of similar elements with a small letter designation referring to specific elements. When referring to the elements collectively or to a non-specific one or more of the elements, the small letter designation may be omitted. In addition, according to common practice, the various features of the drawings are not drawn to scale unless otherwise indicated, and the dimensions of the various features may be expanded or reduced for clarity. Included in the drawings are the following figures:

[0047] FIG. 1A depicts a unit cell of the asymmetric metasurface defined on silicon-on- insulator (SOI) substrate as described herein.

[0048] FIG. 1B depicts an asymmetric metasurface with one-side tapered slots, according to an exemplary embodiment.

[0049] FIG. 1C depicts an asymmetric metasurface with double-flipped taper slots, according to another exemplary embodiment.

[0050] FIG. 2A depicts an asymmetric transmission mechanism with diffraction mode conversion for the single tapered structure of FIG. 1B.

[0051] FIG. 2B depicts an asymmetric transmission mechanism with diffraction mode conversion for the double tapered structure of FIG. 1C.

[0052] FIG. 3 depicts a scanning electron microscope top view image of the asymmetric metasurface of FIG. 2B and a grating coupler as described herein.

[0053] FIG. 4 is an enlarged image of the example asymmetric metasurface of FIG. 2B. FIG. 5 depicts the unit cell geometry of the example asymmetric metasurface of FIG. 3. 2101715-001300

[0054] - 6 -

[0055] FIG. 6 depicts unit cell parameter optimization of the example asymmetric metasurface of FIG. 3.

[0056] FIG. 7 depicts fine-tuning of the unit cell geometry of the example asymmetric metasurface of FIG. 3 for achieving high contrast asymmetric coupling.

[0057] FIG. 8A depicts high contrast power transmission with phase varying asymmetric metasurface implemented in a tapered multi-mode waveguide.

[0058] FIG. 8B depicts suppression of back reflection with and without asymmetric metasurface.

[0059] FIG. 8C depicts a backscattering reflection spectra with and without asymmetric metasurface.

[0060] FIG. 9A depicts angle-sensitivity of the back-excited transmission in the forward and backward transmission spectra.

[0061] FIG. 9B depicts angle-sensitivity of the excitation schematics,

[0062] FIG. 9C depicts angle-dependent forward transmission spectra.

[0063] FIG. 9D depicts angle -dependent backward transmission spectra.

[0064] FIG. 9E depicts transmission for forward and reverse excited waves with tilting angle to the normal incidences.

[0065] FIG. 10 depicts a device implementation of the example asymmetric metasurface of FIG. 3.

[0066] FIG. 11A depicts optical field intensity along the monitors across the example asymmetric metasurface of FIG. 10, with forward and backward excitations.

[0067] FIG. 11B depicts a top view of the asymmetric metasurface of FIG. 10 embedded in a tapered multi-mode waveguide (top), optical mode profile (real part of the electric field) with forward (middle, light ray superimposed on the field distribution), and backward (bottom) excitation of the fundamental mode.

[0068] FIG. 11C depicts simulated and measured transmission.

[0069] FIG. 11D depicts reflection with the excitations of the fundamental modes, compared to the experimentally measured reflection. 2101715-001300

[0070] - 7 -

[0071] FIG. 12A depicts a step coupler-based mode-size converter, with an embedded asymmetric metasurface.

[0072] FIG. 12B depicts a full-field simulation of the forward excitation in the tapered multi-mode waveguide.

[0073] FIG. 12C depicts a backward excitation in the tapered multi-mode waveguide. FIG. 12D depicts a high contrast asymmetric transmission with the step coupler of FIG. 12A.

[0074] FIG. 12E depicts integration of an embedded asymmetric metasurface with an exemplary taper.

[0075] FIG. 12F depicts the electric field distribution that indicates coupling to radiation, which results in high insertion loss and low coupling efficiency to the output waveguide.

[0076] FIG. 12G depicts that high reflection remains the same as the step coupler of FIG.

[0077] 12A.

[0078] FIG. 12H depicts ray-optic illustration of the mode-dependent insertion loss in the waveguide taper.

[0079] FIG. 12I depicts inverted relation on the asymmetric transmission after integration with a 20 μm long tapered coupler.

[0080] FIG. 12J depicts experimental results for asymmetric metasurface with longer tapers and single mode waveguides inputs and outputs, exhibiting symmetric transmission.

[0081] FIG. 13 A depicts an apparatus for measuring the reflection from a low refractive index contrast silicon nitride integrated photonic platform with two ports.

[0082] FIG. 13B depicts a schematics and optical microscope image of the middle region of the metasurface,

[0083] FIG. 13C depicts simulated reflection profile in the tapered multi-mode waveguide without impacts from the taper,

[0084] FIG. 13D depicts measured reflection with forward (RF) and backward (RB) excitations.

[0085] FIG. 13E depicts measured reflection contrast with geometric offset. 2101715-001300

[0086] - 8 -

[0087] FIG. 13F depicts a second device under test DUT2 on the same chiplet, visualizing the asymmetric reflection.

[0088] FIG. 13G depicts a top view on a near-infrared camera with forward excitation of 1480 nm CW light.

[0089] FIG. 13H depicts that the reflected light is identified with the backward excitation. FIG. 14A depicts unit cell simulation of geometric offsets with five different offsets with a 10 nm spacing.

[0090] FIG. 14B depicts unit cell simulation of geometric offsets with forward transmission.

[0091] FIG. 14C depicts unit cell simulation of geometric offsets with backward transmission.

[0092] FIG. 14D depicts unit cell simulation of geometric offsets with transmission contrast according to the offsets.

[0093] FIG. 15A illustrates the dependence of power transmittance contrast versus taper length in a full-field simulation of the electric field distribution (Ey) within a tapered multi-mode waveguide.

[0094] FIG. 15B illustrates the dependence of power transmittance contrast versus taper length from a single mode waveguide to a tapered multi-mode waveguide.

[0095] FIG. 15C illustrates the transmittance for forward and backward excitations without a taper as shown in FIG. 15A.

[0096] FIG. 15D depicts the transmittance for forward and backward excitations for a short taper (20 μm extended taper length) as shown in FIG. 15B.

[0097] FIG. I5E depicts the transmittance for forward and backward excitations for a long taper (40 μm extended taper length).

[0098] FIG. 16 depicts Y junction characterization versus geometric offsets on a Silicon Nitride (SiN) wafer.

[0099] FIG. 17 depicts an exemplary fabrication process of an asymmetric metasurface, according to an embodiment. 2101715-001300

[0100] - 9 -

[0101] FIG. 18 depicts a cross-section of an asymmetric metasurface, according to an embodiment.

[0102] FIG. 19 depicts details and notes regarding the exemplary fabrication process of FIG. 17.

[0103] FIG. 20 depicts an asymmetric metasurface integrated into an optical coupler, according to an embodiment.

[0104] FIG. 21 depicts an integrated asymmetric metasurface and waveguide footprint, according to an embodiment.

[0105] DETAILED DESCRIPTION OF THE INVENTION

[0106] The systems, methods, and devices disclosed herein are suitable for use in manufacturing and producing integrated photonic circuits. Integrated photonics implement complex photonic systems in small chips or chiplets, including optical trapping, biosensing, quantum optics, and optical phase arrays for free-space beam steering. As the critical on / off-chip interface, many efforts have been dedicated to improving the performance of optical couplers. The disclosed examples are capable of achieving near unity coupling efficiency in association with grating couplers, simultaneously achieving a desired beam shape, low insertion loss, and target operation wavelength.

[0107] The disclosed examples may be suitable for improving existing manufacturing processes for these circuits, e.g. from the standpoints of costs, reliability, yield, or throughput. The disclosed examples may further result in photonic semiconductor chips having wider fields of view, higher coupling efficiencies, or lower insertion loss and back reflection, for example. These examples may improve on conventional photonic chips by enabling faster or easier signal transfer or communication.

[0108] The disclosed examples may have applications in a number of fields including, for example, photonic systems across a broad range of power requirements, from distributed gain LiDAR, complex photonic computing architecture, and few-photon quantum communication to high-power RF-photonic remote sensing, etc. Other applications for the discloses systems and methods will be apparent from the description herein. 2101715-001300

[0109] - 10 -

[0110] Metasurface has emerged as a platform for controlling light at subwavelength thickness, enabling new functionalities for imaging, polarization manipulation, and angular momentum conversion w ithin a flat surface.

[0111] Introducing the phase non-uniformity and discontinuity in single and multi-layer metasurface allows the exploration of many physical phenomena. Parallel to the time¬ domain modulation of non-Hermitian photonic systems, parity-symmetry can be engineered through the subwavelength taper along the direction of light propagation. Simple gliding and offsets between double-layer metallic metasurface can enhance sensing through plasmonic exceptional points. Relative rotation at a magic angle can engineer the level of light localization and the formation of photonic Moire lattices, and hyperbolic surface. Stacking multi-layer meta-structure with a specific time reversal symmetry design variation along the direction of out-of-plane incident wave can construct photonic topological isolator metacrystal, Hofstadter butterfly, and topological edge states. In guided wave circuits, more sophisticated and finely adjusted geometric variations along the wave’s propagation direction can be introduced through one-step lithography. Tilted meta structures can lead to low loss and low crosstalk mode conversion in dielectric waveguides and surface plasmon polaritons. Inverse-designed integrated metalens with nanoscale topology optimization can trim the wavefronts for highly efficient mode conversion.

[0112] The embodiments described herein explore the feasibility of asymmetric coupling and transmission between forward and backward propagating modes with a waveguide interface, which may simplify the circuit design complexities used for ion trapping, recurrent photonic neuron networks, and high-power RF -photonic systems.

[0113] Asymmetric meta-atoms in free-space optics, typically with broken in-plane symmetry, can support high Q resonance through symmetry-protected bound states in the continuum, provide arbitrary polarization and phase control, or angular momentum conversion. The combination of bound states in the continuum (BIC) with asymmetric structures enables the manipulation of polarization, leading to asymmetric or unidirectional radiation. In symmetric BIC structure, light typically exhibits linear polarization (LP), which limits polarization diversity. However, breaking the structural symmetry enables the generation of circular polarization (CP), thereby enhancing diversity of polarization.

[0114] Furthermore, introducing twisting or rotational bilayer structures can create asymmetric CP 2101715-001300

[0115] states, amplifying the asymmetric radiation response and further enriching the polarization characteristics.

[0116] Engineering the non-Hermiticity of metasurface and their complex eigenvalues through phase gradience allows the directional coupling of the input light to the radiation channels. The broken spatial parity symmetry leads to distinguished transmission between normally incident forward and backward waveguide channels near the phase singularities in a complex plane,

[0117] The examples disclosed herein focus on introducing asymmetry along the direction of propagation, named phase gradient asymmetric metasurface. With the wave traveling along the direction of broken symmetry, the out-of-plane broken symmetry can simultaneously achieve high transmission and high backward reflection. In the slab or multi-mode waveguides, the control of optical power flow replicates the unidirectional current valve enabled by an electronic diode (FIG. 1A and FIG. IB). Phase-varying asymmetric metasurface allows the asymmetric phase shift for the forward and back -excited modes. The unit-cell level longitudinal asymmetry is critical forbroadband and low-loss transmission while keeping nearly unit reflection for the back-reflected light.

[0118] lire disclosed examples also demonstrate how the compact passive back reflector can be applied to suppress the broadband back reflections from the random backscattering from material nonun iformity or surface roughness.

[0119] In one example, an integrated asymmetric metasurface can simultaneously achieve broadband, low-loss forward power transmission, and back reflection suppression in the tapered multi-mode waveguide. The geometric asymmetry between the bilayers leads to low-loss conversion from the fundamental to high-order modes. The integrated asymmetric metasurface 300 can be defined as having a footprint with a footprint length along the y-axis direction a footprint width along the x-axis direction, as illustrated in FIG. 21. Enhanced by a double-flipped structure, an exemplary metasurface may have an overall footprint length (see FIG. 21) varying from 2.5 pm (metalens footprint length Lmalone, in embodiments without a waveguide footprint taper) to 22.5 pm - 42.5 pm (including a waveguide footprint taper length Lwtin the range of 20 pm - 40 pm) can simultaneously achieve high conversion efficiency (>80%), and back -reflection efficiency of 90% over a 200 nm wavelength range. Broadband, low-loss, and single-side reflectors can be enabling components of gain- integrated adaptive optics on chips. 2101715-001300

[0120] - 12 -

[0121] A phase-varying asymmetric metasurface can allow the asymmetric phase shift for the forward and back -excited modes. Asymmetric power transmission and momentum transfer can be achieved through one-side tapering of the slot width (FIG. 1A). The transmission contrast increases with geometric contrast (W1AV2) of the slot taper (FIG. IB), which introduces the phase modulations and breaks the spatial parity-symmetry in the metasurface. The forward transmission spectra are not sensitive to W1 / W2, but broadband transmission suppression (up to 6.7 dB contrast) can be achieved with backward excitation.

[0122] Such contrast can be significantly enhanced with a second flip-faced trapezoidal slot of asymmetric metasurface (FIG. 1 C). Hie formation of a resonant mode traveling in the transverse direction reflects the back -excited incoming light (from port to) through interference. Geometry-enabled asymmetric coupling coefficients to the transverse traveling guided mode can enhance the transmission contrast up to 25dB. The asymmetric metasurface converts the incoming fundamental mode to a high-order mode. With reverse excitation through the single-mode waveguide, the asymmetric metasurface is expected to reflect most of the normal incident wave. The significant difference in transmission contrast capability' between the single- and double-tapered structures lies in the topological role of the smaller tapered structure. Hie simulated phase profile shows that the smaller tapered structure transforms the sinusoidal phase profile into a square-wave (binary) phase profile, which is a crucial mechanism for mode conversion from the zero-order mode to a higher-order mode in the forward direction (FIG. 2A and FIG. 2B). Based on the equation, the single-tapered structure cannot eliminate the zero-order mode, whereas the double¬ tapered structure can achieve this by realizing a TZ phase difference. However, the double¬ tapered structure described herein can effectively minimize backward transmission by eliminating the zero-order mode m forward excitation, thereby achieving asymmetric transmission in the reciprocal system.

[0123] Additional advantages of the disclosed examples will be apparent from the description herein.

[0124] With reference to the drawings, FIG. 3 illustrates a scanning electron microscope image of an example asymmetric metasurface-based metalens 300 and a grating coupler 2101715-001300

[0125] - 13 -

[0126] The metasurface 300 has a footprint length of 2.5 pm, but the invention is not limited to any particular dimension. It can integrate a taper waveguide, e.g., taper length of 20 pm or 40 pm, without limited taper length.

[0127] The metasurface 300 is configured to simultaneously achieve a conversion efficiency of over 80% and a back-reflection efficiency of 90% over a 200 nm wavelength range.

[0128] " Die asymmetric metasurface 300 is defined by an array of double-flipped taper slots (DFTS) cells 304. The asymmetric metasurface 300 is defined by an arrangement of the first slots 306 having their respective bases distributed across a curve that is concave (viewed in the forward direction, as shown in the left portion of FIG. 3) with the respective truncated apexes linearly aligned (e.g., the relative lengths of the slots 306 located in a central region of the metalens are shorter than on those of the slots located on the outer edges). The bases of the second slots 310 are linearly aligned parallel and spaced in the forw ard direction from the linear alignment of the truncated apexes of the first slots 306, with the apexes of the second slots 310 linearly aligned parallel and spaced in the backward direction from the linear alignment of the truncated apexes of the first slots 306. The invention is not limited to any particular arrangement of the bases of the first slots, which may be linearly aligned (e.g., as depicted in FIGs. IB, 1C), or may be aligned along a convex curve (e.g., as depicted in FIG. 3). The geometric alignment (e.g., linear or curved) of the bases of the slots may be dictated by the geometry of the waveguide, as is known in the art.

[0129] The metasurface 300 is asymmetric along the direction of propagation, with the taper length kept within the dimension comparable to the effective wavelength in the media. The forward and backward excited waves experience different phase shifts. Arrays of meta-units (e.g., silicon oxide void) in silicon photonics can be used to control wavefronts with low' insertion loss.

[0130] As illustrated in FIG. 3, the metasurface 300 includes a plurality of DFTS meta-unit cells 304. Each of the slots of the DFTS meta-unit cells 304 is defined as a silicon void.

[0131] Each of the DFTS meta-unit cells 304 is implemented using a double-flipped slot taper slot structure composed of ahigh-refractive-mdex dielectric material. Each of the DFTS meta-unit cells 304 includes at least one first slot 306 having a taper 308 facing a first direction (e.g., pointing in a forward excitation direction) on one side of the first slot 306. As shown, first slot 306 has a hexagonal geometry' with a generally rectangular base defined 2101715-001300

[0132] - 14 -

[0133] by three vertices that define two right angles and a trapezoidal top defined by three vertices that intersect with one another to form the taper 308. As showm in FIGs. 3, 5, and 7, the geometry of the first slots 306 can be defined by a IF, Lrect, L2, and FKj. Each of the DFTS meta-unit cells 304 also includes at least two second slots 310, each having a trapezoidal shape that approaches an isosceles triangular geometry with an apex 312 facing the opposite direction (i.e., pointed in a backward excitation direction), and disposed adjacent opposite sides of, taper 308 of the at least one first slot 306. As shown in FIGs. 3, 5, and 7, the trapezoid defined by slot 310 can be characterized by dimensions fiG, Wn>and Li. As referred to herein, the “base” of the second slot 310 is defined by the forward-most vertex 504 (FIG. 5) and the apex 312 of the second slot 310 is defined by the intersection of the backward-most vertices 506a and 506b.

[0134] As shown in FIG. 3, the apex 312 of each second slot 310 faces the gap between two adjacent first slot tapers 308 of two first slots 306. In other words, the apex 312 of each second slot 310 is arranged between two first slot tapers 308 of two first slots 306, and each first slot taper 308 is disposed between two apexes of adjacent second slots 310. Each combination of a first slot 306 disposed between adjacent second slots 310 constitutes a LIFTS cell 304. lire first and second slots may form a continuous array, with some (or most) second slots 310 comprising a portion of two adjacent DFTS cells 304.

[0135] Tire first slot 306 has a total length between 11 to 0.5 pm, and the taper 308 has a length of 20 um considering the focal length.

[0136] This double-tapered structure can effectively minimize backward transmission by eliminating the zero-order mode in forward exci tation, thereby achieving asymmetric transmission in the reciprocal system.

[0137] In addition, the insertion loss, phase shift, and asymmetric transmission can be optimized through the parameters in the unit cell 304 of double-flipped taper slots 306 and 310, including the width (W) of the rectangular base of the first slot 306, the widths of the tapers (Wm, Wn), inter-taper gap (G), gap (G2) between the first slots 306 (FIG. 3), and the length of each taper (LI, L2), as illustrated in FIGs. 3 and 5, for example.

[0138] In a non-limiting embodiment, the first slot 306 may have a base width W of 751 nm, for example, and the gap G2 between the first slots 306 (FIG. 3) may be 47 nm, for example. 2101715-001300

[0139] - 15 -

[0140] Turning now to FIG. 5, each second slot 310 can include a taper 312 on one side of the second slot 310.

[0141] In a non-limiting embodiment, the second slot 310 may have a base width Wm of approximately 0.3 pm (or 396 nm), for example, and a width Wn of the taper 312 of 0.15 pm, for example.

[0142] Tn a non-limiting embodiment, the inter-taper gap G between a start point 502 of the taper 308 of the first slot 306 and the apex 312, or the end of the taper 312, of the second slot 310 can be 0.46 pm, for example.

[0143] Transmissions with forward (TF) and backward (TB) excitations can be carefully mapped against these design parameters (FIG. 6 and FIG. 7). The back reflection (or the transmission contrast TF / I'B) is most sensitive to the distance between the double-flipped slot tapers. After fine-tuning the geometries, transmission contrasts up to 50 dB can be achieved within the tens of nm range. The operation wavelength range can be effectively controlled by varying the parameters G. The present inventors have verified that such transmission contrast is insensitive to the length Lrect (FIG. 5 and FIG. 7) of the rectangular portion of the slots 306, so Lrect can be varied to introduce phase gradience for the output wavefront. The simulation shows that optimal 55 dB transmission contrast can be achieved using the parameters Wm: 0.3 pm, Wn: 0.15 pm, G: 0.46 pm.

[0144] Achieving asymmetric or directional light transport does not necessarily require breaking reciprocity, as reciprocal systems can exhibit asymmetric responses through careful structural design in the presence of multimode channels (FIG. 8A). As an illustration, the back reflection in a tapered multi-mode waveguide can be compared wdth and without the optimized structure of the double-flipped asymmetric metasurface. Circular scatterers with random sizes and positions are placed in the waveguide, which leads to 50% reflection over a broad range of wavelengths (FIG. 8C). With the asymmetric metasurface, the broadband reflection from the random scatterers were reduced to be less than 10% across the 300 nm wavelength in near infrared (FIGs. 8B-8C). These scatterers randomly deflect light in different directions. A separate set of numerical simulations was performed to obtain the incident angle dependent forward and backward transmission (FIGs. 9A-9E). The backward excited transmission reduces wdth incident angle. Within ±10° of incidence, backward excited transmission is kept below -lOdB while forward transmission remains high (FIG. 9E). 2101715-001300

[0145] - 16 -

[0146] To establish a theoretical foundation for asymmetric transmission, a two-port system was considered where each port supports multiple diffraction orders due to the periodicity of the metasurface. Acting as a diffraction grating, the metasurface 100 described herein couples light into the zero-order mode (m ------ 0), referred to as Mode A, and the first-order diffraction modes m = ±1), collectively represented as Mode B. The scattering matrix of such a system can be expressed with the following equation [1]:

[0147] s-BE =

[0148] ^12 i

[0149] sA?

[0150]

[0151] 5SS

[0152] where the subscripts denote the port number, and the superscripts denote the mode number.

[0153] Reciprocity requires that "

[0154]

[0155] “, and energy conservation requires that

[0156]

[0157] where is the unitary matrix.

[0158] If the system is excited from Port-1 with Mode-A, the output power measured only J • AA 1 “

[0159] at Port-2 becomes

[0160]

[0161] . On the other hand, if the system is excited in tire opposite direction from Port-2 with the same Mode-A, the output power measured only at Port-1 SrA i " y ™ ^AA

[0162] becomes

[0163]

[0164] ;'rk-'1, Reciprocity requires that 'TS ’ “St., however, in the absence of mirror symmetry along the longitudinal direction,

[0165]

[0166] maybe different than wA. As a result, one can maximize the “asymmetric response” of a reciprocal system by setting

[0167] ,-A&.......,-x

[0168] -‘i:i wi "■which, together with the reciprocity condition, gives the following scattering matrix:

[0169]

[0170] 2101715-001300

[0171] - 17 -

[0172] The efficiency of this system can be further improved by setting

[0173] Bi? ^AB? <^i? B:0

[0174]

[0175] , which would result in the following scattering matrix for a reciprocal and lossless system with an ideal asymmetric response:

[0176] 0 1]

[0177] 8

[0178] 1

[0179]

[0180] 0 el

[0181] 5 In this ideal scenario, if Mode-A is injected into Port-1, it will be completely converted into Mode B at Port-2. On the other hand, if Mode-A is injected into Port-2 it will be completely reflected as Mode-A at Port-2.

[0182] With this optimized unit cell geometry in mind, the metasurface 100 was integrated into a tapered multi-mode waveguide defined on 250 nm silicon-on-msulator (SOI) io substrate (FIG. 3, FIG. 10). Patterns with a set of geometric offsets (in the step of 10 nm, considering the minimum resolution of 7 nm of the E-beam lithography) are included in the layout to compensate for fabrication variations. The right inset of FIG. 3 illustrates the details of the fabri cated metasurface with fine structures, with critical di mensions around 50 nm. With the fundamental mode excited in the 10pm wide waveguide, full field simulation is captures the in-plane field distribution with excitations from forward (port 1) and backward (port 2) excitations (FIGs. 1 IB-11 C). FIG. 11A compares the cross-sectional profile across the waveguide, for the input (black), forward transmitted (orange) and back -excited transmited (purple) modes. FIG. 1 IB indicates that, under forward excitation, the diffracted beam undergoes total internal reflection at the facet and propagates within the co multimode waveguide. In contrast, under backward excitation, the beam is reflected at the metasurface, effectively suppressing backward transmission. The transmitted and reflected power spectra are illustrated in FIGs. 11C-1 ID (with monitors marked in FIG. 1 I B). The reflected spectra were experimentally verified, as the fundamental mode propagation is not susceptible to taper or coupler designs (detailed in FIGs. 12A-12J).

[0183] 25 Another set of devices were implemented on a lower refractive index contrast silicon nitride platform (FIG. 13 A). FIG. 13A depicts an apparatus for measuring the reflection from a low refractive index contrast silicon nitride integrated photonic platform with two ports, FIG. I3A illustrates the test bed with an optical microscope image of a device under 2101715-001300

[0184] - 18 -

[0185] test (DUT1). The apparatus measures the reflection from the device with two ports. P / C: polarization controller. The two-port devices (device under test DUT1 ) are two grating couplers connected to the double-flipped metasurface, with geometry optimized for wafer¬ scale manufacturing of silicon nitride. The zoom-in image of the metasurface in a tapered 5 multi-mode waveguide is illustrated in FIG. I3B, showing forward (Rp) and backward (RB) excitations. The design with full-field simulation of the mode profile in the waveguide was verified, with independent excitations for forward (orange) and backward excitations (purple) (FIGs. 13B-13C). Opposite to the transmission results, the reflection monitor confirmed that the reflected mode remains the fundamental mode with backward excitations io (FIG. 13C), and forward reflection is minimal. Experimentally, clear and consistent results were observed for asymmetric reflection (up to 8 dB, with 20 nm geometric offsets). Four sets of devices with identical design but different geometric offsets (-40, -20, 0, and 20 nm) were compared (FIG. I3E). To visualize such asymmetric reflection, another set of devices was fabricated with destinated reflection ports connected to vertical couplers (FIG. 13F).

[0186] ■ 5 With forward excitation from port 1 on the left, no reflection was observed under top imaging infrared camera (FIG. 13G), while the back reflection leads to noticeable reflections (FIG. 13H), even with additional loss through the couplers. The loss of each coupler was carefully evaluated and compared across devices and verified to be approximately 8dB,

[0187] 0 Numerical simulation was also performed of the design’s sensitivity to fabrication variation. Five different offsets were set up to 40 nm, as illustrated in FIG. 14A. These offsets have a limited impact on the forward transmission coefficient, with a range of -0.2 dB to -3 dB in the wavelength range of 1300-1600 nm (FIG. 14B). However, the offsets reduce the highest contrast for backward transmission. Given 40 nm geometric offset, the 5 transmission dtp is still below ~35dB, indicating more than 98% of backward excited light was reflected (FIG. I4C).

[0188] To extend the utility of the proposed structure, a coupler and interface to the single¬ mode waveguides or waveguides with different dimensions was studied (FIGs. 12A-12J), Two types of couplers (step couplers and conventional taper structures) were considered tor o converting mode A or B to the output waveguide. Simultaneous high forward transmission and high backward reflection can be translated from the metasurface level to the integrated photonic device level with step couplers (FIGs. 12A, 12C, FIG. 12D). The forward 2101715-001300

[0189] - 19 -

[0190] transmission (converted to mode B) experiences high propagation ioss in the taper converter / coupler (FIG. 12F), while high reflection remains the same with alternative taper designs (FIG. 12G). The present inventors analyzed the mode-dependent insertion loss in taper in FIG. 12H. The incident angle on the boundary of the tapered multi-mode waveguide stays beyond the critical angle at the first interface (FIGs. 12B, 12F); however, the relative incident angle reduces as the wave propagations along the taper, eventually coupling to the lossy / leaky wave, 'the conventional taper design cannot deliver asymmetric power transportation to the integrated photonic device level, as the component loss of the taper is also highly asymmetric (FIGs. 121, 12.1). Additional simulation of the taper design- dependent transmission is provided in FIGs. 15A-15E.

[0191] With optimized topologies and phase matching, the present inventors implemented asymmetric transmission on the integrated photonic platform using a phase-vary ing asymmetric metasurface. The asymmetric power transmission, insertion loss, and reflection contrast are enhanced with flipped bilayers. The forward insertion loss and back reflection improved from 1.5 dB and 70% for single layer to 0.96 dB and 80% for bilayers. The performance was consistent over 200 nm in the telecommunication C band. Following the reciprocity, the low loss forward transmission was achieved by converting the incident fundamental mode to the high order mode, while the high reflection applies to the back- excited fundamental mode. Meanwhile, a diffractive focused beam was induced by metalens integration. This can be utilized in far-field beam engineering, such as beam shaping and steering applications, or in on-chip optical interconnects by enhancing signal coupling efficiency within compact waveguide arrays between integrated photonic devices.

[0192] The device concept described herein was experimentally implemented on both silicon and si licon nitride platforms, and demonstrated the effecti veness of the proposed concept by comparing the reflection contrast and insertion loss over a broad range of wavelengths. The strong backward reflection through port 2 remains the same mode as excitations, as thus conventional taper designs are sufficient to validate asymmetric reflection. However, conventional taper design introduces additional loss for the forward transmitted high order mode. To maintain the low insertion loss of the forward transmission, a step-coupler may be involved to modify the mode size. 2101715-001300

[0193] - 20 -

[0194] Table 1 below summarizes the on-chip asymmetric responses achieved with metasurface. Most metasurface works focus on slow-varying geometric parameters (e.g., metalenses) for spot size modification. Tapering or tilting the symmetric metasurface enables mode conversions in multi-mode wavelengths. The footprint and effective length of the device can be minimized with phase-varying asymmetric metasurface design.

[0195] Table 1. Metasurface-based mode / mode size converters

[0196] Meta-unit | Length Reflection Loss Structnre / Materiais Function BW / hi contrast

[0197] 300 nm / Asymmetric 2pm u -6.5 dB

[0198] ■> D p.iel |ectri •c high order i 5dB

[0199] 1550 nm 1 mocic

[0200] Double- |

[0201] -20 dB 200 nm / flipped 2.5pm

[0202] <,-> r Dvie i highor^'-'r0.96dB lectric - -55 dB 1550 nm asymmetric | i moac

[0203] Gradient ' " i Fund. 100 nm / high order -20 dB 3dB symmetric 20pm

[0204] 2400 nm i’iasmoiuc mode ' I16! 1

[0205] Tilted ' Fund. <-->

[0206] >20 nm high order <ldB symmetric 5 pm None

[0207] Z1550nm '

[0038] Dielectricraode

[0208] HHk Fundamental

[0209] 2.00 nm / Symmetric..- lopm jiiilib mode size None 1 dB 1550nm DiJcu'*c conversion

[0210] HiShorder 200 nm / Symmetric

[0211] <0.4dB Nonevmode size

[0212] 1550 nm ' 136JJ°M‘"

[0213] .., conversion

[0214] D’clecii? I

[0215] Fund.

[0216] NA / Symmetric ~~

[0217] z2. pm i high order l.ldB None

[0218]

[0037] 1550nm Dielectric mode

[0219]

[0220] Fund.: fundamental mode

[0221] No backward transmission degradation occurred in a rectangular slab structure with infinite waveguide taper length (i.e., no waveguide taper) (FIGs. ISA); however, spherical waves propagated in the tapered waveguide depicted in FIG. 15B, because the waveguide taper length was too short to propagate as a plane wave. As a result, the short waveguide taper leads to higher transmission with backward excited waves (FIGs. 15C-15E). Therefore, tire present inventors determined that incorporating the metalens with an appropriate focal length can balance the insertion loss and device footprint. For example, in 2101715-001300

[0222] an embodiment emphasizing compactness of the structure, an appropriate waveguide footprint taper length Lwt (FIG. 21) may be 20 pm, whereas if transmission performance is emphasized, a waveguide footprint taper length Lwtof 40 pm may be preferable. As one benefit of the structure disclosed herein incorporating both the first slots 306 and second 5 slots 310 is that acceptable results can be achieved with structures having a waveguide footprint taper length Lwr in the range of 20-40 pm, whereas without second slots 310, waveguide footprint taper lengths in the range of 150-200 pm may be needed to achieve equivalent perform ance.

[0223] Compared to other metasurface base structures, the subwavelength asymmetry io allows low loss, broadband and compact mode conversion, brings the unique function of unidirectional reflection in tapered multi-mode waveguides. The demonstrated device design can be integrated with chip-scale amplifiers and lasers, and thus find applications in photonic sy stems across a broad range of power requirements, from distributed gain LiDAR, complex photonic computing architecture, few-photon quantum communication to ■ 5 high-power RF-photonic remote sensing.

[0224] Turning back to FIG. 3, a semiconductor chip 314 includes at least one optical coupler 302 formed on a surface of the semiconductor chip 314 and an example asymmetric metasurface-based metalens 300. The optical coupler 302 can be a grating coupler.

[0225] The optical coupler 302 can be fabricated on a silicon-on-insulator (SOI), with, e.g., 0 a 250 nm high-refractive index dielectric layer, such as a silicon layer or a silicon nitride layer, for example, and a 3 pm core layer, such as silicon dioxide layer, as illustrated in FIG. 18, for example. For purposes of this disclosure, a “high-refractive index dielectric layer” means a dielectric layer designed to reflect light at angles greater than 45 degrees.

[0226] FIG. 17 depicts an exemplary fabrication method of designing an asymmetric 5 metasurface, according to an embodiment.

[0227] The method includes a step 17a of sample preparation using a high-refractive index dielectric layer, a photoresist layer, and a core layer. The high-refractive index dielectric layer can include a silicon layer or a silicon nitride layer, for example. The core layer can include a silicon dioxide layer, as illustrated m FIG. 18, for example. 2101715-001300

[0228] - 22 -

[0229] The method includes a step 17b of depositing a layer of photoresist onto a substrate comprising a high -refractive index dielectric layer disposed over a core layer.

[0230] The method further includes a step 17c of exposing the layer of photoresist using electron beam lithography in accordance with a pattern corresponding to features of the asymmetric metasurface. The pattern can define at least one first slot having a first slot taper facing a first direction on one side of the at least one first slot.

[0231] The method further includes a step of developing the patterned photoresist to define openings (e.g., open windows) in the photoresist corresponding to the pattern corresponding to features of the asymmetric metasurface.

[0232] The method further includes performing a dry etching step 17e to define openings in the high-refractive index dielectric layer corresponding to the openings in the photoresist. In certain exemplary non limiting embodiments, the dry etching step 17e can be an Inductively Coupled Plasma (TCP) dry' etching, for example.

[0233] The method further includes a step 17f of stripping the photoresist and a step 17g of depositing a cladding layer over the high-refractive index dielectric layer and filling the openings therein.

[0234] In certain exemplary non limiting embodiments, the pattern corresponding to features of the asymmetric metasurface can further comprise a plurality of second slots, each second slot having a trapezoidal shape with an apex facing a second direction opposite the first direction, the plurality of second slots disposed on opposite sides of the first slot taper of at least one first slot of the plurality of first slots, each combination of a first slot and two second slots defining a double-flipped taper slots (DFTS) meta-unit cell.

[0235] In certain exemplary non limiting embodiments, the asymmetric metasurface can be a component of a waveguide. The exemplary fabrication method of designing the asymmetric metasurface further includes tuning the dimensions of the DFTS meta-unit cells to optimize transmission index contrast for suppression of back excited light contrast for a predetermined wavelength range,

[0236] FIG. 18 depicts a cross-section of an asymmetric metasurface, according to an exemplary' non limiting embodiment. As illustrated in FIG. 18, exemplary non limiting dimensions of the asymmetric metasurface can include a 3 pm core layer, such as silicon 2101715-001300

[0237] - 23 -

[0238] dioxide (SiO2) layer, for example, a 0.25 pm (or 250 nm) high-refractive index dielectric layer, such as a silicon layer or a silicon nitride layer, for example, and a 0.91 pm cladding layer, such as silicon dioxide (SiO2) layer, for example, arranged over the high -refractive index dielectric layer and filling the etched openings therein. The openings are etched in the 250 nm high -refractive index dielectric layer, such as a silicon layer or a silicon nitride layer, for example.

[0239] FIG. 19 depicts details and notes regarding the exemplary fabrication process of FIG. 17, according to an exemplary' non limiting embodiment. As illustrated in FIG. 19, the process begins with cleaning the samples for 5 minutes in Pure strip, 5 minutes in Acetone, and 5 minutes in Isopropyl alcohol (IP A), and rinsing the samples in an 80°C water bath.

[0240] In certain exemplary non limiting embodiments, the process further includes exposing the layer of photoresist using electron beam lithography in accordance with a pattern corresponding to features of the asymmetric metasurface.

[0241] In certain exemplary' non limiting embodiments, the layer of photoresist can include a spin-coated photoresist by spinning ARP 6200.09 e-beam resist for 60 seconds at a 3,000 rpm until achieving a resist thickness of approximately 230 nm.

[0242] In certain exemplary non limiting embodiments, the process further includes baking for 5 minutes at a temperature of 170°C.

[0243] In certain exemplary' non limiting embodiments, the process further includes an Electron-beam lithography (EBL) exposure at a current of 0.1 nA and a dose higher than 180 pC / cm2 for less than 1 pm; and at a current of 10 nA and a dose higher than 180 pC / cm2 for more than 1 pm.

[0244] In certain exemplary non limiting embodiments, the process further includes developing the patterned photoresist to define openings in the photoresist corresponding to the pattern, for example, for 60 seconds in AR600-546, and an IP A rinse. After the developing step, the pattern is checked under a microscope.

[0245] In certain exemplary non limiting embodiments, the process further includes an etching step to define openings in the high-refractive index dielectric layer corresponding to the openings in the photoresist. 2101715-001300

[0246] - 24 -

[0247] In certain exemplar}' non limiting embodiments, the etching step can be a dry etching with fluoride-containing gases (F-ICP) that can be performed for 50 seconds.

[0248] In certain exemplary non limiting embodiments, the etching thickness can be approximately 250 nm (Silicon).

[0249] In certain exemplary non limiting embodiments, the process further includes stripping the photoresist. For example, the stripping of the photoresist can be performed for 20 minutes in an N-Methylpyrrolidone (NMP) solvent, followed by an IPA rinse and a 10 minutes Matrix Asher to remove unwanted residue in an 80°C water bath.

[0250] In certain exemplary non limiting embodiments, the process further includes depositing a cladding or protection layer over the high-refractive index dielectric layer for 11 minutes Plasma Enhanced Chemical Vapor Deposition (PECVD), followed by an IPA rinse until achieving a silicon dioxide (SiO2) layer with a thickness of approximately 910 nm.

[0251] FIG. 20 depicts an asymmetric metasurface integrated into an optical coupler, according to an exemplary’ non limiting embodiment, which is an enlarged view of the embodiment described above with reference to FIG. 3.

[0252] An exemplary Silicon Nitride (SiN) wafer with waveguide and metasurface were fabricated in the UCSB Nanofabrication Facility with Deep ultraviolet (DUV) lithography.

[0253] Methods

[0254] Device characterizations: A tunable laser source in the telecommunication C-band sends the TE polarized light to the on-chip grating coupler through a polarization controller and single-mode fiber. The output power was measured using the NEWPORT InGaAs photodiode (818-IG-L-FC / DB) and 1830-R optical power meter. For reflection measurement (FIGs. 11A-11E and FIGs. 13A-13H), an additional circulator was added between the polarization controller and the device. The additional port of the circulator was connected to the optical power meter. More details of the device fabrication and characterizations of the asymmetric power transmission are provided in the present inventors’ previous work H. Lee, A. Kecebas, F. Wang, L. Chang, S. K. Ozdemir, and T. Gu, Chiral Exceptional Point and Coherent Suppression of Backscattering in Silicon Microring with Low Loss Mie Scatterer. eLight 3 (1), 20 (2023). 2101715-001300

[0255] - 25 -

[0256] The fabrication offset sensitive Y junction insertion losses (methods) were characterized (FIG. 16) and subtracted from the total transmission to obtain the asymmetric metasurface-only response.

[0257] Numerical simulation-. The optical field profile, transmission, and excitation spectra were performed by the 3D finite-difference-time-domain method (FDTD). The simulation was conducted in three steps: unit cell structure, metalens structure, and metalens integrated tapered waveguide structure. For unit cell simulation, a silicon dioxide-based double¬ flipped slot taper slot structure was designed on the 250 nm thick Si layer in oxide. A pair of periodic boundary conditions were set in the x-axis direction to consider the metalens structure. A plane wave was used, and the direction of the electric field was set to be orthogonal to the periodic boundary' condition direction. Metalens was designed based on unit cell simulation. A Gaussian mode source was used, considering the SMF excitation, and the boundary conditions were set to a perfect matching layer (PML) to account for a free-space radiation environment. Finally, a metalens was integrated with waveguide simulation. Considering the sizes of the metalens and the waveguide, the present inventors employed an 11 pm to 0.5 pm waveguide footprint taper structure (i.e., tapering from a waveguide footprint width of 11 um to 0.5 m over length Lwt) with a waveguide taper length Lwtof 20 um, considering the focal length. The excitation source and boundary' conditions were set as Gaussian mode and PML boundary, respectively, consistent with the previous configuration.

[0258] Although the invention is illustrated and described herein with reference to specific embodiments, the invention is not intended to be limited to the details shown. Rather, various modifications may be made in the details within the scope and range of equivalents of the claims and without departing from the in vention.

Claims

2101715-001300- 26 -WHAT IS CLAIMED IS:

1. An asymmetric metasurface, comprising:a multilayer substrate comprising at least a high-refractive index dielectric layer disposed over a core layer; anda plurality of meta-unit cells, each of the plurality of DFTS meta-unit cells being defined as a void in the core layer and including:at least one first slot having a first slot taper facing a first direction on one side of the at least one first slot.

2. The asymmetric metasurface of claim 1, wherein the plurality' of meta-unit cells comprises a plurality of double-flipped taper slots (DFTS) meta-unit cells, each of the plurality of DFTS meta-unit cells including:the at least one first slot having the first slot taper facing the first direction on one side of the at least one first slot; andat least two second slots each having a trapezoidal shape with an apex facing a second direction opposite the first direction, the at least two second slots disposed on opposite sides of the first slot taper of the at least one first slot.

3. The asymmetric metasurface of claim 2, wherein the apex of each of the at least two second slots faces two first slot tapers of at least two first slots of the at least one first slot.

4. The asymmetric metasurface of claim 2, wherein each of the at least two second slots includes a second slot taper on one side of the second slot.

5. Tire asymmetric metasurface of claim 4, wherein each of the at least two second slots has a base width of 0.3 μm and a second slot taper width of 0.15 μm.

6. The asymmetric metasurface of claim 2, wherein an inter-taper gap between a start point of each first slot taper of the at least one first slot and each apex of the each of the at least two second slots is 0.46 μm.

7. Tire asymmetric metasurface of claim 1, wherein the plurality'' of meta-unit cells are arranged to define a metalens.2101715-001300- 27 -8. The asymmetric metasurface of claim 1, wherein the metasurface is arranged on a silicon-on-insulator (SOI) substrate with a silicon thickness of 250 nm and a lattice constant of 800 nm.

9. The asymmetric metasurface of claim 1, wherein each of the plurality of meta-unit cells comprises a silicon dioxide-based double-flipped slot taper slot structure arranged on a 250 nm thick silicon (Si) layer in oxide.

10. The asymmetric metasurface of claim 1, wherein the high-refractive index dielectric layer comprises a silicon layer or a silicon nitride layer.

11. The asymmetric metasurface of claim 1, wherein the core layer comprises a silicon dioxide layer.

12. The asymmetric metasurface of claim 1, wherein the metasurface is configured to simultaneously achieve a conversion efficiency of over 80% and a back- reflection efficiency of 90% over a 200 nm wavelength range.

13. The asymmetric metasurface of claim 1, wherein the metasurface is integrated into a tapered multi-mode waveguide arranged on a silicon-on-insulator (SOI) substrate.

14. The asymmetric metasurface of claim 13, wherein the tapered waveguide is tapered from a width of 11 pm to 0.5 pm over a waveguide taper footprint length Lwtin a range of 20 μm to 40 μm.

15. The asymmetric metasurface of claim 14, wherein the metasurface has a metasurface footprint length Lmof 2.5 μm.

14. A semiconductor chip, comprising:at least one optical coupler formed on a surface of the semiconductor chip; and the asymmetric dielectric metasurface of claim 1 connected to the at least one optical coupler.

15. The semiconductor chip of claim 14, wherein the at least one optical coupler is a grating coupler.2101715-001300- 28 -16. The semiconductor chip of claim 15, wherein the asymmetric dielectric metasurface is embedded between the grating coupler and a waveguide arranged on a silicon-on-insulator (SOI) substrate.

17. A method of designing an asymmetric metasurface, the method comprising the steps of:a) depositing a layer of photoresist onto a substrate comprising a high- refractive index dielectric layer disposed over a core layer;b) exposing the layer of photoresist using electron beam lithography in accordance with a pattern corresponding to features of the asymmetric metasurface, the pattern defining at least one first slot having a first slot taper facing a first direction on one side of the at least one first slot;c) developing the patterned photoresist to define openings in the photoresist corresponding to the pattern;d) performing a dry etching step to define openings in the high- refractive index dielectric layer corresponding to the openings in the photoresist;e) stripping the photoresist; andf) depositing a cladding layer over the high-refractive index dielectric layer and filling the openings therein.

18. The method of claim 17, wherein the pattern corresponding to features of the asymmetric metasurface further comprises:a plurality of second slots, each second slot having a trapezoidal shape with an apex facing a second direction opposite the first direction, the plurality of second slots disposed on opposite sides of the first slot taper of at least one first slot of the plurality of first slots, each combination of a first slot and two second slots defining a double -flipped taper slots (DFTS) meta-unit cell.

19. The method of claim 18, wherein the asymmetric metasurface is a component of a waveguide, further comprising tuning dimensions of the DFTS meta-unit cells to optimize transmission contrast for suppression of back excited light contrast for a predetermined wavelength range.2101715-001300- 29 -22. The method of claim 21, further comprising integrating the waveguide containing the asymmetric metasurface on a Silicon Nitride (SiN) wafer using Deep ultraviolet (DUV) lithography.

23. The method of claim 21, wherein the multi-mode waveguide is arranged on a silicon-on-insulator (SOI) substrate.

24. The method of claim 21, wherein tuning the dimensions of the DFTS meta-unit cells further comprises defining parameters including a first slot apex length L?, a second slot apex length Li, and a gap length G for each DTFS meta-unit cell.

25. An optical isolator comprising the metalens of claim 7.

26. The optical isolator of claim 25, wherein the optical isolator comprises a back -reflection suppressor.

27. The optical isolator of claim 26, wherein each DTFS meta-unit cell is defined by parameters including a first slot apex length L?, a second slot apex length Li, and a gap length G, wherein the parameters are selected to optimize transmission contrast for a predetermined wavelength range.

28. A photonic platform comprising:one or more lasers configured to emit a laser signal;one or more photonic integrated circuits positioned to receive the laser signal; and the back -reflection suppressor of claim 26 disposed between the one or more lasers and the one or more photonic integrated circuits.

29. The photonic platform of claim 28, wherein the metalens comprises an asymmetric metalens integrated into a grating coupler.

Images