Display panel and display apparatus

Abstract

The present application provides a display panel and a display apparatus. The display panel comprises a substrate, a first metal layer, a light-sensing unit, and a second metal layer. The first metal layer is arranged on the substrate, and comprises a first light shielding part. By means of configuring the first light shielding part to be connected to a constant voltage source, it is ensured that the potential of the first light shielding part is always in a stable state, preventing the potential of the first light shielding part from floating, and avoiding the problem of electrical noise caused by the floating potential of the first light shielding part.

Description

Display panel and display device

[0001] This application claims priority to Chinese patent application No. 202411655329.1, filed on November 19, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0003] With the rapid development of the panel display industry, the market demand for display panels with high functionality and high integration is constantly increasing. At present, ambient light and color temperature sensing functions are usually achieved through external sensors. The use of such external sensors requires additional installation space, which leads to a wider bezel of the display panel.

[0004] Photoelectric sensors can integrate the functions of ambient light sensors and color temperature sensors, and have the advantages of fast response speed, simple structure and high accuracy. In addition, photocurrent sensors can be directly integrated into the display panel or the inside of the device, thus effectively saving space. Invention Overview

[0005] This invention provides a display panel and display device to alleviate the shortcomings of related technologies.

[0006] To achieve the above functions, the technical solutions provided in this application are as follows:

[0007] In a first aspect, embodiments of this application provide a display panel, including:

[0008] substrate;

[0009] A first metal layer is disposed on the substrate, and the first metal layer includes a first light-shielding portion;

[0010] A photosensitive unit is disposed on the side of the first light-shielding portion away from the substrate. The photosensitive unit includes a photosensitive doped portion, a photosensitive portion, and a photosensitive electrode stacked together. One end of the photosensitive portion is connected to the photosensitive doped portion, and the other end of the photosensitive portion is connected to the photosensitive electrode.

[0011] Wherein, the orthographic projection of the first light-shielding part on the substrate covers the orthographic projection of the photosensitive part on the substrate, and the first light-shielding part is connected to a constant voltage source.

[0012] Secondly, embodiments of this application provide a display device, the display device including a display panel, the display panel including:

[0013] substrate;

[0014] A first metal layer is disposed on the substrate, and the first metal layer includes a first light-shielding portion;

[0015] A photosensitive unit is disposed on the side of the first light-shielding portion away from the substrate. The photosensitive unit includes a photosensitive doped portion, a photosensitive portion, and a photosensitive electrode stacked together. One end of the photosensitive portion is connected to the photosensitive doped portion, and the other end of the photosensitive portion is connected to the photosensitive electrode.

[0016] Wherein, the orthographic projection of the first light-shielding part on the substrate covers the orthographic projection of the photosensitive part on the substrate, and the first light-shielding part is connected to a constant voltage source. Attached Figure Description

[0017] The technical solution and other beneficial effects of the present invention will become apparent from the following detailed description of specific embodiments of the invention, in conjunction with the accompanying drawings.

[0018] Figure 1 is a schematic diagram of the structure of the display panel provided in an embodiment of this application;

[0019] Figure 2 is a cross-sectional schematic diagram of the corresponding AA' position in Figure 1 provided in an embodiment of this application;

[0020] Figure 3 is an enlarged schematic diagram of region B in Figure 1 of the embodiment of this application;

[0021] Figure 4 is an enlarged schematic diagram of the fan-out area corresponding to Figure 3 provided in the embodiment of this application;

[0022] Figure 5 is a cross-sectional schematic diagram of the corresponding CC' position in Figure 4 provided in the embodiment of this application;

[0023] Figures 6A to 6I are schematic diagrams corresponding to the steps of the manufacturing method of the display panel provided in the embodiments of this application;

[0024] Figure 7 is a schematic diagram of the structure of the display device provided in the embodiment of this application. Embodiments of the present invention

[0025] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower in the actual use or working mode of the device, specifically the drawing direction in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0026] Furthermore, the terms "first" and "second" are used for descriptive purposes only, and features defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0027] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections or detachable connections; mechanical connections or electrical connections or connections that allow communication; direct connections or indirect connections through an intermediate medium; and connections within two components or interactions between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0028] The following disclosure provides many different embodiments for implementing different structures of this application. To simplify the disclosure of this application, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0029] This application provides a display panel and a display device. These will be described in detail below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0030] Please refer to Figures 1 and 2; wherein, Figure 1 is a structural schematic diagram of the display panel provided in the embodiment of this application; and Figure 2 is a cross-sectional schematic diagram of the corresponding AA' position in Figure 1 provided in the embodiment of this application.

[0031] In one embodiment, the display panel 1 includes, but is not limited to, a liquid crystal display panel, and the display panel 1 includes a substrate 11, a first metal layer 12, a buffer layer 13, a thin film transistor layer 14, a planarization layer 15, a second transparent electrode layer 16, a passivation layer 17, and a first transparent electrode layer 18.

[0032] The substrate 11 may include either a rigid substrate or a flexible substrate. When the substrate 11 is a rigid substrate, the material may be metal or glass. When the substrate 11 is a flexible substrate, the material may include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, polyurethane-based resin, cellulose resin, siloxane resin, polyimide-based resin, and polyamide-based resin. This embodiment does not impose specific limitations on these aspects.

[0033] The first metal layer 12 is disposed on one side of the substrate 11. The material of the first metal layer 12 includes, but is not limited to, molybdenum (Mo), molybdenum-aluminum (MoAl) stack or molybdenum-aluminum-molybdenum (MoAlMo) stack, thereby reducing the sheet resistance (Rs) of the first metal layer 12, which helps to improve the performance and signal transmission efficiency of the display panel 1.

[0034] The buffer layer 13 is disposed on the side of the first metal layer 12 away from the substrate 11. The buffer layer 13 can play a buffering role. The material of the buffer layer 13 includes, but is not limited to, silicon nitride (SiNx), silicon oxide (SiOx), monolayer silicon oxynitride (SiONx), or a combination of the above films.

[0035] The thin-film transistor layer 14 includes a semiconductor layer 141, a gate insulating layer 142, a third metal layer 143, an interlayer insulating layer 144, and a second metal layer 145 stacked on the substrate 11. The thin-film transistor layer 14 includes a photosensitive unit 1401 and a control unit 1402. The control unit 1402 is connected to the photosensitive unit 1401 and can control the on / off state of the photosensitive unit 1401.

[0036] The semiconductor layer 141 is disposed on the side of the buffer layer 13 away from the first metal layer 12. The semiconductor layer 141 includes photosensitive doped portions 1411 and semiconductor portions 1412 disposed at intervals. The semiconductor portion 1412 includes a first doped portion 14121 and a second doped portion 14122, and a channel portion 14123 located between the first doped portion 14121 and the second doped portion 14122. The material of the channel portion 14123 can be polycrystalline silicon (poly-Si) formed by converting amorphous silicon (a-Si) using an excimer laser annealing (ELA) process. The doping concentrations of the first doped portion 14121 and the second doped portion 14122 are the same. Both the first doped portion 14121 and the second doped portion 14122 can be formed by heavy phosphorus ion doping using polycrystalline silicon.

[0037] The gate insulating layer 142 is disposed on the side of the semiconductor layer 141 away from the buffer layer 13. The gate insulating layer 142 can be used to prevent short circuits between the semiconductor layer 141 and the third metal layer 143. The material of the gate insulating layer 142 includes, but is not limited to, silicon oxide, silicon nitride, aluminum oxide, or a combination of the above films.

[0038] The third metal layer 143 is disposed on the side of the gate insulating layer 142 away from the semiconductor layer 141. The third metal layer 143 includes a gate 1431, which is disposed corresponding to the channel portion 14123. The orthogonal projection of the gate 1431 on the substrate 11 covers the orthogonal projection of the channel portion 14123 on the substrate 11. The material of the third metal layer 143 includes, but is not limited to, at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), and tungsten (W).

[0039] The interlayer insulating layer 144 is disposed on the side of the third metal layer 143 away from the gate insulating layer 142. The material of the interlayer insulating layer 144 includes, but is not limited to, silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiONx), or a combination of the above films.

[0040] The second metal layer 145 is disposed on the interlayer insulating layer 144 away from the third metal layer 143. The material of the second metal layer 145 includes, but is not limited to, at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), and tungsten (W). The second metal layer 145 includes a first electrode 1451, a second electrode 1452, a third electrode 1453, and a fourth electrode 1454. The third electrode 1453 is connected to the first doped portion 14121, and the fourth electrode 1454 is connected to the second doped portion 14122.

[0041] The planarization layer 15, the second transparent electrode layer 16, the passivation layer 17, and the first transparent electrode layer 18 are sequentially stacked on the side of the second metal layer 145 away from the interlayer insulating layer 144. The material of the passivation layer 17 includes, but is not limited to, silicon nitride (SiNx), silicon dioxide (SiOx), silicon oxynitride (SiONx), or a combination of the above films. The first transparent electrode layer 18 includes a photosensitive electrode 181 and a pixel electrode 182. The second transparent electrode layer 16 includes a common electrode 161. The materials of the first transparent electrode layer 18 and the second transparent electrode layer 16 include, but are not limited to, metal oxide materials. The metal oxide material is preferably indium tin oxide (ITO) material with high visible light transmittance and good conductivity.

[0042] The photosensitive unit 1401 can be a photosensitive sensor for detecting ambient photocurrent. The photosensitive unit 1401 includes a photosensitive doped portion 1411, a photosensitive portion 14011, and a photosensitive electrode 181 stacked together. One end of the photosensitive portion 14011 is connected to the photosensitive doped portion 1411, and the other end of the photosensitive portion 14011 is connected to the photosensitive electrode 181. The material of the photosensitive portion 14011 includes, but is not limited to, amorphous silicon (a-Si). When external light shines on the photosensitive portion 14011, a photocurrent can be generated between the photosensitive doped portion 1411 and the photosensitive electrode 181.

[0043] Specifically, the photosensitive unit 1401 can be a PIN structure; specifically, the photosensitive unit 1401 includes an N-type layer, an I-type layer located on the N-type layer, and a P-type layer located on the I-type layer.

[0044] The photosensitive doped portion can be an N-type layer, and the material of the photosensitive doped portion is N-type doped polycrystalline silicon, which provides charge carrier electrons and helps to form an electric field. The photosensitive portion 14011 can be an I-type layer, and the material of the photosensitive portion 14011 can be amorphous silicon. Amorphous silicon is an intrinsic semiconductor with good light absorption capability. Under illumination, the photosensitive portion 14011 can absorb photons and generate electron-hole pairs. The photosensitive electrode 181 can be a P-type layer, and the material of the photosensitive electrode 181 can be indium tin oxide (ITO). The photosensitive electrode 181 can provide holes to help establish a built-in electric field. Light can pass through the photosensitive electrode 181 into the photosensitive portion 14011, thereby realizing the photoelectric effect.

[0045] It is understood that this embodiment integrates the photosensitive element into the display panel 1, thereby realizing the under-screen color temperature sensing and self-adjustment function. Compared with the external photosensitive element solution in related technologies, it has the effects of high integration, low cost, and saves structural space.

[0046] Please refer to Figures 1 and 2. In one embodiment, the first metal layer 12 includes a first light-shielding portion 121, which is disposed corresponding to the photosensitive unit 1401. The orthographic projection of the photosensitive unit 14011 on the substrate 11 is located within the orthographic projection of the first light-shielding portion 121 on the substrate 11, thereby preventing unnecessary light from shining on the photosensitive unit 1401, reducing the impact of light interference on the photosensitive unit 14011, and thus improving the accuracy and stability of the photoelectric signal.

[0047] Specifically, the first light-shielding part 121 is connected to a constant voltage source. It should be noted that the photosensitive unit 1401 can integrate the functions of an ambient light sensor and a color temperature sensor, and has the advantages of fast response speed, simple structure and high accuracy. However, in actual operation, the floating metal inside the display panel 1 may interfere with the reading of the photosensitive unit 1401, resulting in a decrease in the accuracy of sensor measurement.

[0048] It is understood that by directly connecting the first light-shielding part 121 to the constant voltage source in this embodiment, the potential of the first light-shielding part 121 can be ensured to always be in a stable state. The constant voltage source provides a fixed voltage to ensure that the first light-shielding part 121 is not affected by external signals during operation and will not fluctuate. This effectively prevents the potential of the first light-shielding part 121 from drifting or changing (i.e., floating). Since the light interference is effectively controlled, the photosensitive unit 1401 can more accurately sense the light signal and convert it into an electrical signal, thereby improving the efficiency and stability of the photosensitive unit 1401.

[0049] Please refer to Figures 1 and 2; in one embodiment, the first electrode 1451 is connected to the first light-shielding part 121, one end of the second electrode 1452 is connected to the photosensitive doping part 1411, and the other end of the second electrode 1452 is connected to the control unit 1402.

[0050] Specifically, the first electrode 1451 is connected to the first light-shielding part 121 and a constant voltage (e.g., a COM signal) is applied to it, so that the first light-shielding part 121 can maintain a constant voltage state. This can effectively avoid the electrical noise problem caused by the floating potential of the first light-shielding part 121, thereby reducing interference to the photosensitive unit 1401 and helping to improve the accuracy and stability of the photoelectric signal.

[0051] Meanwhile, by connecting the photosensitive doped part 1411 to the second electrode 1452 and connecting the second electrode 1452 to the control unit 1402, a more precise current flow path can be achieved, improving the accuracy of the photoelectric signal. The connection between the photosensitive doped part 1411 and the control unit 1402 helps maintain a stable photocurrent output, ensuring that the photosensitive unit 1401 can correctly detect and respond to changes in external light, without affecting the measurement accuracy due to unnecessary potential interference.

[0052] It should be noted that the technical solution proposed in this embodiment is applicable to the application scenario of integrating photoelectric sensors in the display panel 1. In order to better illustrate the innovation of this embodiment, this embodiment takes the constant voltage as a COM signal as an example to illustrate the technical solution of this embodiment.

[0053] Please refer to Figures 1 and 2. In one embodiment, the control unit 1402 is connected to the photosensitive unit 1401, and the control unit 1402 can control the switching and other states of the photosensitive unit 1401. The control unit 1402 can be a thin-film transistor structure, and the control unit 1402 includes a semiconductor part 1412, a gate insulating layer 142, a gate 1431, an interlayer insulating layer 144, a third electrode 1453, and a fourth electrode 1454. One end of the third electrode 1453 is connected to the first doped part 14121, and the other end of the third electrode 1453 is connected to the second electrode 1452. The fourth electrode 1454 is connected to the second doped part 14122.

[0054] It should be noted that one of the third electrode 1453 and the fourth electrode 1454 can be the source electrode, and the other of the third electrode 1453 and the fourth electrode 1454 can be the drain electrode. The specific locations of the source electrode and the drain electrode can be selected according to design requirements, thereby making this embodiment highly flexible.

[0055] Furthermore, the third electrode 1453 can be connected to the pixel electrode 182. The control unit 1402 can adjust the current of the source electrode and the drain electrode to control the current and voltage changes of the pixel electrode 182, thereby affecting the display effect.

[0056] The first metal layer 12 further includes a second light-shielding portion 122, which is spaced apart from the first light-shielding portion 121. The second light-shielding portion 122 is disposed corresponding to the control unit 1402. The orthographic projection of the semiconductor portion 1412 on the substrate 11 is located at the orthographic projection of the second light-shielding portion 122 on the substrate 11. The second light-shielding portion 122 is used to prevent light from shining on the semiconductor portion 1412 and to prevent it from affecting the device performance of the semiconductor portion 1412.

[0057] It is understood that, in this embodiment, by setting the first metal layer 12 to include a first light-shielding portion 121 and a second light-shielding portion 122, the semiconductor layer 141 to include a photosensitive doped portion 1411 and a semiconductor portion 1412 spaced apart, and the second metal layer 145 to include a first electrode 1451, a second electrode 1452, a third electrode 1453 and a fourth electrode 1454, the process difficulty of the display panel 1 is reduced, manufacturing costs are saved, and production efficiency and yield are improved.

[0058] Meanwhile, the display panel 1 structure design provided in this embodiment simplifies the hierarchical relationship, integrating the photosensitive unit 1401 and the control unit 1402 in the same thin film transistor layer 14. By directly setting the photosensitive unit 1401 in the structure of the display panel 1, the photosensitive unit 1401 can directly respond to external light without the need for additional photosensitive elements, thereby reducing the need for external photosensitive elements, which is conducive to the integration of the device and saves space.

[0059] Please refer to Figures 1 and 2. In one embodiment, the semiconductor portion 1412 further includes a third doped portion 14124 and a fourth doped portion 14125. The third doped portion 14124 is disposed between the channel portion 14123 and the first doped portion 14121. The fourth doped portion 14125 is disposed between the channel portion 14123 and the second doped portion 14122. The first doped portion 14121 and the second doped portion 14122 have the same doping concentration, and the third doped portion 14124 and the fourth doped portion 14125 have the same doping concentration. The doping concentration of the third doped portion 14124 is less than the doping concentration of the first doped portion 14121.

[0060] It is understood that by setting the third doped portion 14124 and the fourth doped portion 14125, and making their doping concentration lower than that of the first doped portion 14121 and the second doped portion 14122, the doping concentration gradient near the channel portion 14123 is reduced, the problem of reduced mobility caused by excessively high doping concentration is alleviated, and the current transmission efficiency and response speed are improved.

[0061] Specifically, since the third doped portion 14124 is provided between the channel portion 14123 and the first doped portion 14121, and the fourth doped portion 14125 is provided between the channel portion 14123 and the second doped portion 14122, both the third doped portion 14124 and the fourth doped portion 14125 can serve as transition portions, which helps to form a smooth current path, reduce current spikes in the switching state, improve the conduction characteristics of the control unit 1402, and avoid current sudden changes.

[0062] Meanwhile, the first doped portion 14121 and the second doped portion 14122 have the same doping concentration, and the third doped portion 14124 and the fourth doped portion 14125 have the same doping concentration, thereby ensuring the uniform distribution of current in the channel portion 14123, avoiding the problem of unbalanced current distribution caused by uneven doping, and improving the performance consistency and stability of the semiconductor portion 1412.

[0063] Please refer to Figures 1 and 2. In one embodiment, the buffer layer 13 is disposed between the first metal layer 12 and the semiconductor layer 141; the gate insulating layer 142 is disposed between the semiconductor layer 141 and the third metal layer 143; and the interlayer insulating layer 144 is disposed on the side of the third metal layer 143 away from the gate insulating layer 142. This ensures that short circuits do not occur between different conductive parts, making signal transmission more stable and thus improving the overall reliability and performance of the display panel 1.

[0064] The display panel 1 has a first through hole 10 and a second through hole 20. The first electrode 1451 passes through the first through hole 10 and is connected to the first light-shielding part 121. The first through hole 10 penetrates the interlayer insulating layer 144, the gate insulating layer 142 and at least part of the buffer layer 13. One end of the second electrode 1452 passes through the second through hole 20 and is connected to the photosensitive doped part 1411. The second through hole 20 penetrates the interlayer insulating layer 144, the gate insulating layer 142, the photosensitive doped part 1411 and the buffer layer 13. The other end of the second electrode 1452 is connected to the third electrode 1453.

[0065] Furthermore, the display panel 1 also has a sixth through hole 60 and a seventh through hole 70. The third electrode 1453 passes through the sixth through hole 60 and is connected to the first doped portion 14121. The sixth through hole 60 penetrates the interlayer insulating layer 144, the gate insulating layer 142, the first doped portion 14121, and the buffer layer 13. The fourth electrode 1454 passes through the seventh through hole 70 and is connected to the second doped portion 14122. The seventh through hole 70 penetrates the interlayer insulating layer 144, the gate insulating layer 142, the second doped portion 14122, and the buffer layer 13.

[0066] It is understood that by providing the second through-hole 20 through the photosensitive doped portion 1411, the second electrode 1452 through the photosensitive doped portion 1411, and the photosensitive doped portion 1411 surrounding the second electrode 1452, the sixth through-hole 60 through the first doped portion 14121, the third electrode 1453 through the first doped portion 14121, and the first doped portion 14121 surrounding the third electrode 1453, the seventh through-hole 70 through the first doped portion 14121, and the fourth electrode 1454 through the second doped portion 14122, and the second doped portion 14122 surrounding the fourth electrode 1454, the isolation between electrodes can be optimized, unnecessary electrical interference or short circuits between electrodes can be prevented, and their stability can be improved.

[0067] At the same time, it can enhance the electrical connection stability between the electrode and the doped part, increase the contact area between the electrode and the doped part, and avoid contact instability caused by poor local contact or mismatch of electrode shape.

[0068] Please refer to Figures 1 and 2; in one embodiment, the orthogonal projection of the second light-shielding portion 122 on the substrate 11 covers the orthogonal projection of the semiconductor portion 1412 on the substrate 11, and the orthogonal projection of the second light-shielding portion 122 on the substrate 11 covers the orthogonal projections of the third doped portion 14124 and the fourth doped portion 14125 on the substrate 11.

[0069] Specifically, the second light-shielding part 122 is provided corresponding to the channel region and the lightly doped region. The second light-shielding part 122 has a semi-enclosed structure, only covering the channel part 14123, the third doped part 14124 and the fourth lightly doped part, thus avoiding the influence of light on these regions. It is understood that the doping concentration of the third doped part 14124 and the fourth lightly doped part is low, and they usually have a significant impact on current control and mobility during operation. Therefore, the design of the second light-shielding part 122 can ensure that these regions are in a stable electrical state, thereby improving the stability and performance of the display panel 1.

[0070] Meanwhile, compared with the full-shield design (the light-shielding layer completely covers the semiconductor part 1412) in related technologies, the semi-enclosed design can simplify the manufacturing process of the second light-shielding part 122, improve manufacturing efficiency and reduce costs, and ensure that the light-shielding effect is not affected.

[0071] Referring to Figures 1 and 2, in one embodiment, the display panel 1 further includes a third through-hole 30, in which at least a portion of the photosensitive portion 14011 is filled, and the third through-hole 30 penetrates the interlayer insulating layer 144 and at least a portion of the gate insulating layer 142. This prevents the photosensitive portion 14011 from contacting other film layers, effectively improving electrical isolation, preventing possible electrical short circuits or leaks, and enhancing the electrical safety and reliability of the display panel 1.

[0072] Specifically, the dimension of the photosensitive portion 14011 on the side away from the substrate 11 is larger than the dimension of the third through-hole 30 on the side away from the substrate 11. More specifically, the side of the photosensitive portion 14011 away from the substrate 11 protrudes beyond the surface of the interlayer insulating layer 144 on the side away from the substrate 11. That is, the distance between the surface of the photosensitive portion 14011 on the side away from the substrate 11 and the substrate 11 is greater than the distance between the surface of the interlayer insulating layer 144 on the side away from the substrate 11 and the substrate 11, thereby making the contact between the photosensitive portion 14011 and the third through-hole 30 more stable.

[0073] It should be noted that the dimensions mentioned in this embodiment refer to the width of the photosensitive part 14011 in the first direction X and the width of the fifth through hole 50 in the first direction X, where the first direction is the X direction in Figure 2.

[0074] Furthermore, the first through hole 10, the second through hole 20, the third through hole 30, the sixth through hole 60, and the seventh through hole 70 can be processed in one step using a single photomask, making the manufacturing process simpler and enabling efficient and correct connection of multiple electrodes, reducing the complexity of multiple processes; at the same time, it helps maintain the production consistency of the display panel 1, reduces process steps, lowers production complexity and cost, ensures performance and structural stability, and improves the product qualification rate.

[0075] Please refer to Figures 1 and 2. In one embodiment, the display panel 1 further includes a protective layer 19, which is disposed on the side of the photosensitive portion 14011 away from the photosensitive doped portion 1411. The protective layer 19 has a fourth through-hole 40 that penetrates the protective layer 19. The planarization layer 15 is disposed on the side of the second metal layer 145 away from the interlayer insulating layer 144. The planarization layer 15 has a fifth through-hole 50 that penetrates at least a portion of the planarization layer 15 and communicates with the fourth through-hole 40. The first transparent electrode layer 18 is disposed on the side of the planarization layer 15 away from the second metal layer 145. The first transparent electrode layer 18 includes the photosensitive electrode 181, which passes through the fourth through-hole 40 and the fifth through-hole 50 and connects to the photosensitive portion 14011.

[0076] The material of the protective layer 19 includes, but is not limited to, silicon nitride (SiNx), silicon dioxide (SiOx), silicon oxynitride (SiONx), or a combination of the above films. The material of the planarization layer 15 includes, but is not limited to, organic photoresist materials. It is understood that by setting the protective layer 19, the photosensitive part 14011 can be effectively prevented from being damaged by the external environment, and panel failures caused by pollution or electrical short circuits can be avoided. Setting the planarization layer 15 not only helps to improve the overall flatness of the panel, but also further optimizes the uniformity of subsequent layers, thereby improving the quality and consistency of the display panel 1.

[0077] Meanwhile, by setting the fourth through hole 40 and the fifth through hole 50, and ensuring that the fifth through hole 50 is connected to the fourth through hole 40, the photosensitive part 14011 and the photosensitive electrode 181 can be accurately connected, avoiding connection errors and ensuring stable electrical performance.

[0078] Please refer to Figures 1, 2, 3 and 4; wherein, Figure 3 is an enlarged schematic diagram of the corresponding region B in Figure 1 of the embodiment of this application; and Figure 4 is an enlarged schematic diagram of the corresponding fan-out region in Figure 3 provided in the embodiment of this application.

[0079] It should be noted that in the manufacturing process of display panels, in order to achieve a narrower bezel design, the size of the bottom bezel needs to be compressed. Display panels usually include a display area and a non-display area. The non-display area can also be called the bezel area. The non-display area corresponding to the bottom bezel can be divided into a bonding area and a fan-out area set between the bonding area and the display area. The fan-out area is used to arrange fan-out traces to lead the traces in the display area to the non-display area and connect them with the chips in the non-display area so that the chips can transmit signals to the display area.

[0080] In related technologies, the connection wiring between signal lines and electrode layers in the fan-out area of ​​the display panel is usually quite complex, resulting in an excessively wide panel bezel, which affects the display effect and aesthetics. In particular, when the bezel design is not compact enough, it affects the overall size and appearance of the display panel.

[0081] In one embodiment, the display panel 1 includes a display area 1000 and a non-display area 2000 disposed on at least one side of the display area 1000. Specifically, the display panel 1 includes the display area 1000 and a bonding terminal 300 located on one side of the display area 1000. The bonding terminal 300 is located within the non-display area 2000 and can be connected to an external circuit to transmit signals input from the external circuit to the display panel 1, thereby driving the display panel to display an image. The non-display area 2000 includes a fan-out area 2100, which is located at one end of the non-display area 2000 closer to the display area 1000.

[0082] The display panel 1 further includes a fan-out portion 211, which is disposed on one side of the substrate 11 and located within the fan-out area 2100. The fan-out portion 211 includes a first fan-out line 123, a second fan-out line 1432, and a third fan-out line 1455 that are stacked and insulated from each other. The first metal layer 12 includes the first fan-out line 123, the third metal layer 143 includes the second fan-out line 1432, and the second metal layer 145 includes the third fan-out line 1455. At least two of the first fan-out line 123, the second fan-out line 1432, and the third fan-out line 1455 are overlapped.

[0083] It is understood that this embodiment arranges the fan-out lines (first fan-out line 123, second fan-out line 1432 and third fan-out line 1455) on different metal layers in an overlapping manner and optimizes the distribution of the fan-out lines in the fan-out area 2100. This allows for the setting of more fan-out lines in the same space, reducing the area of ​​the non-display area 2000. This, in turn, helps to improve the resolution of the display panel 1 and meets the design requirements of a narrow bezel, providing a larger effective display area for the display panel 1.

[0084] Meanwhile, by arranging the first light-shielding part 121, the second light-shielding part 122 and the first fan-out line 123 in the same layer, the gate 1431 and the second fan-out line 1432 in the same layer, and the first electrode 1451, the second electrode 1452, the third electrode 1453, the fourth electrode 1454 and the third fan-out line 1455 in the same layer, the number of film layers of the display panel 1 can be reduced, the stacking structure can be optimized, the manufacturing process of the display panel 1 can be simplified, and the production cost and material consumption can be effectively reduced.

[0085] Furthermore, the first fan-out line 123 and the second fan-out line 1432 are at least partially overlapped; and / or, the third fan-out line 1455 and the second fan-out line 1432 are at least partially overlapped; and / or, the first fan-out line 123 and the third fan-out line 1455 are at least partially overlapped.

[0086] It should be noted that the technical solution proposed in this embodiment is applicable to the application scenario of narrow bezel of display panel 1. In order to better illustrate the innovation of this embodiment, this embodiment uses the example of the first fan-out line 123 and the second fan-out line 1432 being at least partially overlapping, the third fan-out line 1455 and the second fan-out line 1432 being at least partially overlapping, and the first fan-out line 123 and the third fan-out line 1455 being at least partially overlapping to illustrate the technical solution of this embodiment.

[0087] It is understood that by making the first fan-out line 123 and the second fan-out line 1432 at least partially overlap, the third fan-out line 1455 and the second fan-out line 1432 at least partially overlap, and the first fan-out line 123 and the third fan-out line 1455 at least partially overlap, the space occupied by the fan-out lines can be effectively reduced, thereby making the fan-out line layout more compact and thus improving the overall space utilization efficiency of the display panel 1.

[0088] Please refer to Figures 1, 2, 3, 4 and 5; wherein, Figure 5 is a cross-sectional schematic diagram of the corresponding CC' position in Figure 4 provided in the embodiment of this application.

[0089] In one embodiment, the second metal layer 145 further includes a connecting portion 1456 located within the fan-out area 2100. One end of the connecting portion 1456 is connected to the first fan-out line 123, and the other end of the connecting portion 1456 is connected to the second fan-out line 1432. This allows the connecting portion 1456 to serve as a transition bridge for electrical connections, ensuring a stable connection between the first fan-out line 123 and the second fan-out line 1432. At the same time, it avoids complex crossings of fan-out lines within the fan-out area 2100, reduces the space occupied by fan-out lines, and makes the wiring of the display panel 1 more concise and compact.

[0090] Specifically, the display panel 1 also has a tenth through hole 100 and an eleventh through hole 110. One end of the connecting part 1456 passes through the tenth through hole 100 and is connected to the first fan-out line 123. The tenth through hole 100 penetrates the interlayer insulating layer 144, the gate insulating layer 142, and at least part of the buffer layer 13. The other end of the connecting part 1456 passes through the eleventh through hole 110 and is connected to the second fan-out line 1432. The eleventh through hole 110 penetrates at least part of the interlayer insulating layer 144.

[0091] The first through hole 10, the second through hole 20, the third through hole 30, the sixth through hole 60, the seventh through hole 70, the tenth through hole 100 and the eleventh through hole 110 can be processed in one step by one photomask, which makes the manufacturing process simpler and can efficiently achieve the correct connection of multiple electrodes, reducing the complexity of multiple processes.

[0092] Please refer to Figures 2 and 6A to 6I; wherein, Figures 6A to 6I are schematic diagrams corresponding to each step of the manufacturing method of the display panel provided in the embodiments of this application.

[0093] In one embodiment, the method for manufacturing the display panel 1 includes the following steps:

[0094] As shown in Figure 6A, in step S10: a first metal layer 12 is formed on the substrate 11, and the first metal layer 12 is patterned by an exposure etching method to form a first light-shielding part 121 and a second light-shielding part 122 that are spaced apart.

[0095] As shown in Figure 6B, in step S20: a buffer layer 13 and a first amorphous silicon (a-Si) are sequentially formed on the first light-shielding part 121 and the second light-shielding part 122. After excimer laser annealing, the first amorphous silicon (a-Si) is transformed into polycrystalline silicon (poly-Si). Boron ions are then doped all over the surface. The polycrystalline silicon (poly-Si) is patterned by exposure etching to form a photosensitive doped part 1411 and a semiconductor semi-finished product 14120.

[0096] As shown in Figure 6C, in step S30: a gate insulating layer 142 and a third metal layer 143 are sequentially formed on the photosensitive doped portion 1411, the semiconductor semi-finished product 14120, and the buffer layer 13. The third metal layer 143 is patterned to form a gate 1431. The semiconductor semi-finished product 14120 is partially covered by the gate 1431 and photoresist. The semiconductor semi-finished product 14120 not covered by the gate 1431 and photoresist is heavily doped with phosphorus ions to form a first doped portion 14121 and a second doped portion 14122. Then, the photoresist is removed. The semiconductor semi-finished product 14120 not covered by the gate 1431 is lightly doped with phosphorus ions to form a third doped portion 14124 and a fourth doped portion 14125. The semiconductor semi-finished product 14120 covered by the gate 1431 forms a channel portion 14123.

[0097] The first doped portion 14121, the third doped portion 14124, the channel portion 14123, the fourth doped portion 14125, and the second doped portion 14122 form a semiconductor portion 1412. It should be noted that when the portion of the semiconductor portion semi-finished product 14120 not covered by the gate 1431 is lightly doped with phosphorus ions to form the third doped portion 14124 and the fourth doped portion 14125, photoresist can be used to cover the first doped portion 14121 and the second doped portion 14122, thereby ensuring the accurate distribution of different doped portions and avoiding excessively high or low doping concentrations that would cause the device performance to fail to meet requirements.

[0098] As shown in Figure 6D, in step S40: an interlayer insulating layer 144 is formed on the gate 1431 and the gate insulating layer 142. The interlayer insulating layer 144 is patterned by an exposure etching method to form a first sub-via 101, a second sub-via 201, a third sub-via 601, a fourth sub-via 701 and a third sub-via 30 that are spaced apart.

[0099] Wherein, the first sub-via 101 is disposed corresponding to the first light-shielding portion 121, and the first sub-via 101 penetrates the interlayer insulating layer 144, the gate insulating layer 142 and at least a portion of the buffer layer 13; the second sub-via 201 exposes a portion of the photosensitive doped portion 1411, and the second sub-via 201 penetrates the interlayer insulating layer 144 and at least a portion of the gate insulating layer 142; the third sub-via 601 exposes a portion of the first doped portion 14121, and the third sub-via 601 penetrates the interlayer insulating layer 144 and at least a portion of the gate insulating layer 142; the fourth sub-via 701 exposes a portion of the second doped portion 14122, and the fourth sub-via 701 penetrates the interlayer insulating layer 144 and at least a portion of the gate insulating layer 142; the third via 30 exposes a portion of the photosensitive doped portion 1411, and the third via 30 penetrates the interlayer insulating layer 144 and at least a portion of the gate insulating layer 142.

[0100] As shown in Figure 6E, in step S50: a second amorphous silicon (a-Si) is formed in the third through-hole 30, a protective layer 19 is formed on the second amorphous silicon (a-Si), and then the second amorphous silicon (a-Si) is patterned by an exposure etching method to form a photosensitive part 14011; at the same time, the interlayer insulating layer 144 is patterned to form a fifth sub-through-hole 102, a sixth sub-through-hole 202, a seventh sub-through-hole 602 and an eighth sub-through-hole 702 that are spaced apart.

[0101] At least a portion of the photosensitive portion 14011 is filled within the third through hole 30, and the side of the photosensitive portion 14011 away from the substrate 11 protrudes from the surface of the interlayer insulating layer 144 away from the substrate 11.

[0102] The fifth sub-via 102 is provided corresponding to the first sub-via 101, and the fifth sub-via 102 is connected to the first sub-via 101. The fifth sub-via 102 exposes a portion of the first light-shielding portion 121 and penetrates a portion of the buffer layer 13. The first sub-via 101 and the fifth sub-via 102 form a first through-hole 10. The sixth sub-via 202 is provided corresponding to the second sub-via 201, and the sixth sub-via 202 is connected to the second sub-via 201. The sixth sub-via 202 exposes a portion of the substrate 11 and penetrates the photosensitive doped portion 1411 and the buffer layer 13. The second sub-via 201 and the sixth sub-via 202 form a second through-hole 20.

[0103] The seventh sub-via 602 is provided corresponding to the third sub-via 601, and the seventh sub-via 602 communicates with the third sub-via 601. The seventh sub-via 602 exposes a portion of the substrate 11 and penetrates the first doped portion 14121 and the buffer layer 13. The third sub-via 601 and the seventh sub-via 602 form the sixth through-via 60. The eighth sub-via 702 is provided corresponding to the fourth sub-via 701, and the eighth sub-via 702 communicates with the fourth sub-via 701. The eighth sub-via 702 exposes a portion of the substrate 11 and penetrates the second doped portion 14122 and the buffer layer 13. The fourth sub-via 701 and the eighth sub-via 702 form the seventh through-via 70.

[0104] As shown in Figure 6F, in step S60: a second metal layer 145 is formed on the interlayer insulating layer 144. The second metal layer 145 is patterned by an exposure etching method to form a first electrode 1451, a second electrode 1452, a third electrode 1453, and a fourth electrode 1454 spaced apart. The first electrode 1451 passes through the first through-hole 10 and is connected to the first light-shielding part 121. One end of the second electrode 1452 passes through the second through-hole 20 and is connected to the photosensitive doped part 1411. The third electrode 1453 passes through the sixth through-hole 60 and is connected to the first doped part 14121. The fourth electrode 1454 passes through the seventh through-hole 70 and is connected to the second doped part 14122. The semiconductor part 1412, the gate insulating layer 142, the gate 1431, the interlayer insulating layer 144, the third electrode 1453, and the fourth electrode 1454 form a control unit 1402.

[0105] The first electrode 1451 is connected to the first light-shielding part 121 and a constant voltage (e.g., a COM signal) is applied to it, so that the first light-shielding part 121 can maintain a constant voltage state.

[0106] As shown in Figure 6G, in step S70: a planarization layer 15 is formed on the first electrode 1451, the second electrode 1452, the third electrode 1453, the fourth electrode 1454 and the interlayer insulating layer 144. The planarization layer 15 is patterned by exposure and development to form a fifth through hole 50 and an eighth through hole 80. The fifth through hole 50 exposes a portion of the protective layer 19 and penetrates a portion of the planarization layer 15. The eighth through hole 80 exposes a portion of the third electrode 1453 and penetrates a portion of the planarization layer 15.

[0107] As shown in Figure 6H, step S80: a second transparent electrode layer 16 is formed on the planarization layer 15, and the second transparent electrode layer 16 is patterned to form a common electrode 161.

[0108] As shown in Figure 6I, in step S90: a passivation layer 17 is formed on the planarization layer 15, the protective layer 19, and the pixel electrode 182. The planarization layer 15 is patterned using an exposure and development method to form a fourth through-hole 40 and a ninth through-hole 90. The fourth through-hole 40 exposes a portion of the photosensitive part 14011. The fourth through-hole 40 is connected to the fifth through-hole 50 and penetrates the passivation layer 17 and the protective layer 19. The ninth through-hole 90 exposes a portion of the third electrode 1453 and is connected to the eighth through-hole 80 and penetrates the passivation layer 17.

[0109] As shown in Figure 2, in step S100: a first transparent electrode layer 18 is formed on the passivation layer 17 and the photosensitive part 14011. The first transparent electrode layer 18 is patterned to form a pixel electrode 182 and a photosensitive electrode 181. The photosensitive electrode 181 is connected to the photosensitive part 14011 through the fourth through hole 40 and the fifth through hole 50. The pixel electrode 182 is connected to the third electrode 1453 through the eighth through hole 80 and the ninth through hole 90. The photosensitive electrode 181, the photosensitive part 14011 and the photosensitive doped part 1411 form a photosensitive element.

[0110] It is understood that by directly connecting the first light-shielding part 121 to the constant voltage source in this embodiment, the potential of the first light-shielding part 121 can be ensured to always be in a stable state. The constant voltage source provides a fixed voltage to ensure that the first light-shielding part 121 is not affected by external signals during operation and will not fluctuate. This effectively prevents the potential of the first light-shielding part 121 from drifting or changing (i.e., floating). Since the light interference is effectively controlled, the photosensitive unit 1401 can more accurately sense the light signal and convert it into an electrical signal, thereby improving the efficiency and stability of the photosensitive unit 1401.

[0111] Please refer to Figure 7, which is a schematic diagram of the structure of the display device provided in the embodiment of this application.

[0112] This embodiment also provides a display device 2, which includes the display panel 1 described in any of the above embodiments.

[0113] It is understood that the display panel 1 has been described in detail in the above embodiments, and will not be repeated here.

[0114] The display device 2 may also include a housing 2A, which is integrated with the display panel 1 to provide support, fixation and protection for the display panel 1.

[0115] In specific applications, the display device 2 can be at least one of the following devices with display functions: smartphone, tablet computer, mobile phone, video phone, e-book reader, desktop computer, laptop computer, netbook, workstation, server, personal digital assistant, portable media player, MP3 player, mobile medical device, camera, game console, digital camera, car navigation system, electronic billboard, ATM or wearable device.

[0116] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0117] The technical solutions provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions in the embodiments of this application.

Claims

1. A display panel, wherein, include: substrate; A first metal layer is disposed on the substrate, and the first metal layer includes a first light-shielding portion; A photosensitive unit is disposed on the side of the first light-shielding portion away from the substrate. The photosensitive unit includes a photosensitive doped portion, a photosensitive portion, and a photosensitive electrode stacked together. One end of the photosensitive portion is connected to the photosensitive doped portion, and the other end of the photosensitive portion is connected to the photosensitive electrode. Wherein, the orthographic projection of the first light-shielding part on the substrate covers the orthographic projection of the photosensitive part on the substrate, and the first light-shielding part is connected to a constant voltage source.

2. The display panel according to claim 1, wherein, The display panel also includes a control unit, which is spaced apart from the photosensitive unit. The display panel further includes a second metal layer, which is disposed on the side of the first light-shielding portion away from the substrate. The second metal layer includes a first electrode and a second electrode spaced apart. The first electrode is connected to the first light-shielding portion, one end of the second electrode is connected to the photosensitive doping portion, and the other end of the second electrode is connected to the control unit.

3. The display panel according to claim 2, wherein, The display panel further includes a thin-film transistor layer, the thin-film transistor layer including the control unit and the photosensitive unit, the thin-film transistor layer including: A semiconductor layer is disposed on the substrate. The semiconductor layer includes a photosensitive doped portion and a semiconductor portion disposed at intervals. The semiconductor portion includes a first doped portion and a second doped portion, and a channel portion located between the first doped portion and the second doped portion. A third metal layer is disposed on the side of the semiconductor layer away from the substrate, and the third metal layer includes a gate, which is disposed corresponding to the channel portion; The first metal layer includes a second light-shielding portion, which is disposed corresponding to the semiconductor portion. The second metal layer includes a third electrode and a fourth electrode, wherein the third electrode is connected to the first doped portion and the fourth electrode is connected to the second doped portion.

4. The display panel according to claim 3, wherein, The photosensitive doped portion is disposed around the second electrode.

5. The display panel according to claim 4, wherein, The display panel also includes: A buffer layer is disposed between the first metal layer and the semiconductor layer; A gate insulating layer is disposed between the semiconductor layer and the third metal layer; An interlayer insulating layer is disposed on the side of the third metal layer away from the gate insulating layer; The display panel has a first through hole and a second through hole. The first electrode passes through the first through hole and is connected to the first light-shielding part. The first through hole penetrates the interlayer insulating layer, the gate insulating layer and at least part of the buffer layer. One end of the second electrode passes through the second through hole and is connected to the photosensitive doped part. The second through hole penetrates the interlayer insulating layer, the gate insulating layer and the photosensitive doped part and the buffer layer. The other end of the second electrode is connected to the third electrode.

6. The display panel according to claim 5, wherein, The display panel also has a third through hole, at least a portion of the photosensitive part is filled in the third through hole, and the third through hole penetrates the interlayer insulating layer and at least a portion of the gate insulating layer; The dimension of the photosensitive part on the side away from the substrate is larger than the dimension of the third through hole on the side away from the substrate.

7. The display panel according to claim 6, wherein, The display panel also includes: A protective layer is provided on the side of the photosensitive part away from the photosensitive doped part, and the protective layer has a fourth through hole that penetrates the protective layer. A planarization layer is disposed on the side of the second metal layer away from the interlayer insulating layer. The planarization layer has a fifth through hole that penetrates at least a portion of the planarization layer and is connected to the fourth through hole. A first transparent electrode layer is disposed on the side of the planar layer away from the second metal layer. The first transparent electrode layer includes the photosensitive electrode, which is connected to the photosensitive part through the fourth through hole and the fifth through hole.

8. The display panel according to claim 7, wherein, The second doped portion is disposed around the fourth electrode.

9. The display panel according to claim 8, wherein, The display panel also has a sixth through hole and a seventh through hole. The third electrode passes through the sixth through hole and is connected to the first doped part. The sixth through hole penetrates the interlayer insulating layer, the gate insulating layer, the first doped part and the buffer layer. The fourth electrode passes through the seventh through hole and is connected to the second doped part. The seventh through hole penetrates the interlayer insulating layer, the gate insulating layer, the second doped part and the buffer layer.

10. The display panel according to claim 3, wherein, The semiconductor unit also includes: The third doped portion is disposed between the channel portion and the first doped portion; A fourth doped portion is disposed between the channel portion and the second doped portion; Wherein, the first doped portion and the second doped portion have the same doping concentration, the third doped portion and the fourth doped portion have the same doping concentration, and the doping concentration of the third doped portion is less than the doping concentration of the first doped portion; The orthographic projection of the second light-shielding portion on the substrate covers the orthographic projection of the channel portion on the substrate, the orthographic projection of the third doped portion on the substrate, and the orthographic projection of the fourth doped portion on the substrate.

11. The display panel according to claim 10, wherein, The orthographic projection of the second light-shielding part on the substrate covers the orthographic projection of the third doped part on the substrate, and the orthographic projection of the second light-shielding part on the substrate covers the orthographic projection of the fourth doped part on the substrate.

12. The display panel according to claim 3, wherein, The display panel includes a display area and a non-display area disposed on at least one side of the display area; The display panel also includes a fan-out section, which is disposed on one side of the substrate and located in the non-display area. The fan-out section includes a first fan-out line, a second fan-out line, and a third fan-out line that are stacked and insulated from each other. The first metal layer includes a first fan-out line, the second metal layer includes a second fan-out line, and the third metal layer includes a third fan-out line. At least two of the first fan-out line, the second fan-out line, and the third fan-out line are arranged to overlap.

13. The display panel according to claim 12, wherein, The first fan-out line and the third fan-out line are arranged to overlap at least partially.

14. The display panel according to claim 12, wherein, The second fan-out line and the third fan-out line are arranged to overlap at least partially.

15. The display panel according to claim 12, wherein, The first fan-out line and the second fan-out line are arranged to overlap at least partially.

16. The display panel according to claim 12, wherein, The second metal layer further includes a connecting portion located within the fan-out area. One end of the connecting portion is connected to the first fan-out line, and the other end of the connecting portion is connected to the second fan-out line.

17. A display device, wherein, Includes a display panel, the display panel comprising: substrate; A first metal layer is disposed on the substrate, and the first metal layer includes a first light-shielding portion; A photosensitive unit is disposed on the side of the first light-shielding portion away from the substrate. The photosensitive unit includes a photosensitive doped portion, a photosensitive portion, and a photosensitive electrode stacked together. One end of the photosensitive portion is connected to the photosensitive doped portion, and the other end of the photosensitive portion is connected to the photosensitive electrode. Wherein, the orthographic projection of the first light-shielding part on the substrate covers the orthographic projection of the photosensitive part on the substrate, and the first light-shielding part is connected to a constant voltage source.

18. The display device according to claim 17, wherein, The display panel also includes a control unit, which is spaced apart from the photosensitive unit. The display panel further includes a second metal layer, which is disposed on the side of the first light-shielding portion away from the substrate. The second metal layer includes a first electrode and a second electrode spaced apart. The first electrode is connected to the first light-shielding portion, one end of the second electrode is connected to the photosensitive doping portion, and the other end of the second electrode is connected to the control unit.

19. The display device according to claim 18, wherein, The display panel further includes a thin-film transistor layer, the thin-film transistor layer including the control unit and the photosensitive unit, the thin-film transistor layer including: A semiconductor layer is disposed on the substrate. The semiconductor layer includes a photosensitive doped portion and a semiconductor portion disposed at intervals. The semiconductor portion includes a first doped portion and a second doped portion, and a channel portion located between the first doped portion and the second doped portion. A third metal layer is disposed on the side of the semiconductor layer away from the substrate, and the third metal layer includes a gate, which is disposed corresponding to the channel portion; The first metal layer includes a second light-shielding portion, which is disposed corresponding to the semiconductor portion. The second metal layer includes a third electrode and a fourth electrode, wherein the third electrode is connected to the first doped portion and the fourth electrode is connected to the second doped portion.

20. The display device according to claim 19, wherein, The photosensitive doped portion is disposed around the second electrode.

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