Avionics ethernet-based bus architecture for avionics system of trainer aircraft

Abstract

The present application belongs to the technical field of aircraft design, and particularly relates to an avionics Ethernet-based bus architecture for an avionics system of a trainer aircraft. The bus architecture comprises a core processor and devices / subsystems, wherein the devices / subsystems comprise a video processor, a display end, a data loading recorder and an electromechanical management computing system; the video processor, the display end, the data loading recorder and the electromechanical management computing system are all connected to the core processor; the core processor comprises a first core processor and a second core processor, the first core processor and the second core processor are hot standbys for each other, and the first core processor and the second core processor are both interconnected to the devices / subsystems by means of a bus; and when an error occurs in either core processor, the core processor in a normal state can continue operating, without affecting normal task processes of the devices / subsystems, and without propagating the error throughout the entire combat flight software, thereby ensuring the normal operation of the avionics system.

Description

A bus architecture for trainer aircraft avionics systems based on avionics Ethernet Technical Field

[0001] This application belongs to the field of aircraft design technology, and specifically relates to a bus architecture for a trainer aircraft avionics system based on aviation Ethernet. Background Technology

[0002] Currently, most in-service trainer aircraft adopt a combined avionics system configuration, which interconnects most avionics equipment / subsystems via a MIL-STD-1553B bus, with unified information scheduling achieved by a bus controller (BC). Signal and data processing tasks for each subsystem are performed by dedicated computers using real-time operating systems such as VxWorks. However, with increasing demands for aircraft mission capabilities and safety, the number of software function points for each avionics system device / subsystem has surged, and the bus data volume has also grown exponentially. This places higher demands on the data transmission rate and reliability of the avionics system bus network. The traditional MIL-STD-1553B bandwidth (1Mbps) is no longer sufficient to meet the needs of avionics systems. Furthermore, current real-time operating systems lack fault isolation capabilities; if one mission process fails, it can spread to the entire operational flight software, severely impacting the functionality of the avionics system.

[0003] Therefore, how to meet the demand for high-capacity information transmission is a problem that needs to be solved. Summary of the Invention

[0004] The purpose of this application is to provide a trainer aircraft avionics system bus architecture based on aviation Ethernet to solve the problem that the traditional MIL-STD-1553B bandwidth (1Mbps) can no longer meet the usage requirements of the avionics system after the existing bus data volume has increased significantly.

[0005] The technical solution of this application is: a trainer aircraft avionics system bus architecture based on aviation Ethernet, including a core processor and various devices / subsystems, each device / subsystem including a video processor, a display terminal, a data loading recorder, and an electromechanical management computing system; the video processor, the display terminal, the data loading recorder, and the electromechanical management computing system are all connected to the core processor;

[0006] The core processor includes a first core processor and a second core processor, which serve as hot backups for each other. Both the first core processor and the second core processor are interconnected with various devices / subsystems via a bus.

[0007] The first core processor is the primary processor, and the second core processor is the secondary processor. Both the first and second core processors simultaneously acquire data from various devices / subsystems. Simultaneously, the first core processor acquires its own operational data and data from various devices / subsystems within the second core processor, and the second core processor acquires its own operational data and data from various devices / subsystems within the first core processor. The first core processor uses its own operational data and data from various devices / subsystems within the second core processor to determine if the second core processor is malfunctioning; if so, it issues an alarm. The second core processor uses its own operational data and data from various devices / subsystems within the first core processor to determine if the first core processor is malfunctioning; if so, it switches to the primary core processor, and the second core processor becomes the primary processor.

[0008] Preferably, the specific method for anomaly detection of the first core processor and the second core processor is as follows: the first core processor stores standard operating data of the second core processor under different operating states, and obtains its own operating data in real time, compares it with the standard operating data, and if they are different, the second core processor is determined to be abnormal; the second core processor stores standard operating data of the first core processor under different operating states, and obtains its own operating data in real time, compares it with the standard operating data, and if they are different, the first core processor is determined to be abnormal.

[0009] Preferably, the first core processor and the second core processor are further provided with a switching unit. When either core processor sends an abnormal message to the switching unit, the corresponding core processor is shut down and the other core processor is turned on. If both core processors send abnormal messages at the same time, the first core processor and the second core processor are simultaneously disconnected and an alarm is triggered.

[0010] Preferably, the video processor stores digital map information, processes it, and transmits it to the core processor. The core processor determines the data type and then transmits it to the display end for display.

[0011] Preferably, the display terminal includes a first display terminal and a second display terminal. The first display terminal is a large-screen touch-screen LCD display, used to undertake the comprehensive control management and comprehensive display functions of the system. The display terminal is interconnected with the core processor via an AFDX bus, and receives system status, system parameters, status information, and control information collected by the core processor. The display terminal is equipped with a classification display processing module, which, after receiving data sent by the core processor, determines the data type and then determines its display position on the large-screen touch-screen LCD display. The second display terminal receives the system parameters and generates a character display screen.

[0012] Preferably, the data loading recorder is connected to the core processor via an AFDX bus, enabling it to load and record data. The core processor receives data from various devices / subsystems, including AFDX bus data, 1553B bus data, all cockpit switch signals, alarm data, and maintenance data. This data is then sent to the data loading recorder for processing. The data loading recorder sends ground mission planning data to the core processor, which then loads it onto various subsystems / devices via data cards, including but not limited to navigation data, radio data, and data link data.

[0013] Preferably, the electromechanical management computing system collects fuel, hydraulic, landing gear, and engine signals, and connects them to the core processor of the avionics system via the 1553B bus for display. At the same time, the electromechanical management computing system collects parameters from the onboard flight control computer, inertial navigation system, air data, engine, power supply, and hydraulic / fuel system, and sends them to the core processor. After determining the data type, the core processor sends the data to the data loading recorder and the protection recorder for recording.

[0014] Preferably, the equipment / subsystem further includes an atmospheric data system, a communication, navigation and identification system, an inertial navigation system and an airborne data link; the atmospheric data system collects total temperature signals, calculates standard pressure altitude, relative pressure altitude, vacuum speed, indicated airspeed, climb rate and field pressure, and sends them to the core processor; after receiving the data collected by the atmospheric data system, the core processor classifies the data and sends it to the avionics system for its use through the electromechanical system.

[0015] Preferably, the communication, navigation, and identification system is capable of airborne VHF communication, full-aircraft audio management, VOR, TCN, DME, radio altimeter, instrument landing, beacon, air traffic control / IFF response, ADS-B, and data link overt / covert communication. The communication, navigation, and identification system is connected to the core processor via the AFDX bus and sends internal data to the core processor. After determining the data type, the core processor sends the data to the display terminal, which then facilitates interaction with air and ground crew.

[0016] Preferably, the inertial navigation system can acquire aircraft position information, attitude information, and time information. The inertial navigation system transmits position, attitude, and time information to the core processor via the AFDX bus. After determining the data type, the core processor sends different data to different locations of the avionics system. The airborne data link receives the various data summarized by the avionics system and sends them to the core processor. After determining the data type, the core processor sends the data to ground nodes or air nodes for data sharing.

[0017] The avionics system bus architecture for trainer aircraft based on avionics Ethernet proposed in this application ensures that even if any core processor malfunctions, the core processor in normal operation can continue to function without affecting the normal mission of individual devices / subsystems or spreading to the entire combat flight software, thus guaranteeing the normal operation of the waypoint system. Furthermore, through the avionics Ethernet bus network, the integrated display, mission management, navigation, radio communication / navigation, air traffic control and IFF, aircraft status monitoring, and other functions of the avionics system, along with their corresponding devices / subsystems, are integrated into a cohesive whole, achieving a high degree of system resource sharing to realize high utilization of aircraft data and a cost-effective equipment usage ratio. Attached Figure Description

[0018] To more clearly illustrate the technical solutions provided in this application, the accompanying drawings will be briefly described below. Obviously, the drawings described below are merely some embodiments of this application.

[0019] Figure 1 is a schematic diagram of the overall configuration of the avionics system of this application. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] As shown in Figure 1, a bus architecture for a trainer aircraft avionics system based on avionics Ethernet is presented. The architecture uses an avionics Ethernet bus as the main network and ARINC 818, MIL-STD-1553B, RS-422A, ARINC 429, etc. as auxiliary buses. Two core processors that serve as hot backups for each other are used as the core of the entire system, which are interconnected with various devices / subsystems to realize information transmission and control management of the avionics system.

[0022] In Figure 1, MC is the core processor; VPU is the video processor; DISPLAY_1 is the first display terminal; DISPLAY_2 is the second display terminal; EMMS is the electromechanical management computing system; ADS is the air data system; DLR is the data loading recorder; CNI is the communication, navigation and identification system; EGI is the inertial navigation system; and DL is the airborne data link.

[0023] It includes a core processor and various devices / subsystems, including a video processor, display terminal, data load recorder, and electromechanical management computing system. The video processor, display terminal, data load recorder, and electromechanical management computing system are all connected to the core processor to realize information transmission and control management of the avionics system.

[0024] The core processor includes a first core processor and a second core processor, which serve as hot backups for each other. Both the first and second core processors are interconnected with various devices / subsystems through buses such as AFDX, 1553B, and RS422 to realize functions such as bus network management, navigation calculation, mode control, and overall alarm processing. They collect data from inertial navigation, electromechanical management computer, parameter acquisition unit, flight control system, engine, etc., and after comprehensive processing, realize integrated display and control on various display terminals.

[0025] The system consists of a primary processor (first core) and a secondary processor (secondary core). Both cores simultaneously acquire data from various devices / subsystems. The first core acquires its own operational data and data from various devices / subsystems, while the second core acquires its own operational data and data from various devices / subsystems. The first core uses this data to determine if the second core is malfunctioning; if so, it issues an alarm. Similarly, the second core uses the same data to determine if the first core is malfunctioning; if so, it switches to the primary processor.

[0026] Through the above design, even if any core processor malfunctions, the core processor in normal condition can continue to operate without affecting the normal mission of other devices / subsystems or spreading to the entire combat flight software, thus ensuring the normal operation of the waypoint system. Furthermore, through the aviation Ethernet bus network, the avionics system's integrated display, mission management, navigation, radio communication / navigation, air traffic control and IFF, aircraft status monitoring, and other functions, along with their corresponding devices / subsystems, are integrated into a cohesive whole, achieving a high degree of system resource sharing to realize high utilization of aircraft data and a cost-effective equipment usage ratio.

[0027] Preferably, the specific method for anomaly detection of the first core processor and the second core processor is as follows: the first core processor stores standard operating data of the second core processor under different operating states, and the second core processor's own operating data is acquired in real time and compared with the standard operating data. If they are different, the second core processor is determined to be abnormal; the second core processor stores standard operating data of the first core processor under different operating states, and the second core processor's own operating data is acquired in real time and compared with the standard operating data. If they are different, the first core processor is determined to be abnormal.

[0028] Preferably, a switching unit is also provided on the first core processor and the second core processor. When either core processor sends an abnormal message to the switching unit, the corresponding core processor is shut down and the other core processor is turned on. If both core processors send abnormal messages at the same time, the first core processor and the second core processor are simultaneously disconnected and an alarm is triggered.

[0029] Preferably, the video processor is used to process video information. During avionics system operation, the video processor stores information such as digital maps, processes it, and transmits it to the core processor. The core processor determines the data type and then transmits it to the display terminal for display.

[0030] Preferably, the display end includes a first display end and a second display end. The first display end is a large-screen touch-screen LCD display, used to undertake the comprehensive control management and comprehensive display functions of the system. The display end is interconnected with the core processor via an AFDX bus, receiving data such as system status, system parameters, status information, and control information collected by the core processor. The display end is equipped with a classification display processing module, which, after receiving data sent by the core processor, determines the data type and then determines its display position on the large-screen touch-screen LCD display before finally displaying it.

[0031] After modifying device parameters and system status via a large touchscreen LCD display, the modified data is fed back to the core processor, enabling comprehensive control and management of the system. The large touchscreen LCD display receives digital map video signals transmitted from the video processor via a video cable to provide video display capabilities; simultaneously, it transmits video signals to a data loading recorder for recording.

[0032] The second display terminal receives parameters from various systems and generates a character display screen. It can load or modify the operating parameters of the avionics system, select the operating mode of the avionics system, and display the status, operating mode, and relevant data of each aircraft system. It is interconnected with the core processor via the AFDX bus, and the core processor provides the status data and equipment parameters of each system for display.

[0033] Preferably, the data load recorder is connected to the core processor via the AFDX bus, enabling it to load and record data. The core processor receives data from various devices / subsystems, including AFDX bus data, 1553B bus data, all cockpit switch signals, alarm data, maintenance data, etc.; it then sends this data to the data load recorder for processing. The data load recorder sends ground mission planning data to the core processor, which then loads it onto various subsystems / devices via data cards, including but not limited to navigation data, radio data, and data link data. The data load recorder is connected to the video processor via Ethernet for loading digital maps, Jepson charts, and electronic checklists. The data load recorder can acquire video signals from the front cockpit HUD, front / rear cockpit LAD, and UFCP via a video cable for video recording; it also records CNI audio signals via an audio cable. The recorded data is used for ground analysis and debriefing.

[0034] Preferably, the electromechanical management and computing system is responsible for the control and management of landing gear system retraction and extension, and fuel system refueling and delivery. Specifically, the electromechanical management and computing system collects various signals from non-avionics systems such as fuel, hydraulics, landing gear, and engines, and connects them to the core processor of the avionics system via the 1553B bus for display; at the same time, the electromechanical management and computing system collects signal parameters from the onboard flight control computer, inertial navigation, air data, engine, power supply, hydraulic / fuel systems, etc., and sends them to the core processor. After determining the data type, the core processor sends the data to the data loading recorder and the protection recorder for recording.

[0035] Preferably, each device / subsystem also includes an atmospheric data system, a communication, navigation and identification system, an inertial navigation system, and an airborne data link.

[0036] The atmospheric data system collects total temperature signals, calculates standard pressure altitude, relative pressure altitude, vacuum velocity, indicated airspeed, climb rate, and field pressure, and sends these data to the core processor. Upon receiving the data from the atmospheric data system, the core processor classifies the data and, through the electromechanical system, sends it to the avionics system for its use.

[0037] The communication, navigation, and identification (CNA) system is capable of airborne VHF communication, aircraft-wide audio management, VOR, TCN, DME, radio altimeter, instrument landing, beacon, air traffic control / IFF (Identification Friend or Foe) response, ADS-B, and data link overt / covert communication. The CNA system connects to the core processor via the AFDX bus, sending internal data to the core processor. The core processor determines the data type and sends the data to the display terminal, enabling interaction with ground and aircrew personnel.

[0038] The inertial navigation system can acquire aircraft position, attitude and time information. The inertial navigation system transmits position, attitude and time information to the core processor through the AFDX bus. After determining the data type, the core processor sends different data to different locations of the avionics system.

[0039] After receiving various data aggregated by the avionics system, the airborne data link sends them to the core processor. The core processor determines the data type and then sends the data to ground or air nodes to achieve data sharing. After receiving the data, the ground can perform safety monitoring.

[0040] Finally, it should be noted that the accompanying drawings of the embodiments disclosed in this invention only involve the structures involved in the embodiments disclosed in this invention. Other structures can refer to the general design. In the absence of conflict, the same embodiment and different embodiments of this invention can be combined with each other.

[0041] In conclusion, the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A trainer aircraft avionics system bus architecture based on avionics Ethernet, characterized in that: It includes a core processor and various devices / subsystems, including a video processor, a display terminal, a data loading recorder, and an electromechanical management computing system; the video processor, display terminal, data loading recorder, and electromechanical management computing system are all connected to the core processor; The core processor includes a first core processor and a second core processor, which serve as hot backups for each other. Both the first core processor and the second core processor are interconnected with various devices / subsystems via a bus. The first core processor is the primary processor, and the second core processor is the secondary processor. Both the first and second core processors simultaneously acquire data from various devices / subsystems. Simultaneously, the first core processor acquires its own operational data and data from various devices / subsystems within the second core processor, and the second core processor acquires its own operational data and data from various devices / subsystems within the first core processor. The first core processor uses its own operational data and data from various devices / subsystems within the second core processor to determine if the second core processor is malfunctioning; if so, it issues an alarm. The second core processor uses its own operational data and data from various devices / subsystems within the first core processor to determine if the first core processor is malfunctioning; if so, it switches to the primary core processor, and the second core processor becomes the primary processor.

2. The trainer aircraft avionics system bus architecture based on avionics Ethernet as described in claim 1, characterized in that: The specific method for the first core processor and the second core processor to determine anomalies is as follows: The first core processor stores the standard operating data of the second core processor under different working states, and obtains its own working data in real time, compares it with the standard operating data, and if they are different, the second core processor is determined to be abnormal. The second core processor stores the standard operating data of the first core processor under different working states, and obtains its own working data in real time and compares it with the standard operating data. If they are different, the first core processor is judged to be abnormal.

3. The trainer aircraft avionics system bus architecture based on avionics Ethernet as described in claim 1, characterized in that: The first and second core processors are also equipped with a switching unit. When either core processor sends an abnormal message to the switching unit, the corresponding core processor is shut down and the other core processor is turned on. If both core processors send abnormal messages at the same time, the first and second core processors are simultaneously shut down and an alarm is triggered.

4. The trainer aircraft avionics system bus architecture based on avionics Ethernet as described in claim 1, characterized in that: The video processor stores digital map information, processes it, and transmits it to the core processor. The core processor determines the data type and then transmits it to the display end for display.

5. The trainer aircraft avionics system bus architecture based on avionics Ethernet as described in claim 1, characterized in that: The display terminal includes a first display terminal and a second display terminal. The first display terminal is a large-screen touch-screen LCD display used for the comprehensive control management and display functions of the system. The display terminal is interconnected with the core processor via an AFDX bus and receives system status, system parameters, status information, and control information collected by the core processor. The display terminal is equipped with a classification display processing module, which determines the data type and its display position on the large-screen touch-screen LCD display after receiving data sent by the core processor. The second display terminal receives system parameters and generates a character display screen.

6. The trainer aircraft avionics system bus architecture based on avionics Ethernet as described in claim 1, characterized in that: The data loading recorder is connected to the core processor via the AFDX bus and is capable of loading and recording data. The core processor receives data sent by various devices / subsystems, including AFDX bus data, 1553B bus data, all switch signals in the cockpit, alarm data, and maintenance data. The data is sent to the data loading recorder for processing. The data loading recorder sends the ground mission planning data to the core processor, and then loads it to various subsystems / equipment in the form of data cards, including but not limited to navigation data, radio data, and data link data.

7. The trainer aircraft avionics system bus architecture based on avionics Ethernet as described in claim 1, characterized in that: The electromechanical management and computing system collects signals from fuel, hydraulics, landing gear, and engines, and connects them to the core processor of the avionics system via the 1553B bus for display. At the same time, the electromechanical management and computing system collects parameters from the onboard flight control computer, inertial navigation system, air data, engine, power supply, and hydraulic / fuel system, and sends them to the core processor. After determining the data type, the core processor sends the data to the data loading recorder and the protection recorder for recording.

8. The trainer aircraft avionics system bus architecture based on avionics Ethernet as described in claim 1, characterized in that: The equipment / subsystem also includes an atmospheric data system, a communication, navigation and identification system, an inertial navigation system and an airborne data link; the atmospheric data system collects total temperature signals, calculates standard pressure altitude, relative pressure altitude, vacuum speed, indicated airspeed, climb rate and field pressure, and sends them to the core processor; after receiving the data collected by the atmospheric data system, the core processor classifies the data and sends it to the avionics system for its use through the electromechanical system.

9. The trainer aircraft avionics system bus architecture based on avionics Ethernet as described in claim 8, characterized in that: The communication, navigation, and identification system is capable of airborne VHF communication, full-aircraft audio management, VOR, TCN, DME, radio altimeter, instrument landing, beacon, air traffic control / IFF response, ADS-B, and data link overt / covert communication. The communication, navigation, and identification system is connected to the core processor via the AFDX bus and sends internal data to the core processor. After determining the data type, the core processor sends the data to the display terminal, which then facilitates interaction with air and ground crew.

10. The trainer aircraft avionics system bus architecture based on avionics Ethernet as described in claim 8, characterized in that: The inertial navigation system can acquire aircraft position, attitude, and time information. The inertial navigation system transmits position, attitude, and time information to the core processor via the AFDX bus. After determining the data type, the core processor sends different data to different locations of the avionics system. The airborne data link receives the various data summarized by the avionics system and sends them to the core processor. After determining the data type, the core processor sends the data to ground nodes or air nodes for data sharing.

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