SAR-ADC circuit, control method therefor, and communication system

Abstract

A SAR-ADC circuit, a control method therefor, and a communication system. The circuit comprises: a timing control module (20), an output selection module (30) and an asynchronous analog-to-digital conversion module group. The timing control module (20) is configured to output at least two second clock signals having the same frequency and successively delayed. An input signal and each of the second clock signals are input into the asynchronous analog-to-digital conversion module group, which is configured to sample and convert the input signal in each pulse period of each of the second clock signals. The output selection module (30) is connected to the asynchronous analog-to-digital conversion module group, and is configured to selectively output a conversion result of the asynchronous analog-to-digital conversion module group in each pulse period of each of the second clock signals.

Description

SAR-ADC circuit and its control method, communication system

[0001] This application claims priority to Chinese Patent Application No. 202411661717.0, filed with the Chinese Patent Office on November 20, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of integrated circuit technology, such as a SAR-ADC circuit and its control method, and a communication system. Background Technology

[0003] With the rapid development of modern electronic technology, high-speed signal processing and data acquisition have become core requirements in many fields. For example, communication systems such as ultra-wideband radio and broadband Ethernet transceivers require low-power, high-speed, and medium-resolution analog-to-digital converters (ADCs). Successive Approximation Register Analog-to-Digital Converters (SAR-ADCs) have become a powerful choice for these applications due to their low analog complexity and excellent power consumption. However, the 1-bit / cycle serial conversion method of SAR-ADCs greatly limits their conversion speed. Under the demands of high-speed signal processing, the higher the output frequency of the SAR-ADC and the lower the pulse width of the input clock signal, the higher the cost and the greater the processing difficulty. Summary of the Invention

[0004] This application provides a SAR-ADC circuit and its control method and communication system. By combining time interleaving technology and asynchronous analog-to-digital conversion technology, the design difficulty of asynchronous analog-to-digital conversion modules can be reduced, while the SAR-ADC circuit can maintain a high conversion speed.

[0005] In a first aspect, embodiments of this application provide a SAR-ADC circuit, including:

[0006] The timing control module is configured to output at least two second clock signals with the same frequency and sequentially delayed;

[0007] An asynchronous analog-to-digital converter module is connected to an input signal and each of the second clock signals, and is configured to sample and convert the input signal in each pulse period of each of the second clock signals;

[0008] The output selection module is connected to the asynchronous analog-to-digital converter module and is configured to select the output of the conversion result of the asynchronous analog-to-digital converter module in each pulse period of each second clock signal.

[0009] Secondly, embodiments of this application also provide a control method for a SAR-ADC circuit, applicable to the SAR-ADC circuit provided in any embodiment of this application; the method includes:

[0010] The timing control module outputs at least two second clock signals with the same frequency and sequentially delayed;

[0011] The asynchronous analog-to-digital converter module samples and converts the input signal in each pulse period of each of the second clock signals;

[0012] The output selection module selects the conversion result of the asynchronous analog-to-digital converter in each pulse period of the second clock signal.

[0013] Thirdly, embodiments of this application also provide a communication system, including: the SAR-ADC circuit provided in any embodiment of this application. Attached Figure Description

[0014] Figure 1 is a schematic diagram of a SAR-ADC circuit provided in an embodiment of this application;

[0015] Figure 2 is a schematic diagram of another SAR-ADC circuit provided in an embodiment of this application;

[0016] Figure 3 is a schematic diagram of the structure of an asynchronous analog-to-digital conversion module provided in an embodiment of this application;

[0017] Figure 4 is a schematic diagram of a dynamic comparator provided in an embodiment of this application;

[0018] Figure 5 is a schematic diagram of another SAR-ADC circuit provided in an embodiment of this application;

[0019] Figure 6 is a schematic diagram of a capacitive digital-to-analog converter provided in an embodiment of this application;

[0020] Figure 7 is a timing diagram of a SAR-ADC circuit provided in an embodiment of this application. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. The described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort should fall within the scope of protection of this application.

[0022] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0023] This application provides a SAR-ADC circuit that can effectively improve the conversion speed of SAR-ADC. Specifically, the SAR-ADC circuit may include: a timing control module, an asynchronous analog-to-digital converter (ADC) module, and an output selection module. The timing control module outputs at least two second clock signals with the same frequency and sequentially delayed. The asynchronous ADC module receives the input signal and each of the second clock signals, and samples and converts the input signal in each pulse period of each second clock signal. The output selection module is connected to the asynchronous ADC module and selects the conversion result of the asynchronous ADC module in each pulse period of each second clock signal.

[0024] The delay between two adjacent second clock signals is not equal to the pulse period of the second clock signal; for example, it may be shorter than one pulse period of the second clock signal. It can be understood that any clock signal can be a pulse signal with a certain frequency, and its pulse can be high or low level, depending on actual needs. The pulse period of the clock signal can be understood as the time between the start times of two adjacent pulses; the pulse duration can be understood as the duration of a pulse, equal to the pulse width; the duty cycle can be understood as the proportion of time the pulse spends within the pulse period. The timing control module may include: a pulse generation structure for outputting a second clock signal; and a timing processing structure for performing timing processing on the second clock signal output by the pulse generation structure, such as advancing and / or delaying it to obtain other second clock signals and outputting them. The specific structure of the timing control module is not limited here.

[0025] An asynchronous analog-to-digital converter (ADC) module may include multiple asynchronous ADC modules, each corresponding to a second clock signal, and sampling and converting the input signal under the control of the connected second clock signal. For example, each asynchronous ADC module samples and converts at the frequency of the second clock signal; in other words, the asynchronous ADC module samples and converts the input signal once per pulse cycle of the connected second clock signal to obtain a conversion result.

[0026] The output selection module, for example, is used to sequentially output the conversion results of the asynchronous analog-to-digital converter (ADC) in each pulse period of each second clock signal, so that the output frequency of the SAR-ADC is higher than the frequency of the second clock signal. Specifically, the second clock signals are delayed sequentially, that is, the pulse periods of the second clock signals start alternately. Correspondingly, the conversion results of the asynchronous ADC in each pulse period are also obtained alternately. After the asynchronous ADC obtains the conversion result in any pulse period, the output selection module can output it. In this way, the conversion results under the control of different second clock signals are equivalent to being output alternately. For example, the delay between the first and last second clock signals can be set to be shorter than one pulse period of the second clock signal, so that a time window of one pulse period can cover one conversion result obtained by the asynchronous ADC under the control of each second clock signal, thereby maximizing the output frequency.

[0027] The SAR-ADC circuit provided in this application includes a timing control module, an output selection module, and an asynchronous analog-to-digital converter (ADC). By employing an asynchronous ADC, the conversion speed can be improved to some extent compared to synchronous ADC. Furthermore, the timing control module and the output selection module work together to implement time interleaving technology. The timing control module provides at least two sequentially delayed second clock signals, ensuring that the module in the asynchronous ADC that receives any of the second clock signals can sample and convert the input signal at the frequency of the second clock signal. The output selection module outputs the conversion results of the asynchronous ADC in each pulse period of each second clock signal, allowing the conversion results with lower sampling frequencies obtained under the control of each second clock signal to interleave, resulting in a higher output frequency digital output result, thereby improving conversion efficiency. Therefore, this application, by combining time interleaving and asynchronous ADC technologies, enables the asynchronous ADC to sample the input signal at a frequency lower than the output code rate for any of the second clock signals, thus reducing the design difficulty and cost of the asynchronous ADC module while maintaining a high conversion speed for the SAR-ADC circuit.

[0028] Figure 1 is a schematic diagram of a SAR-ADC circuit provided in an embodiment of this application. Referring to Figure 1, the SAR-ADC circuit includes: a timing control module 20, an output selection module 30, and an asynchronous analog-to-digital conversion module. The asynchronous analog-to-digital conversion module includes the same number of asynchronous analog-to-digital conversion modules as the second clock signal.

[0029] The timing control module 20 is connected to a first clock signal Clk1 with a first frequency. The timing control module 20 is used to convert the first clock signal Clk1 into at least two second clock signals with a second frequency that are output sequentially with a delay. The second frequency is lower than the first frequency.

[0030] Furthermore, the first frequency is n times the second frequency, and each second clock signal is delayed sequentially and output separately at a preset time interval; the preset time interval is the pulse period of the first clock signal Clk1; n≥2, and n is a positive integer. This setting allows each asynchronous analog-to-digital converter module to start sampling and converting the input signal VIN at the same time interval, and ensures that within one pulse period of the second clock signal, each asynchronous analog-to-digital converter module sequentially starts sampling and converting the input signal VIN once.

[0031] Based on the above embodiments, optionally, the asynchronous analog-to-digital converter (ADC) module includes n asynchronous ADC modules. Figure 1 exemplarily shows two asynchronous ADC modules, namely a first asynchronous ADC module 101 and a second asynchronous ADC module 102. The input terminal of each asynchronous ADC module is connected to the input signal VIN, the clock terminal of each asynchronous ADC module is connected to a corresponding second clock signal, and the output terminal of each asynchronous ADC module is connected to the output selection module 30. The asynchronous ADC module is used to initiate the sampling and conversion of the input signal VIN according to the signal connected to its clock terminal. The timing control module 20 is connected to the clock terminals of each asynchronous ADC module, and is used to convert the first clock signal Clk1 with a first frequency into n second clock signals with a second frequency, and to sequentially delay each second clock signal at a preset time interval and output them to the clock terminals of each asynchronous ADC module, so that each asynchronous ADC module alternately initiates the sampling and conversion of the input signal VIN. The output selection module 30 is connected to the output terminals of each asynchronous analog-to-digital converter (ADC) module and is used to select the conversion results of each asynchronous ADC module. That is, the asynchronous ADC module performs sampling and conversion of the input signal VIN once in each pulse cycle of the corresponding second clock signal; the output selection module 30 is used to time-divisionally select and alternately output the conversion results of each asynchronous ADC module.

[0032] For example, the asynchronous analog-to-digital converter (ADC) module can be a sub-ADC module constructed using any asynchronous SAR-ADC architecture. Compared to synchronous SAR-ADCs, the asynchronous ADC module has a faster quantization speed. Specifically, in a synchronous SAR-ADC, the comparator's clock signal is controlled by a separate high-frequency clock independent of its output signal. Therefore, the comparison interval of a synchronous SAR-ADC is the same, and the comparison interval is determined by the longest comparison time required by the comparator, which greatly limits the operating speed of the synchronous SAR-ADC. However, in an asynchronous SAR-ADC, the comparator's control signal is controlled by the output state of the previous comparator. The comparison intervals of each comparator can be different, and there is no need to determine a uniform comparison interval based on the longest comparison time required by the comparator. This can effectively speed up the quantization process and greatly improve the operating speed of the asynchronous ADC module.

[0033] The timing control module 20 and the output selection module 30 work together to control the asynchronous analog-to-digital converters to alternately sample, convert (i.e., perform analog-to-digital conversion), and output. This is equivalent to using time interleaving technology to interleave the conversion results of multiple asynchronous analog-to-digital converters, thereby obtaining a high output rate final output result. The timing control module 20 can control the asynchronous analog-to-digital converters to alternately sample and convert at a second frequency, while the output selection module 30 can time-divisionally select and alternately output the conversion results of the asynchronous analog-to-digital converters at a first frequency.

[0034] Specifically, the operation of this SAR-ADC circuit can be as follows:

[0035] The timing control module 20 performs a series of processes, including frequency division and delay, on the first clock signal Clk1 to obtain n second clock signals that are sequentially delayed by a preset time interval from the initial pulse. The first second clock signal Clk2_1 is transmitted to the clock terminal of the first asynchronous analog-to-digital converter module 101, the second second clock signal Clk2_2 is transmitted to the clock terminal of the second asynchronous analog-to-digital converter module 102, and so on. Each asynchronous analog-to-digital converter module samples and converts the input signal VIN once within each pulse period of the second clock signal it receives. In other words, whenever a pulse of the second clock signal arrives, the asynchronous analog-to-digital converter module receiving that second clock signal initiates a sampling and conversion of the input signal VIN.

[0036] In this system, the frequency of each second clock signal is 1 / n of the first clock signal Clk1, meaning the pulse period of each second clock signal is n times that of the first clock signal Clk1, and each second clock signal is delayed by the duration of one pulse period of the first clock signal Clk1. Therefore, the second clock signals have the following timing relationship: the i-th pulse of the n second clock signals starts sequentially, and the start time of the i-th pulse of an adjacent second clock signal is separated by one pulse period of the first clock signal Clk1; after the i-th pulse of the nth second clock signal ends, the (i+1)-th pulse of the first second clock signal Clk2_1 begins, and the start time of the i-th pulse of the nth second clock signal and the start time of the (i+1)-th pulse of the first second clock signal Clk2_1 are separated by one pulse period of the first clock signal Clk1; i is a positive integer. Therefore, under the control of each second clock signal, each asynchronous analog-to-digital converter (ADC) performs multiple rounds of sampling and conversion on the input signal VIN. In each round, each ADC sequentially samples and converts the input signal VIN.

[0037] As can be seen from the above analysis, the sampling frequency of each asynchronous analog-to-digital converter (ADC) module is the second frequency, that is, sampling and conversion are performed once every n pulse cycles of the first clock signal Clk1; however, every one pulse cycle of the first clock signal Clk1, an asynchronous ADC module will perform sampling and conversion. The output selection module 30 can output the conversion result after each asynchronous ADC module completes one sampling and conversion. Therefore, by cyclically and alternately outputting the conversion results of each asynchronous ADC module, the output selection module 30 can interweave the conversion results into a digital output result D with the first frequency. Specifically, the conversion result of the first asynchronous ADC module 101 is denoted as Dout1, the conversion result of the second asynchronous ADC module 102 is denoted as Dout2, and so on. In each round, the digital output result D sequentially includes Dout1, Dout2, ..., Doutn.

[0038] The SAR-ADC circuit provided in this application embodiment includes a timing control module 20, an output selection module 30, and n asynchronous analog-to-digital conversion modules. By employing asynchronous analog-to-digital conversion modules, the conversion speed can be improved to a certain extent compared to synchronous analog-to-digital conversion. Furthermore, the timing control module 20 and the output selection module 30 work together to implement time interleaving technology. By controlling the n asynchronous analog-to-digital conversion modules to alternately sample and convert the input signal VIN, and alternately outputting the conversion results of each asynchronous analog-to-digital conversion module, the conversion results output by the n asynchronous analog-to-digital conversion modules with low sampling frequencies are interleaved to obtain a high-output-frequency digital output result D, thereby improving conversion efficiency. Therefore, this application embodiment, by combining time interleaving technology and asynchronous analog-to-digital conversion technology, enables each asynchronous analog-to-digital conversion module to sample the input signal at a frequency lower than the output code rate, thereby reducing the design difficulty and cost of each asynchronous analog-to-digital conversion module while maintaining a high conversion speed for the SAR-ADC circuit.

[0039] The basic working principle of the SAR-ADC circuit has been explained in the above embodiments. The circuit structure that each module in the circuit may have is illustrated below.

[0040] Figure 2 is a schematic diagram of another SAR-ADC circuit provided in an embodiment of this application. Referring to Figure 2, in one embodiment, optionally, the timing control module 20 includes: a frequency divider unit 210 and n-1 delay units cascaded in sequence. Two delay units are shown exemplary in Figure 2, namely the first delay unit 221 and the second delay unit 222.

[0041] The frequency division unit 210 receives the first clock signal Clk1 and outputs the first second clock signal Clk2_1, while each delay unit outputs the remaining second clock signals. The frequency division unit 210 is used to divide the first clock signal Clk1 by n. The delay unit is used to delay the signal input to its terminal by a preset time interval before outputting it.

[0042] Specifically, the input of the frequency divider unit 210 is connected to the first clock signal Clk1, and the output of the frequency divider unit 210 is connected to the clock terminal of the first asynchronous analog-to-digital converter module 101, outputting the first second clock signal Clk2_1. The frequency divider unit 210 is used to divide the first clock signal Clk1 by n. In Figure 2, for example, n=3, the frequency divider unit 210 divides the first clock signal Clk1 by 3, and the second frequency is 1 / 3 of the first frequency. The input of the first delay unit (i.e., the first delay unit 221) is connected to the output of the frequency divider unit 210, and the input of each subsequent delay unit is connected to the output of the previous delay unit. The output of each frequency divider unit is connected to the clock terminals of the 2nd to nth asynchronous analog-to-digital converter modules, and the outputs of the 1st to n-1th frequency divider units output the 2nd to nth second clock signals, respectively. As shown in Figure 2, the output of the first frequency divider unit 221 is connected to the clock terminal of the second asynchronous analog-to-digital converter module 102, and the output of the second frequency divider unit 222 is connected to the clock terminal of the third asynchronous analog-to-digital converter module 103. The delay unit is used to delay the signal input to its terminal by a preset time interval before outputting it. This allows the timing control module 20 to output each second clock signal sequentially at preset time intervals.

[0043] Based on the above embodiments, n can optionally be selected as any positive integer greater than 1, such as an odd or even number. Preferably, n can be set to an integer power of 2 to simplify the structure of the frequency division unit 210 and make it easy to implement. For example, n can be set to 2 or 4.

[0044] Based on the above embodiments, optionally, each pulse in any second clock signal is aligned with a portion of the pulses in the first clock signal. For example, the frequency divider unit 210 can extract one pulse from the first clock signal Clk1 every n-1 pulse intervals as one pulse in the first second clock signal; since the output delay between adjacent second clock signals is one pulse period of the first clock signal Clk1, each pulse of the remaining second clock signals also corresponds to a different pulse in the first clock signal Clk1.

[0045] Based on this, the output selection module 30 can be connected to the first clock signal Clk1, so that the output selection module 30 selects and alternately outputs the conversion results of each asynchronous analog-to-digital converter according to the first clock signal Clk1, so as to ensure that the output selection module 30 outputs at the first frequency.

[0046] Referring again to Figure 2, based on the above embodiments, optionally, the asynchronous analog-to-digital conversion module includes: a sampling switch unit, a serial comparison unit, and a digital-to-analog conversion unit. Exemplarily shown in Figure 2, the first asynchronous analog-to-digital conversion module 101 includes: a first sampling switch unit 1101, a first serial comparison unit 1201, and a first digital-to-analog conversion unit 1301; the second asynchronous analog-to-digital conversion module 102 includes: a second sampling switch unit 1102, a second serial comparison unit 1202, and a second digital-to-analog conversion unit 1302; and the third asynchronous analog-to-digital conversion module 103 includes: a third sampling switch unit 1103, a third serial comparison unit 1203, and a third digital-to-analog conversion unit 1303.

[0047] In this configuration, for any asynchronous analog-to-digital converter (ADC), a sampling switch unit is connected to both the input and clock terminals of the ADC. The sampling switch unit is activated when the ADC receives a pulse of the corresponding second clock signal, initiating sampling of the input signal. For example, the sampling switch unit samples for the duration of the pulse and deactivates after the pulse ends to stop sampling. A serial comparison unit is connected to the sampling switch unit, the ADC unit, and the clock and output terminals of the ADC. The serial comparison unit, in conjunction with the ADC unit, converts the sampling result output by the sampling switch unit between adjacent pulses of the second clock signal received by the ADC (i.e., from the end of any pulse to the beginning of the next pulse), to obtain a conversion result. For example, the conversion result is an m-bit quantized code. For example, the serial comparison unit compares the sampling results, forms a quantization code of one bit in the conversion result based on the comparison result, and feeds the comparison result back to the digital-to-analog converter unit. The digital-to-analog converter unit processes the comparison result and sends it back to the serial comparison unit for comparison again to generate the next quantization code. The comparison result of the second comparison is then fed back to the digital-to-analog converter unit. This process is repeated until an m-bit quantization code is formed.

[0048] Specifically, for any asynchronous analog-to-digital converter (ADC), the output selection module 30 outputs the conversion result obtained by the ADC in the previous pulse period of the second clock signal within any pulse time of the second clock signal corresponding to the ADC. In other words, the ADC can sample within the current pulse time and perform the conversion after the current pulse ends and before the next pulse arrives; within the next pulse time, the output selection module 30 outputs the conversion result obtained by the ADC in the current pulse period. For any asynchronous ADC, the output process of the conversion result obtained in the current pulse period can be performed simultaneously with the sampling process in the next pulse period. This allows the signal output process to not occupy additional time, further improving the output rate.

[0049] Based on the above embodiments, optionally, referring to Figure 2, the input signal can be a set of differential signals; each asynchronous analog-to-digital converter (ADC) module samples and converts the differential signals. Specifically, the input terminals of the asynchronous ADC module include a first differential input terminal and a second differential input terminal; each first differential input terminal is interconnected, and each second differential input terminal is interconnected, so that each asynchronous ADC module can access the input signal. As shown in Figure 2, the first differential input terminal IN11 of the first asynchronous ADC module 101, the first differential input terminal IN12 of the second asynchronous ADC module 102, and the first differential input terminal IN13 of the third asynchronous ADC module 103 are connected; the second differential input terminals IN21 of the first asynchronous ADC module 101, IN22 of the second asynchronous ADC module 102, and IN23 of the third asynchronous ADC module 103 are connected.

[0050] In any asynchronous analog-to-digital converter (ADC) module: the first input terminal of the sampling switch unit is connected to the first differential input terminal, the second input terminal of the sampling switch unit is connected to the second differential input terminal, and the clock terminal of the sampling switch unit is connected to the clock terminal of the asynchronous ADC module. The first input terminal of the serial comparator unit is connected to the first output terminal of the sampling switch unit and the first output terminal of the ADC unit, the second input terminal of the serial comparator unit is connected to the second output terminal of the sampling switch unit and the second output terminal of the ADC unit, the clock terminal of the serial comparator unit is connected to the clock terminal of the asynchronous ADC module, the first output terminal of the serial comparator unit is connected to the first input terminal of the ADC unit, the second output terminal of the serial comparator unit is connected to the second input terminal of the ADC unit, and the third output terminal of the serial comparator unit is connected to the output terminal of the asynchronous ADC module.

[0051] Figure 3 is a schematic diagram of an asynchronous analog-to-digital converter module provided in an embodiment of this application. Referring to Figure 3, based on the above embodiments, optionally, in the asynchronous analog-to-digital converter module 10, the serial comparison unit 120 includes: m comparison sub-units 121, the conversion result includes m-bit quantization code; m≥2, m is a positive integer. The first input terminal of the digital-to-analog converter unit 130 includes m-1 first sub-input terminals, namely the first first sub-input terminal N11, the second first sub-input terminal N12, ..., the (m-1)th first sub-input terminal N1m-1; the second input terminal of the digital-to-analog converter unit 130 includes m-1 second sub-input terminals corresponding to the m-1 first sub-input terminals, namely the first second sub-input terminal N21, the second second sub-input terminal N22, ..., the (m-1)th second sub-input terminal N2m-1.

[0052] In this configuration, the first input terminal P1 of each comparison subunit 121 is connected to the first input terminal of the serial comparison unit 120, and the second input terminal P2 of each comparison subunit 121 is connected to the second input terminal of the serial comparison unit 120. The first output terminal P5 of the first m-1 comparison subunits 121 is connected to the m-1 first sub-input terminals of the digital-to-analog converter unit 130, and the second output terminal P6 of the first m-1 comparison subunits 121 is connected to the m-1 second sub-input terminals of the digital-to-analog converter unit 130. The third output terminal P7 of each comparison subunit 121 is connected to the output terminal of the asynchronous analog-to-digital converter module 10. The clock terminal P3 of the first comparison subunit 121 is connected to the clock terminal of the serial comparison unit 120. The clock terminal P3 of each subsequent comparison subunit 121 is connected to the identification signal output terminal P4 of the previous comparison subunit 121. The comparison subunit 121 is used to start comparing the signals input to the first input terminal P1 and the second input terminal P2 of the comparison subunit 121 respectively after receiving a pulse at its clock terminal P3. After the comparison is completed, the pulse of the identification signal r is output through the identification signal output terminal P4, the comparison result is fed back to the digital-to-analog converter unit 130 through the first output terminal P5 and the second output terminal P6 of the comparison subunit 121, and one bit of quantization code in the conversion result is output through the third output terminal P7 of the comparison subunit 121. It can be understood that the clock terminal of the first comparison subunit 121 receives the second clock signal corresponding to the asynchronous analog-to-digital converter module, and the pulse it receives is the pulse in the second clock signal; the clock terminals of subsequent comparison subunits 121 receive the identification signal r output by the previous comparison subunit 121, and the pulses they receive are the pulses in the identification signal r.

[0053] It is understandable that the result of an m-bit conversion can be represented as Dout. <m-1:0>The first comparison subunit 121 outputs the first bit of quantized code Dout. <m-1>The second comparison subunit 121 outputs the second quantization code Dout. <m-2>The (m-1)th comparison subunit 121 outputs the (m-1)th bit of quantization code Dout. <1> The m-th comparison subunit 121 outputs the m-th quantized code Dout. <0> Since there is no next comparison subunit 121 after the m-th comparison subunit 121, the identification signal output terminal P4 in the m-th comparison subunit 121 can be set to be empty and not output; and the m-th comparison subunit 121 does not need to feed back the comparison result to the digital-to-analog conversion unit 130.

[0054] Further, the comparator subunit 121 includes a dynamic comparator U1 and a D flip-flop DFF. The clock input of the dynamic comparator U1 is connected to the clock input P3 of the comparator subunit 121. The two inputs of the dynamic comparator U1 are connected to the first input P1 and the second input P2 of the comparator subunit 121, for example, the positive input of the dynamic comparator U1 is connected to the first input P1, and the negative input is connected to the second input P2. The two outputs of the dynamic comparator are connected to the first output P5 and the second output P6 of the comparator subunit 121, for example, the positive output of the dynamic comparator U1 is connected to the first output P5, and the negative output is connected to the second output P6. The input of the D flip-flop DFF is connected to one of the outputs of the dynamic comparator U1, for example, the negative output; the output of the D flip-flop DFF is connected to the third output P7 of the comparator subunit 121. The flag input of the dynamic comparator U1 is connected to the clock input of the D flip-flop DFF and the flag signal output P4 of the comparator subunit 121.

[0055] Figure 4 is a schematic diagram of a dynamic comparator provided in an embodiment of this application. Referring to Figure 4, based on the above embodiments, the dynamic comparator U1 optionally includes an operational amplifier circuit 1211 and a logic circuit 1212. The operational amplifier circuit 1211 serves as the part of the dynamic comparator U1 that implements the comparison function. Specifically, the two input terminals of the operational amplifier circuit 1211 are respectively connected to the two input terminals of the dynamic comparator U1, and then respectively connected to the first input terminal P1 and the second input terminal P2 of the comparison subunit 121; the clock terminal of the operational amplifier circuit 1211 is connected to the clock terminal of the dynamic comparator U1, and then connected to the clock terminal P3 of the comparison subunit 121; the two output terminals of the operational amplifier circuit 1211 are respectively connected to the two output terminals of the dynamic comparator U1, and then respectively connected to the first output terminal P5 and the second output terminal P6 of the comparison subunit 121. Operational amplifier circuit 1211 is used to compare the signals connected to its two input terminals respectively; for example, the comparison of the signals connected to its two input terminals is initiated after a pulse is received at the clock terminal of operational amplifier circuit 1211. For example, operational amplifier circuit 1211 can be a differential operational amplifier. Logic circuit 1212 is used to generate a pulse of the identification signal r based on the comparison result of operational amplifier circuit 1211. The two input terminals of logic circuit 1212 are respectively connected to the two output terminals of operational amplifier circuit 1211, and the output terminal of logic circuit 1212 is connected to the identification terminal of dynamic comparator U1, and then connected to the identification signal output terminal P4 of comparator subunit 121. Logic circuit 1212 can be constructed, for example, using NAND gates or XOR gates. Logic circuit 1212 can determine whether operational amplifier circuit 1211 has completed the comparison based on the voltage changes at the two output terminals of operational amplifier circuit 1211.

[0056] It is understandable that the time required for each comparison subunit 121 to complete the comparison is determined based on the performance of the operational amplifier circuit 1211 and the voltage difference between the signals connected to the two input terminals of the operational amplifier circuit 1211. For example, for the same dynamic comparator U1, the greater the voltage difference between the signals connected to the two input terminals of the current dynamic comparator U1, the shorter the identification time required for the operational amplifier circuit 1211 to perform voltage comparison; and, after the operational amplifier circuit 1211 completes the comparison, the logic circuit 1212 performs logic processing to output the pulse of the identification signal r. Therefore, the shorter the identification time required for the operational amplifier circuit 1211 to perform voltage comparison, the shorter the time required for the dynamic comparator U1 to output the pulse of the identification signal r. In this way, the asynchronous analog-to-digital converter module 10 can adaptively adjust the time required for each comparison subunit 121 to output the pulse of the identification signal r according to the change of the voltage output by the digital-to-analog converter unit 130, thereby minimizing the comparison time and improving the conversion speed while ensuring the accuracy of the comparison result of the dynamic comparator U1. For example, if a voltage jump occurs at at least one output of the current comparison subunit U1, and the voltage jump of the output signal of the digital-to-analog converter 130 is larger due to the feedback of the jump to the digital-to-analog converter 130, it indicates that the change is more easily recognized by the next comparison subunit 121. In this case, the recognition time required for the next comparison subunit 121 to complete the comparison is shorter, and the pulse time of the corresponding output identification signal r is shorter.

[0057] In this system, the D flip-flops (DFFs) in each comparison subunit 121 serve to align the output signals, or in other words, to indicate the completion time of the conversion. Specifically, in the serial comparison unit 120, when the D flip-flop (DFF) in the last comparison subunit 121 is triggered, it indicates that the last dynamic comparator U1 has completed the comparison. At this time, since the next pulse of the second clock signal has not yet arrived, and the next pulse of each indicator signal r has not yet been output, each dynamic comparator U1 still maintains the output state after receiving the previous pulse, which is equivalent to performing output state latching. Therefore, taking the triggering time of the D flip-flop (DFF) in the last comparison subunit 121 as the standard, the output result of each dynamic comparator U1 at this time can represent the comparison result obtained in this conversion. The m-bit quantization code output by the third output terminal of each comparison subunit in the asynchronous analog-to-digital conversion module at this time can be used as the conversion result of the asynchronous analog-to-digital conversion module.

[0058] Figure 5 is a schematic diagram of another SAR-ADC circuit provided in an embodiment of this application. Figure 5 exemplarily shows the specific structure of the first asynchronous analog-to-digital converter module 101. The structure of the second asynchronous analog-to-digital converter module 102 is the same as that of the first asynchronous analog-to-digital converter module 101 and is not specifically shown. Referring to Figure 5, based on the above embodiments, optionally, taking the structure of the first digital-to-analog converter unit 1301 as an example, the digital-to-analog converter unit includes a capacitive digital-to-analog converter (CDAC). Specifically, referring to Figure 6, the capacitive digital-to-analog converter (CDAC) may include a binary capacitor array; in a corresponding set of first sub-input terminals and second sub-input terminals, the capacitance value of the capacitor connected between the first sub-input terminal and the first output terminal of the capacitive digital-to-analog converter (CDAC) is the same as the capacitance value of the capacitor connected between the second sub-input terminal and the second output terminal of the capacitive digital-to-analog converter (CDAC). The capacitance values ​​of the capacitors connected between different first sub-input terminals and the first output terminal of the capacitive digital-to-analog converter (CDAC) may be different.

[0059] Based on this, the time required for each comparison subunit 121 to complete the comparison and output the pulse of the identification signal r can be determined by the capacitance value between the first output terminal of the previous comparison subunit 121 and the first output terminal of the capacitive digital-to-analog converter (CDAC). For example, the larger the capacitance value, the greater the voltage change coupled to the output terminal of the capacitive digital-to-analog converter (CDAC), and the shorter the time required for the next comparison subunit 121 to complete the comparison and output the pulse of the identification signal r.

[0060] Based on the above embodiments, optionally, for each comparison subunit 121, the dynamic comparator U1 can be configured to output the pulse of the identification signal r after a certain delay after completing the comparison, so as to provide a certain time margin for the comparison process of the operational amplifier circuit 1211, ensuring that the comparison is completed before the pulse of the identification signal r is output from the identification signal output terminal P4. The delay time for the dynamic comparator U1 to output the pulse of the identification signal r after completing the comparison can be adjusted according to requirements.

[0061] Specifically, the dynamic comparator U1 may further include a delay control circuit connected to the logic circuit 1212. The delay control circuit controls the delay duration between the time when the operational amplifier circuit 1211 completes the comparison and the time when the pulse of the identifier signal r is output from the identifier signal output terminal P4. For example, the delay control circuit can be connected between the operational amplifier circuit 1211 and the logic circuit 1212, such as connecting the two output terminals of the operational amplifier circuit 1211 and the two input terminals of the logic circuit 1212 respectively. By controlling the delay duration of the output signals from the two output terminals of the operational amplifier circuit 1211 being transmitted to the two input terminals of the logic circuit 1212, the delay duration between the time when the operational amplifier circuit 1211 completes the comparison and the time when the pulse of the identifier signal r is output from the identifier signal output terminal P4 is controlled. Alternatively, the delay control circuit can be connected between the output of logic circuit 1212 and the identification signal output P4. The delay control circuit controls the delay duration from the signal output by logic circuit 1212 to the identification signal output P4. By delaying the output signal of logic circuit 1212 before outputting it, the delay duration between the completion of the comparison by operational amplifier circuit 1211 and the output of the identification signal pulse r by identification signal output P4 is controlled. The delay control circuit can be constructed using any delay device with adjustable delay duration. The specific configuration of the delay control circuit can be adjusted according to actual needs.

[0062] For example, the shorter the recognition time required for comparison in comparison subunit 121, the higher the reliability of its comparison result. Therefore, the delay duration provided by its internal delay control circuit can be set to be shorter. Specifically, the delay duration of the pulse for the output identification signal r of the first comparison subunit 121 after completing the comparison can be set to a minimum value. Since the first comparison subunit 121 can begin comparison from the moment it receives the pulse of the second clock signal, even if its delay duration is set short, the comparison time of the first comparison subunit 121 is still sufficient from the start of the pulse and does not affect the accuracy of its output result.

[0063] Referring again to Figure 5, based on the above embodiments, optionally, taking the structure of the first sampling switch unit 1101 as an example, the sampling switch unit may include two switch subunits whose switching states are controlled by the clock signal of the sampling switch unit, respectively connected between the first input terminal and the first output terminal of the sampling switch unit, and between the second input terminal and the second output terminal of the sampling switch unit, so as to control whether the input signal is transmitted backward through the sampling switch unit.

[0064] Based on the above embodiments, optionally, the SAR-ADC circuit further includes: a reset module, connected to each dynamic comparator U1 and each digital-to-analog converter 130 respectively; the reset module is used to reset each dynamic comparator and each digital-to-analog converter. For any asynchronous analog-to-digital converter 10, the reset module is used to reset each dynamic comparator U1 and digital-to-analog converter 130 in the asynchronous analog-to-digital converter 10 within any pulse period of the second clock signal Clk2 input to the asynchronous analog-to-digital converter 10, after the D flip-flop DFF in the last comparison subunit 121 of the asynchronous analog-to-digital converter 10 is triggered, so as to perform sampling and conversion in the next pulse period. It can be understood that, according to actual needs, the time required for the digital-to-analog converter 130 to perform the three steps of sampling, conversion and reset within one pulse period of the second clock signal Clk2 can be allocated.

[0065] In summary, the embodiments of this application provide a high-speed time-interleaved asynchronous SAR-ADC circuit. By using time-interleaving technology, the conversion results of n asynchronous analog-to-digital conversion modules with low sampling rates are interleaved to obtain quantization codes with high output rates. This can effectively improve conversion efficiency, reduce circuit power consumption, and reduce circuit design difficulty.

[0066] The structure and operation of the time-interleaved asynchronous SAR-ADC circuit will be explained below with reference to Figure 5-7, taking n=2 and m=8 as an example, and with reference to a specific embodiment.

[0067] Referring to Figure 5, exemplarily, the conversion result of the first asynchronous analog-to-digital converter 101 includes Dout1<7:0>, the conversion result of the second asynchronous analog-to-digital converter 102 includes Dout2<7:0>, and the interleaved digital output result is D<7:0>. Taking the first asynchronous analog-to-digital converter 101 as an example, the comparison results of the first seven comparison subunits 121 in the first serial comparison unit 1201 include out_p<7:1> and out_n<7:1>; the signal output from the first output terminal of the first digital-to-analog converter 1301 is Comp_in_p, and the signal output from the second output terminal is Comp_in_m. Referring to Figure 7, the time period includes the sampling time period Ts, the conversion time period Tc, and the reset time period Tr. The dotted dashed line indicates the working stage of the first asynchronous analog-to-digital converter 101 within one pulse cycle of the first second clock signal Clk2_1, and the short dashed line indicates the working stage of the second asynchronous analog-to-digital converter 102 within one pulse cycle of the second second clock signal Clk2_2. Each conversion sub-stage in the conversion period represents the time period during which each comparison sub-unit 121 performs comparisons. It is evident that the delay time corresponding to different comparison sub-units 121 can be different. Referring to Figure 6, which shows the specific structure of the binary capacitor array of the capacitive digital-to-analog converter (CDAC), where C represents the base capacitance value and kC represents the connection of k times the base capacitance value. Specifically, the capacitance value connected between the first sub-input terminal N11 and the first second sub-input terminal N21 and the first output terminal of the CDAC is 32C. The first sub-input terminal N11 is connected to the second output terminal of the CDAC via an inverter (or digital circuit) and a capacitor (32C). The first second sub-input terminal N21 is connected to the second output terminal of the CDAC via an inverter (or digital circuit) and a capacitor (32C). The connection method between the second to fifth first sub-input terminals and the two output terminals of the CDAC is the same as that between the first first sub-input terminal N11 and the two output terminals of the CDAC. The connection method is similar, the difference being that the capacitance value is halved sequentially. The connection method between the 2nd-5th second sub-input terminals and the two output terminals of the capacitive digital-to-analog converter (CDAC) is similar to the connection method between the 1st second sub-input terminal N21 and the two output terminals of the CDAC, the difference being that the capacitance value is halved sequentially. The 6th and 7th first sub-input terminals N16 and N17 are both connected to the first output terminal of the CDAC through an inverter (or digital circuit) and a capacitor (capacitance value C). The 6th and 7th second sub-input terminals N26 and N27 are both connected to the second output terminal of the CDAC through an inverter (or digital circuit) and a capacitor (capacitance value C). For example, during circuit operation, each second sub-input terminal can be set to a fixed potential, such as grounding.

[0068] Referring to Figures 5-7, taking a high-potential pulse as an example, the operation of the SAR-ADC circuit includes:

[0069] Frequency divider unit 210 divides the first clock signal Clk1 by two, adjusting the duty cycle to 25%, to obtain two second clock signals Clk2_1 and Clk2_2, which serve as the sampling clocks for the two asynchronous analog-to-digital converter modules 101 and 102, respectively. When the falling edge of the first second clock signal Clk2_1 arrives, the first asynchronous analog-to-digital converter module 101 finishes sampling and begins conversion; at this time, the second second clock signal Clk2_2 is low, and the second asynchronous analog-to-digital converter module 102 is in a reset state.

[0070] During the conversion process of the first asynchronous analog-to-digital converter module 101, the first comparison subunit 121 begins comparison and obtains the first comparison result out_p. <7> and out_n <7> The feedback control capacitor-type digital-to-analog converter (CDAC) changes the input voltages Comp_in_p and Comp_in_n of all comparator subunits 121, and then latches the first quantization code Dout1. <7> The identification signal r is generated as the comparison clock of the second comparison subunit 121; the second comparison subunit 121 starts comparison and repeats the above steps to perform serial comparison until all comparison subunits 121 complete the comparison and latch the comparison result, and obtain the conversion result Dout1<7:0>.

[0071] In this process, the dynamic comparator U1 in the last comparison subunit 121 completes the comparison and generates an identifier signal r. The comparison results of all dynamic comparators U1 are aligned and output through the D flip-flop DFF to obtain the conversion result Dout1<7:0> composed of the first 8-bit quantized code, which is then latched. Subsequently, all dynamic comparators U1 and the capacitive digital-to-analog converter CDAC are reset, the circuit is reset, and the circuit waits for the next rising edge of the first second clock signal Clk2_1 before repeating the above sampling conversion and reset steps.

[0072] In this process, after being processed by the delay unit 220, the first second clock signal Clk2_1 is delayed by one pulse period of the first clock signal Clk1 to obtain the second second clock signal Clk2_2, which serves as the sampling clock for the second asynchronous analog-to-digital converter module 102. The quantization operation of the first asynchronous analog-to-digital converter module 101 is repeated to obtain the conversion result Dout2<7:0> composed of the second 8-bit quantized code.

[0073] Finally, the first clock signal Clk1 controls the output selection circuit 30 to alternately select the outputs Dout1<7:0> and Dout2<7:0>. At this point, the sampling frequency of the two asynchronous analog-to-digital conversion modules is the second frequency, and the digital output result D<7:0> composed of 8-bit quantized code with the output frequency of the first frequency is obtained.

[0074] For example, the duty cycle of the first clock signal Clk1 is 50%, the sampling period Ts occupies, for example, half the pulse period of the first clock signal Clk1, the conversion phase Tc occupies, for example, 1.25 times the pulse period of the first clock signal Clk1, and the reset phase Tr occupies, for example, 0.25 times the pulse period of the first clock signal Clk1. That is, the duration of one pulse period of the first clock signal Clk1 is denoted as 1clk; for any asynchronous analog-to-digital converter module, after sampling is completed by one high-level pulse of the connected second clock signal, an 8-bit quantization code is obtained after 5 / 4clk. Before the next high-level pulse of the connected second clock signal arrives, another 1 / 4clk is used to complete the reset of each dynamic comparator and digital-to-analog conversion unit in the asynchronous analog-to-digital converter module. It is understood that the time required for each of the above steps is for illustrative purposes only.

[0075] In summary, the SAR-ADC circuit provided in this application has the following advantages:

[0076] 1. By assigning a comparison subunit to the generation of each quantization code, the dynamic comparator is used as a latch, so that the comparison result can be directly passed to the digital logic section of the capacitive digital-to-analog converter (CDAC) by the dynamic comparator. This eliminates the logic register structure steps required by traditional SAR-ADCs, greatly speeds up the quantization time, simplifies the circuit structure, reduces production costs, and reduces the circuit area occupied.

[0077] 2. The delay time of the output identification signal of each comparator subunit after the comparison is completed can be customized and refined, realizing fully asynchronous quantization from dynamic comparator to capacitive digital-to-analog converter (CDAC) and maximizing the utilization of the quantization time of 1-bit / cycle ADC.

[0078] 3. By using time interleaving technology on the n-channel asynchronous analog-to-digital converter modules, the input signal can be sampled at a frequency lower than the output bit rate, reducing the design difficulty of each asynchronous analog-to-digital converter module while maintaining a high output rate.

[0079] This application also provides a control method for a SAR-ADC circuit, which, when applied to the SAR-ADC circuit provided in any embodiment of this application, has corresponding beneficial effects. The control method for the SAR-ADC circuit includes the following steps:

[0080] 1) The timing control module outputs at least two second clock signals with the same frequency and delayed sequentially.

[0081] 2) The asynchronous analog-to-digital converter sampled and converted the input signal in each pulse period of each second clock signal.

[0082] 3) The output selection module selects the conversion result of the asynchronous analog-to-digital converter in each pulse period of each second clock signal.

[0083] This application also provides a communication system, including the SAR-ADC circuit provided in any embodiment of this application, which has corresponding beneficial effects. Exemplarily, the SAR-ADC circuit can be applied to the receive (RX) link of a communication system. This communication system can be a vehicle-mounted communication system or a communication system in other application scenarios.

[0084] The various processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this application can be achieved.

Claims

1. A SAR-ADC circuit, comprising: The timing control module is configured to output at least two second clock signals with the same frequency and sequentially delayed; An asynchronous analog-to-digital converter module is connected to an input signal and each of the second clock signals, and is configured to sample and convert the input signal in each pulse period of each of the second clock signals; The output selection module is connected to the asynchronous analog-to-digital converter module and is configured to select the output of the conversion result of the asynchronous analog-to-digital converter module in each pulse period of each second clock signal.

2. The SAR-ADC circuit according to claim 1, wherein, The timing control module is connected to a first clock signal with a first frequency; The timing control module is configured to convert the first clock signal into at least two second clock signals with a second frequency that are output sequentially with a delay; the second frequency is lower than the first frequency.

3. The SAR-ADC circuit according to claim 2, wherein, The first frequency is n times the second frequency, and each of the second clock signals is delayed sequentially by a preset time interval and then output separately; the preset time interval is the pulse period of the first clock signal. n≥2, and n is a positive integer.

4. The SAR-ADC circuit according to claim 3, wherein, The timing control module includes: a frequency division unit and n-1 delay units cascaded in sequence; The frequency division unit receives the first clock signal and outputs the first second clock signal, and each of the delay units outputs the remaining second clock signals respectively; the frequency division unit is configured to divide the first clock signal by n; the delay unit is configured to delay the signal received at its input terminal by the preset time interval before outputting it.

5. The SAR-ADC circuit according to claim 4, wherein, The input terminal of the frequency divider unit is connected to the first clock signal, and the output terminal of the frequency divider unit outputs the first second clock signal; The input terminal of the first delay unit is connected to the output terminal of the frequency divider unit, and the input terminals of each subsequent delay unit are connected to the output terminal of the previous delay unit; the output terminals of the first to n-1 frequency dividers respectively output the second to nth second clock signals.

6. The SAR-ADC circuit according to any one of claims 1-5, wherein, The asynchronous analog-to-digital conversion module includes: an asynchronous analog-to-digital conversion module with the same number of asynchronous analog-to-digital conversion modules as the second clock signal; Each of the asynchronous analog-to-digital converter modules has its input terminal connected to the input signal, its clock terminal connected to the corresponding second clock signal, and its output terminal connected to the output selection module. The asynchronous analog-to-digital converter module is configured to sample and convert the input signal once per pulse cycle of the corresponding second clock signal. The output selection module is configured to time-divisionally select and alternately output the conversion results of each asynchronous analog-to-digital converter module.

7. The SAR-ADC circuit according to claim 6, wherein, The output selection module is configured to output the conversion result obtained by the asynchronous analog-to-digital converter in the previous pulse period of the second clock signal during any pulse time of the second clock signal corresponding to the asynchronous analog-to-digital converter module.

8. The SAR-ADC circuit according to claim 6, wherein, The asynchronous analog-to-digital conversion module includes: a sampling switch unit, a serial comparison unit, and a digital-to-analog conversion unit; The sampling switch unit is connected to the input terminal and the clock terminal of the asynchronous analog-to-digital converter module, respectively. The sampling switch unit is configured to turn on when the asynchronous analog-to-digital converter module receives the pulse of the corresponding second clock signal, thereby starting the sampling of the input signal. The serial comparison unit is connected to the clock terminal and the output terminal of the sampling switch unit, the digital-to-analog converter unit, and the asynchronous analog-to-digital converter module, respectively. The serial comparison unit is configured to cooperate with the digital-to-analog converter unit to convert the sampling result output by the sampling switch unit between adjacent pulses of the second clock signal received by the asynchronous analog-to-digital converter module, so as to obtain the conversion result.

9. The SAR-ADC circuit according to claim 8, wherein, The digital-to-analog conversion unit includes a capacitive digital-to-analog converter.

10. The SAR-ADC circuit according to claim 8, wherein, The input terminals of the asynchronous analog-to-digital converter module include a first differential input terminal and a second differential input terminal; The first input terminal of the sampling switch unit is connected to the first differential input terminal, the second input terminal of the sampling switch unit is connected to the second differential input terminal, and the clock terminal of the sampling switch unit is connected to the clock terminal of the asynchronous analog-to-digital converter module. The first input terminal of the serial comparison unit is connected to the first output terminal of the sampling switch unit and the first output terminal of the digital-to-analog converter unit, respectively. The second input terminal of the serial comparison unit is connected to the second output terminal of the sampling switch unit and the second output terminal of the digital-to-analog converter unit, respectively. The clock terminal of the serial comparison unit is connected to the clock terminal of the asynchronous analog-to-digital converter module. The first output terminal of the serial comparison unit is connected to the first input terminal of the digital-to-analog converter unit. The second output terminal of the serial comparison unit is connected to the second input terminal of the digital-to-analog converter unit. The third output terminal of the serial comparison unit is connected to the output terminal of the asynchronous analog-to-digital converter module.

11. The SAR-ADC circuit according to claim 10, wherein, The serial comparison unit includes m comparison subunits, and the conversion result includes m-bit quantization code; m ≥ 2, and m is a positive integer; the first input terminal of the digital-to-analog conversion unit includes m-1 first sub-input terminals, and the second input terminal of the digital-to-analog conversion unit includes m-1 second sub-input terminals corresponding to the m-1 first sub-input terminals respectively; The first input terminal of each comparison subunit is connected to the first input terminal of the serial comparison unit, and the second input terminal of each comparison subunit is connected to the second input terminal of the serial comparison unit; the first output terminals of the first m-1 comparison subunits are respectively connected to the m-1 first sub-input terminals of the digital-to-analog converter, and the second output terminals of the first m-1 comparison subunits are respectively connected to the m-1 second sub-input terminals of the digital-to-analog converter; the third output terminal of each comparison subunit is connected to the output terminal of the asynchronous analog-to-digital converter module; wherein, the clock terminal of the first comparison subunit is connected to the clock terminal of the serial comparison unit; the clock terminals of subsequent comparison subunits are connected to the identification signal output terminal of the previous comparison subunit; The comparison subunit is configured to start comparing the signals input to the first and second input terminals of the comparison subunit after receiving a pulse at the clock terminal of the comparison subunit; after the comparison is completed, the pulse of the identification signal is output through the identification signal output terminal, the comparison result is fed back to the digital-to-analog converter through the first and second output terminals of the comparison subunit, and one bit of the quantization code in the conversion result is output through the third output terminal of the comparison subunit.

12. The SAR-ADC circuit according to claim 11, wherein, The comparison subunit includes: a dynamic comparator and a D flip-flop; The clock input of the dynamic comparator is connected to the clock input of the comparator subunit. The two inputs of the dynamic comparator are respectively connected to the first and second inputs of the comparator subunit. The two outputs of the dynamic comparator are respectively connected to the first and second outputs of the comparator subunit. The input of the D flip-flop is connected to one of the outputs of the dynamic comparator. The output of the D flip-flop is connected to the third output of the comparator subunit. The flag input of the dynamic comparator is respectively connected to the clock input of the D flip-flop and the flag signal output of the comparator subunit.

13. The SAR-ADC circuit according to claim 12, wherein, In the asynchronous analog-to-digital converter module, at the moment when the D flip-flop in the last comparison subunit is triggered, the m-bit quantization code output by the third output terminal of each comparison subunit in the asynchronous analog-to-digital converter module is used as the conversion result of the asynchronous analog-to-digital converter module.

14. The SAR-ADC circuit according to claim 12, wherein, The dynamic comparator includes: operational amplifier circuitry and logic circuitry; The two input terminals of the operational amplifier circuit are respectively connected to the two input terminals of the dynamic comparator, the clock terminal of the operational amplifier circuit is connected to the clock terminal of the dynamic comparator, and the two output terminals of the operational amplifier circuit are respectively connected to the two output terminals of the dynamic comparator; the operational amplifier circuit is configured to compare the signals respectively connected to the two input terminals of the operational amplifier circuit. The two output terminals of the operational amplifier circuit are also connected to the two input terminals of the logic circuit, and the output terminal of the logic circuit is connected to the identifier terminal of the dynamic comparator; the logic circuit is configured to generate a pulse of the identifier signal based on the comparison result of the operational amplifier circuit.

15. The SAR-ADC circuit according to claim 14, wherein, The dynamic comparator further includes a delay control circuit connected to the logic circuit; the delay control circuit is configured to control the delay duration between the moment when the operational amplifier circuit completes the comparison and the moment when the pulse of the identification signal is output from the identification signal output terminal.

16. The SAR-ADC circuit according to claim 15, wherein, The delay control circuit is connected between the operational amplifier circuit and the logic circuit. The delay control circuit is configured to control the delay duration for which the output signals of the two output terminals of the operational amplifier circuit are transmitted to the two input terminals of the logic circuit. Alternatively, the delay control circuit is connected between the output terminal of the logic circuit and the output terminal of the identification signal, and the delay control circuit is configured to control the delay duration for the signal output by the logic circuit to be transmitted to the output terminal of the identification signal.

17. The SAR-ADC circuit according to claim 12, further comprising: A reset module is connected to each of the dynamic comparators and each of the digital-to-analog converters, and is configured to reset each of the dynamic comparators and each of the digital-to-analog converters.

18. The SAR-ADC circuit according to claim 17, wherein, The reset module is configured to reset each dynamic comparator and the digital-to-analog conversion unit in the asynchronous analog-to-digital conversion module within any pulse period of the second clock signal accessed by the asynchronous analog-to-digital conversion module, after the D flip-flop in the last comparison subunit of the asynchronous analog-to-digital conversion module is triggered.

19. A control method for a SAR-ADC circuit, applied to the SAR-ADC circuit according to any one of claims 1-18; the method comprising: The timing control module outputs at least two second clock signals with the same frequency and sequentially delayed; The asynchronous analog-to-digital converter module samples and converts the input signal in each pulse period of each of the second clock signals; The output selection module selects the conversion result of the asynchronous analog-to-digital converter in each pulse period of the second clock signal.

20. A communication system, comprising: The SAR-ADC circuit according to any one of claims 1-18.

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