System for identifying a semiconductor assembly comprising a substrate

Abstract

The invention relates to a system (44) for identifying a semiconductor assembly (2) comprising a substrate (4), wherein the substrate (4) has a first substrate metallization (8). In order to simplify the system (44) and to achieve an improved cost position, it is proposed that at least one first partial code (28) is applied to the first substrate metallization (8) in a first partial field of view (30) and a second partial code (32) is applied to a second partial field of view (34), wherein an optical sensor (46) is configured to detect a surface (54) of the semiconductor assembly (2) having the first substrate metallization (8) of the substrate (4), and at least one processor (50) is configured to extract the partial codes (28, 32) from the surface (54) of the semiconductor assembly (2), to combine said partial codes to form a code word, to decode to form a data word, and to identify the semiconductor assembly (2) on the basis of the decoded data word.

Description

[0001] 202414584 Foreign version Fair copy

[0002] 1

[0003] Description

[0004] System for identifying a semiconductor arrangement with a substrate

[0005] The invention relates to a system for identifying a semiconductor arrangement with a substrate.

[0006] Furthermore, the invention relates to a method for identifying a semiconductor arrangement with a substrate.

[0007] Furthermore, the invention relates to a control unit with means for carrying out such a method.

[0008] Furthermore, the invention relates to a computer program product for carrying out such a method when executed in a control unit.

[0009] Such a system can be used, among other things, in the production of semiconductor assemblies. These semiconductor assemblies can include power semiconductor assemblies, which are typically used in a power converter. A power converter can be, for example, a rectifier, an inverter, a converter, or a DC-DC converter. Identifying a semiconductor assembly can be used, for example, to obtain information about the installed batch numbers, machines, and process parameters.

[0010] The patent application EP 3 185 655 A1 describes a method for the individual coding of metal-ceramic substrates. The coding is carried out in the form of a barcode or a data matrix.

[0011] Especially in power semiconductor assemblies for power converters, expensive substrates, such as ceramic DCB substrates, are used. To save space and costs, electronic components, such as power semiconductor elements, are arranged densely and compactly on the substrate. Furthermore, there is significant cost pressure in the manufacturing of such semiconductor assemblies. Data Matrix codes placed between the electronic components are compact and require high resolution, making the application of the code complex and expensive. Moreover, expensive and sophisticated sensors are required to read such codes correctly. 202414584 Foreign version Fair copy

[0012] 2

[0013] Against this background, the object of the present invention is to provide a system for identifying a semiconductor arrangement which is simple and cost-effective.

[0014] The object is achieved according to the invention by a system for identifying a semiconductor arrangement with a substrate, wherein the substrate has a first substrate metallization, wherein at least a first partial code is applied to the first substrate metallization on a first partial field of view and a second partial code is applied to a second partial field of view, wherein an optical sensor is configured to detect a surface of the semiconductor arrangement with the first substrate metallization of the substrate and at least one processor is configured to extract the partial codes from the surface of the semiconductor arrangement, to assemble them into a codeword, to decode them into a data word and to identify the semiconductor arrangement on the basis of the decoded data word, wherein the partial codes are composed of points which have a minimum size of 0.4 mm, in particular 0.8 mm, and furthermore in particular 1.0 mm.

[0015] Furthermore, the object of the invention is achieved by a method for identifying a semiconductor arrangement with a substrate, wherein the substrate has a first substrate metallization, wherein a first partial code is applied to the first substrate metallization on a first partial field of view and a second partial code is applied to a second partial field of view, wherein a surface of the semiconductor arrangement with the first substrate metallization of the substrate is detected by an optical sensor, and wherein the partial codes are extracted from the surface of the semiconductor arrangement by means of a processor, assembled into a codeword and decoded into a data word, and wherein the semiconductor arrangement is identified on the basis of the decoded data word, wherein the partial codes are composed of points which have a minimum size of 0.4 mm, in particular 0.8 mm, and furthermore in particular 1.0 mm.

[0016] Moreover, the problem is solved according to the invention by a control unit with means for carrying out such a method.

[0017] Furthermore, the problem is solved according to the invention by a computer program product for carrying out such a method when running in a control unit.

[0018] The advantages and preferred configurations listed below with regard to the system can be applied analogously to the method, the control unit and the computer program product.

[0019] The invention is based on the consideration of providing a system for identifying a semiconductor arrangement, which allows for cost-effective marking of the semiconductor arrangement. 202414584 Foreign version Fair copy

[0020] 3

[0021] Identification is enabled, and the marking is as easy to read and decode as possible. The semiconductor arrangement is, for example, designed as a power semiconductor arrangement for use in a power converter and comprises a substrate that has at least one initial substrate metallization. The substrate is, for example, a DCB substrate with a dielectric material layer made of a ceramic material, which may contain aluminum oxide or aluminum nitride, and the substrate metallization contains, for example, copper. At least two partial codes of a codeword are applied to the initial substrate metallization, distributed across different partial fields of view on the substrate. Therefore, the at least two partial codes are distributed and thus not physically connected on the substrate.The partial fields of view of the subcodes can be positioned between the electronic components, enabling high information content and easy readability despite dense component placement. Application can be achieved using a laser, among other methods. For example, at least the first subcode and / or the second subcode can be individually configured for a semiconductor array or multiple semiconductor arrays, so that the codeword extractable from the subcodes is unique to that array or multiple arrays. The multiple semiconductor arrays can, among other things, have a uniform configuration and / or arrangement of electronic components. In particular, groups of semiconductor arrays, each with, for example, a different component placement option, can have at least one unique subcode.

[0022] To identify the semiconductor array, an optical sensor, which can be implemented as a camera, for example, is used to capture the surface of the semiconductor array, including the initial substrate metallization. At least one processor extracts the partial codes from the surface of the semiconductor array, assembles them into a codeword, and decodes this into a data word, which is used to identify the semiconductor array. The data word can be, among other things, a batch, version, or type designation assigned to multiple semiconductor arrays, or a designation specific to each individual semiconductor array, such as a serial number. The data word can then be displayed and / or stored, for example, in a database for further processing.

[0023] The subcodes are composed of dots, which have a minimum size of 0.4 mm, in particular 0.8 mm, and furthermore in particular 1.0 mm. For example, a dot can correspond to a bit of a binary code. The dots can be, for example, circular, elliptical, square, rectangular, hexagonal, octagonal, or of another shape. In particular, such a dot corresponds to a "1" and the absence of such a dot to a "0" in the binary code. Alternatively, a "0" can be defined by an unfilled dot. 202414584 Foreign version Fair copy

[0024] A 4 is defined as a "1" in binary code, while a "1" is defined by a dot that is at least partially filled. Such a minimal dot size can be produced cost-effectively, for example using solder mask in a standard process, and the code pattern can be easily read, e.g., with a camera, if it contains sufficient information.

[0025] Another embodiment provides that the first substrate metallization of the substrate has electrically isolated conductor sections, with the first partial code being applied to a first conductor section and the second partial code to a second conductor section. In particular, the partial fields of view of at least two partial codes are arranged on different conductor sections of the first substrate metallization, thus enabling a space-saving distribution of the partial codes on the substrate. In this way, despite the dense placement of the semiconductor array, a high information content and, at the same time, easy readability of the partial codes can be achieved.

[0026] Another embodiment provides that the partial codes are disjoint and together form a unique codeword. A unique codeword is understood to be a codeword that is specific to a semiconductor array or a plurality of semiconductor arrays. Disjoint partial codes allow for optimal information content.

[0027] Another embodiment provides that the partial codes are each applied as a binary code to the first substrate metallization of the substrate. This means that the partial codes are applied as a pattern representing a binary code. Such a pattern allows for easy readability.

[0028] Another embodiment provides that the subcodes together comprise a maximum of 12, and in particular a maximum of 10, bits of the binary code. Such a number of bits is sufficient and allows for both dense configuration and easy readability.

[0029] Another embodiment provides that a position of the respective subcode in the data word is predetermined by its position on the first substrate metallization. In particular, the position of the subcode is determined by capturing the respective partial field of view. This allows for an optimized information content relative to the required area. For example, the arrangement of the partial fields of view relative to each other and / or to other markers, such as characteristic electronic components and / or conductor structures, is used to determine the positions. In this way, reading can be performed without additional aids. 202414584 Foreign version Fair copy

[0030] 5

[0031] Another embodiment provides that the data word is a serial number for identifying the semiconductor assembly. A serial number is a unique identifier for each semiconductor assembly.

[0032] Another embodiment provides that the partial fields of view each have a border, in particular a complete one. Such a border can be easily and cost-effectively detected by a camera, thus enabling simple readout.

[0033] Another embodiment involves applying the partial codes to the first substrate metallization using solder mask. For example, solder mask dots can be applied distributed across the semiconductor array, particularly the substrate, to create a dot matrix representing a binary code. Applying the partial codes using solder mask is cost-effective and can be integrated into existing manufacturing processes.

[0034] Another embodiment provides that at least one electronic component of the semiconductor arrangement, which is connected to the first substrate metallization, is arranged between the first partial viewing area containing the first partial code and the second partial viewing area containing the second partial code. Such an electronic component can be, among other things, a power semiconductor element, a bond wire, a passive component such as a shunt, and / or a pin. This distribution allows for a high information content and, at the same time, easy readability of the partial codes, despite the dense assembly of the semiconductor arrangement.

[0035] Another embodiment provides that the distance between the first partial viewing area with the first partial code and the second partial viewing area with the second partial code is at least 2 mm, and in particular at least 5 mm. Such a distribution allows for a high information content and, at the same time, easy readability of the partial codes, despite the dense population of the semiconductor arrangement.

[0036] Another embodiment provides that at least a fourth partial code is applied to an electronic component of the semiconductor arrangement, which is connected to the first substrate metallization. For example, the electronic component has a flat surface on which a fourth partial view field with the fourth partial code is arranged. Such an electronic component can be, among other things, a shunt resistor or an additional substrate that is smaller than the substrate and is glued or soldered onto it.

[0037] The invention will now be described and explained in more detail with reference to the exemplary embodiments shown in the figures. 202414584 Foreign version Fair copy

[0038] 6

[0039] They show:

[0040] FIG 1 shows a schematic representation of a first embodiment of a semiconductor arrangement with a substrate,

[0041] FIG 2 shows a schematic representation of a second embodiment of a semiconductor arrangement with a substrate,

[0042] FIG 3 shows a schematic representation of a third embodiment of a semiconductor arrangement with a substrate and

[0043] FIG 4 shows a schematic representation of a system for identifying a semiconductor arrangement.

[0044] The exemplary embodiments described below are preferred embodiments of the invention. In these exemplary embodiments, the described components each represent individual features of the invention that can be considered independently of one another. Each of these features further develops the invention independently and can therefore be considered part of the invention individually or in a combination other than that shown. Furthermore, the described embodiments can also be supplemented by other features of the invention already described.

[0045] The same reference symbols have the same meaning in the different figures.

[0046] FIG 1 shows a schematic top view of a first embodiment of a semiconductor arrangement 2 with a substrate 4. The semiconductor arrangement 2 is exemplified as a power semiconductor arrangement for a power converter. The substrate 4, which is exemplified as rectangular, has a dielectric material layer 6 with a first substrate metallization 8 and a second substrate metallization 10, the second substrate metallization 10 being located on the side of the dielectric material layer 6 facing away from the first substrate metallization 8. The substrate 4 is, for example, a DCB substrate with a dielectric material layer 6 made of a ceramic material, which may contain aluminum oxide or aluminum nitride. The first substrate metallization 8 of the substrate 4 has a plurality of electrically insulated conductor sections 8a, 8b, 8c, 8d, 8e.On a first line section 8a and on a second line section 8b 202414584 Foreign version Fair copy.

[0047] Semiconductor elements 12, in particular power semiconductor elements, are arranged in each of the 7 conductor sections. For example, a first transistor T1 and a first diode D1 are arranged on the first conductor section 8a, while a second transistor T2 and a second diode D2 are arranged on the second conductor section 8b. The transistors T1 and T2 are designed as vertical transistors, in particular as insulated-gate bipolar transistors (IGBTs). Alternatively, the vertical transistors can be designed, among other things, as wide-bandgap transistors, in particular as SiC MOSFETs. The transistors T1 and T2 have a control terminal 14 and load terminals 16 and 18, wherein the transistors T1 and T2 are each metallized to the first substrate metallization 8 via a second load terminal 18, in particular by a soldered or sintered connection.The first load terminal 16 of the first transistor T1 is connected via a plurality of bond wires 20 to a third conductor section 8c, wherein the first load terminal 16 of the second transistor T2 is connected via a plurality of bond wires 20 to the first conductor section 8a and a fourth conductor section 8d. A fifth conductor section 8e is connected to the fourth conductor section 8d via a shunt resistor 22. A plurality of free pins 24 are provided for contacting the semiconductor assembly 2. The semiconductor assembly is enclosed by a housing 26.

[0048] For example, on the first conductor section 8a of the first substrate metallization 8, a first partial code 28 is applied to a first partial field of view 30, while on the second conductor section 8b, a second partial code 32 is applied to a third partial field of view 38 and a third partial code 36 is applied to a third partial field of view 38. The partial codes 28, 32, 36, distributed across the substrate 4, are individually implemented for a semiconductor assembly 2 or a plurality of semiconductor assemblies 2, such that the codeword extractable from the partial codes 28, 32, 36 is individual or specific for a semiconductor assembly 2 or a plurality of semiconductor assemblies 2. The plurality of semiconductor assemblies 2 can, among other things, have a uniform assembly and / or arrangement of the electronic components.

[0049] The partial codes 28, 32, and 36 are each applied as a binary code to the first substrate metallization 8 of the substrate 4. The partial codes 28, 32, and 36 in FIG. 1 are composed of dots, where, for example, each dot can correspond to a bit of a binary code. The dots are, by way of example, circular and have a minimum diameter of 0.4 mm, in particular 0.8 mm, and furthermore, in particular 1.0 mm. For example, the first partial code 28 and the second partial code 32 have three bits, which are arranged in a 3x1 dot matrix.

[0050] Subcode 8, while the third subcode 36 has two bits arranged in a 2x1 dot matrix. Specifically, a filled dot corresponds to a "1" and the absence of such a dot to a "0" in the binary code. Alternatively, a "0" can be defined by an unfilled dot. Subcodes 28, 32, and 36 are disjoint and together form an individual codeword. In particular, the position of each subcode 28, 32, or 36 within the codeword is determined by its position on the first substrate metallization 8.

[0051] As an example, the partial codes 28, 32, and 36 are applied to the first substrate metallization 8 using solder mask. The partial viewing areas 30, 34, and 38 each have a complete or continuous border, which is also applied with, in particular, the same solder mask. Alternatively, the partial codes 28, 32, and 36 can be glued to the border of the partial viewing areas 30, 34, and 38 or laser-etched into the metallization. The bordered partial codes 28, 32, and 36 are applied to free areas of the first substrate metallization 8. These free areas do not contain, among other things, semiconductor elements 12, bond wires 20, or pins 24.A distance between the partial viewing fields 30, 34, 38 with partial codes 28, 32, 36 is at least 2 mm, in particular at least 5 mm, wherein, due to the dense assembly between the partial viewing fields 30, 34, 38, at least one semiconductor element 12 and / or bond wires 20 which are connected on the first substrate metallization 8 are arranged.

[0052] FIG. 2 shows a schematic representation of a second embodiment of a semiconductor arrangement 2 with a substrate 4 in a top view, wherein the partial codes 28, 32, 36 are formed from square dots having a minimum side length of 0.4 mm, in particular 0.8 mm, and furthermore in particular 1.0 mm. The partial viewing areas 30, 34, 38 each have a broken border. The further embodiment of the semiconductor arrangement 2 in FIG. 2 corresponds to the embodiment in FIG. 1.

[0053] FIG 3 shows a schematic representation of a third embodiment of a semiconductor arrangement 2 with a substrate 4 in a top view, wherein a fourth partial code 40 is applied to a fourth partial viewing area 42 on the shunt resistor 22. The fourth partial code 40 is implemented as an example as a 4-bit code and is applied to a component surface (58) of the shunt resistor 22 by means of a varnish, in particular solder mask, within the border of the fourth partial viewing area 42. The 4 bits are arranged in a 2x2 dot matrix. The partial codes 28, 32, 36, 40 are disjoint and together form an individual codeword. In particular, the position of the respective partial code 28, 32, 36, 40 in the codeword is indicated by its position.

[0054] 9 on the first substrate metallization 8. The further design of the semiconductor arrangement 2 in FIG. 3 corresponds to the embodiment in FIG. 1.

[0055] FIG 4 shows a schematic representation of a system 44 for identifying a semiconductor arrangement 2, wherein the semiconductor arrangement 2 is implemented as shown in FIG 1 by way of example. The system comprises an optical sensor 46, which can be implemented, for example, as a camera, as well as an evaluation unit 48, which includes a processor 50, and an output unit 52, which includes, for example, a display.

[0056] A surface 54 of the semiconductor assembly 2 with the first substrate metallization 8 of the substrate 4 is detected by the camera. Using the processor 50 of the evaluation unit 48, the partial codes 28, 32, 36, 40 are extracted from the surface 54 of the semiconductor assembly 2. The processor 50 can comprise multiple processors. A control unit can be part of the evaluation unit. In particular, the processor 50 can also function as a control unit. The extraction of the partial codes 28, 32, 36, 40 is performed by comparing the sensor data of the optical sensor 46 with at least one reference structure 56. The reference structure, for example, has a K-model that can take into account external influences, in particular lighting conditions, manufacturing and component tolerances, as well as placement options, especially of the semiconductor elements 12.In a further step, the extracted partial codes are assembled into a codeword using processor 50 and decoded into a data word. The semiconductor arrangement 2 is then identified using the data word.

[0057] For example, the data word used to identify semiconductor assembly 2 is a serial number. The serial number is displayed by output unit 52 and / or entered into a database for further processing.

[0058] The serial number, which is decoded from the partial codes 28, 32, 36, and 40 distributed across the substrate, can be used, among other things, for tracking during a manufacturing process. This can involve manufacturing with the following steps:

[0059] - Determining a batch lot, for example by scanning a package of substrate 4,

[0060] - Placing the substrates 4 onto at least one carrier,

[0061] - Assembling soldering aids, also called jigs or soldering jigs, whereby the assembly can be done manually, for example,

[0062] - Placing solder and components in a pick-and-place machine

[0063] - Exemptions from subcodes 28, 32, 36, 40, excluding jigs in these areas. 202414584 Foreign version Fair copy

[0064] 10

[0065] - Determining the serial number of semiconductor assembly 2 by scanning part codes 28, 32, 36, 40 using a camera according to the process described above.

[0066] - Further processing of semiconductor assembly 2, whereby the subcodes 28, 32, 36, 40 are scanned during further manufacturing steps to determine the serial number. - Storing information about the manufacturing process along with the serial number.

[0067] In summary, the invention relates to a system 44 for identifying a semiconductor arrangement 2 with a substrate 4, wherein the substrate 4 has a first substrate metallization 8. To simplify the system 44 and achieve an improved cost position, it is proposed that at least a first partial code 28 on a first partial field of view 30 and a second partial code 32 on a second partial field of view 34 are applied to the first substrate metallization 8, wherein an optical sensor 46 is configured to detect a surface 54 of the semiconductor arrangement 2 with the first substrate metallization 8 of the substrate 4, and at least one processor 50 is configured to extract the partial codes 28, 32 from the surface 54 of the semiconductor arrangement 2, assemble them into a codeword, decode them into a data word, and identify the semiconductor arrangement 2 based on the decoded data word.

Claims

202414584 Foreign version Fair copy 11 Patent claims 1. System (44) for identifying a semiconductor arrangement (2) with a substrate (4), wherein the substrate (4) has a first substrate metallization (8), wherein at least a first partial code (28) is applied to the first substrate metallization (8) on a first partial field of view (30) and a second partial code (32) is applied to a second partial field of view (34), wherein an optical sensor (46) is configured to detect a surface (54) of the semiconductor arrangement (2) with the first substrate metallization (8) of the substrate (4) and at least one processor (50) is configured to extract the partial codes (28, 32) from the surface (54) of the semiconductor arrangement (2), to assemble them into a codeword, to decode them into a data word and to identify the semiconductor arrangement (2) on the basis of the decoded data word, characterized in that the partial codes (28, 32) are composed of points which have a minimum size of 0.4 mm, in particular 0.8 mm, and furthermore in particular 1 ,exhibit 0 mm.

2. System (44) according to claim 1, comprising the first substrate metallization (8) of the substrate (4) having electrically insulated conductor sections (8a, 8b, 8c, 8d, 8e) arranged, wherein the first partial code (28) is applied to a first conductor section (8a) and the second partial code (32) is applied to a second conductor section (8b).

3. System (44) according to one of claims 1 or 2, wherein the partial codes (28, 32) are disjoint and together form an individual codeword.

4. System (44) according to claim 3, wherein the partial codes (28, 32) are each applied as a binary code on the first substrate metallization (8) of the substrate (4).

5. System (44) according to claim 4, wherein the partial codes (28, 32) together comprise a maximum of 12, in particular a maximum of 10, bits of the binary code.

6. System (44) according to any one of claims 3 to 5, 202414584 Foreign version Fair copy 12 where the position of the respective subcode (28, 32) in the codeword is determined by its position on the first substrate metallization (8).

7. System (44) according to any of the preceding claims, wherein the data word is a serial number for identifying the semiconductor arrangement (2).

8. System (44) according to one of the preceding claims, wherein the partial viewing fields (30, 34) each have a border, in particular a closed one.

9. System (44) according to one of the preceding claims, wherein the partial codes (28, 32) are applied by solder mask to the first substrate metallization (8).

10. System (44) according to one of the preceding claims, wherein at least one electronic component of the semiconductor arrangement (2), which is connected to the first substrate metallization (8), is arranged between the first partial viewing area (30) with the first partial code (28) and the second partial viewing area (34) with the second partial code (32).

11. System (44) according to one of the preceding claims, wherein the distance between the first partial field of view (30) with the first partial code (28) and the second partial field of view (34) with the second partial code (32) is at least 2 mm, in particular at least 5 mm.

12. System (44) according to one of the preceding claims, wherein at least a fourth partial code (40) is applied to a component surface (58) of a, in particular passive, electronic component of the semiconductor arrangement (2) which is connected to the first substrate metallization (8).

13. Method for identifying a semiconductor arrangement (2) with a substrate (4), wherein the substrate (4) has a first substrate metallization (8), wherein a first partial code (28) is applied to the first substrate metallization (8) on a first partial viewing area (30) and a second partial code (32) is applied to a second partial viewing area (34), 202414584 Foreign version Fair copy 13 wherein a surface (54) of the semiconductor arrangement (2) with the first substrate metallization (8) of the substrate (4) is detected by an optical sensor (46), and wherein the partial codes (28, 32) are extracted from the surface (54) of the semiconductor arrangement (2) by means of a processor (50), assembled into a codeword and decoded into a data word, and wherein the semiconductor arrangement (2) is identified on the basis of the decoded data word, characterized in that the partial codes (28, 32) are composed of points which have a minimum size of 0.4 mm, in particular 0.8 mm, and furthermore in particular 1.0 mm.

14. Method according to claim 13, wherein sensor data from the optical sensor (46) are compared with at least one reference structure (56) to extract the partial codes (28, 32).

15. Control unit with means for carrying out a method according to one of claims 13 or 14, wherein the means comprise a sensor, in particular a camera, and a processor.

16. Computer program product for carrying out a method according to one of claims 14 or 15 when executed in a control unit according to claim 15.

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