Integrated monolithic ASIC for controlling and driving non-isolated buck APFC circuit, motor controller and driver

Abstract

The present disclosure provides a non-isolated buck Active Power Factor Correction (APFC) circuit (100) including an integrated monolithic Application-Specific Integrated Circuit (ASIC) (110) for controlling and driving the non-isolated buck APFC circuit and a motor controller and driver circuit. The APFC circuit (100) includes a bridge rectifier (102), an Electromagnetic Interference (EMI) filter (104), and a non-isolated buck APFC power converter (106) configured to convert a high voltage DC to a low voltage DC, using one or more switching components, to achieve an active power factor correction. The APFC circuit (100) includes a motor controller and driver circuit (108) configured to generate Pulse Width Modulation (PWM) pulses to drive windings of a motor (M1) for controlling a speed of the motor (M1). The non-isolated buck APFC power converter (106) and the motor controller and driver circuit (108) are configured to share common ground.

Description

INTEGRATED MONOLITHIC ASIC FOR CONTROLLING AND DRIVING NON¬ISOLATED BUCK APFC CIRCUIT, MOTOR CONTROLLER AND DRIVERTECHNICAL FIELD

[0001] The embodiments of the present disclosure generally relate to a field of power electronics and integrated circuits. In particular, the present disclosure pertains to an integrated monolithic Application- Specific Integrated Circuits (ASICs) for controlling and driving a non-isolated buck Active Power Factor Correction (APFC) circuit and a motor controller and driver circuit.BACKGROUND

[0002] The following description of the related art is intended to provide background information pertaining to the field of the disclosure. This section may include certain aspects of the art that may be related to various features of the present disclosure. However, it should be appreciated that this section is used only to enhance the understanding of the reader with respect to the present disclosure, and not as admissions of the prior art.

[0003] Power conversion, especially transformation of Alternating Current (AC) voltage to Direct Current (DC) voltage, is a rapidly evolving and continually advancing technical field. In current technology, Brushless DC (BLDC) motors are typically controlled using two or more separate integrated circuits (for implementing AC to DC and BLDC control functionality) (Application-Specific Integrated Circuits (ASICs)). The use of two or more separate integrated circuits increases power consumption, cost, and physical size of the system. Therefore, there is a demand for higher-performance converter circuits that utilize an integrated monolithic solution for low voltage non-isolated buck Active Power Factor Correction (APFC) combined with a BLDC motor controller. This integrated approach may lead to more efficient, cost-effective, and compact systems. Additionally, there is a need for voltage converter circuits for the BLDC motors to be more compact in size, reducing an overall footprint of the motor controller.

[0004] In the current state of technology, BLDC motor drivers solutions deriving power from AC mains are typically controlled using multiple ASICs, which include both a AC-DC power converter with Power Factor Correction (PFC) and a BLDC motor controller and driver. One of the significant limitations of this existing technology is an inability to share a common ground between the power converter and the controller ASICs. This separation leads to increased complexity, higher costs, lower efficiency, and bulkier systems.The need for separate grounds increases design and manufacturing challenges, ultimately making the existing solutions less desirable in terms of performance and integration.

[0005] Therefore, there is, a need for an integrated monolithic ASICs for controlling and driving non-isolated buck APFC circuits, and motor controllers and drivers by overcoming the deficiencies in the prior art(s).OBJECTS OF THE PRESENT DISCLOSURE

[0006] Some of the objects of the present disclosure, which at least one embodiment herein satisfies are listed herein below.

[0007] It is an object of the present disclosure to provide an integrated monolithic Application- Specific Integrated Circuit (ASIC) for controlling and driving a non-isolated buck Active Power Factor Correction (APFC) circuit with a motor controller and driver.

[0008] It is an object of the present disclosure to provide a non-isolated buck APFC power converter to convert high voltage Direct Current (DC) to low voltage DC, using one or more switching components, to achieve an active power factor correction.

[0009] It is an object of the present disclosure to provide a motor controller and driver circuit configured to generate Pulse Width Modulation (PWM) pulses to drive windings of a motor for controlling a speed of the motor efficiently.

[0010] It is an object of the present disclosure to provide a current sensing resistor for precise buck inductor current sensing, thereby ensuring enhanced control and efficiency in power management and motor control applications.

[0011] It is an object of the present disclosure to provide an integrated monolithic ASIC that enables low cost, highly efficient, and compact solution with a low standby power.SUMMARY

[0012] This section is provided to introduce certain objects and aspects of the present disclosure in a simplified form that are further described below in the detailed description. This summary is not intended to identify the key features or the scope of the claimed subject matter.

[0013] In an aspect, the present disclosure relates to a non-isolated buck Active Power Factor Correction (APFC) circuit for a motor driver system, including an integrated monolithic Application- Specific Integrated Circuit (ASIC) for controlling and driving the non-isolated buck Active Power Factor Correction (APFC) circuit with a motor controller and driver. The APFC circuit includes a bridge rectifier configured to convert an AlternatingCurrent (AC) to a high voltage Direct Current (DC). The APFC circuit includes an Electromagnetic Interference (EMI) filter operatively connected to an output of the bridge rectifier and configured to minimize electromagnetic compatibility (EMC) noise in an AC main supply. Further, the APFC circuit includes a non-isolated buck APFC power converter electrically connected to the bridge rectifier and the EMI filter and configured to convert the high voltage DC to a low voltage DC, using one or more switching components, to achieve an active power factor correction.

[0014] An output of the EMI filter is connected to a drain of a high side N-channel Metal-Oxide-Semiconductor Field-Effect Transistor (N-MOSFET) (QEXT). A source of the high side N-MOSFET (QEXT) is connected to a first terminal of an output capacitor (Cout), a cathode of a low side buck diode (D5), and a Vout bus pin of the ASIC. A ground pin of the ASIC is connected to a second terminal of the output capacitor and a first terminal of a current sensing resistor (Rsns). A second terminal of the current sensing resistor (Rsns) is connected to a first terminal of a buck inductor (Lext) and a Visns pin of the ASIC. A second terminal of the buck inductor (Lext) is connected to an anode of the low side buck diode (D5), a return path of the EMI filter, and the bridge rectifier.

[0015] Furthermore, the APFC circuit includes a motor controller and driver circuit operatively connected to the non-isolated buck APFC power converter and configured to generate Pulse Width Modulation (PWM) pulses to drive windings of a motor for controlling a speed of the motor. The non-isolated buck APFC power converter and the motor controller and driver circuit are configured to share a common ground.

[0016] In an embodiment, the non-isolated buck APFC power converter may include at least one or a combination of the high side buck N-MOSFET (QEXT), the low side buck diode (D5), the buck inductor (Lext), the output capacitor (Cout), a start-up circuit resistor (Rst), and the current sensing resistor (Rsns).

[0017] In an embodiment, the high side buck N-MOSFET (QEXT) may be driven by PWM pulses (PWM-N), using an integrated charge pump as a supply to a PWM-N driver, where the ASIC may generate PWM pulses (PWM-N) for controlling the QEXT. The integrated charge pump may include an external capacitor for driving one or more higher capacitive loads.

[0018] In an embodiment, the non-isolated buck APFC power converter may include a P-channel Metal-Oxide-Semiconductor Field-Effect Transistor (P-MOSFET) (QPEXT) configured to increase an operating power range and reduce losses in the non-isolated buckAPFC power converter, where the ASIC may generate PWM pulses (PWM-P) for controlling the QPEXT.

[0019] In an embodiment, the non-isolated buck APFC power converter may be configured to perform the active power factor correction to achieve a close to unity power factor, by adjusting a duty cycle of the one or more switching components, by sensing current through the current sensing resistor (Rsns), to align an input current waveform with an input voltage waveform.

[0020] In an embodiment, the start-up circuit resistor (Rst) may be used during startup of the non-isolated buck APFC power converter.

[0021] In an embodiment, the motor controller and driver circuit may include a low voltage high side driver MOSFET. The low voltage high side driver MOSFET may be one of the N-MOSFET or the P-MOSFET.

[0022] In an embodiment, when the low voltage high side driver MOSFET is the N- MOSFET, the motor controller and driver circuit may include the integrated charge pump which may be reused from the QEXT driver and configured to drive a gate terminal of the N- MOSFET above a supply voltage. The integrated charge pump may include an external capacitor for charge pump operation.BRIEF DESCRIPTION OF DRAWINGS

[0023] The accompanying drawings, which are incorporated herein, and constitute a part of this disclosure, illustrate exemplary embodiments of the disclosed methods and systems which like reference numerals refer to the same parts throughout the different drawings. Components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Some drawings may indicate the components using block diagrams and may not represent the internal circuitry of each component. It will be appreciated by those skilled in the art that disclosure of such drawings includes the disclosure of electrical components, electronic components, or circuitry commonly used to implement such components.

[0024] FIG. 1 illustrates a circuit diagram of a non-isolated buck Active Power Factor Correction (APFC) circuit (100) incorporating an integrated monolithic Application-Specific Integrated Circuit (ASIC) (110) for a motor driver system, in accordance with embodiments of the present disclosure.

[0025] FIG. 2 illustrates a circuit diagram depicting different components of the nonisolated buck APFC circuit (100), in accordance with an embodiment of the present disclosure.

[0026] FIG. 3 illustrates an example circuit diagram (100) depicting a flow of current through a current sensing resistor and an inductor when a Buck FET (QEXT) is turned ON, in accordance with embodiments of the present disclosure.

[0027] FIG. 4 illustrates an example circuit diagram (100) depicting a flow of current when a Buck FET (QEXT) is turned OFF, in accordance with embodiments of the present disclosure.

[0028] FIG. 5 illustrates a circuit diagram incorporating the non-isolated buck APFC circuit (100) with a P-channel Metal-Oxide-Semiconductor Field-Effect Transistor (P- MOSFET), in accordance with embodiments of the present disclosure.

[0029] The foregoing shall be more apparent from the following more detailed description of the disclosure.DETAILED DESCRIPTION

[0030] In the following description, for the purposes of explanation, various specific details are set forth in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent, however, that embodiments of the present disclosure may be practiced without these specific details. Several features described hereafter can each be used independently of one another or with any combination of other features. An individual feature may not address all of the problems discussed above or might address only some of the problems discussed above. Some of the problems discussed above might not be fully addressed by any of the features described herein.

[0031] The ensuing description provides exemplary embodiments only and is not intended to limit the scope, applicability, or configuration of the disclosure. Rather, the ensuing description of the exemplary embodiments will provide those skilled in the art with an enabling description for implementing an exemplary embodiment. It should be understood that various changes may be made in the function and arrangement of elements without departing from the spirit and scope of the disclosure as set forth.

[0032] Specific details are given in the following description to provide a thorough understanding of the embodiments. However, it will be understood by one of ordinary skill in the art that the embodiments may be practiced without these specific details. For example, circuits, systems, networks, processes, and other components may be shown as componentsin block diagram form in order not to obscure the embodiments in unnecessary detail. In other instances, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary detail to avoid obscuring the embodiments.

[0033] The word “exemplary” and / or “demonstrative” is used herein to mean serving as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited by such examples. In addition, any aspect or design described herein as “exemplary” and / or “demonstrative” is not necessarily to be construed as preferred or advantageous over other aspects or designs, nor is it meant to preclude equivalent exemplary structures and techniques known to those of ordinary skill in the art. Furthermore, to the extent that the terms “includes,” “has,” “contains,” and other similar words are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term “comprising” as an open transition word without precluding any additional or other elements.

[0034] Reference throughout this specification to “one embodiment” or “an embodiment” or “an instance” or “one instance” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0035] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context indicates otherwise. It will be further understood that the terms “comprises” and / or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0036] The present disclosure discloses a non-isolated buck Active Power Factor Correction (APFC) circuit including an integrated monolithic Application-Specific Integrated Circuit (ASIC) for a motor driver system. The ASIC efficiently manages both the buck APFC circuit and a controller and driver circuit of a motor, for examples, but not limited to, aBrushless Direct Current (BLDC) motor, a Permanent Magnet Synchronous Motor (PMSM), and a Switched Reluctance Motor (SRM). The non-isolated buck APFC circuit of the motor driver system includes a bridge rectifier, an Electromagnetic Interference (EMI) filter, and a non-isolated buck APFC power converter. The bridge rectifier converts an Alternating Current (AC) to high-voltage DC, while the EMI filter minimizes electromagnetic compatibility (EMC) noise in an AC main supply. The buck APFC circuit functions as a buck converter, stepping down the high-voltage DC to a low-voltage DC, with a high side N- channel Metal-Oxide-Semiconductor Field-Effect Transistor (N-MOSFET) (QEXT) operating as a switching power FET. The motor controller and driver circuit are configured to generate Pulse Width Modulation (PWM) pulses to drive windings of a motor for controlling a speed of the motor. Thereby, enhancing control and efficiency in power management and motor control applications.

[0037] Various embodiments of the present disclosure will be explained in detail with reference to FIGs. 1-5.

[0038] FIGs. 1 and 2 illustrate a circuit diagram of a non-isolated buck Active Power Factor Correction (APFC) circuit (100) for a motor driver system, incorporating an integrated monolithic Application-Specific Integrated Circuit (ASIC) () for controlling and driving the non-isolated buck APFC convertor (106) and a motor controller and driver (108), and different components of the non-isolated buck APFC circuit (100), respectively, in accordance with embodiments of the present disclosure.

[0039] With reference to FIGs. 1 and 2, the non-isolated buck APFC circuit (100) of the motor driver system may include the integrated monolithic ASIC (110), a bridge rectifier (102), an Electromagnetic Interference (EMI) filter (104), a non-isolated buck APFC power converter (106), and a motor controller and driver circuit (108). The motor driver system may be for example, but not limited to, a H-Bridge motor driver, a stepper motor driver, a Brushless Direct Current (BLDC) motor driver, a servo motor driver, etc.

[0040] In an embodiment, the bridge rectifier (102) may be configured to convert an Alternating Current (AC) to a high voltage Direct Current (DC) by rectifying an input voltage. The bridge rectifier (102) may include four diodes arranged in a bridge configuration. The four diodes may effectively rectify both halves of an AC input waveform, ensuring a continuous flow of current in a single direction.

[0041] In an embodiment, the EMI filter (104) may be operatively connected to an output of the bridge rectifier (102). In an embodiment, EMI filter (104) may be configured to filter out ripple current from a load, preventing its entry into an AC Main supply. Therefore,the EMI filter (104) may be configured to minimize electromagnetic compatibility (EMC) noise in an AC main supply.

[0042] In an embodiment, the EMI filter (104) may include passive electronic components such as capacitors, inductors, and resistors, arranged in a configuration to attenuate unwanted electromagnetic noise generated by the switching of HV buck and motor controller or external sources. The EMI filter (104) may be operated by providing a bypass path for high-frequency noise so that the high-frequency noise may not reach the sensitive components, and the sensitive components may be protected, while allowing desired signals to pass through unaffected components. By suppressing the electromagnetic noise, the EMI filter (104) may maintain signal integrity, prevent malfunctions, and ensure proper operation of electronic devices in various applications which includes, but not limited to, telecommunications, power electronics, and consumer electronics. The EMI filter (104) may be configured to block high frequency noise on the AC main to reach high voltage / APFC buck and output of high voltage buck, thereby protecting sensitive circuitry like ASIC and other components.

[0043] In an embodiment, the non-isolated buck APFC power converter (106) may be electrically connected to the bridge rectifier (102) and the EMI filter (104). The non-isolated buck APFC power converter (106) may be configured to convert the high voltage DC to a low voltage DC, using one or more switching components, thereby achieving an active power factor correction. In an embodiment, the non-isolated buck APFC power converter (106) may include, but not limited to, a high side N-channel Metal-Oxide-Semiconductor Field-Effect Transistor (N-MOSFET) (QEXT), a low side buck diode (D5), a buck inductor (Lext), an output capacitor (Cout), a start-up circuit resistor (Rst), and a current sensing resistor (Rsns).

[0044] In an embodiment, the high side buck N-MOSFET (QEXT) may be driven by PWM pulses (PWM-N), using an integrated charge pump as a supply to a PWM-N driver. The integrated charge pump may include, but not limited to, an external capacitor for driving one or more higher capacitive loads. The higher capacitive loads may be, for example, but not limited to, N-MOSFET gate capacitor.

[0045] In an embodiment, an output of the EMI filter (104), i.e., a DC link voltage, may be connected to a drain of the high side N-MOSFET (QEXT). In an embodiment, a source of the high side N-MOSFET (QEXT) may be connected to a first terminal of the output capacitor (Cout), a cathode of the low side buck diode (D5), and a Vout bus pin of the ASIC (110). In an embodiment, a ground pin of the ASIC (110) may be connected to a second terminal of the output capacitor (Cout) and a first terminal of a current sensingresistor (Rsns). In an embodiment, a second terminal of the current sensing resistor (Rsns) may be connected to a first terminal of a buck inductor (Lext) and a Visns pin of the ASIC (110). In an embodiment, a second terminal of the buck inductor (Lext) may be connected to an anode of the low side buck diode (D5), and to a return path of the EMI filter (104), and the bridge rectifier (102).

[0046] In an embodiment, the non-isolated buck APFC power converter (106) may include a P-channel Metal-Oxide-Semiconductor Field-Effect Transistor (P-MOSFET) (QPEXT) configured to increase an operating power range and reduce losses in the nonisolated buck APFC power converter (106). In an embodiment, the ASIC (110) may generate PWM pulses (PWM-P) for controlling the P-MOSFET (QPEXT). In an embodiment, when the QPEXT is utilized, the usage of the low side buck diode (D5) may be optional.

[0047] In an embodiment, the non-isolated buck APFC power converter (106) may be configured to perform the active power factor correction to achieve a close to unity power factor, by adjusting a duty cycle of the one or more switching components. In an embodiment, the duty cycle of the one or more switching components may be adjusted by sensing current through the current sensing resistor (Rsns), to align an input current waveform with an input voltage waveform, thereby improving the power factor. This may minimize reactive power consumption and optimize the efficiency of an electrical system.

[0048] In an embodiment, the non-isolated buck APFC power converter (106) may be configured to convert AC rectified voltage to low voltage DC using a buck converter topology to achieve active power factor correction. The non-isolated buck APFC power converter (106) may reduce the input voltage to a lower level, thereby providing an efficient voltage regulation and reducing power losses.

[0049] In an embodiment, the motor controller and driver circuit (108) may be operatively connected to the non-isolated buck APFC power converter (106). The motor controller and driver circuit (108) may be configured to generate Pulse Width Modulation (PWM) pulses to drive windings of a motor (Ml). Examples of motor (Ml) may include, but not limited to, a Brushless Direct Current (BLDC) motor, a Permanent Magnet Synchronous Motor (PMSM), and a Switched Reluctance Motor (SRM). The motor controller and driver circuit (108) may drive the windings of the motor (Ml) for controlling the speed of the motor (Ml) efficiently.

[0050] In an embodiment, the motor controller and driver circuit (108) may include a low voltage high side driver MOSFET. The low voltage high side driver MOSFET may be one of the N-MOSFET or the P-MOSFET. In an embodiment, when the low voltage highside driver MOSFET is the N-MOSFET, the motor controller and driver circuit (108) may include the integrated charge pump. The integrated charge pump may be reused from a QEXT driver and configured to drive a gate terminal of the N-MOSFET above a supply voltage.

[0051] In an embodiment, the charge pump may be configured for generating elevated gate drive voltages needed to drive high-side NMOS switches in a motor's power stage. As the motors operate using electronic commutation, precise control of power transistors is essential for efficient performance. The charge pump may generate the elevated gate drive voltages by boosting the voltage from the DC power supply to levels required for proper gate drive, typically exceeding the supply voltage. This elevated gate drive voltages may ensure swift and reliable switching of the high-side NMOS switches, enabling smooth commutation and efficient motor operation. Furthermore, the charge pump may include protection mechanisms to safeguard against voltage spikes and fault conditions, enhancing a reliability and a durability of the motor. The integration of the charge pump within the motor controller and driver circuit (108) may improve an overall efficiency and effectiveness of the motor controller and driver circuit (108).

[0052] In an embodiment, the non-isolated buck APFC power converter (106) and the motor controller and driver circuit (108) may be configured to share a common ground. In an embodiment, the current sensing resistor (Rsns) may be configured to measure the load current, while the buck inductor (Lext) filters the switching voltage alongside the output capacitor (Cout), thereby maintaining a constant output voltage.

[0053] In an embodiment, the start-up circuit resistor (Rst) may be used during startup of the non-isolated buck APFC power converter (106). In an embodiment, the start-up circuit resistor (Rst) may be configured to power up one or more internal blocks of the ASIC (110). The one or more internal blocks of the ASIC (110) may include, but not limited to, a bandgap, a bias circuitry, critical protection circuits, Low Dropout Regulator (LDO), etc. In an embodiment, the start-up circuit resistor (Rst) may be used as a sensing circuit to monitor the input voltage to the buck converter to lower Total Harmonic Distortion (THD) and significantly enhance power factor of the motor driver system (100).

[0054] FIG. 3 illustrates an example circuit diagram (100) depicting a flow of current through the current sensing resistor (Rsns) and the buck inductor (Lext) when a buck FET (QEXT) is turned ON, in accordance with embodiments of the present disclosure.

[0055] With reference to FIG. 3, in an embodiment, the EMI filter (104) may include, but not limited to, a first capacitor Cl, a second capacitor C2, and a first inductor LI. Thesecond capacitor C2 may supply transient current while simultaneously filtering out noise originating from a primary AC side.

[0056] During a first phase, when the buck FET (QEXT) (also known as high side N- MOSFET) is turned ON, the current may be allowed to flow through the output capacitor (Cout) to charge the output capacitor (Cout). Further, the current may continue to flow from the output capacitor (Cout) through the current sensing resistor (Rsns) and the buck inductor (Lext). During the first phase, the voltage across the second capacitor C2 may be VC2. A voltage difference between the VC2 and Vout may be applied across the buck inductor (Lext), causing the current of the buck inductor (Lext) to ramp up. The current flowing in the buck inductor (Lext) may be a combination of the current coming from the AC main supply and an instantaneous current supplied by the capacitor C2. During the first phase, the low side buck diode (D5) may be in a reverse-biased condition.

[0057] FIG. 4 illustrates an example circuit diagram (100) depicting a flow of current when the buck FET (QEXT) is turned OFF, in accordance with embodiments of the present disclosure.

[0058] With reference to FIG. 4, during a second phase, when the buck FET (QEXT) is turned OFF, the current built up in the buck inductor (Lext) during phase 1 may not drop to zero instantaneously. As a result, the flow of current may be facilitated through the low side buck diode (D5), thereby flowing through the output capacitor (Cout) and the current sensing resistor (Rsns), and then back to the buck inductor (Lext). This may allow the energy stored in the buck inductor (Lext) to be transferred to the load when the buck FET (QEXT) is turned OFF. During the second phase, the low side buck diode (D5) may remain in a forward-biased condition until the current in the buck inductor (Lext) decreases to zero.

[0059] The turn-on and turn-off voltages of the buck FET (QEXT) may be controlled by the PWM signals generated by the integrated monolithic ASIC (110).

[0060] FIG. 5 illustrates a circuit diagram incorporating the integrated monolithic ASIC (110) with the P-MOSFET, in accordance with embodiments of the present disclosure.

[0061] With reference to FIG. 5, the integrated monolithic ASIC (110) may include the P-MOSFET (QPEXT). The P-MOSFET (QPEXT) may be configured to increase the operating power range and reduce losses in the non-isolated buck APFC power converter (106). In an embodiment, the ASIC (110) may generate PWM pulses (PWM-P) for controlling the P-MOSFET (QPEXT). In an embodiment, when the QPEXT is utilized, the usage of the low side buck diode (D5) may be optional. When the QEXT is turned OFF, the QPEXT may provide a current return path when the current in the buck inductor (Lext) isgreater than zero. And when the current in the buck inductor (Lext) becomes less than zero, the QPEXT may be turned OFF.

[0062] Therefore, the integrated monolithic ASIC (110) controlling the buck operation and the load control or motor controller may benefit from a common ground. This approach may optimize the usage of the ASIC (110), reduce the overall die cost, and minimize standby power consumption.

[0063] While considerable emphasis has been placed herein on the preferred embodiments, it will be appreciated that many embodiments can be made and that many changes can be made in the preferred embodiments without departing from the principles of the disclosure. These and other changes in the preferred embodiments of the disclosure will be apparent to those skilled in the art from the disclosure herein, whereby it is to be distinctly understood that the foregoing descriptive matter is to be implemented merely as illustrative of the disclosure and not as a limitation.ADVANTAGES OF THE PRESENT DISCLOSURE

[0064] The present disclosure provides an integrated monolithic Application-Specific Integrated Circuit (ASIC) for controlling and driving a non-isolated buck with an Active Power Factor Correction (APFC) circuit and a motor controller and driver circuit efficiently.

[0065] The present disclosure provides an integrated monolithic ASIC that controls a non-isolated buck APFC power converter to convert high voltage Direct Current (DC) to low voltage DC, using one or more switching components, to achieve an active power factor correction.

[0066] The present disclosure provides an integrated monolithic ASIC that includes a motor controller and driver circuit configured to generate Pulse Width Modulation (PWM) pulses to drive windings of a motor for controlling a speed of the motor efficiently.

[0067] The present disclosure provides an integrated monolithic ASIC that includes voltage sense across a current sensing resistor for precise buck inductor current control, to achieve better Active power factor correction (APFC) and lower THD, thereby ensuring enhanced control and efficiency in power management and motor control applications.

[0068] The present disclosure provides a start-up circuit resistor (Rst) to perform a start-up operation and used as a sensing circuit to monitor the input voltage to the buck converter buck converter to lower Total Harmonic Distortion (THD) and significantly enhance power factor of the motor driver system (100).

[0069] The present disclosure provides an integrated monolithic ASIC that enables low cost, highly efficient, and compact solution with a low standby power.

Claims

We Claim:

1. A non-isolated buck Active Power Factor Correction (APFC) circuit (100) for a motor driver system, comprising: an integrated monolithic Application-Specific Integrated Circuit (ASIC) (110) for controlling and driving the non-isolated buck APFC circuit and controlling and driving a motor; a bridge rectifier (102) configured to convert an Alternating Current (AC) to a high voltage Direct Current (DC); an Electromagnetic Interference (EMI) filter (104) operatively connected to an output of the bridge rectifier (102), and configured to minimize electromagnetic compatibility (EMC) noise in an AC main supply; a non-isolated buck APFC power converter (106) electrically connected to the bridge rectifier (102) and the EMI filter (104), and configured to convert the high voltage DC to a low voltage DC, using one or more switching components, to achieve an active power factor correction, wherein an output of the EMI filter (104) is connected to a drain of a high side N- channel Metal-Oxide-Semiconductor Field-Effect Transistor (N-MOSFET) (QEXT), wherein a source of the high side N-MOSFET (QEXT) is connected to a first terminal of an output capacitor (Cout), a cathode of a low side buck diode (D5), and a Vout bus pin of the ASIC (HO), wherein a ground pin of the ASIC (110) is connected to a second terminal of the output capacitor (Cout) and a first terminal of a current sensing resistor (Rsns), wherein a second terminal of the current sensing resistor (Rsns) is connected to a first terminal of a buck inductor (Lext) and a Visns pin of the ASIC (110), wherein a second terminal of the buck inductor (Lext) is connected to an anode of the low side buck diode (D5), a return path of the EMI filter (104), and the bridge rectifier (102); and a motor controller and driver circuit (108) operatively connected to the non-isolated buck APFC power converter (106), and configured to generate Pulse Width Modulation (PWM) pulses to drive windings of a motor (Ml) for controlling a speed of the motor (Ml), wherein the non-isolated buck APFC power converter (106) and the motor controller and driver circuit (108) are configured to share a common ground.

2. The non-isolated buck APFC circuit (100) as claimed in claim 1, wherein the nonisolated buck APFC power converter (106) comprises at least one or a combination of: thehigh side buck N-MOSFET (QEXT), the low side buck diode (D5), the buck inductor (Lext), the output capacitor (Cout), a start-up circuit resistor (Rst), and the current sensing resistor (Rsns).

3. The non-isolated buck APFC circuit (100) as claimed in claim 2, wherein the high side buck N-MOSFET (QEXT) is driven by PWM pulses (PWM-N), using an integrated charge pump as a supply to a PWM-N driver, wherein the integrated charge pump comprises an external capacitor for driving one or more higher capacitive loads.

4. The non-isolated buck APFC circuit (100) as claimed in claim 2, wherein the nonisolated buck APFC power converter (106) further comprises a P-channel Metal-Oxide- Semiconductor Field-Effect Transistor (P-MOSFET) (QPEXT) configured to increase an operating power range and reduce losses in the non-isolated buck APFC power converter (106), wherein the ASIC (110) generates PWM pulses (PWM-P) for controlling the QPEXT.

5. The non-isolated buck APFC circuit (100) as claimed in claim 1, wherein the nonisolated buck APFC power converter (106) is configured to perform the active power factor correction to achieve a close to unity power factor, by adjusting a duty cycle of the one or more switching components, by sensing current through the current sensing resistor (Rsns), to align an input current waveform with an input voltage waveform.

6. The non-isolated buck APFC circuit (100) as claimed in claim 2, wherein the start-up circuit resistor (Rst) is used during start-up of the non-isolated buck APFC power converter (106).

7. The non-isolated buck APFC circuit (100) as claimed in claim 1, wherein the motor controller and driver circuit (108) comprises a low voltage high side driver MOSFET, wherein the low voltage high side driver MOSFET is one of: a N-channel Metal-Oxide- Semiconductor Field-Effect Transistor (N-MOSFET) or a P-channel Metal-Oxide- Semiconductor Field-Effect Transistor (P-MOSFET).

8. The non-isolated buck APFC circuit (100) as claimed in claim 7, wherein when the low voltage high side driver MOSFET is the N-MOSFET, the motor controller and driver circuit (108) comprises an integrated charge pump which is reused from a QEXT driver and configured to drive a gate terminal of the N-MOSFET above a supply voltage.

Images