Semiconductor device

Abstract

Provided is a highly reliable semiconductor device capable of multiplication. This semiconductor device comprises first and second cells and a drive circuit. Each of the first cell and the second cell includes first to third transistors and a resistance change element. The drive circuit includes a first input terminal, a second input terminal, and an output terminal. The resistance change element includes a conductive layer and an MTJ element. The conductive layer includes a first region connected to one of the source and the drain of the first transistor, a second region connected to one of the source and the drain of the second transistor, and a region in contact with a free layer of the MTJ element located between the first region and the second region. A fixed layer of the MTJ element includes a third region connected to one of the source and the drain of the third transistor. The drive circuit has a function of outputting to the output terminal, as a signal, information corresponding to a difference between a current flowing between the first cell and the first input terminal and a current flowing between the second cell and the second input terminal.

Description

Semiconductor equipment

[0001] One aspect of the present invention relates to a semiconductor device.

[0002] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. The technical field of the invention disclosed herein relates to objects, methods of operation, or methods of manufacturing. Alternatively, one aspect of the present invention relates to processes, machines, manufactures, or compositions of matter. More specifically, examples of the technical field of one aspect of the present invention disclosed herein include semiconductor devices, display devices (including liquid crystal display devices), light-emitting devices, energy storage devices, imaging devices, memory devices, processing devices, signal processing devices, sensors, computing devices (including processors), electronic devices, systems, methods for driving them, methods for manufacturing them, or methods for testing them.

[0003] Currently, there is a lot of activity in developing integrated circuits that mimic the structure of the human brain. These integrated circuits incorporate the brain's structure as electronic circuits, and have circuits that mimic the "neurons" and "synapses" of the human brain. For this reason, such integrated circuits are sometimes called, for example, "neuromorphic," "brainmorphic," or "brain-inspired." These integrated circuits have a non-von Neumann architecture and are expected to be able to perform parallel processing with extremely low power consumption compared to the von Neumann architecture, where power consumption increases with increasing processing speed.

[0004] A model of information processing that mimics a neural network having "neurons" and "synapses" is called an artificial neural network (ANN). For example, Patent Document 1 discloses a computing device that constructs an ANN using magnetoresistive elements.

[0005] International Publication No. 2021 / 176656

[0006] When a resistive switching element is used as a multiplier, by setting either the multiplier or the multiplicand as the conductance of the resistive switching element and the other multiplier or multiplicand as the voltage applied to the resistive switching element, the multiplication result can be expressed as a current which is the product of the conductance and the voltage.

[0007] Incidentally, when performing pruning in artificial neural networks, the weight coefficient of the corresponding neuron is sometimes set to 0. In the resistive switching element described above, if the weight coefficient corresponds to conductance, theoretically, the resistance value would need to be infinite to make the conductance 0. In particular, when using a magnetoresistive element as the resistive switching element, there is a limit to the range of variable resistance values, making it difficult to set 0 as the multiplier or multiplicand in a multiplier element using a magnetoresistive element.

[0008] Furthermore, when constructing a multiply-accumulate circuit by arranging resistive switching elements in an array, the operation of writing weight coefficients to the resistive switching elements requires sequential selection of the resistive switching elements, and the operation of multiply-accumulate requires selection of all resistive switching elements. Since the access transistors for the resistive switching elements may be common to both operations, the multiply-accumulate circuit requires both a drive circuit that transmits sequential selection signals and a drive circuit that transmits a selection signal all at once.

[0009] One aspect of the present invention aims to provide a highly reliable semiconductor device. Alternatively, one aspect of the present invention aims to provide a semiconductor device capable of multiplication including zero. Alternatively, one aspect of the present invention aims to provide a semiconductor device with a reduced number of drive circuits. Alternatively, one aspect of the present invention aims to provide a semiconductor device with reduced power consumption. Alternatively, one aspect of the present invention aims to provide a novel semiconductor device.

[0010] It should be noted that the problems addressed by one aspect of the present invention are not limited to the above-mentioned problems. The above-mentioned problems do not preclude the existence of other problems. These other problems are those not mentioned in this section, which are described below. Those skilled in the art can deduce these other problems from the description in the specification or drawings, and can be appropriately extracted from these descriptions. It should be noted that one aspect of the present invention solves at least one of the above-mentioned problems and other problems, but it is not necessary to solve all of them.

[0011] The present invention has been made in view of the above problems, and is an arithmetic circuit having two arithmetic cells each equipped with a resistive switching element to be used as a multiplication element. A resistance value corresponding to the sum of a weight coefficient w and a reference value b is set for the resistive switching element of one arithmetic cell, and a resistance value corresponding to the reference value b is set for the resistive switching element of the other arithmetic cell. Next, by applying a voltage corresponding to the input value x to each resistive switching element, a current proportional to (w + b) × x flows through the resistive switching element of one arithmetic cell, and a current proportional to bx flows through the resistive switching element of the other arithmetic cell. By taking the difference in the amounts of current from both, the multiplication result w × x with the reference value canceled out can be output. A specific configuration example of an arithmetic circuit, which is a semiconductor device according to one aspect of the present invention, will be described below.

[0012] (1) One aspect of the present invention is a semiconductor device having a first cell, a second cell, and a first drive circuit. The first cell and the second cell each have a first to third transistor and a resistive switching element. The first drive circuit has a first input terminal, a second input terminal, and a first output terminal. The resistive switching element has a conductive layer and a magnetic tunnel junction element (also called an MTJ element). The conductive layer has a first region that functions as a first terminal, a second region that functions as a second terminal, and a region that is in contact with the free layer of the MTJ element on the path of the current flowing between the first and second regions. The fixed layer of the MTJ element has a region that functions as a third terminal.

[0013] One of the sources or drains of the first transistor is electrically connected to the first terminal, one of the sources or drains of the second transistor is electrically connected to the second terminal, and one of the sources or drains of the third transistor is electrically connected to the third terminal. In addition, the other of the sources or drains of the first transistor in the first cell is electrically connected to the first input terminal, and the other of the sources or drains of the first transistor in the second cell is electrically connected to the second input terminal.

[0014] The first drive circuit has the function of outputting a signal to the first output terminal that corresponds to the difference between the first current flowing through the first input terminal and the second current flowing through the second input terminal.

[0015] (2) Alternatively, in one aspect of the present invention, in (1) above, the gates of the first transistors of the first cell and the second cell are electrically connected to the first wiring, the gates of the second transistors of the first cell and the second cell are electrically connected to the second wiring, and the gates of the third transistors of the first cell and the second cell are electrically connected to the third wiring.

[0016] (3) Alternatively, in one aspect of the present invention, in (2) above, each of the first to third transistors may have an oxide containing indium in the channel forming region.

[0017] (4) Alternatively, in one aspect of the present invention, the configuration in (3) above may include a second drive circuit. In particular, it is preferable that the second drive circuit includes a shift register, a selector, a first sequence circuit, and a second sequence circuit. Furthermore, it is preferable that the shift register has a second output terminal, the selector has a third input terminal, a third output terminal, and a fourth output terminal, the first sequence circuit has a fourth input terminal, a fifth output terminal, and a first control terminal, and the second sequence circuit has a fifth input terminal, a sixth output terminal, and a second control terminal.

[0018] Furthermore, it is preferable that the second output terminal is electrically connected to the third input terminal, the third output terminal is electrically connected to the first control terminal, the fifth output terminal is electrically connected to the fifth input terminal, and the sixth output terminal and the fourth output terminal are electrically connected to the first wiring. Furthermore, it is preferable that the selector has the function of making the third input terminal conductive between the third output terminal and one of the third and fourth output terminals, and non-conductive between the third input terminal and the other of the third and fourth output terminals. Furthermore, it is preferable that the first sequential circuit has the function of holding first information input to the fourth input terminal and the function of outputting the first information as a signal to the fifth output terminal in response to a control signal input to the first control terminal. Furthermore, it is preferable that the second sequential circuit has the function of holding second information input to the fifth input terminal and the function of outputting the second information as a signal to the sixth output terminal in response to a control signal input to the second control terminal.

[0019] (5) Alternatively, in one aspect of the present invention, in (4) above, the transistor included in the second drive circuit may have an oxide containing indium in the channel formation region.

[0020] Furthermore, by using two arithmetic cells equipped with MTJ elements, for example, it is possible to multiply a weight coefficient of three values ​​("-1", "0", or "1") by an input value of three values ​​("-1", "0", or "1"). Below, a specific example of the configuration of an arithmetic circuit, which is a semiconductor device according to one aspect of the present invention, will be described. An example of the configuration of a drive circuit that drives the arithmetic circuit will also be described.

[0021] (6) One aspect of the present invention is a semiconductor device having a first cell, a second cell, and a first drive circuit. Each of the first and second cells has a first to fourth transistor and a resistive switching element including a magnetic tunnel junction element. The resistive switching element has a first terminal through which read current and write current flow, a second terminal through which write current flows, and a third terminal through which read current flows. The first drive circuit has a first input terminal, a second input terminal, and a first output terminal.

[0022] Furthermore, one source or drain of the first transistor and one source or drain of the fourth transistor are electrically connected to the first terminal, one source or drain of the second transistor is electrically connected to the second terminal, and one source or drain of the third transistor is electrically connected to the third terminal. Also, the other source or drain of the first transistor in the first cell and the other source or drain of the fourth transistor in the second cell are electrically connected to the first input terminal, and the other source or drain of the first transistor in the second cell and the other source or drain of the fourth transistor in the first cell are electrically connected to the second input terminal.

[0023] The first drive circuit has the function of outputting a signal to the first output terminal corresponding to the difference between the first current flowing through the first input terminal and the second current flowing through the second input terminal.

[0024] (7) Alternatively, in one aspect of the present invention, in (6) above, the gates of the first transistors of the first cell and the second cell are electrically connected to the first wiring, the gates of the second transistors of the first cell and the second cell are electrically connected to the second wiring, the gates of the third transistors of the first cell and the second cell are electrically connected to the third wiring, and the gates of the fourth transistors of the first cell and the second cell are electrically connected to the fourth wiring.

[0025] (8) Alternatively, in one aspect of the present invention, the configuration in (7) above may include a second drive circuit. In particular, it is preferable that the second drive circuit includes a shift register, a selector, a first sequence circuit, a second sequence circuit, a first switch circuit, a second switch circuit, and a switch. It is also preferable that the shift register has a second output terminal, the selector has a third input terminal, a third output terminal, and a fourth output terminal, the first sequence circuit has a fourth input terminal, a fifth output terminal, and a first control terminal, the second sequence circuit has a fifth input terminal, a sixth output terminal, and a second control terminal, the first switch circuit has a fourth terminal, a fifth terminal, and a third control terminal, and the second switch circuit has a sixth terminal, a seventh terminal, and a fourth control terminal. It is also preferable that the switch has an eighth terminal.

[0026] Furthermore, it is preferable that the second output terminal is electrically connected to the third input terminal, the third output terminal is electrically connected to the first control terminal and the second control terminal, the fifth output terminal is electrically connected to the fourth terminal, the sixth output terminal is electrically connected to the sixth terminal, the fourth output terminal and the fifth terminal are electrically connected to the first wiring, and the eighth terminal and the seventh terminal are electrically connected to the fourth wiring. It is also preferable that the third control terminal and the fourth control terminal are electrically connected to the fifth wiring.

[0027] Furthermore, it is preferable that the shift register has the function of outputting a first control signal from the second output terminal. The selector preferably has the function of making the third input terminal conductive between the third output terminal and one of the fourth output terminals, and non-conducting between the third input terminal and the other of the third output terminal and the fourth output terminal. Furthermore, it is preferable that the first sequential circuit has the function of holding first information input to the fourth input terminal and the function of outputting the first information as a first signal to the fifth output terminal in response to the first control signal input to the first control terminal. Furthermore, it is preferable that the second sequential circuit has the function of holding second information input to the fifth input terminal and the function of outputting the second information as a second signal to the sixth output terminal in response to the control signal input to the second control terminal. Preferably, the first switch circuit has the function of making the connection between the fourth terminal and the fifth terminal conductive or non-conductive in response to the second control signal input to the third control terminal, and preferably the second switch circuit has the function of making the connection between the sixth terminal and the seventh terminal conductive or non-conductive in response to the second control signal input to the fourth control terminal.

[0028] (9) Alternatively, in one aspect of the present invention, in (8) above, the first switch circuit and the second switch circuit may each be configured to have a three-state buffer circuit. In particular, in the first switch circuit, it is preferable that the input terminal of the three-state buffer circuit is electrically connected to the fourth terminal, the output terminal of the three-state buffer circuit is electrically connected to the fifth terminal, and the enable terminal of the three-state buffer circuit is electrically connected to the third control terminal. Furthermore, in the second switch circuit, it is preferable that the input terminal of the three-state buffer circuit is electrically connected to the sixth terminal, the output terminal of the three-state buffer circuit is electrically connected to the seventh terminal, and the enable terminal of the three-state buffer circuit is electrically connected to the fourth control terminal.

[0029] (10) Alternatively, in any one of (6) to (9) above, the first transistor, the second transistor, the third transistor, and the fourth transistor may each have an oxide containing indium in the channel forming region.

[0030] In the configuration described in (1) above, for example, by setting a resistance value corresponding to the sum of the weight coefficient w and the reference value b for the resistive element of the first cell, and setting a resistance value corresponding to the reference value b for the resistive element of the second cell, and applying a voltage corresponding to the input value x to each resistive element, a current proportional to (w + b) × x can be made to flow through the resistive element of one calculation cell, and a current proportional to bx can be made to flow through the resistive element of the other calculation cell. Furthermore, by taking the difference between the two currents using a drive circuit, a signal corresponding to the multiplication result w × x can be output. Also, by setting w = 0, the difference between the two currents becomes 0, so the drive circuit outputs a signal corresponding to 0 as the multiplication result. In this way, by configuring the semiconductor device described in (1) above, multiplication including 0 can be performed.

[0031] Furthermore, by using the configuration described in (6) above, it is possible to multiply a weight coefficient w of three values, "-1", "0", or "1", by an input value x of three values, "-1", "0", or "1". Specifically, the result of the operation w × x performed by the configuration described in (6) above is determined by the difference in current between the current corresponding to the multiplication result in the first cell and the current corresponding to the multiplication result in the second cell, similar to the configuration described in (1) above. Also, by setting w = 0 or x = 0, the difference between the two currents becomes 0, so the drive circuit outputs a signal corresponding to 0 as the multiplication result. In this way, multiplication including 0 can also be performed by configuring the semiconductor device described in (6) above.

[0032] According to one aspect of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device capable of multiplication including zero can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with a reduced number of drive circuits can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one aspect of the present invention, a novel semiconductor device can be provided.

[0033] Furthermore, the effects of one aspect of the present invention are not limited to the effects described above. The effects described above do not preclude the existence of other effects. Other effects are those described below that are not mentioned in this section. Effects not mentioned in this section can be derived by those skilled in the art from the description in the specification or drawings, etc., and can be appropriately extracted from these descriptions. Furthermore, one aspect of the present invention has at least one of the effects described above and other effects. Accordingly, one aspect of the present invention may, in some cases, not have the effects listed above.

[0034] Figure 1 is a circuit diagram showing an example configuration of the arithmetic unit. Figure 2 is a block diagram showing an example configuration of the resistive switching element. Figures 3A and 3B are timing charts showing an example operation of the arithmetic unit. Figure 4 is a circuit diagram showing an example configuration of the arithmetic unit. Figures 5A, 5B, and 5C are circuit diagrams showing an example configuration of the drive circuit included in the arithmetic unit. Figures 6A and 6B are circuit diagrams showing an example configuration of the drive circuit included in the arithmetic unit. Figures 7A and 7B are timing charts showing an example operation of the drive circuit included in the arithmetic unit. Figures 8A and 8B are circuit diagrams showing an example configuration of the drive circuit included in the arithmetic unit. Figures 9A and 9B are circuit diagrams showing an example configuration of the drive circuit included in the arithmetic unit. Figure 10A is a circuit diagram showing an example configuration of the drive circuit included in the arithmetic unit, and Figure 10B is a circuit diagram showing an example configuration of the circuit included in the drive circuit. Figure 11 is a circuit diagram showing an example configuration of the drive circuit included in the arithmetic unit. Figures 12A and 12B are circuit diagrams showing an example configuration of the drive circuit included in the arithmetic unit. Figures 13A and 13B are circuit diagrams showing example configurations of the drive circuits included in the arithmetic unit. Figure 14 is a timing chart showing an example of the operation of the arithmetic unit. Figure 15 is a circuit diagram showing example configurations of the arithmetic unit. Figure 16 is a circuit diagram showing example configurations of the drive circuits included in the arithmetic unit. Figure 17 is a circuit diagram showing example configurations of the arithmetic unit. Figure 18 is a circuit diagram showing example configurations of the drive circuits included in the arithmetic unit. Figure 19 is a circuit diagram showing example configurations of the arithmetic unit. Figures 20A and 20B are timing charts showing example operation of the arithmetic unit. Figure 21 is a circuit diagram showing example configurations of the arithmetic unit. Figure 22 is a circuit diagram showing example configurations of the drive circuits included in the arithmetic unit. Figure 23 is a circuit diagram showing example configurations of the drive circuits included in the arithmetic unit. Figure 24 is a circuit diagram showing example configurations of the drive circuits included in the arithmetic unit. Figure 25 is a timing chart showing an example of the operation of the arithmetic unit. Figure 26 is a timing chart showing an example of the operation of the arithmetic unit. Figure 27 is a circuit diagram showing example configurations of the drive circuits included in the arithmetic unit. Figure 28 is a timing chart showing an example of the operation of the arithmetic unit. Figure 29 is a circuit diagram showing an example of the configuration of the arithmetic unit.Figure 30 is a circuit diagram showing an example of the configuration of a drive circuit included in the arithmetic unit. Figure 31 is a circuit diagram showing an example of the configuration of the arithmetic unit. Figure 32 is a circuit diagram showing an example of the configuration of a drive circuit included in the arithmetic unit. Figure 33 is a schematic plan view showing an example of the arithmetic circuit included in the arithmetic unit. Figure 34 is a schematic cross-sectional view showing an example of the configuration of the arithmetic unit. Figure 35 is a schematic cross-sectional view showing an example of the configuration of a transistor. Figures 36A and 36B are schematic cross-sectional views showing an example of the configuration of a transistor. Figure 37A is a schematic plan view showing an example of the configuration of a transistor, and Figures 37B and 37C are schematic cross-sectional views showing an example of the configuration of a transistor. Figure 38 is a schematic perspective view showing an example of the configuration of a transistor. Figures 39A, 39B, 39C, and 39D show examples of electronic components. Figure 40 shows an example of an information processing system. Figure 41 shows an example of space equipment. Figure 42 shows an example of a storage system applicable to a data center. Figures 43A1, 43A2, 43A3, 43A4, 43A5, 43A6, 43A7 and 43B1, 43B2, 43B3, 43B4, 43B5, and 43B6 are circuit diagrams illustrating electrical connections.

[0035] (Notes relating to this specification) In this specification, a semiconductor device is a device that utilizes semiconductor properties, and refers to a circuit containing semiconductor elements (e.g., transistors, diodes, and photodiodes), or a device having such a circuit. Furthermore, a semiconductor device refers to any device that can function by utilizing semiconductor properties. An example of a semiconductor device is an integrated circuit. Another example of a semiconductor device is a chip equipped with an integrated circuit. Another example of a semiconductor device is an electronic component in which a chip is housed in a package. Furthermore, for example, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices may be semiconductor devices themselves or may have semiconductor devices.

[0036] In this specification, "connection" includes, for example, "electrical connection." When "electrical connection" is used to define the connection relationship of circuit elements as a physical object, "electrical connection" includes, for example, "direct connection" and "indirect connection." "A and B are directly connected" means, for example, that A and B are connected without the use of a circuit element (e.g., a transistor or a switch; however, wiring is not a circuit element). On the other hand, "A and B are indirectly connected" means, for example, that A and B are connected via one or more circuit elements. A, B, and C (described later) refer to objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0037] Here, when we define "A and B are indirectly connected," it refers to the following type of connection, as an example: That is, assuming the circuit is operating, if there are times during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then such a circuit can be defined as having "A and B indirectly connected" as a physical object. Even if there are times when no electrical signals are exchanged or potential interactions occur between A and B, if there are times during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined as having "A and B indirectly connected." Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as a physical object. Therefore, for example, even if no power supply voltage is supplied to the circuit and the circuit is not operating, the circuit can still be defined as having "A and B indirectly connected" as a physical object (however, as an example, this is limited to cases where, when power supply voltage is supplied to the circuit and the circuit is operating, electrical signals are exchanged or potential interactions occur between A and B during the circuit's operation).

[0038] The following are specific examples of "indirect connections". First, an example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors, as shown in Figures 43A1 and 43A2. Another example of a case where "A and B are indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected", assuming the circuit is operating, one transistor between A and B will be in an ON state, conducting state, or a state in which current can flow at least once. Note that when "A and B are indirectly connected", this includes a time when one transistor between A and B is in an OFF state or non-conducting state. When "A and B are indirectly connected" and multiple transistors are connected between A and B, assuming the circuit is operating, each of the multiple transistors between A and B will be in an ON state, conducting state, or a state in which current can flow at least once. In other words, when "A and B are indirectly connected," it is not necessary for all of the transistors to be in an ON state, a conducting state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it includes cases where the transistors between A and B are in an OFF state or a non-conducting state, either simultaneously or at different times. As another example, as shown in Figure 43A3, when A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be discussed later, if a constant potential V is supplied to C from a power supply or GND, it can be said that "A and C are indirectly connected," or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0039] Having shown examples of cases where a connection can be considered "indirect" and cases where it cannot, let's look at another example of a case where a connection cannot be considered "indirect." Even if electrical signals are exchanged or potential interactions occur between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of when A and B are connected via an insulator is when a capacitive element is connected between A and B, as shown in Figure 43A4. Another example of when A and B are connected via an insulator is when a transistor gate insulating film is interposed between A and B, as shown in Figure 43A5. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0040] Another example of a situation where it cannot be said that "A and B are indirectly connected" is when there is no timing for the exchange of electrical signals or potential interaction between A and B. For example, as shown in Figures 43A6 and 43A7, multiple transistors are connected via sources and drains in the path from A to B, and a constant potential V is supplied to the nodes between the transistors from a power source or GND. In this case, it cannot be said that "A and B are indirectly connected," but it can be said that "A and V are indirectly connected," or "B and V are indirectly connected." In Figure 43A3, if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power supply or GND, then the connection relationship is the same as in Figures 43A6 and 43A7, so it cannot be said that "A and B are indirectly connected," but it can be said that "A and C are indirectly connected" or "B and C are indirectly connected."

[0041] As shown above, we have provided an example of "indirect connection." As an example, the provisions for "indirect connection" are included in the provisions for "electrical connection," so if "A and B are indirectly connected," then "A and B are electrically connected."

[0042] Next, we will show specific examples of "direct connection." An example of "A and B being directly connected" is when A and B are connected without any circuit elements in between, as shown in Figures 43B1, 43B2, and 43B3. Furthermore, as shown in Figures 43B4 and 43B5, when A and B are connected to a power source that supplies a constant potential V, or to GND, without any circuit elements in between, we can say that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." Furthermore, as shown in Figure 43B6, even when A (or B) is connected to a constant potential V via the source and drain of a transistor, we can say that "A and B are directly connected." Furthermore, since A and V, or B and V, are connected via the source and drain of a transistor, they cannot be said to be directly connected, and we can say that "A and V are indirectly connected," or "B and V are indirectly connected."

[0043] As shown above, an example of "direct connection" has been given, but as an example, since the provisions for "direct connection" are included in the provisions for "electrical connection," if "A and B are directly connected," then "A and B are electrically connected."

[0044] Even if independent components are shown connected in a circuit diagram, one component may possess the functions of multiple components. For example, if part of a "wire" also functions as an "electrode," then one conductive film possesses the functions of both a "wire" and an "electrode." Similarly, if part of a "wire" also functions as a "terminal," then one conductive film possesses the functions of both a "wire" and a "terminal." Therefore, it can be said that two or more components selected from "electrodes," "wires," and "terminals" are formed as a single unit. Furthermore, the terms "electrode," "wire," or "terminal" may be replaced with the term "region" depending on the context. Accordingly, in this specification, connection includes cases where a single conductive film possesses the functions of multiple components.

[0045] The switches described herein are described as having the function of being in an ON or OFF state and controlling whether or not to allow current to flow, or having the function of selecting and switching the path through which current flows.

[0046] Furthermore, in this specification, "conductive state" means a state in which current can flow between two input / output terminals, and "non-conductive state" means a state in which the two input / output terminals can be considered electrically disconnected. Also, in this specification, the ON state of a switch falls under the category of "conductive state," and the OFF state of a switch falls under the category of "non-conductive state." For this reason, in this specification, "conductive state" and "ON state" are interchangeable with each other, and "non-conductive state" and "OFF state" are interchangeable with each other.

[0047] Furthermore, in this specification, the terms "conductive" or "conductive state" used when conductive layers are in direct contact with each other refer, for example, to a state in which an electric current can flow between the conductive layers.

[0048] Furthermore, a switch may have two or more terminals for conducting current, in addition to its control terminals. Examples include electrical switches and mechanical switches. In other words, a switch is not limited to a specific type, as long as it has the function of controlling current.

[0049] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, and diode-connected transistors), or logic circuits combining these. An example of a mechanical switch is a switch using MEMS (Micro-Electro-Mechanical Systems) technology. This switch has mechanically movable electrodes, and the movement of these electrodes controls the on and off states.

[0050] In this specification, a transistor has three terminals called the gate, source, and drain. The gate is a control terminal that controls the switching between the conductive and non-conductive states of the transistor. The two terminals that function as either the source or the drain are the input and output terminals of the transistor. Depending on the conductivity type of the transistor (n-channel or p-channel) and the potential applied to the three terminals of the transistor, one of the two input and output terminals becomes the source and the other becomes the drain. For this reason, in this specification, the terms source and drain may be interchangeable. In this specification, when describing the connection relationships of a transistor, the notations "one of the source and drain" and "the other of the source and drain" are used. In this specification, one of the source and drain may be referred to as the "first electrode of the transistor" or "first terminal of the transistor," and the other of the source and drain may be referred to as the "second electrode of the transistor" or "second terminal of the transistor." Depending on the structure of the transistor, in addition to the three terminals described above, there may be a back gate. In this specification, one of the gate or back gate of a transistor may be referred to as the first gate, and the other of the gate or back gate of a transistor may be referred to as the second gate. Furthermore, in the same transistor, the terms "gate" and "back gate" may be interchangeable. Also, if a transistor has three or more gates, each gate may be referred to as the first gate, second gate, third gate, and so on.

[0051] For example, one example of a transistor described herein may include a multi-gate transistor with two or more gate electrodes. In a multi-gate structure, the channel formation regions are connected in series, resulting in a structure where multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-current and improve the transistor's breakdown voltage (improve reliability). Alternatively, the multi-gate structure allows for the acquisition of an Id-Vds characteristic where, when operating in the saturation region of the Id (source-drain current)-Vds (drain-source voltage) characteristic, the current between the drain and source does not change much even when the voltage between the drain and source changes, resulting in a flat slope. By utilizing the Id-Vds characteristic in this region, an ideal current source circuit or an active load with a very high resistance can be realized. As a result, a differential circuit or current mirror circuit with good characteristics can be realized.

[0052] Furthermore, in this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of components. Therefore, they do not limit the number of components. Nor do they limit the order of components, such as process order or layering order. In addition, even if a term in this specification does not have an ordinal number, an ordinal number may be added in the claims to avoid confusion of components. Also, even if a term in this specification has an ordinal number, a different ordinal number may be added in the claims. Furthermore, even if a term in this specification has an ordinal number, the ordinal number may be omitted in the claims. For example, a component that is designated with the ordinal number "first" in one embodiment of this specification may be designated with a different ordinal number such as "second," "third," etc., in other embodiments or claims. Also, for example, a component that is designated with the ordinal number "first" in one embodiment of this specification may be omitted in other embodiments or claims.

[0053] Furthermore, this specification may use timing charts to explain the operation of semiconductor devices. The timing charts used in this specification represent ideal operating examples, and the periods, magnitudes of signals (e.g., potential or current) and timings shown in the timing charts are not limited unless otherwise specified. Depending on the situation, the magnitudes and timings of the signals (e.g., potential or current) input to each wiring (including nodes) in the timing charts described herein may be modified. For example, even if two periods are shown at equal intervals in a timing chart, the lengths of the two periods may differ. Also, for example, even if one period is shown as longer and the other as shorter, the lengths of the two periods may be equal, or one period may be shorter and the other longer. Furthermore, in order to clearly illustrate the timing chart, for example, two or more overlapping signals may be intentionally offset in the illustration.

[0054] The embodiments described herein are explained with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope thereof. Therefore, the present invention is not to be interpreted as being limited to the contents described in the embodiments. In the configuration of the invention in the embodiments, the same reference numerals are used in common across different drawings for the same parts or parts having similar functions, and repeated explanations may be omitted. Also, in perspective views and the like, some components may be omitted in order to ensure clarity of the drawings.

[0055] In this specification, when the same reference numeral is used for multiple elements, and especially when it is necessary to distinguish them, the reference numeral may be accompanied by an identifying numeral such as "_1", "[n]", or "[m,n]". In addition, in drawings, etc., when an identifying numeral such as "_1", "[n]", or "[m,n]" is accompanied by a reference numeral, the identifying numeral may be omitted in this specification if it is not necessary to distinguish them.

[0056] Furthermore, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, they may include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences.

[0057] (Embodiment 1) This embodiment describes a semiconductor device according to one aspect of the present invention.

[0058] <Example of arithmetic unit configuration 1> Figure 1 is a circuit diagram showing an example of the configuration of an arithmetic unit, which is a semiconductor device according to one aspect of the present invention. The arithmetic unit CDV shown in Figure 1 has the function of multiplying a binary first data w, which is "0" or "1", and a binary second data x, which is "0" or "1". In the case of calculations for an artificial neural network, the first data w can be treated as a weight coefficient and the second data x can be treated as an input value.

[0059] Furthermore, the first data point w will be represented using two variables, wp and wn. For example, when w = 0, we define wp = 0 and wn = 0, and when w = 1, we define wp = 1 and wn = 0. In this case, wn is sometimes called the reference value.

[0060] The arithmetic unit CDV includes, for example, an arithmetic circuit CC, a drive circuit WCD, a drive circuit WXCD, a drive circuit WSD, a drive circuit XSD, and a drive circuit ITS. The arithmetic circuit CC also includes, for example, an arithmetic cell IMp and an arithmetic cell IMn.

[0061] For example, the calculation cell IMp has the function of holding wp. Also, for example, the calculation cell IMp has the function of obtaining x and outputting the result of multiplying wp and x. Similarly, for example, the calculation cell IMn has the function of holding wn. Also, for example, the calculation cell IMn has the function of obtaining x and outputting the result of multiplying wn and x.

[0062] An example of a calculation cell IMp includes transistors M1p, M2p, M3p, and a resistive switching element MRp. Similarly, an example of a calculation cell IMn includes transistors M1n, M2n, M3n, and a resistive switching element MRn.

[0063] Each of the transistors M1p through M3p and M1n through M3n functions as a switching transistor. Therefore, these transistors are described as operating in the linear region when they are ON. Furthermore, the operation of these transistors when they are ON includes cases where the gate, source, and drain of each transistor are appropriately biased to a potential that allows them to operate in the linear region. These transistors may also operate in the saturation region when they are ON.

[0064] Furthermore, in Figure 1, transistors M1p to M3p and transistors M1n to M3n are each n-channel type transistors. It is also preferable that these transistors include an oxide semiconductor in the channel formation region (also called an OS transistor). OS transistors have the characteristic of having an extremely low off-current. In particular, it is even more preferable that the OS transistors include indium oxide in the channel formation region (also called an IO transistor). IO transistors have a large on-current among OS transistors. Therefore, the ratio of the on-current to the off-current of an IO transistor is 1.0 × 10⁻⁶. １７ The above characteristics are highly desirable. By applying an I / O transistor to this transistor, malfunctions due to current leakage can be prevented, and the drive speed can be improved by increasing the on-current. Indium oxide will be described in detail in Embodiment 4.

[0065] Furthermore, for each of the transistors M1p to M3p and M1n to 3n, in addition to OS transistors, transistors containing silicon in the channel formation region (also called Si transistors) can be used. Also, the drive circuits WCD, WXCD, WSD, XSD, and ITS can be configured as CMOS circuits using Si transistors to reduce the circuit area and increase the drive speed. In this case, these drive circuits are formed on a semiconductor substrate made of silicon. By using Si transistors for transistors M1p to M3p and M1n to 3n, they can be manufactured simultaneously with the drive circuits, thus shortening the manufacturing time for the semiconductor device.

[0066] Each of the resistive switching elements MRp and MRn may, for example, have an MTJ (magnetic tunnel junction) element. Therefore, the resistance values ​​of each of the resistive switching elements MRp and MRn can be changed by the TMR (tunnel magnetoresistance) effect of the MTJ element.

[0067] Examples of the configurations of resistive switching elements MRp and MRn (which may be collectively referred to as resistive switching element MR in this specification) will be described. Figure 2 is a block diagram showing an example of the configuration of resistive switching element MR, which has layers RL, TIS, FL, and CR. Here, layers RL, TIS, and FL are assumed to be included in the MTJ element ME. Also, for convenience, terminals IT1, IT2, and OT are shown in Figure 2. For this reason, the above resistive switching element may be called a three-terminal resistive switching element or a three-terminal magnetic tunnel junction element.

[0068] Layer CR, for example, has a conductive layer. This conductive layer has a first region that functions as terminal IT1, a second region that functions as terminal IT2, and a third region that is in contact with layer FL and lies on the current path between the first and second regions. Therefore, terminals IT1 and IT2 are connected to each other via the third region of the conductive layer. Furthermore, by applying a voltage between terminals IT1 and IT2, a current flows between terminals IT1 and IT2. Layer CR is sometimes referred to as a channel layer.

[0069] Furthermore, the film in question is a film containing a material that exhibits the spin Hall effect when an electric current is passed between terminals IT1 and IT2. The spin Hall effect is a phenomenon in which a spin current is generated in a direction approximately perpendicular to the direction of the electric current. Specifically, for example, when an electric current flows in a two-dimensional plane such as a thin film, electrons with different spin directions are polarized on the upper and lower surfaces of the thin film, respectively, and this generates a spin current approximately perpendicular to the thin film. Therefore, layer CR can generate a spin current approximately perpendicular to layer CR when an electric current flows between terminals IT1 and IT2. In other words, it can also be said that a spin current approximately perpendicular to layer CR can be generated by passing an electric current between the first region and the second region.

[0070] In this specification, "approximately perpendicular" refers to a state in which two straight lines are positioned at an angle of 60° to 120°. Therefore, "approximately perpendicular" also includes cases where the angle is 80° to 100°, and 85° to 95°.

[0071] As described above, it is preferable that the layer CR contains a metallic material in which the spin Hall effect occurs. Specifically, it is preferable to use a transition metal with strong spin-orbit interaction as the metallic material. Examples of such transition metals include tungsten, platinum, and tantalum. Alternatively, the layer CR may contain a topological insulator that causes the spin Hall effect, in which case, for example, an alloy of bismuth and antimony, or an alloy of bismuth and selenium may be used.

[0072] Layer FL functions as a free layer in the MTJ element ME. Layer FL has a ferromagnetic material, and this ferromagnetic material allows it to have a magnetic moment state that is parallel or antiparallel to the magnetization direction of layer RL, which will be described later. Layer FL is sometimes also called a magnetic layer.

[0073] The ferromagnetic material included in layer FL is preferably a material whose magnetization reverses with a small spin current. Furthermore, the ferromagnetic material included in layer FL is preferably a material that is not easily affected by thermal energy. As the ferromagnetic material, for example, one or more alloys selected from iron, cobalt, and nickel can be used. For example, an alloy of cobalt, iron, and boron can be used. Other examples include an alloy of manganese and gallium, or an alloy of manganese and germanium.

[0074] Furthermore, as described later, layer FL is positioned in contact with the third region of the conductive layer contained in layer CR. The magnetic moment of layer FL is subjected to a spin torque by the spin current generated in layer CR. The magnetic moment of layer FL reverses direction, for example, when the spin torque exceeds a threshold. In other words, the magnetization direction of layer FL can be changed by passing a current through the third region between terminals IT1 and IT2 of layer CR. This operation allows information to be recorded in the MTJ element ME. Also, since the direction of the spin current generated by the spin Hall effect is determined by the direction of the current flowing between terminals IT1 and IT2 of layer CR, it can be said that the direction of the magnetic moment of layer FL is determined by the direction of the current.

[0075] The TIS layer functions as a tunnel insulator layer in the MTJ element ME. Therefore, by applying a voltage between layer FL and layer RL (terminal OT), a tunnel current can be passed through layer TIS due to the TMR effect. At this time, the resistance value of layer TIS (also called tunnel resistance) changes depending on the direction of the magnetic moment of layer FL. Specifically, the resistance value of layer TIS changes depending on whether the magnetization directions of layer FL and layer RL are parallel or antiparallel. For example, when the magnetization directions of layer FL and layer RL are parallel, the resistance value of layer TIS becomes small, and when the magnetization directions of layer FL and layer RL are antiparallel, the resistance value of layer TIS may become large. In other words, when the magnetization directions of layer FL and layer RL are parallel, the tunnel current flowing through layer TIS becomes large, and when the magnetization directions of layer FL and layer RL are antiparallel, the tunnel current flowing through layer TIS may become small.

[0076] For example, magnesium oxide, aluminum oxide, etc., can be used as the tunnel insulator. In particular, it is preferable to use crystalline magnesium oxide as the tunnel insulator.

[0077] Layer RL functions as a fixed layer in the MTJ element ME. Layer RL contains a ferromagnetic material. Unlike the ferromagnetic material in layer FL, the magnetization direction of the ferromagnetic material in layer RL is fixed. Layer RL, like layer FL, is sometimes referred to as a magnetic layer. As the ferromagnetic material contained in layer RL, for example, a material applicable to the ferromagnetic material contained in layer FL can be used.

[0078] Furthermore, it is preferable to combine the ferromagnetic material and tunnel insulator included in the MTJ element ME in such a way that the magnetoresistance ratio (MR ratio) of the MTJ element ME is increased.

[0079] Here, we will explain examples of methods for writing and reading information in the resistive switching element MR shown in Figure 2.

[0080] When writing information to the resistive switching element MR, an intermediate potential is applied to terminal IT2, a high-level potential higher than the intermediate potential is applied to terminal IT1, and terminal OT is set to high impedance. As a result, a writing current flows between terminals IT1 and IT2 in the resistive switching element MR, corresponding to the difference between the intermediate potential and the high-level potential. Therefore, the writing current flows through layer CR of the MTJ element ME, generating a spin current in layer CR, and this spin current determines the magnetization direction of the ferromagnetic material in layer FL. Furthermore, by applying a potential lower than the intermediate potential to terminal IT1, the spin current generated in layer CR can be reversed, and the magnetization direction of the ferromagnetic material in layer FL is also reversed. By treating the information to be written as binary data and corresponding it to the magnetization direction of the ferromagnetic material in layer FL, the information can be written to the resistive switching element MR.

[0081] When reading information from the resistive switching element MR, a low-level potential is applied to terminal IT1, a high-level potential to terminal OT, and terminal IT2 is set to high impedance. This causes a tunnel current (readout current) to flow between terminal IT1 and terminal OT. At this time, the resistance value of the MTJ element ME changes depending on whether the magnetization directions of layers RL and FL are parallel or antiparallel, and therefore the amount of tunnel current flowing through layer TIS of the MTJ element ME also changes. In other words, the information recorded in the MTJ element ME can be read from the amount of tunnel current flowing between terminal IT1 and terminal OT of the resistive switching element MR.

[0082] Furthermore, as described above, terminal IT1 functions as a terminal through which both read current and write current flow. Terminal IT2 functions as a terminal through which write current flows. Terminal OT functions as a terminal through which read current flows.

[0083] In this embodiment, an example configuration in which an MTJ element ME is provided with a resistive switching element MR has been described, but the semiconductor device according to one aspect of the present invention is not limited to this. For example, a magnetic domain wall-moving type magnetoresistive effect element can be used, which can change the resistance value continuously rather than binary by moving the magnetic domain wall. By using a magnetic domain wall-moving type magnetoresistive effect element, multiplication can be performed with wp and wn as analog values.

[0084] Furthermore, for example, the resistive switching element MR may have circuit elements other than the MTJ element ME whose resistance value changes. For example, the resistive switching element MR may have one of the following: a resistive switching element utilizing the CER (electric field-induced giant resistance change) effect, an FTJ (Ferroelectric Tunnel Junction) element, or a phase-change memory (also known as PCM or PRAM). In addition, the resistive switching element MR may have a ferroelectric capacitor that induces current when a pulse voltage is applied.

[0085] Next, the connection configuration of calculation cells IMp and IMn will be described. For convenience, the terminals IT1, IT2, and OT on the resistive switching element MR used in the explanation of Figure 2 will here be referred to as the first terminal, second terminal, and third terminal of the resistive switching element MR, respectively.

[0086] In the calculation cell IMp, the first terminal of the resistive switching element MRp is connected to the first terminal of transistor M1p, the second terminal of the resistive switching element MRp is connected to the first terminal of transistor M2p, and the third terminal of the resistive switching element MRp is connected to the first terminal of transistor M3p. Furthermore, the second terminal of transistor M1p is connected to wiring WCLp, and the gate of transistor M1p is connected to wiring WXL. Also, the second terminal of transistor M2p is connected to wiring VWE, and the gate of transistor M2p is connected to wiring WSL. Furthermore, the second terminal of transistor M3p is connected to wiring VRE, and the gate of transistor M3p is connected to wiring XSL.

[0087] In the calculation cell IMn, the first terminal of the resistive switching element MRn is connected to the first terminal of transistor M1n, the second terminal of the resistive switching element MRn is connected to the first terminal of transistor M2n, and the third terminal of the resistive switching element MRn is connected to the first terminal of transistor M3n. Furthermore, the second terminal of transistor M1n is connected to wiring WCLn, and the gate of transistor M1n is connected to wiring WXL. Also, the second terminal of transistor M2n is connected to wiring VWE, and the gate of transistor M2n is connected to wiring WSL. Furthermore, the second terminal of transistor M3n is connected to wiring VRE, and the gate of transistor M3n is connected to wiring XSL.

[0088] With the above connection configuration, each of the arithmetic cell IMp and arithmetic cell IMn can be, for example, a three-terminal memory element using an MTJ element, called SOT-MRAM (Spin Orbit Torque-Magnetoresisticive Random Access Memory).

[0089] Wiring WXL functions, for example, as a wire (also called a selection signal line) for sending selection signals to the calculation cells IMp and IMn, respectively, when writing the multipliers wp and wn to those calculation cells. Wiring WXL also functions as a wire for sending non-selection signals to calculation cells IMp and IMn that are not destinations for writing. Furthermore, wiring WXL functions, for example, as a wire for sending the multiplicand, the second data x, when performing multiplication in calculation cells IMp and IMn.

[0090] Wired WSL functions, for example, as wiring to send selection signals to calculation cells IMp and IMn, which are the destinations for writing multipliers wp and wn, respectively, when writing to calculation cells IMp and IMn. Wired WSL also functions as wiring to send non-selection signals to calculation cells IMp and IMn that are not destinations for writing.

[0091] For example, the wiring XSL functions as a wire for transmitting selection signals to the calculation cells IMp and IMn when multiplication is performed in the calculation circuit CC.

[0092] The wiring VWE functions, for example, as wiring for providing a fixed potential. Preferably, this fixed potential is, for example, a reference potential for writing information to the resistive switching element MR. In this specification, the fixed potential is set to the intermediate potential V. Ｍ This will be explained as follows.

[0093] Wiring VRE functions, for example, as wiring for providing a fixed potential. Preferably, this fixed potential is, for example, the potential used to read information from the resistive element MR. In this specification, this fixed potential is defined as potential V. Ｒ This will be explained as follows.

[0094] Next, we will describe the various drive circuits that are provided as peripheral circuits to the arithmetic circuit CC.

[0095] The drive circuit WCD includes switches SAp and SAN, and circuit WCDa. The input terminal of circuit WCDa is connected to wiring IWL, the first output terminal of circuit WCDa is connected to the first terminal of switch SAp, and the second output terminal of circuit WCDa is connected to the first terminal of switch SAN. The second terminal of switch SAp is connected to wiring WCLp, and the second terminal of switch SAN is connected to wiring WCLn. The control terminals of switch SAN and switch SAp are connected to wiring SWLA.

[0096] Circuit WCDa has the function of generating two variables wp and wn that represent the first data w by acquiring w from the input terminal, outputting wp to the first output terminal of circuit WCDa, and outputting wn to the second output terminal of circuit WCDa. Specifically, for example, when w = 1, circuit WCDa outputs a potential corresponding to wp = 1 from the first output terminal, and also outputs a potential corresponding to wn = 0 from the second output terminal. Also, for example, when w = 0, circuit WCDa outputs a potential corresponding to wp = 0 from the first output terminal, and also outputs a potential corresponding to wn = 0 from the second output terminal.

[0097] The wiring IWL, for example, functions as a wire for supplying the first data w to the input terminal of circuit WCDa from outside the computing unit CDV.

[0098] As an example, electrical switches can be used for switches SAp and SAN. For example, a transistor can be used as an electrical switch. In addition, the OS transistor described above can be used as the transistor. Furthermore, in this specification, when a high level potential is applied to the control terminal of the switch, the switch is in the ON state, and when a low level potential is applied to the control terminal of the switch, the switch is in the OFF state. In addition, switches SAp and SAN can be used for switches other than electrical switches, for example, mechanical switches.

[0099] The SWLA wiring, for example, functions as wiring for transmitting control signals to turn switch SAP and switch SAN on or off. Furthermore, as described above, these control signals can be at a high or low potential.

[0100] The drive circuit WSD, for example, has the function of generating selection signals to be sent to the calculation cells IMp and IMn that will be the destinations for writing the multipliers wp and wn, respectively, when writing them to the calculation cells IMp and IMn, and the function of sending said selection signals to the wiring WSL. The drive circuit WSD also has, for example, the function of generating non-selection signals to be sent to the calculation cells IMp and IMn that will not be the destinations for writing, and the function of sending said non-selection signals to the wiring WSL.

[0101] The drive circuit XSD, for example, has the function of generating selection signals to be sent to the calculation cells IMp and IMn when multiplication is performed in each of the calculation cells IMp and IMn, and the function of sending said selection signals to the wiring XSL.

[0102] The drive circuit WXCD, for example, similar to the drive circuit WSD, has the function of generating a selection signal to send to the calculation cells IMp and IMn, respectively, which are the destinations for writing the multipliers wp and wn, and the function of sending the selection signal to the wiring WXL. Furthermore, the drive circuit WXCD also has, for example, the function of generating a non-selection signal to send to the calculation cells IMp and IMn, respectively, which are not the destinations for writing, and the function of sending the non-selection signal to the wiring WSL. In addition, the drive circuit WXCD also has, for example, the function of sending the second data x, which is the multiplicand, to the wiring WXL when multiplication is performed in each of the calculation cells IMp and IMn.

[0103] The drive circuit ITS includes switches SBp and SBn, and circuit ITSa. The first terminal of switch SBp is connected to wiring WCLp, and the second terminal of switch SBp is connected to the first input terminal of circuit ITSa. The first terminal of switch SBn is connected to wiring WCLn, and the second terminal of switch SBn is connected to the second input terminal of circuit ITSa. The control terminals of switch SBp and switch SBn are each connected to wiring SWLB. The output terminal of circuit ITSa is connected to wiring OL.

[0104] Circuit ITSa, for example, has the function of supplying a fixed potential to the calculation cell IMp via the wiring WCLp from the first input terminal and to the calculation cell IMn via the wiring WCLn from the second input terminal when the calculation circuit CC performs a multiplication operation. Note that each fixed potential is the potential V supplied by the aforementioned wiring VRE. Ｒ The potential is set to be lower than the fixed potential, and in this specification, the fixed potential is defined as potential V Ｓ This will be explained as follows.

[0105] Furthermore, circuit ITSa has a function, for example, to compare the amount of current input to the first input terminal and the second input terminal of circuit ITSa, and to output the difference information to the output terminal of circuit ITSa. In this specification, the amount of current flowing between wiring WCLp and the first input terminal of circuit ITSa is denoted as Isp, and the amount of current flowing between wiring WCLn and the second input terminal of circuit ITSa is denoted as Isn. Therefore, it can be said that circuit ITSa obtains Isp and Isn, calculates Isp - Isn, and outputs information corresponding to Isp - Isn to the output terminal. This information includes the result of multiplying the first data and the second data, and this information can be, for example, a potential corresponding to the difference current Isp - Isn. Examples of circuits that output a potential corresponding to the difference current Isp - Isn include a current comparator, an integrating circuit, and a QV circuit. In other words, circuit ITSa can be equipped with these circuits.

[0106] For example, switches SBp and SBn can be the same switches that are applicable to switches SAP and SAN. Therefore, for switches SBp and SBn, you can refer to the descriptions of switches SAP and SAN, respectively.

[0107] Wiring SWLB, for example, functions as wiring for transmitting control signals to turn switches SBp and SBn on or off, similar to wiring SWLA. Furthermore, as described above, these control signals can be at a high or low potential.

[0108] Wiring OL functions as wiring for outputting the result of multiplying the first data w and the second data x, which are output from the output terminal of circuit ITSa, to the outside of the arithmetic unit CDV.

[0109] <<Example of operation of the arithmetic unit 1>> Next, an example of operation of the arithmetic unit CDV shown in Figure 1 will be explained.

[0110] Figure 3A is a timing chart showing an example of the writing operation of the first data w to the arithmetic circuit CC in the arithmetic unit CDV, and Figure 3B is a timing chart showing an example of the multiplication operation of the first data w and the second data x in the arithmetic unit CDV.

[0111] The timing chart in Figure 3A shows the changes in potential of wiring SWLA, SWLB, WXL, WSL, XSL, WCLp, and WCLn during periods T01 to T03. The timing chart in Figure 3B shows the changes in potential of wiring SWLA, SWLB, WXL, WSL, and XSL during periods T04 to T06. The timing chart in Figure 3B also shows the changes in the amount of current Isp flowing through wiring WCLp and the amount of current Isn flowing through wiring WCLn.

[0112] Furthermore, in the timing charts of Figures 3A and 3B, the types of wiring and nodes are indicated on the left side, and the potential height, current amount, etc. are indicated on the right side. In each timing chart, "High" indicates a high-level potential in that wiring, and similarly, "Low" indicates a low-level potential in that wiring. The same applies to the timing charts in other drawings in this specification.

[0113] [Writing Operation] During period T01, a high-level potential is applied to both wiring WXL and wiring WSL, and a low-level potential is applied to both wiring SWLA, wiring SWLB, and wiring XSL. The start time of period T01 can be the timing when the potential of one or both of wiring WXL and wiring WSL changes.

[0114] As described above, a high-level potential is applied to the gates of transistors M1p and M1n, so transistors M1p and M1n turn ON. Also, a high-level potential is applied to the gates of transistors M2p and M2n, so transistors M2p and M2n turn ON.

[0115] Furthermore, since a low potential is applied to the control terminals of switches SAp and SAN, switches SAp and SAN are in the off state. Similarly, since a low potential is applied to the control terminals of switches SBp and SBn, switches SBp and SBn are in the off state. Furthermore, since a low potential is applied to the gates of transistors M3p and M3n, transistors M3p and M3n are in the off state.

[0116] In the calculation cell IMp, transistors M1p and M2p are ON, so there is conductivity between wiring VWE and wiring WCLp. Therefore, the potentials of the first and second terminals of the resistive switching element MRp and wiring WCLp are the intermediate potential V supplied by wiring VWE. Ｍ Similarly, in the calculation cell IMn, since transistors M1n and M1p are ON, there is conduction between the wiring VWE and the wiring WCLn. Therefore, the potentials of the first and second terminals of the resistive switching element MRn and the wiring WCLn are also the intermediate potential V supplied from the wiring VWE. Ｍ This is the result.

[0117] During period T02, a high-level potential is applied to the wiring SWLA. As a result, the control terminals of switches SAP and SAN are also supplied with a high-level potential, causing switches SAP and SAN to be in the ON state. The start time of period T02 can be defined as the timing when the potential of wiring SWLA changes.

[0118] Furthermore, during period T02, the computing unit CDV receives a low-level potential V from the wiring IWL corresponding to the value of the first data w. Ｌor a high-level potential V Ｈ is provided. Therefore, in the drive circuit WCD, the circuit WCDa supplies, from the first output terminal, via the switch Sap, to the wiring WCLp, a low-level potential V Ｌ or a high-level potential V Ｈ as wp, and supplies, from the second output terminal, via the switch San, to the wiring WCLn, a low-level potential V Ｌ as wn. When a high-level potential V Ｈ is provided from the wiring IWL (when w = 1), the potential change of the wiring WCLp during the period T02 shown in FIG. 3A is indicated by a thick solid line, and when a low-level potential V Ｌ is provided from the wiring IWL (when w = 0), the potential change of the wiring WCLp during the period T02 shown in FIG. 3A is indicated by a thick dashed line.

[0119] When w = 1, a high-level potential V Ｈ is provided from the wiring IWL. Also, a high-level potential V Ｈ is provided to the first terminal of the resistance change element MRp, and an intermediate potential V Ｍ is provided to the second terminal of the resistance change element MRp. Here, it is assumed that a current flows from the first terminal to the second terminal of the resistance change element MRp, and a spin current is generated by the current, so that the direction of the magnetic moment in the layer FL becomes substantially parallel to the direction of the magnetic moment in the layer RL. Also, when the magnetic moments of the layer FL and the layer RL are substantially parallel to each other, the amount of the tunnel current flowing through the layer TIS increases.

[0120] When w = 0, a low-level potential V Ｌ is provided from the wiring IWL. Also, a low-level potential V Ｌ is provided to the first terminal of the resistance change element MRp, and an intermediate potential V ＭThe following is given. Here, it is assumed that a current flows from the second terminal to the first terminal of the resistive switching element MRp, and that this current generates a spin current, so that the direction of the magnetic moment in layer FL is approximately antiparallel to the direction of the magnetic moment in layer RL. Also, when the magnetic moments of layer FL and layer RL are approximately antiparallel to each other, the amount of tunnel current flowing through layer TIS becomes small.

[0121] Regardless of the value of w, a low-level potential V is present at the first terminal of the resistive switching element MRn. Ｌ Given, an intermediate potential V is applied to the second terminal of the resistive element MRn. Ｍ The following is given. As a result, a current flows from the second terminal to the first terminal of the resistive switching element MRn, and this current generates a spin current, which determines the direction of the magnetic moment in layer FL of the resistive switching element MRn. At this time, the direction of the magnetic moment in layer FL is assumed to be approximately antiparallel to the direction of the magnetic moment in layer RL.

[0122] Furthermore, during period T02, as described above, after determining the direction of the magnetic moments within the respective layers FL of the resistive switching elements MRp and MRn, a low-level potential is applied to the wiring SWLA to turn off switches SAp and SAN. As a result, the potentials of wiring WCLp and WCLn are set to the intermediate potential V supplied from wiring VWE. Ｍ This is the result. Note that the potential of the wiring WCLn is V Ｍ After that, the program transitions to period T03.

[0123] During period T03, low-level potentials are applied to both wiring WXL and wiring WSL. As a result, in calculation cell IMp, transistors M1p and M2p are in the off state, and wiring WCLp is in the floating state. Similarly, in calculation cell IMn, transistors M1n and M2n are in the off state, and wiring WCLn is in the floating state. The start time of period T03 can be the timing when the potential of one or both of wiring WXL and wiring WSL changes.

[0124] As described above, by performing the operations during periods T01 to T03, data corresponding to wp can be stored in the calculation cell IMp, and data corresponding to wn can be stored in the calculation cell IMn.

[0125] [Multiplication Operation] During period T04, a high-level potential is applied to wiring SWLB and wiring XSL, while a low-level potential is applied to wiring SWLA, wiring WXL, and wiring WSL. The start time of period T04 can be the timing when the potential of one or both of wiring SWLB and wiring XSL changes.

[0126] As described above, a high-level potential is applied to the control terminals of switches SBp and SBn, so switches SBp and SBn are turned ON. Also, a high-level potential is applied to the gates of transistors M3p and M3n, so transistors M3p and M3n are turned ON.

[0127] Furthermore, since a low potential is applied to the control terminals of switches SAp and SAN, switches SAp and SAN are turned off. Also, since a low potential is applied to the gates of transistors M1p and M1n, transistors M1p and M1n are turned off. Furthermore, since a low potential is applied to the gates of transistors M2p and M2n, transistors M2p and M2n are turned off.

[0128] In the calculation cell IMp, since transistor M3p is ON, the third terminal of the resistive switching element MRp has a potential V from the wiring VRE. Ｒ The following is given. Similarly, in the calculation cell IMn, since transistor M3n is ON, the third terminal of the resistive switching element MRn has a potential V from the wiring VRE. Ｒ It is given.

[0129] Furthermore, since switches SBp and SBn are in the ON state, the potential V output from the first input terminal of circuit ITSa is present in the wiring WCLp. ＳThe following is given: and the wiring WCLn is connected to the potential V output from the second input terminal of circuit ITSa. Ｓ It is given.

[0130] During period T05, a potential corresponding to the second data x is applied to the wiring WXL. Specifically, when x = 1, a high-level potential is applied to the wiring WXL as the potential corresponding to x = 1. When x = 0, a low-level potential is applied to the wiring WXL as the potential corresponding to x = 0. The start time of period T02 can be the timing when the second data x is input to the wiring WXL.

[0131] When x = 1, transistors M1p and M1n are turned on, and the potential V output from the first input terminal of circuit ITSa is transmitted to the first terminal of the resistive switching element MRp via the wiring WCLp. Ｓ A voltage V is given, and the first terminal of the resistive switching element MRn is connected via the wiring WCLn to the potential V output from the second input terminal of the circuit ITSa. Ｓ It is given.

[0132] In the resistive switching element MRp, the first terminal has a potential V Ｓ A potential V is given to the third terminal. Ｒ Since is given, a tunnel current of a certain amount flows through the TIS layer of the resistive switching element MRp, corresponding to the direction of the magnetic moment of layer FL. When the direction of the magnetic moment of layer FL is approximately parallel to the direction of the magnetic moment of layer RL, the amount of the tunnel current becomes large, and when the magnetic moment of layer FL is approximately antiparallel to the direction of the magnetic moment of layer RL, the amount of the tunnel current becomes small. Here, for example, the amount of tunnel current that flows when wp written to the resistive switching element MRp is "1" is I Ｂ Furthermore, the amount of tunnel current that flows when wp, which is written to the resistive switching element MRp, is I Ｂ Smaller than I Ｓ Let's assume that.

[0133] Therefore, when the second data x is "1" and wp is "1", the amount of current flowing from the calculation cell IMp to the wiring WCLp is Isp = IＢ And when the second data x is "1" and wp is "0", the amount of current flowing from the calculation cell IMp to the wiring WCLp is Isp = I Ｓ This is the result.

[0134] Furthermore, in the resistive switching element MRn, the first terminal has a potential V Ｓ A potential V is given to the third terminal. Ｒ Since is given, a tunnel current of an amount corresponding to the direction of the magnetic moment of layer FL flows through layer TIS of the resistive switching element MRn. Note that since "0" is written as wn in the resistive switching element MRn, a quantity I flows through layer TIS of the resistive switching element MRn. Ｓ A tunnel current flows. In other words, the amount of current flowing from the calculation cell IMn to the wiring WCLn is Isn = I Ｓ This is the result.

[0135] When the second data x is "0", transistors M1p and M1n are in the off state, and the potential V output from circuit ITSa is present at the first terminals of the resistive switching elements MRp and MRn. Ｓ This is because no voltage is given. In other words, no voltage is applied between the first and third terminals of the resistive switching element MRp and the resistive switching element MRn, and no tunnel current is generated in the layer TIS. Therefore, the amount of current Isp flowing from the calculation cell IMp to the wiring WCLp and the amount of current Isn flowing from the calculation cell IMn to the wiring WCLn are both 0.

[0136] For convenience, in this specification, the statement "the amount of current flowing from A to B is 0" may be rephrased as "a current of 0 flows from A to B."

[0137] Furthermore, during period T05, circuit ITSa acquires the difference between the amount of current Isp flowing through wiring WCLp and the amount of current Isn flowing through wiring WCLn, and outputs this difference information to the output terminal of circuit ITSa. Here, when the difference current between Isp and Isn is denoted as ΔI, ΔI will be as shown in the table below, depending on the result of multiplying the first data w and the second data x. Note that Isp and Isn are also shown in the table.

[0138]

[0139] As shown in the table above, when both the first data w and the second data x are "1", the product of the first data w and the second data x is w × x = 1, and ΔI = I Ｂ -I Ｓ This is the result. Also, when one or both of the first data w and the second data x are "0", the product of the first data w and the second data x is w × x = 0, and ΔI = 0. In this way, by defining wp and wn and the second data x as shown in the table above, and using the calculation unit CDV in Figure 1, the product of the first data w and the second data x can be obtained from the differential current ΔI.

[0140] During period T06, a low-level potential is applied to wiring SWLB and wiring XSL, causing switches SBp and SBn to be in the off state, and transistors M3p and M3n to be in the off state. This terminates the multiplication operation in the arithmetic unit CDV. The start time of period T06 can be the timing when the potential of one or both of wiring WXL and wiring WSL changes.

[0141] <Example of arithmetic unit configuration 2> The arithmetic unit CDV shown in Figure 1 has a configuration that includes one arithmetic circuit CC, but the number of arithmetic circuits CC may be two or more. For example, the arithmetic unit CDVA shown in Figure 4 is a modified example of the arithmetic unit CDV in Figure 1, and differs from the arithmetic unit CDV in Figure 1 in that multiple arithmetic circuits CC are arranged in a matrix.

[0142] The arithmetic unit CDVA in Figure 4 has a cell array CA containing multiple arithmetic circuits CC as shown in Figure 1. Specifically, in Figure 4, the multiple arithmetic circuits CC are arranged in a matrix of m rows and n columns (where m and n are integers of 1 or more) in the cell array CA. Note that Figure 4 shows excerpts of the arithmetic circuit CC[1,j] located in the 1st row and jth column (where j is an integer between 1 and n) and the arithmetic circuit CC[m,j] located in the mth row and jth column.

[0143] Furthermore, each arithmetic circuit CC includes an arithmetic cell IMp and an arithmetic cell IMn, similar to the arithmetic circuit CC in Figure 1. Therefore, in the cell array CA in Figure 4, the arithmetic cells IMp and IMn are arranged alternately in the row direction.

[0144] In Figure 4, the signs of the calculation cells IMp and IMn located at the address of row i, column j (where i is an integer between 1 and m) are denoted with [i,j]. Furthermore, each of the calculation cells IMp[1,1] through IMp[m,n] has the same circuit configuration as the calculation cell IMp in Figure 1, and each of the calculation cells IMn[1,1] through IMn[m,n] has the same circuit configuration as the calculation cell IMn in Figure 1. Therefore, for the circuit configurations of each of the calculation cells IMp[1,1] through IMp[m,n] and IMn[1,1] through IMn[m,n], refer to the explanation of calculation cells IMp and IMn in Figure 1.

[0145] Furthermore, the drive circuit WCD in the arithmetic unit CDVA in Figure 4 includes circuits WCDa[1] to WCDa[n] corresponding to circuit WCDa in Figure 1, switches SAP[1] to SAP[n] corresponding to switch SAP in Figure 1, and switches SAN[1] to SAN[n] corresponding to switch SAN in Figure 1. Note that the drive circuit WCD in Figure 1 shows only circuits WCDa[j], switches SAP[j] and SAN[j] as an excerpt. In addition, wiring IWL[1] to IWL[n] is connected one-to-one to each input terminal of circuits WCDa[1] to WCDa[n]. Note that Figure 4 shows only an excerpt of the connection between circuit WCDa[j] and wiring IWL[j].

[0146] Furthermore, the drive circuit ITS in the arithmetic unit CDVA in Figure 4 includes circuits ITSa[1] to ITSa[n] corresponding to circuit ITSaa in Figure 1, switches SBp[1] to SBp[n] corresponding to switch SBp in Figure 1, and switches SBn[1] to SBn[n] corresponding to switch SBn in Figure 1. Note that in Figure 4, circuit ITSa[j], switch SBp[j], and switch SBn[j] are shown as an excerpt from the drive circuit ITS. In addition, wiring OL[1] to OL[n] are connected one-to-one to the output terminals of circuits ITSa[1] to ITSa[n]. Note that in Figure 4, the connection between circuit ITSa[j] and wiring OL[j] is shown as an excerpt.

[0147] In the cell array CA of the arithmetic unit CDVA in Figure 4, wiring WCLp[1] to WCLp[n] corresponding to wiring WCLp in Figure 1, and wiring WCLn[1] to WCLn[n] corresponding to wiring WCLn in Figure 1, extend in the column direction. Note that Figure 4 shows an excerpt of wiring WCLp[j] and wiring WCLn[j]. In addition, in the cell array CA of the arithmetic unit CDVA in Figure 4, wiring WXL[1] to WXL[m] corresponding to wiring WXL in Figure 1, wiring WSL[1] to WSL[m] corresponding to wiring WSL in Figure 1, and wiring XSL[1] to XSL[m] corresponding to wiring XSL in Figure 1, extend in the row direction. Figure 4 shows excerpts of wiring WXL[1], wiring WXL[m], wiring WSL[1], wiring WSL[m], wiring XSL[1], and wiring XSL[m].

[0148] Wirings WXL[1] to WXL[m] are connected to drive circuit WXCD. Wirings WSL[1] to WSL[m] are connected to drive circuit WSD. Wirings XSL[1] to XSL[m] are connected to drive circuit XSD.

[0149] <<Examples of Drive Circuit Configurations>> Next, we will explain the configuration examples of the drive circuits WCD, WXCD, and ITS of the arithmetic unit CDVA shown in Figure 4. In particular, the configuration examples of the drive circuits WCD and ITS described below can also be applied to the drive circuits WCD and ITS of the arithmetic unit CDV shown in Figure 1.

[0150] [Drive Circuit WCD] Figure 5A is a circuit diagram showing an example of the circuit configuration of the drive circuit WCD shown in Figures 1 and 4. In particular, Figure 5A also shows an example of the circuit configuration of circuit WCDa. In addition, the addresses assigned to the symbols shown in Figure 4 are omitted in Figure 5A.

[0151] As shown in Figure 5A, circuit WCDa includes, for example, a buffer circuit BF. The buffer circuit BF, for example, functions as a type of logic gate, outputting a signal with the same logic as the signal input to the input terminal to the output terminal.

[0152] The input terminal of buffer circuit BF is connected to wiring IWL via the input terminal of circuit WCDa. The output terminal of buffer circuit BF is connected to the first terminal of switch SAp via the first output terminal of circuit WCDa. The first terminal of switch SAN is connected to wiring VLE via the second output terminal of circuit WCDa.

[0153] Wiring VLE functions, for example, as wiring to provide a fixed potential. This fixed potential is the intermediate potential V provided by the aforementioned wiring VWE. Ｍ Lower low-level potential V Ｌ It is preferable to do so.

[0154] The first data w is transmitted to the wiring IWL from outside the arithmetic unit CDV. As described above, w is binary digital data representing "0" or "1", and can be represented as a high-level potential or a low-level potential, respectively. Here, the potential corresponding to w=0 is the low-level potential V. Ｌ Let w=1 correspond to the high-level potential V Ｈ Therefore, as mentioned above, the low-level potential V corresponding to w=0 ＬIt is preferable that this is equal to the potential supplied by the wiring VLE.

[0155] Therefore, the low-level potential V, which indicates w=0, is present in the wiring IWL. Ｌ When given, a low-level potential V is present at the input terminal of the buffer circuit BF. Ｌ Because this is input, a low-level potential V is emitted from the output terminal of the buffer circuit BF. Ｌ The following is output. Here, when both switch SAP and switch SAN are turned ON, the circuit WCDa has a low-level potential V indicating wp = 0. Ｌ This is output from the first output terminal of circuit WCDa to wiring WCLp via switch SAp, and also a low-level potential V indicating wn=0. Ｌ This signal is output from the second output terminal of circuit WCDa to wiring WCLn via switch SAN.

[0156] Furthermore, a high-level potential V, where w=1, is present in the wiring IWL. Ｈ When given, a high-level potential V is present at the input terminal of the buffer circuit BF. Ｈ Because this is input, a high-level potential V is emitted from the output terminal of the buffer circuit BF. Ｈ The following is output. Here, when both switch SAp and switch SAN are turned ON, the circuit WCDa has a high-level potential V indicating wp = 1. Ｈ This is output from the first output terminal of circuit WCDa to wiring WCLp via switch SAp, and also a low-level potential V indicating wn=0. Ｌ This signal is output from the second output terminal of circuit WCDa to wiring WCLn via switch SAN.

[0157] The drive circuit WCD according to one aspect of the present invention is not limited thereto. Depending on the circumstances, the circuit configuration of the drive circuit WCD according to one aspect of the present invention may be modified. For example, as shown in Figure 5B, the drive circuit WCD according to one aspect of the present invention may be configured such that the circuit WCDa does not have a buffer circuit BF. In Figure 5A, the buffer circuit BF provided in the circuit WCDa has the role of transmitting a signal corresponding to the first data w to the wiring WCLp without attenuation. Conversely, if the signal is not attenuated in the wiring WCLp, there is no need to provide a buffer circuit BF, and the drive circuit WCD shown in Figure 5B can be used. In the drive circuit WCD of Figure 5B, since the buffer circuit BF is not provided, the circuit area of ​​the drive circuit WCD can be reduced. This makes it possible to reduce the circuit area of ​​the arithmetic unit CDV and the arithmetic unit CDVA, and thus miniaturize the arithmetic unit CDV and the arithmetic unit CDVA.

[0158] Furthermore, for example, as an embodiment of the present invention, the drive circuit WCD may be a configuration in which the circuit configuration of circuit WCDa is changed, as shown in Figure 5C. Specifically, the circuit configuration of circuit WCDa in Figure 5C is such that the input terminals are changed to a first input terminal and a second input terminal, and a buffer circuit BFp and a buffer circuit BFn are included. Also, in Figure 5C, the wiring IWL is shown as two wires, wiring IWLp and wiring IWLn, with wiring IWLp being given a potential corresponding to wp, and wiring IWLn being given a potential corresponding to wn.

[0159] In the circuit WCDa shown in Figure 5C, wiring IWLp is connected to the input terminal of buffer circuit BFp via the first input terminal of circuit WCDa, and the output terminal of buffer circuit BFp is connected to the first terminal of switch SAp via the first output terminal of circuit WCDa. Also, wiring IWLn is connected to the input terminal of buffer circuit BFn via the second input terminal of circuit WCDa, and the output terminal of buffer circuit BFn is connected to the first terminal of switch SAN via the second output terminal of circuit WCDa.

[0160] For details on buffer circuits BFp and BFn, please refer to the description of buffer circuit BF above.

[0161] The circuit WCDa shown in Figures 5A and 5B is an example of a circuit that outputs two variables, wp and wn, which represent the first data w, a binary value of "0" or "1". However, the circuit WCDa shown in Figure 5C can output two variables, wp and wn, which represent the first data w, a trivalent value of "-1", "0", or "1". For example, when w = 0, wp = 0, wn = 0 or wp = 1, wn = 1 is defined, and when w = 1, wp = 1, wn = 0 is defined, and when w = -1, wp = 0, wn = 1 is defined, so the arithmetic unit CDV equipped with the circuit WCDa shown in Figure 5C can handle the first data w, a trivalent value of "-1", "0", or "1".

[0162] Specifically, when w=1, the wiring IWLp has a high-level potential V indicating wp=1. Ｈ A low-level potential V that gives and shows wn = 0 Ｌ By applying this, when both switch SAP and switch SAN are ON, a high-level potential V is applied to the wiring WCLP. Ｈ Given a low-level potential V in the wiring WCLn Ｌ The following is given. Also, when w = -1, the wiring IWLp has a low-level potential V indicating wp = 0. Ｌ A high-level potential V that gives and shows wn=1 Ｈ By providing this, when both switch SAP and switch SAN are ON, a low-level potential V is applied to the wiring WCLP. Ｌ Given, a high-level potential V is applied to the wiring WCLn. Ｈ The following is given. Also, when w=0, the wiring IWLp and IWLn have a low-level potential V indicating wp=wn=0. Ｌ By providing a high-level potential V where wp = wn = 1, Ｈ By providing this, a high-level potential V is introduced to each of the wirings WCLp and WCLn. Ｈ Or low-level potential V Ｌ It is given.

[0163] In particular, when x = 1 is given as the second data by writing the first data w = -1 to the calculation circuit CC in Figure 1, for example, the amount of current flowing from the calculation cell IMp to the wiring WCLp is Isp = I Ｓ And the amount of current flowing from the calculation cell IMn to the wiring WCLn is Isp = I Ｂ This is the result. At this time, the difference current between wiring WCLp and wiring WCLn is ΔI = I Ｓ -I Ｂ And so, I Ｓ -I Ｂ This can be made to correspond to the result of multiplying w = -1 and x = 1, which is w × x = -1.

[0164] As described above, by applying the circuit configuration shown in Figure 5C as the drive circuit WCD, the first data w can be treated as one of three values: "-1", "0", or "1" in the arithmetic unit CDV or arithmetic unit CDVA.

[0165] [Drive Circuit WXCD] Figure 6A is a circuit diagram showing an example of the circuit configuration of the drive circuit WXCD that can be provided in the computing device CDVA shown in Figure 4.

[0166] As shown in Figure 6A, the drive circuit WXCD includes, as an example, a shift register SR, selectors SLC[1] to SLC[m], sequential circuits LTS[1] to LTS[m], sequential circuits LTH[1] to LTH[m], and level shifters LV[1] to LV[m].

[0167] In Figure 6A, the following are extracted and shown: selector SLC[1], sequential circuit LTS[1], sequential circuit LTH[1], level shifter LV[1], and wiring WXL[1] located in the first row; selector SLC[2], sequential circuit LTS[2], sequential circuit LTH[2], level shifter LV[2], and wiring WXL[2] located in the second row; and selector SLC[m], sequential circuit LTS[m], sequential circuit LTH[m], level shifter LV[m], and wiring WXL[m] located in the mth row.

[0168] Furthermore, in the descriptions of selectors SLC[1] to SLC[m], the [x] (where x is an integer between 1 and m) appended to the symbols may be omitted for content common to all of them. This also applies to other circuits such as sequential circuits LTS[1] to LTS[m], sequential circuits LTH[1] to LTH[m], and level shifters LV[1] to LV[m].

[0169] The shift register SR has a first input terminal that receives a start pulse signal SP, a second input terminal that receives a clock signal CK, and terminals SO[1] to SO[m] that function as output terminals. In Figure 6A, terminals SO[1], SO[2], and SO[m] are shown as an excerpt.

[0170] The shift register SR has the function of sequentially outputting potentials corresponding to the start pulse signal input to the first input terminal to each of terminals SO[1] through SO[m] each time the rising edge of a clock signal is input to the second input terminal. For example, when a high-level potential is applied to the first input terminal as a start pulse signal, and the first rising edge of the clock signal is input to the second input terminal, the shift register SR outputs a high-level potential to terminal SO[1] and low-level potentials to each of terminals SO[2] through SO[m]. Subsequently, when the second rising edge of the clock signal is input to the second input terminal, the shift register SR outputs a high-level potential to terminal SO[2] and low-level potentials to terminals SO[1] and each of terminals SO[3] through SO[m].

[0171] The selector SLC has an input terminal, a first output terminal, a second output terminal, and a control terminal. As an example, the selector SLC has the function of making the connection between the input terminal and one of the first and second output terminals conductive, and the connection between the input terminal and the other of the first and second output terminals non-conductive, in response to a control signal input to the control terminal. In other words, the selector SLC has the function of selecting one of the first and second output terminals in response to a control signal input to the control terminal and outputting the signal input to the input terminal to the selected output terminal.

[0172] In this specification, the selector SLC is configured such that when a high-level potential is applied to the control terminal, it conducts between the input terminal and the first output terminal and deconducts between the input terminal and the second output terminal, and when a low-level potential is applied to the control terminal, it deconducts between the input terminal and the first output terminal and conducts between the input terminal and the second output terminal.

[0173] Each of the sequential circuits LTS and LTH has an input terminal, an output terminal, a control terminal, and an enable terminal. The sequential circuits listed above have the function of holding information input to the input terminal when enabled, and the function of outputting the held information as a signal to the output terminal in response to a control signal input to the control terminal. Specific examples of these sequential circuits include latch circuits and flip-flops. In this specification, these sequential circuits will be described as latch circuits as an example.

[0174] Furthermore, in this specification, sequential circuits LTS and LTH are defined as being enabled when a high-level potential is applied to the enable terminal, and disabled when a low-level potential is applied to the enable terminal. In particular, when the sequential circuits listed above are disabled, the output terminals are defined as having a high impedance.

[0175] A level shifter (LV) has an input terminal and an output terminal. The level shifter (LV) acquires a digital signal input to the input terminal, converts one or both of the high and low levels of the digital signal to a different level, and outputs the converted digital signal to the output terminal. The level shifter (LV) is used to convert the input voltage to a level that can be handled by the output device.

[0176] Let's focus on the i-th row of the drive circuit WXCD. Terminal SO[i] is connected to the input terminal of selector SLC[i]. Also, the first output terminal of selector SLC[i] is connected to the control terminal of sequential circuit LTS[i], the second output terminal of selector SLC[i] is connected to the input terminal of level shifter LV[i] and the output terminal of sequential circuit LTH[i], and the control terminal of selector SLC[i] is connected to wiring SLL. Also, the output terminal of sequential circuit LTS[i] is connected to the input terminal of sequential circuit LTH[i].

[0177] In particular, in this specification, the connection point between the output terminal of sequential circuit LTS[i] and the input terminal of sequential circuit LTH[i] is referred to as node SN[i]. Note that in Figure 6A, node SN[1], node SN[2], and node SN[m] are shown as examples.

[0178] The input terminal of the sequential circuit LTS[i] is connected to wiring IXL, and the enable terminal of the sequential circuit LTS[i] is connected to wiring EN1. Furthermore, the control terminal of the sequential circuit LTH[i] is connected to wiring LL, and the enable terminal of the sequential circuit LTH[i] is connected to wiring EN2.

[0179] Wiring SLL functions as a wire for transmitting a control signal to the control terminal of selector SLC[i]. Wiring LL also functions as a wire for transmitting a control signal to the control terminal of sequential circuit LTH[i]. Wiring EN1 functions as a wire for transmitting an enable signal or a disable signal to the enable terminal of sequential circuit LTS[i]. Wiring EN2 also functions as a wire for transmitting an enable signal or a disable signal to the enable terminal of sequential circuit LTH[i].

[0180] Next, we will explain an example of the operation of the drive circuit WXCD shown in Figure 6A.

[0181] Figure 7A is a timing chart showing an example of the operation of the drive circuit WXCD when sequentially writing first data to each of the multiple arithmetic circuits CC of the arithmetic unit CDVA. Specifically, the timing chart shows an example of the operation in which the drive circuit WXCD transmits selection signals to each of the wirings WXL[1] to WXL[m] to sequentially turn on transistors M1p and M1n, respectively, which are provided in the arithmetic circuit CC. The timing chart also shows the changes in potential of terminal SO[1], terminal SO[2], terminal SO[m], wiring SLL, wiring WXL[1], wiring WXL[2], and wiring WXL[m] during periods T11 to T13.

[0182] During periods T11 to T13, low-level potentials are assumed to be applied to wiring EN1 and wiring EN2 (not shown). In other words, sequential circuits LTS[1] to LTS[m] and sequential circuits LTH[1] to LTH[m] are each disabled during periods T11 to T13. Also, as described above, the output terminals of sequential circuits LTH[1] to LTH[m] are high impedance.

[0183] During period T11, a low potential is applied to the wiring SLL. As a result, the control terminals of selectors SLC[1] to SLC[m] are each supplied with this low potential, causing selectors SLC[1] to SLC[m] to be non-conductive between their input terminal and the first output terminal, and conductive between their input terminal and the second output terminal. Consequently, in row i, the terminal SO[i] of the shift register SR and the input terminal of the level shifter LV[i] become conductive.

[0184] Furthermore, during period T11, low-level potentials are assumed to be output from each of the terminals SO[1] to SO[m] of the shift register SR. Therefore, low-level potentials are applied to each of the input terminals of the level shifters LV[1] to LV[m]. Consequently, each of the level shifters LV[1] to LV[m] acquires the low-level potential input to its input terminal and applies the converted potential of the voltage level of the low-level potential to the wiring WXL[1] to WXL[m]. In Figure 7A, for convenience, the potential applied to the wiring WXL[1] to WXL[m] is treated as the low-level potential. In addition, this low-level potential can be used as a non-selection signal output by the drive circuit WXCD in the arithmetic unit CDVA.

[0185] During period T12, the shift register SR sequentially outputs high-level potentials from each of terminals SO[1] to SO[m]. For example, when a high-level potential is output from terminal SO[i], that high-level potential is input to the input terminal of the level shifter LV[i]. The level shifter LV[i] also acquires the high-level potential applied to its input terminal and applies a potential converted from the voltage level of that high-level potential to the wiring WXL[i]. As a result, the drive circuit WXCD can output a high-level potential to the wiring WXL[i]. This operation is performed from the first line to the m line, so that the drive circuit WXCD can sequentially apply a high-level potential as a selection signal to each of the wirings WXL[1] to WXL[m].

[0186] During period T13, as in period T11, a low-level potential is output from each of the terminals SO[1] to SO[m] of the shift register SR. In other words, the drive circuit WXCD can provide a non-selection signal as a low-level potential to each of the wirings WXL[1] to WXL[m] collectively.

[0187] As described above, by performing the operations shown in Figure 7A for periods T11 to T13, the first data can be sequentially written to each of the multiple arithmetic circuits CC of the arithmetic unit CDVA.

[0188] Next, an example of the operation of the drive circuit WXCD when multiple arithmetic circuits CC of the arithmetic unit CDVA perform multiplication of the first data and the second data will be explained using the timing chart in Figure 7B. The timing chart shows an example of the operation in which the drive circuit WXCD simultaneously transmits x[1] to x[m] to each of the wirings WXL[1] to WXL[m]. Specifically, the timing chart shows the changes in potential of terminal SO[1], terminal SO[2], terminal SO[m], wiring SLL, and wiring LL during periods T14 to T16. The timing chart also shows the signals given to wiring IXL, node SN[1], node SN[2], node SN[m], wiring WXL[1], wiring WXL[2], and wiring WXL[m] during periods T14 to T16.

[0189] During periods T14 to T16, high-level potential is assumed to be applied to wiring EN1 and wiring EN2 (not shown). In other words, sequential circuits LTS[1] to LTS[m] and sequential circuits LTH[1] to LTH[m] are each enabled during periods T14 to T16.

[0190] During period T14, a high-level potential is applied to the wiring SLL. As a result, a high-level potential is applied to the control terminals of selectors SLC[1] to SLC[m], causing selectors SLC[1] to SLC[m] to conduct between their input terminal and the first output terminal, and to conduct between their input terminal and the second output terminal. Consequently, in row i, the terminal SO[i] of the shift register SR and the control terminal of the sequential circuit LTS[i] become conductive.

[0191] Furthermore, during period T14, it is assumed that a low-level potential is output from each of the terminals SO[1] to SO[m] of the shift register SR. Therefore, a low-level potential is applied to each of the control terminals of the sequential circuits LTS[1] to LTS[m]. While a low-level potential is applied to the control terminal of the sequential circuit LTS[i], the potential of the output terminal of the sequential circuit LTS[i] does not change even if the potential of the input terminal of the sequential circuit LTS[i] changes. Also, during period T14, the potentials of each of the output terminals of the sequential circuits LTS[1] to LTS[m] are not specifically defined.

[0192] Furthermore, during period T14, a low-level potential is applied to wiring LL. Therefore, a low-level potential is applied to each control terminal of sequential circuit LTH[1] to sequential circuit LTH[m]. Similar to sequential circuit LTS[i], while a low-level potential is applied to the control terminal of sequential circuit LTH[i], the potential of the output terminal of sequential circuit LTH[i] does not change even if the potential of the input terminal of sequential circuit LTH[i] changes. Also, during period T14, the potential or signal of each output terminal of sequential circuit LTH[1] to sequential circuit LTH[m] is not specifically defined and is therefore not shown in the timing chart of Figure 7A. Furthermore, since the level shifter LV[i] acquires the signal output from the output terminal of sequential circuit LTH[i] and transmits a signal with a changed voltage level to wiring WXL[i], the potential of wiring WXL[i] is also not specifically defined. Therefore, the timing chart in Figure 7A does not include information about the potential or signal of wiring WXL[1] to wiring WXL[m].

[0193] During period T15, the shift register SR sequentially outputs high-level potentials from terminals SO[1] to SO[m]. When a high-level potential is output from terminal SO[1], the signal x[1] is provided to wiring IXL as second data to be transmitted to wiring WXL[1]. Similarly, when a high-level potential is output from terminal SO[2], the signal x[2] is provided to wiring IXL as second data to be transmitted to wiring WXL[2]. Likewise, when a high-level potential is output from terminal SO[m], the signal x[m] is provided to wiring IXL as second data to be transmitted to wiring WXL[m].

[0194] When a high-level potential output from terminal SO[i] is applied to the control terminal of sequential circuit LTS[i], sequential circuit LTS[i] acquires x[i] as the signal applied to the input terminal of sequential circuit LTS[i] and holds the potential corresponding to x[i]. Sequential circuit LTS[i] also outputs this potential from its output terminal. This potential is applied to the input terminal of sequential circuit LTH[i]. Subsequently, even if the potential output from terminal SO[i] changes from a high-level potential to a low-level potential, that is, even if a low-level potential is applied to the control terminal of sequential circuit LTS[i], sequential circuit LTS[i] continues to hold the potential corresponding to x[i] and continues to output this potential from its output terminal.

[0195] The operation described above during period T15 is performed from the first line to the m line, so that the output terminals of sequential circuits LTS[1] to LTS[m] continuously output signals corresponding to x[1] to x[m].

[0196] During period T16, a high-level potential is applied to wiring LL. As a result, a high-level potential is applied to the control terminals of sequential circuits LTH[1] through LTH[m]. Consequently, sequential circuit LTH[i] acquires x[i] input to its input terminal and holds a potential corresponding to x[i]. Furthermore, sequential circuit LTH[i] outputs this potential from its output terminal. This potential is then applied to the input terminal of level shifter LV[i].

[0197] In other words, sequential circuit LTH[1] holds a potential corresponding to x[1] and outputs this potential from the output terminal of sequential circuit LTH[1] to the input terminal of level shifter LV[1]. Similarly, sequential circuit LTH[2] holds a potential corresponding to x[2] and outputs this potential from the output terminal of sequential circuit LTH[2] to the input terminal of level shifter LV[2]. Likewise, sequential circuit LTH[m] holds a potential corresponding to x[m] and outputs this potential from the output terminal of sequential circuit LTH[m] to the input terminal of level shifter LV[m]. For this reason, each of the level shifters LV[1] to LV[m] transmits the respective signals of x[1] to x[m], which have undergone voltage level conversion, to wiring WXL[1] to WXL[m] all at once.

[0198] Furthermore, since x[i] is held in the sequential circuit LTH[i] during period T16, after period T16, the x[i] held in the sequential circuit LTS[i] may be updated with other data. Specifically, after period T16, the same operation as in period T15 is performed, and in synchronization with the shift register SR, for example, y[1] to y[m] are sequentially transmitted from wiring IXL as update data, thereby allowing y[1] to y[m] to be held in each of the sequential circuits LTS[1] to LTS[m]. For this reason, the drive circuit WXCD in Figure 6A can hold the x[i] transmitted to wiring WXL[i] and the y[i] transmitted after this x[i]. In other words, the drive circuit WXCD in Figure 6A can output x[i] and y[i] consecutively.

[0199] As described above, by performing the operations shown in Figure 7B from period T14 to period T16, the multiplication of the first data and the second data can be performed simultaneously in each of the multiple arithmetic circuits CC of the arithmetic unit CDVA.

[0200] It should be noted that the configuration example of the drive circuit WXCD according to one aspect of the present invention is not limited to the circuit configuration shown in Figure 6A. In the drive circuit WXCD shown in Figure 6A, x[1] to x[m] are sequentially provided to the wiring IXL as the second data values, but it is also possible to configure it so that x[1] to x[m] are provided to the drive circuit WXCD all at once.

[0201] The drive circuit WXCD shown in Figure 6B differs from the drive circuit WXCD in Figure 6A in that it is provided with selectors SLCA[1] to SLCA[m] instead of selectors SLC[1] to SLLC[m], and does not have sequential circuits LTS[1] to SLTS[m] and sequential circuits LTH[1] to SLTH[m]. In addition, the drive circuit WXCD in Figure 6B is connected to wiring IXL[1] to SLCA[m] as wiring IXL.

[0202] Each of the selector SLCA[1] to selector SLCA[m] has a first input terminal, a second input terminal, an output terminal, and a control terminal. Each of the selector SLCA[1] to selector SLCA[m] has, for example, a function to make one of the first and second input terminals conduct to the output terminal and the other of the first and second input terminals conduct to the output terminal, in response to a control signal input to the control terminal. In other words, each of the selector SLCA[1] to selector SLCA[m] has a function to select the first and second input terminals in response to a control signal input to the control terminal and to output the signal input to the selected input terminal to the output terminal.

[0203] In this specification, each of the selectors SLCA[1] to SLCA[m] is configured such that when a low-level potential is applied to the control terminal, the connection between the first input terminal and the output terminal becomes conductive, and the connection between the second input terminal and the output terminal becomes non-conductive. Furthermore, when a high-level potential is applied to the control terminal, the connection between the first input terminal and the output terminal becomes non-conductive, and the connection between the second input terminal and the output terminal becomes conductive.

[0204] Let's focus on row i of the drive circuit WXCD. Terminal SO[i] is connected to the first input terminal of selector SLCA[i], and wiring IXL[i] is connected to the second input terminal of selector SLCA[i]. Also, the output terminal of selector SLCA[i] is connected to the input terminal of level shifter LV[1]. Furthermore, wiring SLL is connected to the control terminals of selector SLCA[1] through selector SLCA[m].

[0205] When sequentially writing the first data to each of the multiple arithmetic circuits CC of the arithmetic unit CDVA using the drive circuit WXCD shown in Figure 6B, a low-level potential is applied to the wiring SLL, causing conduction between the first input terminal and output terminal of each of the selectors SLCA[1] to SLCA[m], and a high-level potential is output sequentially from each of the terminals SO[1] to SO[m] of the shift register SR. This allows selection signals to be sequentially transmitted from the output terminals of each of the level shifters LV[1] to LV[m] to the wiring WXL[1] to WXL[m].

[0206] Furthermore, when multiplying the first data and the second data of the arithmetic unit CDVA using the drive circuit WXCD shown in Figure 6B, a high-level potential is applied to the wiring SLL to create a conductive state between the second input terminal and output terminal of selector SLCA[1] to selector SLCA[m], and signals corresponding to x[1] to x[m] are transmitted as the second data to each of the wiring IXL[1] to wiring IXL[m]. This allows signals corresponding to x[1] to x[m] to be transmitted simultaneously from the output terminals of level shifters LV[1] to level shifters LV[m] to wiring WXL[1] to wiring WXL[m].

[0207] The drive circuit WXCD in Figure 6B, compared to the drive circuit WXCD in Figure 6A, does not have sequential circuits LTS[1] to LTS[m] and sequential circuits LTH[1] to LTH[m], thus reducing the circuit area compared to the drive circuit WXCD in Figure 6A. This leads to a reduction in the circuit area of ​​the arithmetic unit CDVA, and enables miniaturization of both the arithmetic unit CDVA and the electronic equipment including the arithmetic unit CDVA.

[0208] Furthermore, if the high-level potential and low-level potential handled by the drive circuit WXCD are the same as the high-level potential and low-level potential handled by the calculation circuit CC, then the level shifters LV[1] to LV[m] shown in Figures 6A and 6B of the drive circuit WXCD do not need to be provided.

[0209] The drive circuit WXCD shown in Figure 8A has a configuration that does not include level shifters LV[1] to LV[m] compared to the drive circuit WXCD shown in Figure 6A. Similarly, the drive circuit WXCD shown in Figure 8B has a configuration that does not include level shifters LV[1] to LV[m] compared to the drive circuit WXCD shown in Figure 6B. Specifically, in the drive circuit WXCD of Figure 8A, the second output terminal of selector SLC[i] and the output terminal of sequential circuit LTH[i] are directly connected to wiring WXL[i]. Also, in the drive circuit WXCD of Figure 8B, the output terminal of selector SLCA[i] is directly connected to wiring WXL[i].

[0210] The drive circuit WXCD in Figure 8A has a configuration that does not include level shifters LV[1] to LV[m] compared to the drive circuit WXCD in Figure 6A, and therefore its circuit area can be reduced compared to the drive circuit WXCD in Figure 6A. Similarly, the drive circuit WXCD in Figure 8B can have a smaller circuit area than the drive circuit WXCD in Figure 6B. This leads to a reduction in the circuit area of ​​the arithmetic unit CDVA, and enables miniaturization of the arithmetic unit CDVA and the electronic equipment including the arithmetic unit CDVA.

[0211] Furthermore, if the high-level potential and low-level potential handled by the drive circuit WXCD are the same as the high-level potential and low-level potential handled by the arithmetic circuit CC, then in Figures 6A and 6B, the level shifters LV[1] to LV[m] may be replaced with buffer circuits. For example, in the drive circuit WXCD shown in Figure 6A, each of the level shifters LV[1] to LV[m] can be replaced with buffer circuits BFL[1] to BFL[m], as shown in Figure 9A. Similarly, in the drive circuit WXCD shown in Figure 6B, each of the level shifters LV[1] to LV[m] can be replaced with buffer circuits BFL[1] to BFL[m], as shown in Figure 9B.

[0212] Next, as an example, the circuit configurations of the selector SLC, the sequential circuit LTS, and the sequential circuit LTH, which are included in the drive circuit WXCD shown in Figures 6A, 8A to 9B, will be explained.

[0213] Figure 10A is a circuit diagram showing the i-th row of the drive circuit WXCD in Figure 6A as an example. Selector SLC[i] includes, as an example, inverter IVE1, switch ST1, and switch ST2. Sequential circuit LTS[i] has a latch circuit configuration as an example, and includes switch SH1, switch SH2, switch SG1, switch SG2, inverter IVF1, inverter IVF2, inverter IVF3, and inverter IVE2. Sequential circuit LTH[i] has a latch circuit configuration as an example, similar to sequential circuit LTS[i]. Therefore, for sequential circuit LTH[i], refer to the explanation of sequential circuit LTS[i].

[0214] In selector SLC[i], the first terminal of switch ST1 and the first terminal of switch ST2 are connected to each other, and each of them corresponds to an input terminal of selector SLC[i]. The control terminal of switch ST1 is connected to wiring SLL, the control terminal of switch ST2 is connected to the output terminal of inverter IVE1, and the input terminal of inverter IVE1 is connected to wiring SLL. The second terminal of switch ST1 corresponds to the first output terminal of selector SLC[i], and the second terminal of switch ST2 corresponds to the second output terminal of selector SLC[i]. Furthermore, the control terminal of switch ST1 and the input terminal of inverter IVE1 correspond to the control terminals of selector SLC[i].

[0215] In the sequential circuit LTS[i], the first terminal of switch SH1 corresponds to the input terminal of the sequential circuit LTS[i]. The second terminal of switch SH1 is connected to the input terminal of inverter IVF1, and the output terminal of inverter IVF2 is connected to the first terminal of switch SG1. The second terminal of switch SG1 is connected to the input terminal of inverter IVF2 and the first terminal of switch SG2. The output terminal of inverter IVF2 is connected to the input terminal of inverter IVF3 and the first terminal of switch SH2. The output terminal of inverter IVF3 is connected to the second terminal of switch SG2. The second terminal of switch SH2 corresponds to the output terminal of the sequential circuit LTS[i]. The control terminal of switch SG2 is connected to the output terminal of inverter IVE2. The control terminal of switch SG1 and the control terminal of switch SH2 are connected to each other, and each of them corresponds to the enable terminal of the sequential circuit LTS[i]. Furthermore, the control terminal of switch SG1 and the input terminal of inverter circuit IVE2 are connected to each other, and each of them corresponds to the control terminal of sequential circuit LTS[i].

[0216] Each of the switches described above can be replaced with a switch applicable to either switch SAP or switch SAN. For example, electrical switches can be used for these switches, and OS transistors, Si transistors, etc., can be used as electrical switches. In particular, by using an IO transistor as the OS transistor, the off-current of the transistor can be reduced, thereby preventing malfunctions and failures of the arithmetic unit due to current leakage. In addition, since IO transistors have a large on-current, it is possible to improve the driving speed of the drive circuit WXCD provided in the arithmetic unit.

[0217] Furthermore, the inverter described above can be adapted to the circuit configuration shown in Figure 10B as an example. The inverter IV in Figure 10B includes, as an example, transistor M1, transistor M2, transistor M3, and capacitive element C1.

[0218] The first terminal of transistor M1 is connected to wiring VHE. The first terminal of transistor M3 and the gate of transistor M3 are connected to each other, and each of them is also connected to wiring VHE. The second terminal of transistor M1, the first terminal of capacitive element C1, and the first terminal of transistor M2 are connected to each other, and each of them corresponds to the output terminal of inverter IV. The gate of transistor M1, the second terminal of transistor M3, and the second terminal of capacitive element C1 are connected to each other. The gate of transistor M2 corresponds to the input terminal of inverter IV.

[0219] Transistors M1 to M3 can be OS transistors, Si transistors, etc., similar to the switches described above. In particular, OS transistors, such as IO transistors, have a high ratio of on-current to off-current, which can speed up the driving of logic circuits such as inverter IV, and thus improve the driving speed of the drive circuit WXCD.

[0220] Similarly, OS transistors can be used for the shift register SR and the level shifter LV[i]. Also, similarly, by using an IO transistor as the OS transistor, the drive speed of the drive circuit WXCD can be increased.

[0221] Furthermore, the drive circuit WXCD shown in Figure 6A, which relates to a semiconductor device according to one aspect of the present invention, can be modified to the configuration of the drive circuit WXCD shown in Figure 11. The drive circuit WXCD of Figure 11 has the same configuration as the drive circuit WXCD of Figure 6A, but with the sequential circuit LTS[i] changed to the sequential circuit LT[i] and the sequential circuit LTH[i] changed to the switch circuit SW[i].

[0222] Figure 11 shows an excerpt of the shift register SR, the selector SLC[1], sequence circuit LT[1], switch circuit SW[1], level shifter LV[1] and wiring WXL[1] located in the first row, the selector SLC[2], sequence circuit LT[2], switch circuit SW[2], level shifter LV[2] and wiring WXL[2] located in the second row, and the selector SLC[m], sequence circuit LT[m], switch circuit SW[m], level shifter LV[m] and wiring WXL[m] located in the mth row.

[0223] Unlike the sequential circuit LTS[i], the sequential circuit LT[i] does not have an enable terminal. Therefore, the drive circuit WXCD does not have wiring EN1 extending to it for transmitting an enable signal or a disable signal.

[0224] The switch circuit SW[i] has a first terminal, a second terminal, and a control terminal, and has the function of switching between a conductive state and a non-conductive state between the first terminal and the second terminal according to the signal input to the control terminal. The switch circuit SW[i] can also be equipped with a switch, a three-state buffer circuit, etc. Furthermore, since the switch circuit SW[i] does not have a control terminal corresponding to the sequential circuit LTH[i], the drive circuit WXCD does not have wiring LL extending to transmit control signals.

[0225] The control terminal of the sequential circuit LT[i] is connected to the first output terminal of the selector SLC[i], the input terminal of the sequential circuit LT[i] is connected to wiring IXL, and the output terminal of the sequential circuit LT[i] is connected to the first terminal of the switch circuit SW[i]. In addition, the second terminal of the switch circuit SW[i] is connected to the second output terminal of the selector SLC[i] and to the input terminal of the level shifter LV[i].

[0226] Each of the switch circuits SW[1] to SW[m] has an enable terminal. Note that the enable terminal may be referred to as a control terminal depending on the situation. Each of the switch circuits SW[1] to SW[m] can be switched between the ON state and the OFF state collectively by connecting wiring EN2 to their respective enable terminals. In other words, when the switch circuit SW[i] is ON, it has the function of transmitting the second data x[i] held by the sequential circuit LT[i] from the second terminal to the input terminal of the level shifter LV[i], and when the switch circuit SW[i] is OFF, it has the function of making the second terminal of the switch circuit SW[i] high impedance.

[0227] The switch circuits SW[1] to SW[m] of the drive circuit WXCD in Figure 11, like the sequential circuits LTH[1] to LTH[m] of the drive circuit WXCD in Figure 6A, can transmit the second data all at once, as described above, and can also set the second terminal to high impedance all at once. Furthermore, unlike the sequential circuit LTH[i] in Figure 6A, the switch circuit SW[i] in Figure 11 does not have a data retention function, so the circuit area of ​​the switch circuit SW[i] can be reduced compared to the sequential circuit LTH[i]. In addition, since the drive circuit WXCD does not have wiring EN1 and wiring LL, the circuit area of ​​the drive circuit WXCD can be reduced as a result, including this point.

[0228] Figures 12A and 12B show the circuit configuration of the drive circuit WXCD, which includes a sequential circuit LT[i] and a switch circuit SW[i]. Figures 12A and 12B also show specific examples of the circuit configurations of the sequential circuit LT[i] and the switch circuit SW[i]. Furthermore, for the shift register SR, selector SLC[i], and level shifter LV[i] shown in Figures 12A and 12B, refer to the explanation in Figure 10A.

[0229] In Figures 12A and 12B, the sequential circuit LT[i] is configured in such a way that switches SH1 and SH2 are not included in the sequential circuit LTS[i] of Figure 10A. In the sequential circuit LT[i], the input terminal of inverter IVF1 is connected to wiring IXL as an input terminal of the sequential circuit LT[i], and the output terminal of inverter IVF2 and the input terminal of inverter IVF3 are connected to the first terminal of switch circuit SW[i] as output terminals of the sequential circuit LT[i].

[0230] In the drive circuit WXCD shown in Figure 12A, as an example, the switch circuit SW[i] is configured to include a buffer circuit BFE, and the buffer circuit BFE is a three-state buffer circuit. In the buffer circuit BFE, the input terminal can be the first terminal of the switch circuit SW[i], and the output terminal can be the second terminal of the switch circuit SW[i]. In addition, the enable terminal of the buffer circuit BFE can be the enable terminal of the switch circuit SW[i].

[0231] The three-state buffer circuit BFE, when an enable signal is input to its enable terminal, functions similarly to the buffer circuit BF, outputting a signal with the same logic as the signal input to its input terminal to its output terminal as a type of logic gate. Furthermore, when a disable signal is input to its enable terminal, the buffer circuit BFE has the function of making the output terminal high impedance.

[0232] The switch circuit SW[i] in the drive circuit WXCD shown in Figure 12A, which includes the buffer circuit BFE, has fewer circuit elements than the sequential circuit LTH[i] in the drive circuit WXCD shown in Figure 6A. Therefore, the drive circuit WXCD in Figure 12A can have a smaller circuit area than the drive circuit WXCD in Figure 6A. In addition, the switch circuit SW[i] in Figure 12A, which includes the buffer circuit BFE, has the function of amplifying the input signal and the function of making the output high impedance, similar to the sequential circuit LTH[i] in Figure 6A. Therefore, if it is desirable to reduce the circuit area of ​​the arithmetic unit CDV or arithmetic unit CDVA, it is preferable to use the drive circuit WXCD in Figure 12A.

[0233] In the drive circuit WXCD shown in Figure 12B, as an example, the switch circuit SW[i] includes a switch SF, and the switch SF can be a switch applicable to the above-mentioned switch SAP or switch SAN. The first terminal of switch SF is the first terminal of switch circuit SW[i], the second terminal of switch SF is the second terminal of switch circuit SW[i], and the control terminal of switch SF can be the enable terminal of switch circuit SW[i].

[0234] The switch circuit SW[i] in the drive circuit WXCD shown in Figure 12B, which includes switch SF, can have fewer circuit elements than the switch circuit SW[i] in the drive circuit WXCD shown in Figure 12A. Therefore, the drive circuit WXCD in Figure 12B can have a smaller circuit area than the drive circuit WXCD in Figure 12A. Note that, unlike the switch circuit SW[i] in Figure 12A, the switch circuit SW[i] in Figure 12B does not have the function of amplifying the input signal, so it is preferable that a level shifter LV[i] is connected to the second terminal of the switch circuit SW[i] as shown in Figure 12B. Alternatively, it is preferable that a buffer circuit is connected instead of the level shifter LV[i] (not shown).

[0235] It should be noted that the drive circuit that can be provided in a semiconductor device according to one aspect of the present invention is not limited to the circuit configuration of the drive circuit WXCD shown in Figure 11. For example, the drive circuit that can be provided in a semiconductor device according to one aspect of the present invention may have a configuration in which the drive circuit WXCD is not provided with a level shifter LV, similar to Figures 8A and 8B (not shown). Alternatively, the drive circuit may have a configuration in which a buffer circuit BFL is provided instead of a level shifter LV, similar to Figures 9A and 9B (not shown).

[0236] [Drive Circuit ITS] Figure 13A is a circuit diagram showing an example of the drive circuit ITS shown in Figures 1 and 4. In particular, Figure 13A also shows an example of the circuit configuration of circuit ITSa. In addition, the addresses assigned to the symbols shown in Figure 4 are omitted in Figure 13A.

[0237] As shown in Figure 13A, circuit ITSa includes, for example, a differential amplifier circuit OPp, a differential amplifier circuit OPn, a load LDp, a load LDn, and a circuit ACF. For loads LDp and LDn, resistors, diodes, transistors, etc., can be used as examples.

[0238] The ACF circuit has a first input terminal, a second input terminal, and an output terminal. The ACF circuit has the function of outputting a potential signal to the output terminal that corresponds to the potential difference between the potential input to the first input terminal and the potential input to the second input terminal. In other words, the ACF circuit can be described as a circuit that converts the result of calculations performed by the arithmetic circuit CC into a signal and outputs it to the wiring OL. Note that the ACF circuit can also utilize comparators, analog-to-digital conversion circuits, etc.

[0239] In particular, when the arithmetic units CDV and CDVA perform calculations for an artificial neural network, the circuit ACF can be a circuit that performs calculations for activation functions. That is, the circuit ACF can perform calculations on a function to which the results of the sum-of-accumulate operations transmitted from the wirings WCLp and WCLn have been substituted as variables, and output the result of the calculation of that function to the wiring OL. For example, the activation function can be a sigmoid function, a tanh function, a softmax function, a ReLU function, or a threshold function.

[0240] The second terminal of switch SBp is connected to the inverting input terminal of differential amplifier circuit OPp and to the first terminal of load LDp. The output terminal of differential amplifier circuit OPp is connected to the second terminal of load LDp and to the first input terminal of circuit ACF. The non-inverting input terminal of differential amplifier circuit OPp is connected to wiring VSE. The second terminal of switch SBn is connected to the inverting input terminal of differential amplifier circuit OPn and to the first terminal of load LDn. The output terminal of differential amplifier circuit OPn is connected to the second terminal of load LDn and to the second input terminal of circuit ACF. The non-inverting input terminal of differential amplifier circuit OPn is connected to wiring VSE.

[0241] In circuit ITSa, the differential amplifier circuit OPp has a negative feedback configuration in which its inverting input terminal is connected to the output terminal via the load LDp. Therefore, the potential of the inverting input terminal of the differential amplifier circuit OPp is approximately equal to the potential of the non-inverting input terminal of the differential amplifier circuit OPp due to a virtual short circuit. Similarly, the differential amplifier circuit OPn has a negative feedback configuration in which its inverting input terminal is connected to the output terminal via the load LDn. Therefore, the potential of the inverting input terminal of the differential amplifier circuit OPn is approximately equal to the potential of the non-inverting input terminal of the differential amplifier circuit OPn due to a virtual short circuit.

[0242] Wiring VSE functions, for example, as wiring that provides a fixed potential. This fixed potential is the potential V described above. Ｓ This can be done. Also, in both the differential amplifier circuit OPp and the differential amplifier circuit OPn, the inverting input terminal and the non-inverting input terminal are virtually short-circuited to each other, so the potential of the inverting input terminals of both the differential amplifier circuit OPp and the differential amplifier circuit OPn is potential V Ｓ Therefore, by turning on switches SBp and SBn, a potential V is introduced into the wiring WCLp and WCLn, respectively. Ｓ It can give.

[0243] Furthermore, OS transistors can be used in the differential amplifier circuits OPp, OPn, and ACF, similar to the drive circuit WXCD. In particular, by using I / O transistors as OS transistors, the drive speed of these circuits can be increased.

[0244] The configuration of the drive circuit ITS in one aspect of the present invention is not limited to the circuit configuration shown in Figure 13A. For example, the drive circuit ITS in the semiconductor device can be configured such that the circuit ITSa includes an analog-to-digital converter (ADC) circuit.

[0245] Figure 13B shows an example of the circuit configuration of circuit ITSa equipped with an ADC circuit. The circuit ITSa shown in Figure 13B is a successive approximation register (SAR) type ADC circuit and includes a current mirror circuit CMRp, a current mirror circuit CMRn, a current comparator CPR, a digital-to-analog conversion (DAC) circuit DTAp, a DAC circuit DTAn, and a logic circuit LGC. In particular, the current mirror circuits CMRp and CMRn can be current-drawing type current mirror circuits, and the DAC circuits DTAp and DTAn can be current-discharge type current ladder DAC circuits.

[0246] Figure 13B also shows the connection configuration around circuit ITSa, including switches SBp and SBn, and wiring WCLp and WCLn.

[0247] The second terminal of switch SBp is connected to the input terminal of current mirror circuit CMRp and the output terminal of DAC circuit DTAp. The second terminal of switch SBn is connected to the input terminal of current mirror circuit CMRn and the output terminal of DAC circuit DTAn. The output terminal of current mirror circuit CMRp is connected to the first input terminal of current comparator CPR, and the output terminal of current mirror circuit CMRn is connected to the second input terminal of current comparator CPR. The output terminal of current comparator CPR is connected to the input terminal of logic circuit LGC. The terminal LFTp of logic circuit LGC is connected to the input terminal of DAC circuit DTAp, and the terminal LFTn of logic circuit LGC is connected to the input terminal of DAC circuit DTAn. The output terminal of logic circuit LGC is connected to wiring OL.

[0248] The circuit ITSa shown in Figure 13B converts the difference between the amount of current flowing through wiring WCLp and the amount of current flowing through wiring WCLn into a digital signal, and outputs this digital signal to wiring OL.

[0249] Specifically, for example, if we want to calculate the difference between Iop and Ion, where Ion is the current flowing through wiring WCLp and Ion is the current flowing through wiring WCLn, we first operate the DAC circuit DTAp and stop the DAC circuit DTAN. Also, if we let Icp be the current flowing from the output terminal of the current mirror circuit CMRp and Icn be the current flowing from the output terminal of the current mirror circuit CMRn, then in the initial state, Icp = Iop and Icn = Ion hold true. Here, the current comparator CPR compares the magnitudes of Icp and Icn and transmits the comparison result to the logic circuit LGC. The logic circuit LGC transmits a signal corresponding to the comparison result from terminal LFTp to the DAC circuit DTAP, generates a current of amount Ifp based on this signal, and supplies the current of amount Ifp to the current of amount Iop from the output terminal of the DAC circuit DTAN. At this point, Icp = Iop + Ifp and Icn = Ion. The current comparator CPR compares the magnitudes of Icp and Icn again and transmits the comparison result to the logic circuit LGC. This process is repeated to sequentially change Ifp until Icp = Icn. When the DAC circuit DTAp generates a current of the amount Ifp such that Icp = Icn using the digital signal output from terminal LFTp of the logic circuit LGC, the value of this digital signal corresponds to the difference between Iop and Ion as a reference. Thus, the logic circuit LGC can generate a digital signal corresponding to the difference between Iop and Ion as a reference. This digital signal is then output to wiring OL by the logic circuit LGC.

[0250] The drive circuit ITS shown in Figures 13A and 13B can convert the results of the sum-of-accumulate operation in the cell array CA into a digital signal and output it to the outside of the arithmetic unit CDV.

[0251] <<Example of Operation of the Arithmetic Unit 2>> Next, an example of operation of the arithmetic unit CDVA shown in Figure 4 will be explained. The arithmetic unit CDVA used in the explanation of the operation example is configured to include the drive circuit WCD shown in Figure 5A, the drive circuit WXCD shown in Figure 6A, and the drive circuit ITS shown in Figure 13B.

[0252] Figure 14 is a timing chart showing an example of the writing operation of the first data w to each of the multiple arithmetic circuits CC in the j-th column of the cell array CA in the arithmetic unit CDVA (operation during period TW), and an example of the multiplication operation of the first data w and the second data x performed by each of the multiple arithmetic circuits CC in the j-th column of the cell array CA (operation during period TR). Specifically, the timing chart shows the potential changes of wiring SWLA, wiring SWLB, wiring WXL[1], wiring WXL[2], wiring WXL[m], wiring WSL[1], wiring WSL[2], wiring WSL[m], wiring XSL[1], wiring XSL[2], wiring XSL[m], wiring WCLp[j], and wiring WCLn[j] during periods TW and TR.

[0253] Note that in the timing chart of Figure 14, the potential V Ｓ This is a low-level potential V Ｌ Higher than, high-level potential V Ｈ Although it is set to a lower potential than, low-level potential V Ｌ Lower potential or higher level potential V Ｈ It may also be a higher potential.

[0254] Furthermore, the thick dotted lines shown in the wiring WCLp[j] and WCLn[j] for period TW indicate that no potential is specifically defined. Therefore, the potential indicated by the thick dotted line may be a high-level potential, a low-level potential, or any other potential. Also, the thick solid line shown in the wiring WCLp[j] for period TW indicates that the first data to be written to the corresponding calculation cell IMp is w=1, and the thick dashed line shown in the wiring WCLp[j] for period TW indicates that the first data to be written to the corresponding calculation cell IMp is w=0.

[0255] Furthermore, the thick solid lines shown in the wiring WXL[1] to WXL[m] of period TR included in period TR indicate that the second data transmitted to the corresponding calculation cell IMp is x = 1, and the thick dashed lines shown in the wiring WXL[1] to WXL[m] of period TR indicate that the second data transmitted to the corresponding calculation cell IMn is x = 0.

[0256] During the period TW, when writing the first data w to each of the multiple arithmetic circuits CC in the j-th column of the cell array CA, a high-level potential is first applied to the wiring SWLA to turn on switches SAP[j] and SAN[j]. While switches SAP[j] and SAN[j] are turned on, the drive circuit WXCD sequentially applies high-level potentials to each of the wirings WXL[1] through WXL[m], and the drive circuit WSD sequentially applies high-level potentials to each of the wirings WSL[1] through WSL[m].

[0257] Furthermore, the rows of wiring WXL[1] to WXL[m] to which a high-level potential is applied will coincide with the rows of wiring WSL[1] to WSL[m] to which a high-level potential is applied. For example, when wiring WXL[1] is given a high-level potential, wiring WSL[1] will also be given a high-level potential, and when wiring WXL[i] is given a high-level potential, wiring WSL[i] will also be given a high-level potential. In other words, the timing of sequentially applying a high-level potential to each of wiring WXL[1] to WXL[m] will coincide with the timing of sequentially applying a high-level potential to each of wiring WSL[1] to WSL[m].

[0258] Furthermore, when a high-level potential is applied to wiring WXL[1] and wiring WSL[1], transistors M1p and M2p of calculation cell IMp[1,j] and transistors M1n and M2n of calculation cell IMn[1,j] are turned ON. At this time, the first data w[1,j] transmitted to wiring IWL[j] is written to calculation cell IMp[1,j] and calculation cell IMn[1,j], respectively.

[0259] Specifically, the first data w[1,j] transmitted to the wiring IWL[j] is used as wp[1,j] ("0" or "1") and wn[1,j] ("0"), similar to the operation example 1 of the arithmetic unit. The drive circuit WCD applies a potential to the wiring WCLp[j] corresponding to the value of wp[1,j], and a low-level potential V corresponding to wn[1,j] = 0 is applied.Ｌ By supplying this to the wiring WCLn[j], the resistance value of the resistance-changing element MRp changes in the calculation cell IMp[1,j] according to wp[1,j], and the resistance value of the resistance-changing element MRn changes in the calculation cell IMn[1,j] according to wn[1,j]=0.

[0260] After a high-level potential is applied to wiring WXL[1] and wiring WSL[1], a high-level potential is applied to the next row of wiring WXL[2] and wiring WSL[2]. At this time, the first data w[2,j] transmitted to wiring IWL[j] is written to calculation cells IMp[2,j] and IMn[2,j], respectively. After the first data w[2,j] is written to the calculation cells IMp[2,j] and IMn[2,j] of the second row, the first data w is written sequentially to the calculation cells IMp and IMn from the third row to the mth row.

[0261] During period TW, as described above, when a high-level potential is sequentially applied to wiring WXL[1] through WXL[m], the first data w transmitted to wiring IWL[j] is written to the calculation cells IMp and IMn of that row.

[0262] During period TR, when multiplication is performed in each of the multiple arithmetic circuits CC in the j-th column of the cell array CA, a high-level potential is first applied to the wiring SWLB to turn on switches SBp[j] and SBn[j]. As a result, a potential V is transmitted from circuit ITSa to wiring WCLp[j] and WCLn[j]. Ｓ It is given.

[0263] Furthermore, while switches SBp[j] and SBn[j] are in the ON state, the drive circuit WXCD applies a potential corresponding to the second data x[1] to x[m] to each of the wirings WXL[1] to WXL[m] collectively, and the drive circuit XSD applies a high-level potential to each of the wirings XSL[1] to XSL[m] collectively.

[0264] During the period TRa, it is assumed that the second data x applied to the wirings WXL[1] to WXL[m], and the high-level potential applied to the wirings XSL[1] to XSL[m], are given simultaneously. That is, the timing for simultaneously applying the second data to each of the wirings WXL[1] to WXL[m] and the timing for simultaneously applying the high-level potential to each of the wirings XSL[1] to XSL[m] are assumed to coincide with each other.

[0265] When a high-level potential is applied to the wirings XSL[1] to XSL[m], the transistors M3p of each of the arithmetic cells Imp[i, j] to Imp[m, j] and the transistors M3n of each of the arithmetic cells Imn[1, j] to Imn[m, j] are turned on.

[0266] Also, when a potential (high-level potential) corresponding to x = 1 is applied as the second data among the wirings WXL[1] to WXL[m], the transistors M3p of the arithmetic cells Imp and the transistors M3n of the arithmetic cells Imn in the corresponding row are each turned on. As a result, a voltage of V Ｒ −V Ｓ is applied between the first terminal and the third terminal of the resistive change element MRp, and a tunnel current corresponding to the amount of wp written in the resistive change element MRp flows between the first terminal and the third terminal. Similarly, a tunnel current corresponding to the amount of wn written in the resistive change element MRn also flows between the first terminal and the third terminal of the resistive change element MRn.

[0267] Also, when a potential (low-level potential) corresponding to x = 0 is applied as the second data among the wirings WXL[1] to WXL[m], the transistors M3p of the arithmetic cells Imp and the transistors M3n of the arithmetic cells Imn in the corresponding row are each turned off. As a result, the potential V Ｓ is not applied to the first terminal of the resistive change element MRp, and no current flows from the arithmetic cell Imp to the wiring WCLp. Similarly, the potential V Ｓ is not applied to the first terminal of the resistive change element MRn, and no current flows from the arithmetic cell Imn to the wiring WCLn.

[0268] Here, let Ip[i,j] be the amount of current flowing from the calculation cell IMp[i,j] to the wiring WCLp, and let In[i,j] be the amount of current flowing from the calculation cell IMn[i,j] to the wiring WCLn. Note that Ip[i,j] and In[i,j] are as shown in the table in Operation Example 1 of the calculation unit. Ｂ , I Ｓ Let it be either 0 or 0. In this case, the amount of current Isp[j] flowing from wiring WCLp[j] to the first input terminal of circuit ITSa, the amount of current Isn[j] flowing from wiring WCLn[j] to the second input terminal of circuit ITSa, and the difference current between Isp[j] and Isn[j] can be expressed as shown in the following equations (1.1) to (1.3).

[0269]

[0270] K is the number of arithmetic circuits CC[1,j] to CC[1,j] where the first data is w=1 and the second data is x=1. Therefore, K is an integer between 0 and m, and is also the result of a sum-of-products operation. As a result, during period TR, circuit ITSa calculates the difference current between Isp[j] and Isn[j], which is proportional to K, the result of the sum-of-products operation, and a signal corresponding to K is transmitted from the output terminal of circuit ITSa to wiring OL.

[0271] As described above, by configuring the arithmetic unit CDVA shown in Figure 4, it is possible to perform sum-of-products operations on multiple first data points w and multiple second data points. Furthermore, by making the circuit ITSa a circuit that performs function calculations, it is possible to perform calculations on functions in which the results of the sum-of-products operations are substituted as variables.

[0272] <<Example of modification of the drive circuit 1>> Referring to the timing chart in Figure 14 explained in the above example of operation of the calculation device 2, during period TW, when a high-level potential is applied to wiring WXL[i], a high-level potential is also applied to wiring WSL[i]. In other words, during period TW, the signals applied to wiring WXL[i] and wiring WSL[i] can be shared with each other.

[0273] The arithmetic unit CDVB shown in Figure 15 has a configuration in which the drive circuits WSD and WXCD of the arithmetic unit CDVA in Figure 4 are combined into a single drive circuit WXS1. The drive circuit WXS1 has the function of sharing and outputting the signals to wiring WXL[i] and wiring WSL[i] during the period TW of the timing chart in Figure 14. For this reason, in the arithmetic unit CDVB, the drive circuit WXS1 is connected to wiring WXL[1] to wiring WXL[m] and wiring WSL[1] to wiring WSL[m].

[0274] An example of the circuit configuration of the drive circuit WXS1 is shown in Figure 16. The drive circuit WXS1 in Figure 16 is a modified version of the drive circuit WXCD in Figure 6A, and is configured by adding switches SCa[1] to SCa[m], switches SCb[1] to SCb[m], and level shifters LW[1] to LW[m] to the drive circuit WXCD. In addition, wiring SLLb and wiring VSE extend to the drive circuit WXS1.

[0275] Switch SCa and switch SCb can each be a switch applicable to switch SAP or switch SAN. Furthermore, for level shifters LW[1] to LW[m], refer to the description of level shifters LV[1] to LV[m] in Figure 6A.

[0276] Let's focus on row i of the drive circuit WXS1. The first terminal of switch SCa[i] is connected to the first output terminal of selector SLC[1], the output terminal of sequential circuit LTH[i], and the input terminal of level shifter LV[i]. The second terminal of switch SCa[i] is connected to the first terminal of switch SCb[i] and the input terminal of level shifter LW[i], and the second terminal of switch SCb[i] is connected to wiring VSE. The output terminal of level shifter LW[i] is connected to wiring WSL[i]. The control terminal of switch SCa[i] is connected to wiring SLLb, and the control terminal of switch SCb[i] is connected to wiring SLL.

[0277] The wiring VSE functions, for example, as wiring that provides a fixed potential. In particular, this fixed potential can be a non-selection signal for calculation cells IMp and IMn, which are not the destinations for writing the first data. For example, in the case of the calculation circuit CC shown in Figure 1, the fixed potential can be a low-level potential.

[0278] In the drive circuit WXS1, the wiring SLL functions not only as a wiring for transmitting a control signal to the control terminal of selector SLC[i], but also as a wiring for transmitting a control signal to the control terminal of switch SCb. Furthermore, wiring SLLb functions as a wiring for transmitting a control signal to the control terminal of switch SCa. In particular, the control signal can be a signal inverted in logic from the signal input to wiring SLL. Therefore, wiring SLL and wiring SLLb may be connected to each other via an inverter, which is a logic gate that inverts the logic (not shown).

[0279] Next, an example of the operation of the drive circuit WXS1 will be described. For an example of the operation of the drive circuit WXS1 when sequentially writing the first data to each of the multiple arithmetic circuits CC of the arithmetic unit CDVB, please refer to the timing chart in Figure 7A. Note that since a low level potential is always applied to wiring SLL, it is assumed that a high level potential is always applied to wiring SLLb.

[0280] In Figure 7A, during periods T11 to T13, a high-level potential is applied to the control terminal of switch SCa[i], causing switch SCa[i] to be in the ON state. Conversely, a low-level potential is applied to the control terminal of switch SCb[i], causing switch SCb[i] to be in the OFF state. This allows the signal output from the second output terminal of selector SLC[i] to be supplied not only to wiring WXL[i] but also to wiring WSL[i] via level shifter LW[i]. Therefore, in the calculation circuit CC of Figure 1, transistors M1p and M2p, and transistors M1n and M2n can be simultaneously turned ON or OFF.

[0281] Furthermore, for an example of the operation of the drive circuit WXS1 when multiple arithmetic circuits CC of the arithmetic unit CDVB perform multiplication of the first data and the second data, refer to the timing chart in Figure 7B. Note that from period T14 onward, a high-level potential is applied to wiring SLL, and a low-level potential is applied to wiring SLLb.

[0282] In Figure 7B, during periods T14 to T16, a high-level potential is applied to the control terminal of switch SCa[i], causing switch SCa[i] to be in the off state. Conversely, a high-level potential is applied to the control terminal of switch SCb[i], causing switch SCb[i] to be in the on state. As a result, a signal corresponding to the second data output from the output terminal of the sequential circuit LTH[i] is applied to wiring WXL[i] via level shifter LV[i]. Therefore, in the arithmetic circuit CC of Figure 1, signals corresponding to the second data can be applied to the gates of transistors M1p and M1n. Furthermore, a fixed potential (here, a low-level potential) from wiring VSE is applied to wiring WSL[i] via level shifter LW[i]. Therefore, this fixed potential can be applied to the gates of transistors M2p and M2n, turning transistors M2p and M2n in the off state.

[0283] As shown in the arithmetic unit CDVB in Figure 15, by using the drive circuit WXS1, the signals supplied to wiring WXL[i] and wiring WSL[i] can be shared when writing the first data to the arithmetic unit CC. Furthermore, since the drive circuit WXS1 of the arithmetic unit CDVB combines the functions of the drive circuits WXCD and WSD in the arithmetic unit CDVA in Figure 4, the circuit area of ​​the arithmetic unit CDVB can be made smaller than that of the arithmetic unit CDVA.

[0284] <<Example of modification of the drive circuit 2>> Referring to the timing chart in Figure 14 explained in the above example of operation of the arithmetic unit, during period TR, when a signal corresponding to the second data (high-level potential or low-level potential) is applied to the wiring WXL[i], a high-level potential is applied to the wiring XSL[i]. However, when the value of the second data x is 0, in the arithmetic circuit CC in Figure 1, even if a high-level potential is applied from the wiring XSL to the gates of transistors M3p and M3n, no current flows from the arithmetic cell IMp to the wiring WCLp, nor does any current flow from the arithmetic cell IMn to the wiring WCLn. In other words, when the value of the second data x is 0, the potential applied from the wiring XSL to the gates of transistors M3p and M3n may be a low-level potential.

[0285] On the other hand, when the value of the second data x is "1", a high-level potential needs to be applied to the gates of transistors M3p and M3n from the wiring XSL in the calculation circuit CC in Figure 1.

[0286] One aspect of the present invention, a semiconductor device, has been made in view of the above, and has the function of generating a signal to be transmitted to wiring XSL using a signal supplied to wiring WXL.

[0287] The arithmetic unit CDVC shown in Figure 17 has a configuration in which the drive circuits WSD, XSD, and WXCD from the arithmetic unit CDVA in Figure 4 are combined into a single drive circuit WXS2. Furthermore, the drive circuit WXS2 can be described as a configuration in which the drive circuits WXS1 and XSD from the arithmetic unit CDVB in Figure 15 are combined. Therefore, for some aspects of the drive circuit WXS2, the explanation of the drive circuit WXS1 can be referenced.

[0288] The drive circuit WXS2 has the function of sharing and outputting signals to wiring WXL[i] and wiring WSL[i] during the period TW of the timing chart in Figure 14, and the function of generating and outputting a signal to wiring XSL[i] using the signal transmitted to wiring WXL[i] during the period TR of the timing chart in Figure 14. For this reason, in the arithmetic unit CDVC, the drive circuit WXS2 is connected to wiring WXL[1] to wiring WXL[m], wiring WSL[1] to wiring WSL[m], and wiring XSL[1] to wiring XSL[m].

[0289] An example of the circuit configuration of the drive circuit WXS2 is shown in Figure 18. The drive circuit WXS2 in Figure 18 is a modified version of the drive circuit WXS1 in Figure 16, and is configured by adding switches SCc[1] to SCc[m], switches SCd[1] to SCd[m], and level shifters LX[1] to LX[m] to the drive circuit WXS1.

[0290] Switch SCc and switch SCd can each be switches applicable to switch SAP or switch SAN. Furthermore, for each of the level shifters LX[1] to LX[m], refer to the description of level shifters LV[1] to LV[m] in Figure 6A.

[0291] Let's focus on row i of the drive circuit WXS2. The first terminal of switch SCc[i] is connected to the first terminal of switch SCa[i], the first output terminal of selector SLC[i], the output terminal of sequential circuit LTH[i], and the input terminal of level shifter LV[i]. The second terminal of switch SCc[i] is connected to the first terminal of switch SCd[i] and the input terminal of level shifter LX[i], and the second terminal of switch SCd[i] is connected to wiring VSE. The output terminal of level shifter LX[i] is connected to wiring XSL[i]. The control terminal of switch SCc[i] is connected to wiring SLL, and the control terminal of switch SCd[i] is connected to wiring SLLb.

[0292] In the drive circuit WXS2, the wiring SLL functions not only as a wire for transmitting control signals to the control terminals of selector SLC[i] and switch SCa[i], but also as a wire for transmitting control signals to the control terminal of switch SCc[i]. Furthermore, the wiring SLLb functions not only as a wire for transmitting control signals to the control terminal of switch SCa[i], but also as a wire for transmitting control signals to the control terminal of switch SCd[i].

[0293] Next, an example of the operation of the drive circuit WXS2 will be described. For an example of the operation of the drive circuit WXS2 when sequentially writing the first data to each of the multiple arithmetic circuits CC of the arithmetic unit CDVC, please refer to the timing chart in Figure 7A. Note that a low level potential is always applied to wiring SLL, and a high level potential is always applied to wiring SLLb.

[0294] In Figure 7A, during periods T11 to T13, a high-level potential is applied to the control terminals of switches SCa[i] and SCd[i], causing them to be ON. Conversely, a low-level potential is applied to the control terminals of switches SCb[i] and SCc[i], causing them to be OFF. As a result, the signal output from the second output terminal of selector SLC[i] is supplied not only to wiring WXL[i] but also to wiring WSL[i] via level shifter LW[i]. Therefore, in the calculation circuit CC of Figure 1, transistors M1p and M2p, and transistors M1n and M2n can be simultaneously turned ON or OFF. Furthermore, a fixed potential (here referred to as a low-level potential) is supplied from wiring VSE to wiring XSL[i] via level shifter LX[i]. Therefore, in the calculation circuit CC of Figure 1, transistors M3p and M3n can be turned off simultaneously.

[0295] Furthermore, for an example of the operation of the drive circuit WXS2 when multiple arithmetic circuits CC of the arithmetic unit CDVC perform multiplication of the first data and the second data, refer to the timing chart in Figure 7B. Note that from period T14 onward, a high-level potential is applied to wiring SLL, and a low-level potential is applied to wiring SLLb.

[0296] In Figure 7B, during periods T14 to T16, a low-level potential is applied to the control terminals of switches SCa[i] and SCd[i], causing them to be in the off state. Conversely, a high-level potential is applied to the control terminals of switches SCb[i] and SCc[i], causing them to be in the on state. As a result, a signal corresponding to the second data output from the output terminal of the sequential circuit LTH[i] is applied not only to the wiring WXL[i] but also to the wiring XSL[i] via the level shifter LX[i]. Therefore, in the arithmetic circuit CC of Figure 1, a signal corresponding to the second data can be applied to the gates of transistors M1p, M1n, M3p, and M3n. In other words, transistors M1p, M1n, M3p, and M3n can each be simultaneously turned on or off according to the signal. Furthermore, a fixed potential (referred to here as a low-level potential) from wiring VSE can be applied to wiring WSL[i] via level shifter LW[i]. This fixed potential can also be applied to the gates of transistors M2p and M2n, thereby turning off transistors M2p and M2n.

[0297] For example, when the second data x is "0", transistors M1p and M1n, and transistors M3p and M3n are in the off state, so in the calculation circuit CC in Figure 1, no current flows from the calculation circuit CC to the wiring WCLp, and no current flows from the calculation circuit CC to the wiring WCLn. Also, when the second data is "-1" or "1", transistors M1p and M1n, and transistors M3p and M3n are in the on state, so current flows from the calculation circuit CC to the wiring WCLp, and from the calculation circuit CC to the wiring WCLn, according to the result of multiplying the first data and the second data.

[0298] As described above, the arithmetic unit CDVC in Figure 17, which is equipped with a drive circuit WXS2 that combines the drive circuits WXCD, WSD, and XSD shown in Figure 4, can also perform sum-of-products operations on the first data and the second data, similar to the operation example of the arithmetic unit CDVA in Figure 4.

[0299] As shown in Figure 17 of the arithmetic unit CDVC, by using the drive circuit WXS2, the signals supplied to wiring WXL[i] and wiring WSL[i] can be shared when writing the first data to the arithmetic unit CC. Furthermore, when multiplying the first data and the second data in the arithmetic unit CC, the signal transmitted to wiring WXL[i] can be used to generate the signal transmitted to wiring XSL[i]. In addition, since the drive circuit WXS2 of the arithmetic unit CDVC combines the functions of the drive circuit WXS1 and drive circuit XSD in the arithmetic unit CDVB shown in Figure 15, the circuit area of ​​the arithmetic unit CDVC can be made smaller than that of the arithmetic unit CDVB.

[0300] This embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, and methods shown in this embodiment can be appropriately combined with other configurations, structures, and methods shown in this embodiment. Also, for example, the configurations, structures, and methods shown in this embodiment can be appropriately combined with configurations, structures, and methods shown in other embodiments.

[0301] (Embodiment 2) This embodiment describes an example of a modification of the semiconductor device described in Embodiment 1.

[0302] <Example of arithmetic unit configuration 1> Figure 19 is a circuit diagram showing a modified example of the arithmetic unit in Figure 1 of Embodiment 1. The arithmetic unit CDV2 shown in Figure 19 has the function of multiplying a first data w which is a trivalent value of "-1", "0", or "1", and a second data x which is a trivalent value of "-1", "0", or "1".

[0303] Furthermore, the first data w in this embodiment is expressed using two variables, wp and wn. For example, when w = 0, wp = 0 and wn = 0 are defined, and when w = 1, wp = 1 and wn = 0 are defined. Also, when w = -1, wp = 0 and wn = 1 are defined. Similarly, the second data x in this embodiment is expressed using two variables, xp and xn. For example, when x = 0, xp = 0 and xn = 0 are defined, and when x = 1, xp = 1 and xn = 0 are defined. Also, when x = -1, xp = 0 and xn = 1 are defined. Therefore, w can be written as wp - wn, and x can also be written as xp - xn.

[0304] As mentioned above, since the arithmetic unit CDV2 is a modified version of the arithmetic unit CDV in Figure 1, the contents of the arithmetic unit CDV2 that are common to the arithmetic unit CDV may be omitted from the explanation.

[0305] Unlike the CDV, the CDV2 arithmetic unit has a new configuration in which transistor M4p is added to the arithmetic cell IMp and transistor M4n is added to the arithmetic cell IMn. In addition, the CDV2 arithmetic unit has wiring WXLp and WXLn extending from it, corresponding to wiring WXL in the CDV. Wiring WXLp is connected to the gates of transistors M1p and M1n, respectively, and wiring WXLn is connected to the gates of transistors M4p and M4n, respectively.

[0306] Furthermore, transistors applicable to transistors M1p to M3p or transistors M1n to M3n can be used for each of transistors M4p and M4n. Therefore, when describing transistors M4p and M4n, refer to the descriptions of transistors M1p to M3p and transistors M1n to M3n, respectively.

[0307] Furthermore, the configuration of the drive circuit WCD of the arithmetic unit CDV2 differs from the configuration of the drive circuit WCD of the arithmetic unit CDV. Specifically, the drive circuit WCD of the arithmetic unit CDV2 does not include the circuit WCDa shown in Figure 1. In addition, the drive circuit WCD of the arithmetic unit CDV2 is connected to wiring IWLp, which transmits wp, and wiring IWLn, which transmits wn. Note that here, wiring IWLp and wiring IWLn may be collectively referred to as wiring IWL. In addition, the drive circuit WXCD of the arithmetic unit CDV2 is connected to wiring IXLp, which transmits xp, and wiring IXLn, which transmits xn. Note that here, wiring IXLp and wiring IXLn may be collectively referred to as wiring IXL.

[0308] Wiring WXLp functions, for example, as a wire (also called a selection signal line) for sending selection signals to the calculation cells IMp and IMn, respectively, when writing the multipliers wp and wn to those calculation cells. Wiring WXLp also functions as a wire for sending non-selection signals to calculation cells IMp and IMn that are not destinations for writing. Furthermore, wiring WXLp functions, for example, as a wire for sending xp, which is treated as the multiplicand when performing multiplication in calculation cells IMp and IMn.

[0309] Furthermore, the wiring WXLn functions, for example, as wiring for transmitting xn, which is treated as the multiplicand when multiplication is performed in each of the calculation cells IMp and IMn.

[0310] Next, we will describe the various drive circuits that are provided as peripheral circuits to the arithmetic circuit CC.

[0311] The drive circuit WCD in the arithmetic unit CDV2 has switches SAp and SAN. The first terminal of switch SAp is connected to wiring IWLp, and the second terminal of switch SAp is connected to wiring WCLp. The first terminal of switch SAN is connected to wiring IWLn, and the second terminal of switch SAN is connected to wiring WCLn. The control terminals of switches SAp and SAN are connected to wiring SWLA.

[0312] In this case, wp transmitted to wiring IWLp and wn transmitted to wiring IWLn can each be represented as binary potentials as digital data.

[0313] Furthermore, the drive circuit WXCD in the arithmetic unit CDV2, as an example, similar to the drive circuit WXCD shown in Figure 1, has the function of generating a selection signal to be sent to the arithmetic circuit CC, which is the writing destination, when writing the multipliers wp and wn to the arithmetic cells IMp and IMn respectively, and sending the selection signal to the wiring WXLp, and the function of sending a signal to the wiring WXLn to turn off transistors M4p and M4n, which are included in the arithmetic circuit CC. Furthermore, the drive circuit WXCD also has, as an example, the function of generating a non-selection signal to be sent to the arithmetic circuit CC, which is not the writing destination, and sending the non-selection signal to the wiring WSL, and the function of sending signals to the wiring WXLp and WXLn to turn off transistors M1p, M1n, M4p and M4n, respectively. Furthermore, the drive circuit WXCD has the function of, for example, transmitting the multiplicand xp to the wiring WXLp and the multiplicand xn to the wiring WXLn when multiplication is performed in the calculation cells IMp and IMn, respectively.

[0314] <<Example of operation of the arithmetic unit 1>> Next, an example of operation of the arithmetic unit CDV2 shown in Figure 19 will be explained.

[0315] Figure 20A is a timing chart showing an example of the writing operation of the first data w to the arithmetic circuit CC in the arithmetic unit CDV2, and Figure 20B is a timing chart showing an example of the multiplication operation of the first data w and the second data x in the arithmetic unit CDV2.

[0316] The timing chart in Figure 20A shows the changes in potential of wiring SWLA, SWLB, WXLp, WXLn, WSL, XSL, WCLp, and WCLn during periods T21 to T23. The timing chart in Figure 20B shows the changes in potential of wiring SWLA, SWLB, WXLp, WXLn, WSL, and XSL during periods T24 to T26. The timing chart in Figure 20B also shows the changes in the amount of current Isp flowing through wiring WCLp and the amount of current Isn flowing through wiring WCLn.

[0317] [Writing Operation] During period T21, a high-level potential is applied to both wiring WXLp and wiring WSL, and a low-level potential is applied to both wiring SWLA, wiring SWLB, wiring WXLn, and wiring XSL. The start time of period T21 can be the timing when the potential of one or both of wiring WXLp and wiring WSL changes.

[0318] As described above, a high-level potential is applied to the gates of transistors M1p and M1n, so transistors M1p and M1n turn ON. Also, a high-level potential is applied to the gates of transistors M2p and M2n, so transistors M2p and M2n turn ON.

[0319] Also, since a low-level potential is applied to each control terminal of switch SAP and switch SAN, switches SAP and SAN are in an off state. Also, since a low-level potential is applied to each control terminal of switch SBP and switch SBN, switches SBP and SBN are in an off state. Also, since a low-level potential is applied to each gate of transistor M3p and transistor M3n, transistors M3p and M3n are in an off state. Also, since a low-level potential is applied to each gate of transistor M4p and transistor M4n, transistors M4p and M4n are in an off state.

[0320] In arithmetic cell IMP, since transistors M1p and M2p are in an on state, conduction is established between wiring VWE and wiring WCLp. Therefore, the potentials of the first terminal and the second terminal of resistance change element MRp and wiring WCLp are the intermediate potential V given from wiring VWE Ｍ and become the same. Similarly, in arithmetic cell IMN, since transistors M1n and M1p are in an on state, conduction is established between wiring VWE and wiring WCLn. Therefore, the potentials of the first terminal and the second terminal of resistance change element MRn and wiring WCLn are also the intermediate potential V given from wiring VWE Ｍ and become the same.

[0321] In period T22, a high-level potential is applied to wiring SWLA. Therefore, since a high-level potential is applied to each control terminal of switch SAP and switch SAN, switches SAP and SAN are in an on state. Note that the time when period T22 starts can be the timing when the potential of wiring SWLA changes.

[0322] Also, in period T22, it is assumed that the arithmetic device CDV2 is supplied with a potential corresponding to wp from wiring IWLp and a potential corresponding to wn from wiring IWLn. Note that the potential corresponding to wp = 0 is the low-level potential V Ｌ and the potential corresponding to wp = 1 is the high-level potential V ＨSimilarly, the potential corresponding to wn=0 is the low-level potential V. Ｌ The potential corresponding to wn=1 is set to the high-level potential V Ｈ Let's assume that.

[0323] Specifically, when w = -1, the low-level potential V corresponding to wp = 0 is reached from the wiring IWLp. Ｌ Given, and a high-level potential V corresponding to wn=1 is given from the wiring IWLn. Ｈ The potential difference between the first and second terminals of the resistive switching element MRp is V. Ｌ -V Ｍ Therefore, similar to Embodiment 1, the direction of the magnetic moment in layer FL is assumed to be approximately antiparallel to the direction of the magnetic moment in layer RL. Also, the potential difference between the first terminal and the second terminal of the resistive switching element MRn is V Ｈ -V Ｍ Therefore, similar to Embodiment 1, the direction of the magnetic moment in layer FL is assumed to be approximately parallel to the direction of the magnetic moment in layer RL.

[0324] Furthermore, when w=0, the low-level potential V corresponding to wp=0 is obtained from the wiring IWLp. Ｌ Given, and a low-level potential V corresponding to wn=0 is given from the wiring IWLn. Ｌ The following is given: The potential difference between the first and second terminals of the resistive switching element MRp and the resistive switching element MRn is V Ｌ -V Ｍ Therefore, similar to Embodiment 1, the direction of the magnetic moment in layer FL is assumed to be approximately antiparallel to the direction of the magnetic moment in layer RL.

[0325] Furthermore, when w=1, the high-level potential V corresponding to wp=1 is obtained from the wiring IWLp. Ｈ Given, and a low-level potential V corresponding to wn=0 is given from the wiring IWLn. Ｌ The potential difference between the first and second terminals of the resistive switching element MRp is V. Ｈ -V Ｍ Therefore, similar to Embodiment 1, the direction of the magnetic moment in layer FL is assumed to be approximately parallel to the direction of the magnetic moment in layer RL. Also, the potential difference between the first terminal and the second terminal of the resistive switching element MRn is V Ｌ -V ＭTherefore, similar to Embodiment 1, the direction of the magnetic moment in layer FL is assumed to be approximately antiparallel to the direction of the magnetic moment in layer RL.

[0326] Furthermore, during period T22, as described above, after determining the direction of the magnetic moments within the respective layers FL of the resistive switching elements MRp and MRn, a low-level potential is applied to the wiring SWLA to turn off switches SAp and SAN. As a result, the potentials of wiring WCLp and WCLn are set to the intermediate potential V supplied from wiring VWE. Ｍ This is the result. Note that the potential of the wiring WCLn is V Ｍ After that, the program transitions to period T23.

[0327] During period T23, low-level potentials are applied to both wiring WXLp and wiring WSL. As a result, in calculation cell IMp, transistors M1p and M2p are in the off state, and wiring WCLp is in the floating state. Similarly, in calculation cell IMn, transistors M1n and M2n are in the off state, and wiring WCLn is in the floating state. The start time of period T23 can be the timing when the potential of one or both of wiring WXLp and wiring WSL changes.

[0328] As described above, by performing the operations during periods T21 to T23, data corresponding to wp can be stored in the calculation cell IMp, and data corresponding to wn can be stored in the calculation cell IMn.

[0329] [Multiplication Operation] During period T24, a high-level potential is applied to both wiring SWLB and wiring XSL, while a low-level potential is applied to both wiring SWLA, wiring WXLp, wiring WXLn, and wiring WSL. The start time of period T24 can be the timing when the potential of one or both of wiring SWLB and wiring XSL changes.

[0330] As described above, a high-level potential is applied to the control terminals of switches SBp and SBn, so switches SBp and SBn are turned ON. Also, a high-level potential is applied to the gates of transistors M3p and M3n, so transistors M3p and M3n are turned ON.

[0331] Furthermore, a low-level potential is applied to the control terminals of switches SAp and SAN, so switches SAp and SAN are in the OFF state. Also, a low-level potential is applied to the gates of transistors M1p and M1n, so transistors M1p and M1n are in the OFF state. Also, a low-level potential is applied to the gates of transistors M2p and M2n, so transistors M2p and M2n are in the OFF state. Also, a low-level potential is applied to the gates of transistors M4p and M4n, so transistors M4p and M4n are in the OFF state.

[0332] In the calculation cell IMp, since transistor M3p is ON, the third terminal of the resistive switching element MRp has a potential V from the wiring VRE. Ｒ The following is given. Similarly, in the calculation cell IMn, since transistor M3n is ON, the third terminal of the resistive switching element MRn has a potential V from the wiring VRE. Ｒ It is given.

[0333] Furthermore, since switches SBp and SBn are in the ON state, the potential V output from the first input terminal of circuit ITSa is present in the wiring WCLP. Ｓ The following is given: and the potential V output from the second input terminal of circuit ITSa is given to the wiring WCLn. Ｓ It is given.

[0334] During period T25, the wiring WXLp is given a potential corresponding to xp, one of the two variables representing the second data x. Specifically, when xp = 1, the wiring WXLp has a high-level potential V Ｈ Given that and xp = 0, there is a low-level potential V in the wiring WXLp.Ｌ The following is given. Also, during period T25, the wiring WXLn is given a potential corresponding to xn, the other of the two variables that represent the second data x. Specifically, when xn = 1, the wiring WXLn has a high-level potential V Ｈ Given that xn = 0, there is a low-level potential V in the wiring WXLn. Ｌ The following is given. The time when period T25 begins can be the timing when xp is input to wiring WXLp or the timing when xn is input to wiring WXLn.

[0335] Specifically, when x = -1, xp = 0 and xn = 1, so transistors M1p and M1n are in the off state, and transistors M4p and M4n are in the on state. Therefore, the potential V output from the second input terminal of circuit ITSa is transmitted to the first terminal of the resistive switching element MRp via the wiring WCLn. Ｓ A potential V is provided, and the first terminal of the resistive switching element MRn is connected via the wiring WCLp to the potential V output from the first input terminal of the circuit ITSa. Ｓ It is given.

[0336] Furthermore, when x = 0, xp = 0 and xn = 0, so transistors M1p, M1n, M4p, and M4n are in the off state. At this time, the first and second terminals of the resistive switching element MRp, and the first and second terminals of the resistive switching element MRn are in a floating state.

[0337] Furthermore, when x = 1, xp = 1 and xn = 0, so transistors M1p and M1n are turned on, and transistors M4p and M4n are turned off. Therefore, the first terminal of the resistive switching element MRp receives the potential V output from the first input terminal of circuit ITSa via the wiring WCLp. Ｓ A voltage V is given, and the first terminal of the resistive switching element MRn is connected via the wiring WCLn to the potential V output from the second input terminal of the circuit ITSa. Ｓ It is given.

[0338] By the way, when x = -1 or x = 1, a potential Vs is applied to the first terminals of the resistive switching element MRp and the resistive switching element MRn, and a potential V is applied to the third terminals of each element. Ｒ When given, a tunnel current of a certain magnitude flows through each of the resistive switching elements MRp and MRn, corresponding to the direction of the magnetic moment of layer FL. For example, when wp=1 is written to resistive switching element MRp, the direction of the magnetic moment of layer FL becomes parallel to the direction of the magnetic moment of layer RL, and the amount of tunnel current becomes I Ｂ Assuming that this is the case, and that wp=0 is written to the resistive switching element MRp, the direction of the magnetic moment of layer FL becomes antiparallel to the direction of the magnetic moment of layer RL, and the amount of the tunnel current is I Ｂ Smaller than I Ｓ It shall be assumed that the following is true. Similarly, if wn=1 is written to the resistive switching element MRn, the amount of tunnel current is I Ｂ It is assumed that, and if wn=0 is written to the resistive switching element MRn, the amount of the tunnel current is I Ｓ This shall be the case.

[0339] Therefore, when w=1 is held in the arithmetic circuit CC, and the second data x=1 is input to the arithmetic circuit CC, the amount of current flowing through the wiring WCLp is the amount of tunnel current of the resistive element MRp, Isp = I Ｂ Therefore, the amount of current flowing through the wiring WCLn is the amount of tunnel current through the resistive switching element MRn, Isn = I Ｓ This is the result. Also, when the second data x = -1 is input to the arithmetic circuit CC, the amount of current flowing through the wiring WCLp is the amount of tunnel current through the resistive switching element MRn, Isp = I Ｓ Therefore, the amount of current flowing through the wiring WCLn is the amount of tunnel current through the resistive switching element MRp, Isn = I Ｂ This is the result. Also, when the second data x = 0 is input to the arithmetic circuit CC, transistors M1p, M4p, M1n, and M4n are turned off, so the amount of current flowing through the wiring WCLp is Isp = 0, and the amount of current flowing through the wiring WCLn is Isn = 0.

[0340] Furthermore, when w = -1 is held in the arithmetic circuit CC, and the second data x = 1 is input to the arithmetic circuit CC, the amount of current flowing through the wiring WCLp is the amount of tunnel current of the resistive switching element MRp, Isp = I Ｓ Therefore, the amount of current flowing through the wiring WCLn is the amount of tunnel current through the resistive switching element MRn, Isn = I Ｂ This is the result. Also, when the second data x = -1 is input to the arithmetic circuit CC, the amount of current flowing through the wiring WCLp is the amount of tunnel current through the resistive switching element MRn, Isp = I Ｂ Therefore, the amount of current flowing through the wiring WCLn is the amount of tunnel current through the resistive switching element MRp, Isn = I Ｓ This is the result. Also, when the second data x = 0 is input to the arithmetic circuit CC, transistors M1p, M4p, M1n, and M4n are turned off, so the amount of current flowing through the wiring WCLp is Isp = 0, and the amount of current flowing through the wiring WCLn is Isn = 0.

[0341] Furthermore, when w=0 is held in the arithmetic circuit CC, and the second data x=1 or x=-1 is input to the arithmetic circuit CC, the amount of current flowing through the wiring WCLp is Isp = I Ｓ Therefore, the amount of current flowing through the wiring WCLn is Isn = I Ｓ This is the result. Also, when the second data x = 0 is input to the arithmetic circuit CC, transistors M1p, M4p, M1n, and M4n are turned off, so the amount of current flowing through the wiring WCLp is Isp = 0, and the amount of current flowing through the wiring WCLn is Isn = 0.

[0342] Furthermore, during period T25, circuit ITSa acquires the difference between the amount of current Isp flowing through wiring WCLp and the amount of current Isn flowing through wiring WCLn, and outputs this difference information to the output terminal of circuit ITSa. Here, when the difference current between Isp and Isn is denoted as ΔI, ΔI will be as shown in the table below, depending on the result of multiplying the first data w and the second data x. Note that Isp and Isn are also shown in the table.

[0343]

[0344] As shown in the above table, when the multiplication result of the first data w and the second data x is w × x = 1, ΔI = I Ｂ −I Ｓ and when the multiplication result of the first data w and the second data x is w × x = −1, ΔI = I Ｓ −I Ｂ holds. Also, when the multiplication result of the first data w and the second data x is w × x = 0, ΔI = 0. As such, by defining wp and wn for expressing the first data w and xp and xn for expressing the second data x as shown in the above table and using the arithmetic unit CDV2 in FIG. 19, the multiplication result of the first data w and the second data x can be obtained from the differential current ΔI.

[0345] During period T26, low-level potentials are applied to each of the wiring SWLB and the wiring XSL, the switches SBp and SBn are in the off state, and the transistors M3p and M3n are in the off state. As a result, the multiplication operation in the arithmetic unit CDV2 ends. Note that the timing at which period T26 starts can be the timing at which the potential of one or both of the wiring WXL and the wiring WSL changes.

[0346] <Configuration Example 2 of Arithmetic Unit> The arithmetic unit CDV2 shown in FIG. 19 is configured to include one arithmetic circuit CC. However, similar to the arithmetic unit CDVA in FIG. 4, the number of arithmetic circuits CC may be two or more.

[0347] The arithmetic unit CDVD shown in FIG. 21 is a modification example of the arithmetic unit CDV2 in FIG. 19 and is different from the arithmetic unit CDV2 in FIG. 19 in that a plurality of arithmetic circuits CC are arranged in a matrix. Specifically, the arithmetic unit CDVD in FIG. 21 has a configuration in which a plurality of arithmetic circuits CC are arranged in an m-row n-column matrix in the cell array CA, similar to the arithmetic unit CDVA in FIG. 4. In FIG. 21, the arithmetic circuits CC[1, j] and CC[m, j] are shown in an extracted manner. Also, each arithmetic circuit CC can be said to be arranged such that the arithmetic cells IMp and IMn are arranged alternately in the row direction, similar to the arithmetic unit CDVA in FIG. 4.

[0348] Note that since the arithmetic unit CDVD in FIG. 21 is a modified example of the arithmetic unit CDV2 in FIG. 19, for a part of the arithmetic unit CDVD, the description of the arithmetic unit CDVA in FIG. 4 can be referred to. Also, since the arithmetic unit CDVD in FIG. 21 can also be said to be a modified example of the arithmetic unit CDVA in FIG. 4, for a part of the arithmetic unit CDVD, the description of the arithmetic unit CDVA in FIG. 4 can be referred to. Further, below, the parts of the arithmetic unit CDVD that are different from the arithmetic unit CDVA in FIG. 4 and the parts that are different from the arithmetic unit CDV2 in FIG. 19 will be described.

[0349] The drive circuit WCD has switches SAP[1] to SAP[n] corresponding to the switch SAP in FIG. 19 and switches SAN[1] to SAN[j] corresponding to the switch SAN in FIG. 19. Also, the drive circuit WCD is connected to wirings IWLp[1] to IWLp[n] corresponding to the wiring IWLp in FIG. 19 and wirings IWLn[1] to IWLn[n] corresponding to the wiring IWLn in FIG. 19.

[0350] In the cell array CA of the arithmetic unit CDVD in FIG. 21, wirings WXLp[1] to WXLp[m] corresponding to the wiring WXLp in FIG. 19 and wirings WXLn[1] to WXLn[m] corresponding to the wiring WXLn in FIG. 19 extend in the row direction. Note that in FIG. 21, wirings WXLp[1], WXLn[1], WXLp[m], and WXLn[m] are shown in an excerpt. The drive circuit WXCD is connected to wirings WXLp[1] to WXLp[m] and wirings WXLn[1] to WXLn[m].

[0351] For each of the drive circuit ITS, drive circuit WSD, and drive circuit XSD of the arithmetic unit CDVD shown in FIG. 21, each of the drive circuit ITS, drive circuit WSD, and drive circuit XSD of the arithmetic unit CDVA in FIG. 4 can be referred to.

[0352] The drive circuit WXCD in Figure 21 can be configured as, for example, the drive circuit WXCD shown in Figure 22. The drive circuit WXCD in Figure 22 includes, as an example, a shift register SR, a selector SLC[i], sequential circuits LTp[1] to LTp[m], sequential circuits LTn[1] to LTn[m], switch circuits SWp[1] to SWp[m], switch circuits SWn[1] to SWn[m], level shifters LVp[1] to LVp[m], level shifters LVn[1] to LVn[m], and switches SDa[1] to SDa[m]. Note that in Figure 22, only the circuits, circuit elements, wiring, etc. arranged in the first, second, and m rows are shown.

[0353] The drive circuit WXCD in Figure 22 is a modified version of the drive circuit WXCD in Figure 11. Therefore, some of the connection configurations of the drive circuit WXCD in Figure 22 can be explained by referring to the description of the drive circuit WXCD in Figure 11.

[0354] Furthermore, for the shift register SR and selectors SLC[1] to SLC[m] shown in Figure 22, refer to the description of the shift register SR and selectors SLC[1] to SLC[m] in Figure 11. Also, for the sequential circuits LTp[1] to LTp[m] and sequential circuits LTn[1] to LTn[m] shown in Figure 22, refer to the description of the sequential circuits LT[1] to LT[m] in Figure 11. Also, for the switch circuits SWp[1] to SWp[m] and switch circuits SWn[1] to SWn[m] shown in Figure 22, refer to the description of the switch circuits SW[1] to SW[m] in Figure 11. Furthermore, the level shifters LVp[1] to LVp[m] and level shifters LVn[1] to LVn[m] shown in Figure 22 can be described by referring to the explanation of level shifters LV[1] to LV[m] in Figure 11.

[0355] Switches SDa[1] to SDa[m] can be, for example, switches applicable to switches SAP and SAN.

[0356] Focus on row i of the drive circuit WXCD in Figure 22. The terminal SO[i] of the shift register SR is connected to the input terminal of the selector SLC[i]. The second output terminal of the selector SLC[i] is connected to the input terminal of the level shifter LVp[i], and the first output terminal of the selector SLC[i] is connected to the control terminals of the sequential circuit LTp[i] and sequential circuit LTn[i], respectively. The input terminal of the sequential circuit LTp[i] is connected to the wiring IXLp, the output terminal of the sequential circuit LTp[i] is connected to the first terminal of the switch circuit SWp[i], and the second terminal of the switch circuit SWp[i] is connected to the second output terminal of the selector SLC[i] and the input terminal of the level shifter LVp[i]. The output terminal of the level shifter LVp[i] is connected to the wiring WXLp[i]. The input terminal of the sequential circuit LTn[i] is connected to wiring IXLn, the output terminal of the sequential circuit LTn[i] is connected to the first terminal of the switch circuit SWn[i], and the second terminal of the switch circuit SWn[i] is connected to the input terminal of the level shifter LVp[i] and the first terminal of the switch SDa[i]. The output terminal of the level shifter LVn[i] is connected to wiring WXLn[i]. The second terminal of the switch SDa[i] is connected to wiring VSE, and the control terminal of the switch SDa[i] is connected to wiring SLLb. The enable terminals of the switch circuits SWp[i] and SWn[i] are connected to wiring EN2.

[0357] Furthermore, the connection point between the output terminal of the sequential circuit LTp[i] and the input terminal of the switch circuit SWp[i] is denoted as node SNp[i], and the connection point between the output terminal of the sequential circuit LTn[i] and the input terminal of the switch circuit SWn[i] is denoted as node SNn[i].

[0358] Wiring SLLb, for example, functions as wiring for transmitting a control signal to the control terminal of switch SDa[i]. In particular, this control signal can be a signal inverted in logic from the signal input to wiring SLL, similar to wiring SLLb shown in Figure 16.

[0359] The wiring VSE, for example, functions as wiring that provides a fixed potential, similar to the wiring VSE in Figure 16. In particular, it is preferable that the fixed potential is a potential that turns off transistor M4p in the calculation cell IMp and transistor M4n in the calculation cell IMn. For example, in the case of the calculation circuit CC shown in Figure 19, the fixed potential can be a low-level potential.

[0360] It should be noted that the drive circuit WXCD according to one aspect of the present invention is not limited to the configuration of the drive circuit WXCD shown in Figure 22. For example, the drive circuit WXCD according to one aspect of the present invention may be configured such that, similar to Figure 8A, the drive circuit WXCD in Figure 22 does not have level shifters LVp and LVn, and the second terminal of the switch circuit SWp and the first terminal of the selector SLC are directly connected to the wiring WXLp, and the second terminal of the switch circuit SWn and the first terminal of the switch SDa are directly connected to the wiring WXLn (see Figure 23).

[0361] In particular, in the drive circuit WXCD shown in Figure 23, it is preferable to provide the buffer circuit BFE, which is a three-state buffer circuit as shown in Figure 12A, to the switch circuits SWp[i] and SWn[i]. Since the drive circuit WXCD in Figure 23 does not have level shifters LVp[i] and LVn[i] which have a signal amplification effect, by providing the buffer circuit BFE to the switch circuits SWp[i] and SWn[i], the signal amplified by the buffer circuit BFE can be transmitted to the wiring WXLp[i] or WXLn[i]. Furthermore, the drive circuit WXCD with the buffer circuit BFE provided to the switch circuits SWp[i] and SWn[i] can have fewer circuit elements than the drive circuit WXCD in Figure 22, thus reducing the circuit area.

[0362] Furthermore, the drive circuit WXCD according to one aspect of the present invention may be configured, for example, in the drive circuit WXCD of Figure 22, similar to Figure 9A, in which the level shifter LVp is replaced with a buffer circuit BFLp and the level shifter LVn is replaced with a buffer circuit BFLn (see Figure 24).

[0363] In particular, in the drive circuit WXCD shown in Figure 24, it is preferable to provide the switch SF shown in Figure 12B to the switch circuits SWp[i] and SWn[i]. Since the drive circuit WXCD in Figure 24 is provided with buffer circuits BFLp[i] and BFLn[i] which have a signal amplification effect, it is preferable to provide the switch SF to the switch circuits SWp[i] and SWn[i], which can reduce the number of circuit elements compared to providing the buffer circuit BFE which has a signal amplification effect, in order to reduce the circuit area of ​​the drive circuit WXCD.

[0364] Furthermore, the drive circuit WXCD according to one embodiment of the present invention may be configured such that, similar to the drive circuit WXCD in Figure 6A, the switch circuits SWp and SWn of the drive circuit WXCD in Figure 22 are each replaced with sequential circuits LTH (not shown).

[0365] Next, we will explain an example of the operation of the drive circuit WXCD shown in Figure 22.

[0366] Figure 25 is a timing chart showing an example of the operation of the drive circuit WXCD when sequentially writing first data to each of the multiple arithmetic circuits CC of the arithmetic unit CDDVD. Specifically, the timing chart shows an example of operation in which the drive circuit WXCD sequentially transmits selection signals to each of the wirings WXLp[1] to WXLp[m] to turn on transistors M1p and M1n of the arithmetic circuit CC, and transmits signals to each of the wirings WXLn[1] to WXLn[m] to turn off transistors M4p and M4n of the arithmetic circuit CC.

[0367] Furthermore, the timing chart shows the changes in potential of terminal SO[1], terminal SO[2], terminal SO[m], wiring SLL, wiring SLLb, wiring WXLp[1], wiring WXLn[1], wiring WXLp[2], wiring WXLn[2], wiring WXLp[m], and wiring WXLn[m] during periods T31 to T33.

[0368] During periods T31 to T33, a low-level potential is applied to wiring SLL, and a high-level potential is applied to wiring SLLb. Therefore, a low-level potential is applied to the control terminals of selectors SLC[1] to SLC[m], causing each of selectors SLC[1] to SLC[m] to be non-conductive between its input terminal and the first output terminal, and conductive between its input terminal and the second output terminal. As a result, in row i, the terminal SO[i] of the shift register SR and the input terminal of the level shifter LVp[i] become conductive. Also, a high-level potential is applied to the control terminals of switches SDa[1] to SDa[m], causing switches SDa[1] to SDa[m] to be turned on. As a result, in row i, the wiring VSE and wiring WXLn[i] become conductive, and the fixed potential applied by wiring VSE is applied to wiring WXLn[i]. Therefore, transistors M4p and M4n, which are included in all arithmetic circuits CC within the cell array CA, are turned off.

[0369] Furthermore, during periods T31 to T33, a low-level potential is applied to the wiring EN2. In other words, during periods T31 to T33, each of the switch circuits SWp[1] to SWp[m] and SWn[1] to SWn[m] are in the off state, and the second terminals of each of the switch circuits SWp[1] to SWp[m] and SWn[1] to SWn[m] are in a high impedance state.

[0370] Furthermore, during period T31, a low-level potential is output from each of the terminals SO[1] to SO[m] of the shift register SR. Therefore, a low-level potential is applied to each of the input terminals of the level shifters LVp[1] to LVp[m]. Consequently, each of the level shifters LVp[1] to LVp[m] acquires this low-level potential and applies the converted potential of the voltage level of this low-level potential to the wiring WXLp[1] to WXLp[m]. In Figure 25, for convenience, the potential applied to the wiring WXLp[1] to WXLp[m] is treated as the low-level potential. This low-level potential can also be used as the non-selection signal output by the drive circuit WXCD for the calculation cells IMp and IMn.

[0371] During period T32, the shift register SR sequentially outputs high-level potentials from each of terminals SO[1] to SO[m]. For example, when a high-level potential is output from terminal SO[i], that high-level potential is input to the input terminal of level shifter LVp[i]. The level shifter LVp[i] acquires the high-level potential and provides the wire WXLp[i] with a potential converted from the voltage level of that high-level potential. As a result, the drive circuit WXCD can output a high-level potential to the wire WXLp[i]. This operation is performed sequentially from the first row to the mth row, so that the drive circuit WXCD can sequentially provide a high-level potential as a selection signal to each of the wires WXLp[1] to WXLp[m].

[0372] During period T33, as in period T31, a low-level potential is output from each of the terminals SO[1] to SO[m] of the shift register SR. In other words, the drive circuit WXCD can provide a non-selection signal as a low-level potential to each of the wirings WXLp[1] to WXLp[m] collectively.

[0373] As described above, by performing the operations shown in Figure 25 from period T31 to period T33, the first data can be sequentially written to each of the multiple arithmetic circuits CC of the arithmetic unit CDDVD.

[0374] Next, an example of the operation of the drive circuit WXCD when multiple arithmetic circuits CC of the arithmetic unit CDDVD perform multiplication of the first data and the second data will be explained using the timing chart in Figure 26. The timing chart shows an example of the operation in which the drive circuit WXCD simultaneously transmits xp[1] to xp[m] to each of the wirings WXLp[1] to WXLp[m], and simultaneously transmits xn[1] to xn[m] to each of the wirings WXLn[1] to WXLn[m]. Specifically, the timing chart shows the changes in potential of terminal SO[1], terminal SO[2], terminal SO[m], wiring SLL, and wiring SLLb during periods T34 to T36. Furthermore, the timing chart shows the signals supplied to wiring IXLp, wiring IXLn, node SNp[1], node SNn[1], node SNp[2], node SNn[2], node SNp[m], node SNn[m], wiring WXLp[1], wiring WXLn[1], wiring WXLp[2], wiring WXLn[2], wiring WXLp[m], and wiring WXLn[m] during periods T34 to T36.

[0375] During period T34, a high-level potential is applied to the wiring SLL. As a result, a high-level potential is applied to the control terminals of selectors SLC[1] to SLC[m], causing selectors SLC[1] to SLC[m] to conduct between their input terminal and the first output terminal, and to deconduct between their input terminal and the second output terminal. Consequently, in row i, a conduction occurs between the terminal SO[i] of the shift register SR and the control terminal of the sequential circuit LTp[i].

[0376] Furthermore, during period T34, a low-level potential is assumed to be output from each of the terminals SO[1] to SO[m] of the shift register SR. Therefore, a low-level potential is applied to each of the control terminals of the sequential circuits LTp[1] to LTp[m], and during this period, even if the potential of the input terminal of the sequential circuit LTp[i] changes, the potential of the output terminal of the sequential circuit LTp[i] does not change. Note that the potentials of each of the output terminals of the sequential circuits LTp[1] to LTp[m] are not specifically defined during period T34.

[0377] During period T35, the shift register SR sequentially outputs high-level potentials from each of terminals SO[1] to SO[m]. Also, when a high-level potential is output from terminal SO[i], the wiring IXLp is supplied with the signal xp[i], one of two variables representing the second data x[i] to be transmitted to wiring WXLp[i], and the wiring IXLn is supplied with the signal xn[i], the other of two variables representing the second data x[i] to be transmitted to wiring WXLn[i]. Specifically, during period T35, xp[1] to xp[m] are sequentially supplied to wiring IXLp, and xn[1] to xn[m] are sequentially supplied to wiring IXLn.

[0378] When a high-level potential output from terminal SO[i] is applied to the control terminal of sequential circuit LTp[i], sequential circuit LTp[i] acquires xp[i] as a signal applied to the input terminal of sequential circuit LTp[i] and holds the potential corresponding to xp[i]. Furthermore, sequential circuit LTp[i] outputs this potential from its output terminal. This potential is applied to the input terminal of switch circuit SWp[i]. Subsequently, even if the high-level potential output from terminal SO[i] changes to a low-level potential, sequential circuit LTp[i] continues to hold the potential corresponding to xp[i] and continues to output this potential from its output terminal. Similarly, sequential circuit LTn[i] continues to hold the potential corresponding to xn[i] and continues to output this potential from its output terminal.

[0379] Regarding the operation during the above period T35, by performing the operations from the first line to the m-th line, signals corresponding to xp[1] to xp[m] are continuously output from the respective output terminals of the sequential circuits LTp[1] to LTp[m], and signals corresponding to xn[1] to xn[m] are continuously output from the respective output terminals of the sequential circuits LTn[1] to LTn[m].

[0380] During period T36, a high-level potential is applied to wiring EN2. For this reason, each of the switch circuits SWp[1] to SWp[m] and the switch circuits SWn[1] to SWn[m] is turned on. Thus, focusing on the i-th line, a signal corresponding to xp[i] is applied from the output terminal of the sequential circuit LTp[i] to the input terminal of the level shifter LVp[i], and a signal corresponding to xn[i] is applied from the output terminal of the sequential circuit LTn[i] to the input terminal of the level shifter LVn[i].

[0381] For this reason, each of the level shifters LVp[1] to LVp[m] collectively transmits the signals of xp[1] to xp[m] for which voltage level conversion has been performed to the wirings WXLp[1] to WXLp[m], and each of the level shifters LVn[1] to LVn[m] collectively transmits the signals of xn[1] to xn[m] for which voltage level conversion has been performed to the wirings WXLn[1] to WXLn[m].

[0382] As described above, in the arithmetic unit CDVD of FIG. 21, by performing the operations during periods T34 to T36 shown in FIG. 26, the drive circuit WXCD can collectively transmit the second data to each of the plurality of arithmetic circuits CC.

[0383] Note that the configuration example of the drive circuit WXCD according to the semiconductor device of one aspect of the present invention is not limited to the circuit configuration shown in FIG. 22. The drive circuit WXCD shown in FIG. 22 is configured such that each of the two variables xp and xn representing the second data x is sequentially applied to the wirings IXLp and IXLn, but it may be configured such that xp[1] to xp[m] and xn[1] to xn[m] are collectively applied to the drive circuit WXCD.

[0384] The drive circuit WXCD shown in Figure 27 differs from the drive circuit WXCD in Figure 22 in that it is provided with selectors SLCA[1] to SLCA[m], switches SEa[1] to SEa[m], and switches SEb[1] to SEb[m], but does not have selectors SLC[1] to SLLC[m], sequential circuits LTp[1] to LTp[m], sequential circuits LTn[1] to LTn[m], switches SWp[1] to SWp[m], and switches SWn[1] to SWn[m]. In addition, the drive circuit WXCD in Figure 27 is connected to wiring IXLp[1] to IXLp[m] as wiring IXLp, and to wiring IXLn[1] to IXLn[m] as wiring IXLn.

[0385] Note that each of the selectors SLCA[1] to SLCA[m] refers to the selectors SLCA[1] to SLCA[m] shown in Figure 3B. Also, for each of the switches SEa[1] to SEa[m] and SEb[1] to SEb[m], for example, switches applicable to switches SDa[1] to SDa[m] in Figure 22 can be used. For this reason, for switches SEa[1] to SEa[m] and SEb[1] to SEb[m], refer to the description of switches SDa[1] to SDa[m].

[0386] Let's focus on row i of the drive circuit WXCD in Figure 27. Terminal SO[i] is connected to the first input terminal of selector SLCA[i], and wiring IXLp[i] is connected to the second input terminal of selector SLCA[i]. The output terminal of selector SLCA[i] is connected to the input terminal of level shifter LVp[1]. Wiring SLL is connected to the control terminals of selector SLCA[1] through selector SLCA[m]. Wiring IXLn[i] is connected to the input terminal of level shifter LVn[i], the output terminal of level shifter LVn[i] is connected to the first terminal of switch SEb[i], the second terminal of switch SEb[i] is connected to the first terminal of switch SEa[i] and wiring WXLn[i], and the control terminal of switch SEb[i] is connected to wiring SLL.

[0387] When sequentially writing the first data to multiple arithmetic circuits CC of the arithmetic unit CDDVD using the drive circuit WXCD shown in Figure 27, a low-level potential is applied to the wiring SLL, causing conduction between the first input terminal and output terminal of selector SLCA[1] to selector SLCA[m], and high-level potentials are output sequentially from each of the terminals SO[1] to terminal SO[m] of the shift register SR. This allows selection signals to be sequentially transmitted from the output terminals of level shifters LV[1] to level shifters LV[m] to wiring WXLp[1] to wiring WXLp[m].

[0388] Furthermore, while a low-level potential is supplied to wiring SLL, a high-level potential is supplied to wiring SLLb. As a result, switches SEb[1] through SEb[m] are each in the off state, and switches SEa[1] through SEa[m] are each in the on state. Consequently, wiring WXLn[1] through WXLn[m] are each supplied with a fixed potential (in this case, a low-level potential) from wiring VSE.

[0389] Furthermore, when multiplying the first data and the second data of the arithmetic unit CDDVD using the drive circuit WXCD shown in Figure 27, a high-level potential is applied to the wiring SLL to create a conductive state between the second input terminal and output terminal of selector SLCA[1] to selector SLCA[m], and a signal corresponding to xp[1] to xp[m], which is one of the two variables representing the second data x, is transmitted to each of the wiring IXLp[1] to IXLp[m]. This makes it possible to transmit signals corresponding to xp[1] to xp[m] simultaneously from the output terminals of level shifters LVp[1] to level shifters LVp[m] to wiring WXLp[1] to WXLp[m].

[0390] Furthermore, while a high-level potential is applied to wiring SLL, a low-level potential is applied to wiring SLLb. As a result, switches SEb[1] through SEb[m] are each in the ON state, and switches SEa[1] through SEa[m] are each in the OFF state. At this point, signals corresponding to xn[1] through xn[m], which are the other of the two variables representing the second data x, are transmitted to each of wiring IXLn[1] through IXLn[m]. This allows signals corresponding to xn[1] through xn[m] to be transmitted collectively from the output terminals of level shifters LVn[1] through LVn[m] to wiring WXLn[1] through WXLn[m].

[0391] The drive circuit WXCD in Figure 27, compared to the drive circuit WXCD in Figure 22, is provided with switches SEb[1] to SEb[m] and does not have sequential circuits LTS[1] to LTS[m] and sequential circuits LTH[1] to LTH[m]. Therefore, the circuit area can be reduced compared to the drive circuit WXCD in Figure 22. This leads to a reduction in the circuit area of ​​the arithmetic unit CDDVD, and enables miniaturization of the arithmetic unit CDDVD and the electronic equipment including the arithmetic unit CDDVD.

[0392] <<Example of Operation of the Arithmetic Unit 2>> Next, an example of operation of the arithmetic unit CDDVD shown in Figure 21 will be described. The arithmetic unit CDDVD used in the explanation of the operation example will be configured to include the drive circuit WXCD shown in Figure 22 and the drive circuit ITS shown in Figure 13B.

[0393] Figure 28 is a timing chart showing an example of the writing operation of the first data w to each of the multiple arithmetic circuits CC in the j-th column of the cell array CA in the arithmetic unit CDDVD (operation during period TW), and an example of the multiplication operation of the first data w and the second data x performed by each of the multiple arithmetic circuits CC in the j-th column of the cell array CA (operation during period TR). Specifically, the timing chart shows the potential changes of wiring SWLA, wiring SWLB, wiring WXLp[1], wiring WXLn[1], wiring WXLp[2], wiring WXLn[2], wiring WXLp[m], wiring WXLn[m], wiring WSL[1], wiring WSL[2], wiring WSL[m], wiring XSL[1], wiring XSL[2], wiring XSL[m], wiring WCLp[j], and wiring WCLn[j] during periods TW and TR.

[0394] Note that in Figure 28, the potential V Ｓ This is a low-level potential V Ｌ Higher than, high-level potential V Ｈ Although it is set to a lower potential than, low-level potential V Ｌ Lower potential or higher level potential V Ｈ It may also be a higher potential.

[0395] Furthermore, in period TW, the thick dotted lines shown in wiring WCLp[j] and wiring WCLn[j] indicate that no potential is specifically defined. Therefore, the potential indicated by these thick dotted lines may be a high-level potential, a low-level potential, or any other potential. Also, the thick solid line shown in wiring WCLp[j] indicates that the wp written to the corresponding calculation cell IMp is "1", and the thick dashed line shown in wiring WCLp[j] indicates that the wp written to the corresponding calculation cell IMp is "0". Similarly, the thick solid line shown in wiring WCLn[j] indicates that the wn written to the corresponding calculation cell IMn is "1", and the thick dashed line shown in wiring WCLn[j] indicates that the wn written to the corresponding calculation cell IMn is "0".

[0396] Furthermore, in the period TRa included in period TR, the thick solid lines shown in wiring WXLp[1] to wiring WXLp[m] indicate the case where xp transmitted to the corresponding arithmetic circuit CC is "1", and the thick dashed lines shown in wiring WXLp[1] to wiring WXLp[m] indicate the case where xp transmitted to the corresponding arithmetic circuit CC is "0". Similarly, the thick solid lines shown in wiring WXLn[1] to wiring WXLn[m] indicate the case where xn transmitted to the corresponding arithmetic circuit CC is "1", and the thick dashed lines shown in wiring WXLn[1] to wiring WXLn[m] indicate the case where xn transmitted to the corresponding arithmetic circuit CC is "0".

[0397] During the period TW, when writing the first data w to each of the multiple arithmetic circuits CC in the j-th column of the cell array CA, a high-level potential is first applied to the wiring SWLA to turn on switches SAP[j] and SAN[j]. While switches SAP[j] and SAN[j] are turned on, the drive circuit WXCD sequentially applies a high-level potential to wirings WXLp[1] through WXLp[m], and the drive circuit WSD sequentially applies a high-level potential to wirings WSL[1] through WSL[m].

[0398] Furthermore, it is assumed that the rows of wiring WXLp[1] to WXLp[m] that are given a high-level potential and the rows of wiring WSL[1] to WSL[m] that are given a high-level potential are the same. For example, when wiring WXLp[i] is given a high-level potential, wiring WSL[i] is also given a high-level potential. Also, during period TW, each of wiring WXLn[1] to WXLn[m] is given a low-level potential by the drive circuit WXCD.

[0399] For example, when a high-level potential is applied to wiring WXLp[1] and wiring WSL[1], transistors M1p, M2p, M1n, and M2n in the arithmetic circuit CC[1,j] are turned ON. Also, when a low-level potential is applied to wiring WXLn[1], transistors M4p and M4n in the arithmetic circuit CC[1,j] are turned OFF. At this timing, the first data w[1,j] is written to the arithmetic circuit CC[1,j]. Specifically, the drive circuit WCD writes wp[1,j] transmitted to wiring IWLp[j] to the arithmetic cell IMp[1,j], and wn[1,j] transmitted to wiring IWLn[j] is written to the respective arithmetic cells IMn[1,j]. By applying a potential corresponding to the value of wp[1,j] to the wiring WCLp[j] and a potential corresponding to the value of wn[1,j] to the wiring WCLn[j], the resistance value of the resistance change element MRp changes in the calculation cell IMp[1,j] according to wp[1,j], and the resistance value of the resistance change element MRn changes in the calculation cell IMn[1,j] according to wn[1,j]. As a result, the first data w[1,j] is written to the calculation circuit CC.

[0400] After a high-level potential is applied to wiring WXLp[1] and wiring WSL[1], a high-level potential is applied to the next row of wiring WXLp[2] and wiring WSL[2]. At this timing, the first data w[2,j] is written to the arithmetic circuit CC[2,j]. Specifically, wp[2,j] sent to wiring IWLp[j] is written to the arithmetic cell IMp[2,j], and wn[2,j] sent to wiring IWLn[j] is written to the arithmetic cell IMn[2,j]. After the first data w[2,j] is written to the arithmetic cells IMp[2,j] and IMn[2,j] of the second row, the first data w is written sequentially to the arithmetic cells IMp and IMn from the third row to the mth row.

[0401] During period TW, as described above, when a high-level potential is sequentially applied to wiring WXL[1] through WXL[m], the first data w transmitted to wiring IWL[j] is written to the calculation cells IMp and IMn of that row.

[0402] During period TR, when multiplication is performed in each of the multiple arithmetic circuits CC in the j-th column of the cell array CA, a high-level potential is first applied to the wiring SWLB to turn on switches SBp[j] and SBn[j]. As a result, a potential V is transmitted from circuit ITSa to wiring WCLp[j] and WCLn[j]. Ｓ It is given.

[0403] Furthermore, while switches SBp[j] and SBn[j] are in the ON state, the drive circuit WXCD applies a potential to each of the wires WXLp[1] to WXLp[m] collectively, corresponding to xp[1] to xp[m], and applies a potential to each of the wires WXLn[1] to WXLn[m] collectively, corresponding to xn[1] to xn[m]. In addition, the drive circuit XSD applies a high-level potential to each of the wires XSL[1] to XSL[m] collectively.

[0404] Furthermore, during period TR, xp given to wiring WXLp[1] to wiring WXLp[m], xn given to wiring WXLn[1] to wiring WXLn[m], and the high-level potential given to wiring XSL[1] to wiring XSL[m] are assumed to be given simultaneously to each other. In other words, the timing at which the second data x is simultaneously given to wiring WXLp[1] to wiring WXLp[m] and wiring WXLn[1] to wiring WXLn[m], and the timing at which the high-level potential is simultaneously given to wiring XSL[1] to wiring XSL[m] are assumed to coincide with each other.

[0405] When a high-level potential is applied to wiring XSL[1] through wiring XSL[m], transistors M3p and M3n included in arithmetic circuits CC[1,j] through CC[m,j] are turned ON.

[0406] When xp is "1" and xn is "0", transistors M1p and M1n are ON, and transistors M4p and M4n are OFF, so V is present between the first and third terminals of the resistive switching element MRp. Ｒ -V Ｓ When a voltage is applied, a tunnel current corresponding to the wp written to the resistive switching element MRp flows through the first terminal to the third terminal into the wiring WCLp[j]. Similarly, a tunnel current corresponding to the wn written to the resistive switching element MRn flows through the first terminal to the third terminal into the wiring WCLn[j].

[0407] Furthermore, when xp is "0" and xn is "1", transistors M1p and M1n are in the off state, and transistors M4p and M4n are in the on state. As a result, a tunnel current corresponding to the wp written to the resistive switching element MRp flows through the first terminal to the third terminal and into the wiring WCLn[j]. Similarly, in the resistive switching element MRn, a tunnel current corresponding to the wn written to the resistive switching element MRn flows through the first terminal to the third terminal and into the wiring WCLp[j].

[0408] When xp is "0" and xn is "0", transistors M1p, M1n, M4p, and M4n are in the off state, so no tunnel current flows between the first and third terminals of resistive switching elements MRp and MRn. Therefore, no current flows from the calculation cell IMp to the wiring WCLp[j] and WCLn[j], and similarly, no current flows from the calculation cell IMn to the wiring WCLp[j] and WCLn[j].

[0409] Here, as described in Embodiment 1 above, the amount of current flowing from the calculation cell IMp[i,j] to the wiring WCLp is denoted as Ip[i,j], and the amount of current flowing from the calculation cell IMn[i,j] to the wiring WCLn is denoted as In[i,j]. Note that Ip[i,j] and In[i,j] are as described in Operation Example 2 of the arithmetic unit in Embodiment 1 above. Ｂ , I Ｓ This is set to either 0 or 0. In this case, the current Isp[j] flowing from wiring WCLp[j] to the first input terminal of circuit ITSa, the current Isn[j] flowing from wiring WCLn[j] to the second input terminal of circuit ITSa, and the difference current between Isp[j] and Isn[j] can each be expressed as shown in equations (1.1) to (1.3) above. Therefore, during period TR, circuit ITSa determines the difference current between Isp[j] and Isn[j], which is proportional to K, the result of the sum-of-products operation, and a signal corresponding to K is transmitted from the output terminal of circuit ITSa to wiring OL.

[0410] As described above, by configuring the arithmetic unit CDDVD shown in Figure 21, it is possible to perform a sum-of-products operation on a first data set w[1,j] to w[m,j] consisting of three values ​​"-1", "0", and "1", and a second data set x[1,j] to x[m,j] consisting of three values ​​"-1", "0", and "1". Furthermore, by making the circuit ITSa a circuit that performs function calculations, it is possible to perform calculations on a function in which the result of the sum-of-products operation is substituted as a variable.

[0411] <<Example of drive circuit modification 1>> Referring to the timing chart in Figure 28, which is an example of the operation of the calculation unit CDDVD in Figure 21, during period TW, when a high-level potential is applied to wiring WXLp[i], a high-level potential is also applied to wiring WSL[i]. In other words, during period TW, the signals applied to wiring WXLp[i] and wiring WSL[i] can be shared with each other.

[0412] The arithmetic unit CDVE shown in Figure 29 has a configuration in which the drive circuits WSD and WXCD of the arithmetic unit CDDVD in Figure 21 are combined into a single drive circuit WXS3. The drive circuit WXS3 has the function of sharing and outputting the signals to wiring WXL[i] and wiring WSL[i] during the period TW of the timing chart in Figure 28. For this reason, in the arithmetic unit CDVE, the drive circuit WXS3 is connected to wiring WXLp[1] to wiring WXLp[m], wiring WXLn[1] to wiring WXLn[m], and wiring WSL[1] to wiring WSL[m].

[0413] Figure 30 shows an example of the circuit configuration of the drive circuit WXS3. The drive circuit WXS3 in Figure 30 is a modified version of the drive circuit WXCD in Figure 22, and is configured by adding switches SDb[1] to SDb[m], switches SDc[1] to SDc[m], and level shifters LW[1] to LW[m] to the drive circuit WXCD. Therefore, for some of the configurations of the drive circuit WXS3, you can refer to the explanation of the drive circuit WXCD in Figure 22.

[0414] Switch SDb and switch SDc can each be switches applicable to switch SAP or switch SAN. Furthermore, for level shifter LW, refer to the description of level shifter LVp or level shifter LVn in Figure 22.

[0415] Let's focus on row i of the drive circuit WXS3. The first terminal of switch SDb[i] is connected to the output terminal of switch circuit SWp[i], the input terminal of level shifter LVp[i], and the second output terminal of selector SLC[i]. The second terminal of switch SDb[i] is connected to the first terminal of switch SDc[i] and the input terminal of level shifter LW[i]. The second terminal of switch SDc[i] is connected to wiring VSE. The control terminal of switch SDb[i] is connected to wiring SLLb, and the control terminal of switch SDc[i] is connected to wiring SLL.

[0416] The wiring VSE functions as a wiring that provides a fixed potential, similar to the wiring VSE in Figure 22. In particular, it is preferable that this fixed potential is the potential that turns off transistors M4p and M4n included in the arithmetic circuit CC. Furthermore, the wiring VSE can be a wiring that provides a fixed potential corresponding to a non-selection signal transmitted to the arithmetic circuit CC, which is not the destination for writing the first data. As a result, for example, in the case of the arithmetic circuit CC shown in Figure 19, the fixed potential provided by the wiring VSE can be a low-level potential.

[0417] In the drive circuit WXS3, the wiring SLL functions not only as a wiring for transmitting control signals to the control terminal of selector SLC, but also as a wiring for transmitting control signals to the control terminal of switch SDc. Furthermore, the wiring SLLb functions not only as a wiring for transmitting control signals to the control terminal of switch SDa, but also as a wiring for transmitting control signals to the control terminal of switch SDb. In particular, the control signal can be a signal in which the logic of the signal input to the above wiring SLL is inverted, similar to the control signal transmitted to wiring SLLb in Figure 22.

[0418] Next, an example of the operation of the drive circuit WXS3 will be described. For an example of the operation of the drive circuit WXS3 when sequentially writing the first data to each of the multiple arithmetic circuits CC of the arithmetic unit CDVE, please refer to the timing chart in Figure 25.

[0419] In the period T31 to T33 of Figure 25, a high-level potential is applied to the control terminals of switches SDa[i] and SDb[i], so switches SDa[i] and SDb[i] are both in the ON state. Also, a low-level potential is applied to the control terminal of switch SDc[i], so switch SDc[i] is in the OFF state. As a result, the signal output from the second output terminal of selector SLC[i] can be applied to wiring WXLp[i] via level shifter LVp[i] and to wiring WSL[i] via level shifter LW[i]. Therefore, in the arithmetic circuit CC of Figure 19, transistors M1p, M2p, M1n, and M2n can be simultaneously in the ON or OFF state.

[0420] Furthermore, since a fixed potential (here referred to as a low-level potential) from wiring VSE is supplied to wiring WXLn[i] via level shifter LVn[i], transistors M4p and M4n can be simultaneously turned off in the arithmetic circuit CC of Figure 19.

[0421] Furthermore, for an example of the operation of the drive circuit WXS3 when multiple arithmetic circuits CC of the arithmetic unit CDVE perform multiplication of the first data and the second data, refer to the timing chart in Figure 26. Note that from period T34 onward, a high-level potential is applied to wiring SLL, and a low-level potential is applied to wiring SLLb.

[0422] In the period T34 to T36 of Figure 26, a low-level potential is applied to the control terminals of switches SDa[i] and SDb[i], so switches SDa[i] and SDb[i] are both in the off state. Also, a high-level potential is applied to the control terminal of switch SDc[i], so switch SDc[i] is in the on state. As a result, a signal corresponding to the second data output from the output terminal of the sequential circuit LTp[i] is supplied to the wiring WXLp[i] via the switch circuit SWp[i] and level shifter LVp[i], and a signal corresponding to the second data output from the output terminal of the sequential circuit LTn[i] is supplied to the wiring WXLn[i] via the switch circuit SWn[i] and level shifter LVn[i]. Therefore, in the arithmetic circuit CC of Figure 19, signals corresponding to the second data can be supplied to the gates of transistors M1p, M1n, M4p, and M4n.

[0423] Furthermore, a fixed potential (referred to here as a low-level potential) from wiring VSE can be applied to wiring WSL[i] via level shifter LW[i]. This allows the fixed potential to be applied to the gates of transistors M2p and M2n, thereby turning off transistors M2p and M2n.

[0424] As shown in Figure 29 of the arithmetic unit CDVE, by using the drive circuit WXS3, the signals supplied to the wiring WXLp[i] and wiring WSL[i] can be shared when writing the first data to the arithmetic unit CC. Furthermore, since the drive circuit WXS3 of the arithmetic unit CDVE combines the functions of the drive circuit WXCD and the drive circuit WSD in the arithmetic unit CDDVD shown in Figure 21, the circuit area of ​​the arithmetic unit CDVE can be made smaller than that of the arithmetic unit CDDVD.

[0425] <<Example of modification of the drive circuit 2>> Referring to the timing chart in Figure 28, which is an example of the operation of the calculation unit CDDVD in Figure 21, during period TR, when a signal (high-level potential or low-level potential) corresponding to the second data is applied to the wiring WXLp[i] and wiring WXLn[i], a high-level potential is applied to the wiring XSL[i]. However, when the value of the second data x is 0, that is, when xp is "0" and xn is "0", in the calculation circuit CC in Figure 19, even if a high-level potential is applied from wiring XSL to the gates of transistors M3p and M3n, no current flows from calculation cell IMp to wiring WCLp and wiring WCLn, and no current flows from calculation cell IMn to wiring WCLn and wiring WCLp. In other words, when the value of the second data x is 0, the potential applied from wiring XSL to the gates of transistors M3p and M3n may be a low-level potential.

[0426] On the other hand, if the value of the second data x is "-1" or "1", that is, if one of xp and xn is "0" and the other is "1", then in the calculation circuit CC of Figure 19, a high-level potential needs to be applied from the wiring XSL to the gates of transistors M3p and M3n, respectively.

[0427] One aspect of the present invention, a semiconductor device, has been made in view of the above, and has the function of generating a signal to be transmitted to wiring XSL using signals provided to wiring WXLp and wiring WXLn, respectively.

[0428] The arithmetic unit CDVF shown in Figure 31 has a configuration in which the drive circuits WSD, XSD, and WXCD of the arithmetic unit CDDVD in Figure 21 are combined into a single drive circuit WXS4. Furthermore, the drive circuit WXS4 can be described as a configuration in which the drive circuits WXS3 and XSD of the arithmetic unit CDVE in Figure 29 are combined. Therefore, for some aspects of the drive circuit WXS4, the explanation of the drive circuit WXS3 can be referenced.

[0429] The drive circuit WXS4 has the function of sharing and outputting signals to wiring WXL[i] and wiring WSL[i] during the period TW of the timing chart in Figure 28, and the function of generating and outputting a signal to wiring XSL[i] using signals transmitted to wiring WXLp[i] and wiring WXLn[i] during the period TR of the timing chart in Figure 28. For this reason, in the arithmetic unit CDVF, the drive circuit WXS4 is connected to wiring WXLp[1] to wiring WXLp[m], wiring WXLn[1] to wiring WXLn[m], wiring WSL[1] to wiring WSL[m], and wiring XSL[1] to wiring XSL[m].

[0430] An example of the circuit configuration of the drive circuit WXS4 is shown in Figure 32. The drive circuit WXS4 in Figure 32 is a modified version of the drive circuit WXS3 in Figure 30, and is configured by adding switches SDd[1] to SDd[m], switches SDe[1] to SDe[m], logic circuits LGO[1] to LGO[m], and level shifters LX[1] to LX[m] to the drive circuit WXS3. Therefore, for some of the configurations of the drive circuit WXS4, you can refer to the explanation of the drive circuit WXS3 in Figure 30.

[0431] Switch SDd and Switch SDe can use switches applicable to Switch SAP or Switch SAN. Furthermore, for each of the Level Shifters LX[1] to LX[m], refer to the description of Level Shifter LVp or Level Shifter LVn in Figure 22.

[0432] Let's focus on row i of the drive circuit WXS4. The first input terminal of the logic circuit LGO[i] is connected to the second output terminal of the selector SLC[i], the output terminal of the switch circuit SWp[i], the first terminal of the switch SDb[i], and the input terminal of the level shifter LVp[i]. The second input terminal of the logic circuit LGO[i] is connected to the output terminal of the switch circuit SWn[i], the first terminal of the switch SDa[i], and the input terminal of the level shifter LVn[i]. The output terminal of the logic circuit LGO[i] is connected to the first terminal of the switch SDd[i], the second terminal of the switch SDd[i] is connected to the first terminal of the switch SDe[i], and the input terminal of the level shifter LX[i], and the control terminal of the switch SDd[i] is connected to wiring SLL. The second terminal of switch SDe[i] is connected to wiring VSE, and the control terminal of switch SDe[i] is connected to wiring SLLb.

[0433] In the drive circuit WXS4, the wiring SLL functions not only as a wire for transmitting control signals to the control terminals of selector SLC and switch SDc, but also as a wire for transmitting control signals to the control terminal of switch SDd. Furthermore, the wiring SLLb functions not only as a wire for transmitting control signals to the control terminals of switch SDa and switch SDb, but also as a wire for transmitting control signals to the control terminal of switch SDe.

[0434] The logic circuit LGO can be an OR circuit (logical disjunction circuit) as an example. Specifically, the logic circuit LGO has the function of outputting "1" from the output terminal when one or both of the logic inputs to the first input terminal and the second input terminal are "1", and outputting "0" from the output terminal when both of the logic inputs to the first input terminal and the second input terminal are "0".

[0435] Next, an example of the operation of the drive circuit WXS4 will be described. For an example of the operation of the drive circuit WXS4 when sequentially writing the first data to each of the multiple arithmetic circuits CC of the arithmetic unit CDVF, please refer to the timing chart in Figure 25. Note that a low level potential is always applied to wiring SLL, and a high level potential is always applied to wiring SLLb.

[0436] Focusing on row i of the drive circuit WXS4, during periods T31 to T33 shown in Figure 25, a high-level potential is applied to the control terminals of switches SDa[i], SDb[i], and SDe[i], so switches SDa[i], SDb[i], and SDe[i] are in the ON state. Also, a low-level potential is applied to the control terminals of switches SDc[i] and SDd[i], so switches SDc[i] and SDd[i] are in the OFF state.

[0437] This allows the signal output from the second output terminal of selector SLC[i] to be supplied to wiring WXLp[i] via level shifter LVp[i] and to wiring WSL[i] via level shifter LW[i]. Therefore, in the arithmetic circuit CC of Figure 19, transistors M1p and M2p, and transistors M1n and M2n can be simultaneously turned on or off. Furthermore, a fixed potential (here referred to as a low-level potential) from wiring VSE is supplied to wiring WXLn[i] via level shifter LVn[i]. Therefore, in the arithmetic circuit CC of Figure 19, transistors M4p and M4n can be simultaneously turned off. Also, a fixed potential from wiring VSE is supplied to wiring XSL[i] via level shifter LX[i]. Therefore, in the arithmetic circuit CC of Figure 19, transistors M3p and M3n can be simultaneously turned off.

[0438] During periods T31 to T33, since switch SDd[i] is in the off state, regardless of the potential supplied to the first and second input terminals of logic circuit LGO[i], no potential is supplied to the input terminal of level shifter LX[i] from the output terminal of logic circuit LGO[i].

[0439] Furthermore, for an example of the operation of the drive circuit WXS4 when multiple arithmetic circuits CC of the arithmetic unit CDDVD perform multiplication of the first data and the second data, refer to the timing chart in Figure 26. Note that from period T34 onward, a high-level potential is applied to wiring SLL, and a low-level potential is applied to wiring SLLb.

[0440] Focusing on row i of the drive circuit WXS4, during periods T34 to T36 shown in Figure 26, a low-level potential is applied to the control terminals of switches SDa[i], SDb[i], and SDe[i], so switches SDa[i], SDb[i], and SDe[i] are in the off state. Also, a high-level potential is applied to the control terminals of switches SDc[i] and SDd[i], so switches SDc[i] and SDd[i] are in the on state. This allows a signal corresponding to xp, one of the two variables of the second data output from the output terminal of the sequential circuit LTp[i], to be supplied to the wiring WXLp[i] via the switch circuit SWp[i] and the level shifter LVp[i], and a signal corresponding to xn, the other of the two variables of the second data output from the output terminal of the sequential circuit LTn[i], to be supplied to the wiring WXLn[i] via the switch circuit SWn[i] and the level shifter LVn[i]. Therefore, in the arithmetic circuit CC of Figure 19, signals corresponding to the second data can be supplied to the gates of transistors M1p, M1n, M4p, and M4n, respectively.

[0441] Furthermore, a fixed potential (referred to here as a low-level potential) from wiring VSE can be applied to wiring WSL[i] via level shifter LW[i]. This allows the fixed potential to be applied to the gates of transistors M2p and M2n, thereby turning off transistors M2p and M2n.

[0442] Furthermore, during periods T34 to T36, since switch SDd[i] is ON, a potential corresponding to the logical OR of xp (one of the two variables input to the first input terminal) and xn (the other of the two variables input to the second input terminal), generated by logic circuit LGO[i], is supplied from the output terminal of logic circuit LGO[i] to the input terminal of level shifter LX[i]. Specifically, when at least one of xp and xn is "1" (when the second data x is "-1" or "1"), logic circuit LGO[i] supplies a high-level potential to the input terminal of level shifter LX[i], and when both xp and xn are "0" (when the second data x is "0"), logic circuit LGO[i] supplies a low-level potential to the input terminal of level shifter LX[i]. As a result, in the arithmetic circuit CC in Figure 19, the gates of transistors M3p and M3n are each given a potential corresponding to the logical OR of xp and xn, and the open / closed state of transistors M3p and M3n is determined by this potential. Specifically, when the second data is "0", transistors M3p and M3n are in the off state, and when the second data is "-1" or "1", transistors M3p and M3n are in the on state.

[0443] Furthermore, when the second data x is "0", transistors M1p and M1n, and transistors M4p and M4n are all in the off state, so in the arithmetic circuit CC of Figure 19, no current flows from the arithmetic circuit CC to the wiring WCLp, and no current flows from the arithmetic circuit CC to the wiring WCLn. Also, when the second data is "-1" or "1", one of the pairs of transistors M1p and M1n, and the pair of transistors M4p and M4n are in the on state, and the other is in the off state, so current flows from the arithmetic circuit CC to the wiring WCLp, and from the arithmetic circuit CC to the wiring WCLn, according to the result of multiplying the first data and the second data.

[0444] As described above, the arithmetic unit CDVF in Figure 31, which includes the drive circuit WXCD, drive circuit WSD, and drive circuit XSD shown in Figure 21, and a drive circuit WXS4 that combines them, can also perform sum-of-products calculations between the first data and the second data, similar to the operation example of the arithmetic unit CDV2 in Figure 21.

[0445] Furthermore, as shown in the arithmetic unit CDVF in Figure 31, by using the drive circuit WXS4, the signals given to wiring WXLp[i] and wiring WSL[i] can be shared when writing the first data to the arithmetic unit CC. Moreover, when multiplying the first data and the second data in the arithmetic unit CC, the signals given to wiring WXLp and wiring WXLn can be used to generate a signal to be transmitted to wiring XSL[i]. In addition, since the drive circuit WXS4 of the arithmetic unit CDVF combines the functions of the drive circuit WXS3 and drive circuit XSD in the arithmetic unit CDVE in Figure 29, the circuit area of ​​the arithmetic unit CDVF can be made smaller than that of the arithmetic unit CDVE.

[0446] This embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, and methods shown in this embodiment can be appropriately combined with other configurations, structures, and methods shown in this embodiment. Also, for example, the configurations, structures, and methods shown in this embodiment can be appropriately combined with configurations, structures, and methods shown in other embodiments.

[0447] (Embodiment 3) In this embodiment, an example of the layout of the arithmetic circuit, an example of the cross-sectional structure, etc., related to a semiconductor device according to one aspect of the present invention described in the above embodiment will be explained.

[0448] <Example of Semiconductor Device Circuit Layout> Figure 33 is a schematic plan view of a circuit showing an example of the circuit configuration of the arithmetic cell IMp and arithmetic cell IMn shown in Figure 4, which are semiconductor devices described in the above embodiment. As an example, Figure 33 shows the arithmetic cell IMp[h,k] and arithmetic cell IMn[h,k] located in the h row and k column (h and k are integers of 1 or more), and the arithmetic cell IMp[h+1,k] and arithmetic cell IMn[h+1,k] located in the h+1 row and k column.

[0449] The schematic plan view of Figure 33 shows an example of a circuit layer containing the calculation cells IMp[h,k], IMp[h+1,k], IMn[h,k], and IMn[h+1,k] in a plan view. This circuit layer includes conductive layers 232, 233, 234, 235, 236, 237, semiconductor layer 251, and layer 220. For clarity, the insulating layer included in this circuit layer is not shown in the schematic plan view of Figure 33.

[0450] In Figure 33, each of the transistors M1p to M3p and M1n to M3n has an island-shaped insulating layer, a semiconductor layer 251 formed on the insulating layer, a conductive layer 232 formed on the semiconductor layer 251, a gate insulating film formed on the semiconductor layer 251, and a conductive layer 233 formed on the gate insulating film. Furthermore, each of the transistors listed above can have a GL (Gate Last) structure, which will be described later.

[0451] Furthermore, in Figure 33, each of the resistive switching element MRp and the resistive switching element MRn has a layer 220 and a portion of a conductive layer 235. The portion of the conductive layer 235 includes a first region that functions as a first terminal, a second region that functions as a second terminal, and a region located between the first and second regions that is in contact with a conductive layer (not shown) that functions as the free layer of the MTJ element. Layer 220 is formed in this region. Layer 220 has a conductive layer that functions as the free layer of the MTJ element, an insulating layer (not shown) that includes a tunnel insulator of the MTJ element, and a conductive layer that functions as the fixed layer of the MTJ element.

[0452] For example, the semiconductor layer 251 is located below the conductive layers 232 and 233. For example, the conductive layer 234 is located above the conductive layers 232 and 233. For example, the conductive layer 235 is located above the conductive layer 234. For example, the conductive layer 236 is located above the conductive layer 235. For example, the conductive layer 237 is located above the conductive layer 236 and the layer 220, which will be described later. The formation order can be, for example, semiconductor layer 251 first, conductive layer 232 second, conductive layer 233 third, conductive layer 234 fourth, conductive layer 235 fifth, layer 220 sixth, conductive layer 236 seventh, and conductive layer 237 eighth. In the schematic plan view of Figure 33, a portion of the conductive layer 234 has a region that overlaps with the conductive layer 236.

[0453] In the schematic plan view of Figure 33, a portion of the conductive layer 232 functions, for example, as the source or drain of transistors M1p to M3p and transistors M1n to M3n, respectively. Furthermore, a portion of the conductive layer 233 functions, for example, as the gate of the transistors listed above.

[0454] Furthermore, the conductive layer 234 functions, for example, as wiring to connect the conductive layer 232 and the conductive layer 235 electrically. For this reason, the conductive layer 234 is sometimes referred to as a contact plug. Similarly, the conductive layer 236 functions, for example, as wiring to connect the conductive layer 235 and the conductive layer 237 electrically. For this reason, the conductive layer 236 is sometimes referred to as a contact plug.

[0455] Furthermore, a portion of each of the conductive layer 233 and conductive layer 237 functions as wiring. For example, a portion of the conductive layer 233 is provided as wiring WXL[h], wiring WSL[h], wiring XSL[h], wiring WXL[h+1], wiring WSL[h+1], and wiring XSL[h+1], extending in the left-right direction of the drawing. Also, for example, a portion of the conductive layer 237 is provided as wiring WCLp[k], wiring WCLn[k], wiring VWE, and wiring VRE, extending in the up-down direction of the drawing. For this reason, it is preferable to use a highly conductive material for each of the conductive layer 233 and conductive layer 237. Furthermore, since a portion of each of the conductive layer 233 and conductive layer 237 also functions as wiring, it is preferable to use a highly conductive material for each of the conductive layer 233 and conductive layer 237.

[0456] Furthermore, each of the conductive layers described above can be formed, for example, using lithography. Specifically, for example, when forming the conductive layer 233, the conductive material that will become the conductive layer 233 can be formed using one or more methods selected from sputtering, CVD (Chemical Vapor Deposition), PLD (Pulsed Laser Deposition), and ALD (Atomic Layer Deposition), and then the desired pattern can be formed by lithography. In addition, conductive layers other than the conductive layer 233, semiconductor layers, and insulating layers can also be formed by the same methods as described above.

[0457] In this specification, lithography includes, for example, photolithography, ion beam lithography, X-ray lithography, electron beam lithography, multiphoton lithography, interference lithography, and nanoimprinting.

[0458] In the regions where conductive layers 233 and 237 extend as wiring, parasitic capacitance may form in the regions where they overlap. If the parasitic capacitance is large, the time required for charging and discharging in the wiring will be longer, which may slow down the operation speed of the computing unit. Therefore, it is preferable to have small parasitic capacitance. In Figure 33, the area of ​​the region is formed to be small in order to reduce parasitic capacitance. Specifically, in the region, the width of the wiring on which conductive layers 233 and 237 extend is formed to be shorter than that of the other.

[0459] Specifically, in a portion of the conductive layer 233 that functions as wiring, the width of the wiring is d1, and in the region where the conductive layer 233 overlaps with the conductive layer 237 and in its vicinity, the width of the wiring is shorter than d1, d2. Similarly, in a portion of the conductive layer 237 that functions as wiring, the width of the wiring is d3, and in the region where the conductive layer 237 overlaps with the conductive layer 233 and in its vicinity, the width of the wiring is shorter than d3, d4. In this way, by shortening the width of the overlapping wiring in the region where the conductive layer 233 and the conductive layer 237 overlap each other and in its vicinity, the parasitic capacitance formed in that region can be reduced. This makes it possible to improve the driving speed of the computing unit.

[0460] Furthermore, in Figure 33, the size of transistor M1p is shown with channel length d11 and channel width d12. As mentioned above, transistor M1p functions as a switching transistor, so it is preferable that the off-current of transistor M1p be small. Specifically, for example, the off-current of transistor M1p can be reduced by increasing the channel length d11 and decreasing the channel width d12 of transistor M1p. Relatively speaking, it is preferable that the channel length d11 of transistor M1p be longer than the channel width d12. By reducing the off-current of transistor M1p, it is possible to prevent malfunctions and failures of the arithmetic unit due to current leakage.

[0461] Furthermore, since transistors M2p, M3p, and M1n to M3n each also function as switching transistors, it is preferable to increase the channel length and decrease the channel length for these transistors as well. Relatively speaking, it is preferable to make the channel length longer than the channel width.

[0462] Note that the schematic plan view of a semiconductor device according to one embodiment of the present invention is not limited to Figure 33. The schematic plan view of an arithmetic circuit according to one embodiment of the present invention can be modified from Figure 33 as appropriate, depending on the circumstances.

[0463] <Example of Cross-Sectional Device Configuration> Figure 34 is a schematic cross-sectional diagram showing an example of the configuration of the arithmetic unit CDV and arithmetic unit CDVA (sometimes collectively referred to as arithmetic unit CDVZ) described in the above embodiment. The arithmetic unit CDVZ shown in Figure 34, as an example, has a configuration that includes circuit layer PHRL and circuit layer OMAL located above circuit layer PHRL. In the schematic cross-sectional diagram of Figure 34, the arithmetic unit CDVZ has a configuration in which transistors M1p to M3p, transistors M1n to M3n, resistive switching element MRp, and resistive switching element MRn are each included in circuit layer OMAL.

[0464] Note that the circuit layer OMAL in the cross-sectional schematic diagram of Figure 34 shows transistors M1p, M2p, and the resistive switching element MRp, respectively, and therefore the arrangement of circuit elements differs from that in the plan schematic diagram shown in Figure 33.

[0465] The circuit layer PHRL can be constructed, for example, by providing circuit elements such as transistors and capacitive elements on a substrate. A semiconductor substrate (for example, a single-crystal substrate made of silicon or germanium) can be used as the substrate. Other substrates that can be used include, for example, SOI (Silicon On Insulator) substrates, glass substrates, quartz substrates, plastic substrates, sapphire glass substrates, metal substrates, stainless steel substrates, substrates with stainless steel foil, tungsten substrates, substrates with tungsten foil, flexible substrates, laminated films, paper containing fibrous materials, or base films. In this embodiment, the substrate included in the circuit layer PHRL will be described as a semiconductor substrate containing silicon.

[0466] By using a silicon semiconductor substrate as the substrate included in the circuit layer PHRL, the transistors included in each of the drive circuits WCD, WXCD, WSD, XSD, and ITS shown in Figure 1 can be formed on the semiconductor substrate. Similarly, the transistors included in each of the drive circuits WCD, WXCD, WSD, XSD, and ITS shown in Figure 4 can be formed on the semiconductor substrate. In this case, the transistors will be Si transistors. Since Si transistors have high field-effect mobility, they can carry large on-currents. This makes it possible to increase the driving speed of each of the drive circuits listed above, widen the signal range, and so on.

[0467] Figure 34 illustrates a transistor 100 in the circuit layer PHRL. By making transistor 100, for example, a Si transistor, a CMOS circuit including a p-channel transistor and an n-channel transistor can be configured in the circuit layer PHRL. In particular, the drive circuit WXCD described in the above embodiment includes, for example, a shift register, a selector, a sequential circuit, etc., and these circuits can be made into a CMOS circuit including a p-channel transistor and an n-channel transistor. Also, the drive circuit ITS described in the above embodiment includes, for example, a differential amplifier circuit, and this differential amplifier circuit can be made into a CMOS circuit including a p-channel transistor and an n-channel transistor. It is preferable that the drive circuits WCD, WXCD, WSD, XSD, and ITS are provided in the circuit layer PHRL as CMOS circuits.

[0468] Furthermore, the laminated structure of circuit layer PHRL and circuit layer OMAL can be fabricated by directly forming circuit layer OMAL on top of circuit layer PHRL. Alternatively, circuit layer OMAL can be fabricated by mounting the substrate on top of circuit layer PHRL, with circuit elements such as transistors and capacitive elements provided on the substrate. When circuit layer OMAL is directly formed on top of circuit layer PHRL, it is preferable that circuit layer OMAL includes an OS transistor. An I / O transistor can be used as the OS transistor. Since the OS transistor can be formed on a substrate such as a semiconductor substrate, an insulating substrate, or a conductive substrate, or on a film such as a conductive film, an insulating film, or a semiconductor film, it can be easily provided on a semiconductor substrate (on circuit layer PHRL) on which a Si transistor is formed.

[0469] Alternatively, p-channel transistors may be provided as Si transistors in the circuit layer PHRL, and n-channel transistors may be provided as OS transistors in the circuit layer OMAL. Specifically, for example, transistors M1p to M3p and transistors M1n to M3n included in the arithmetic circuit CC shown in Figure 1 may be provided in the circuit layer OMAL.

[0470] Furthermore, when forming circuit elements such as transistors and capacitive elements on a substrate as the circuit layer OMAL, and mounting the substrate on the circuit layer PHRL, a flip-chip bonding method or a wire bonding method can be used. Alternatively, the circuit layer OMAL may be mounted on the circuit layer PHRL by providing a first bonding layer on the circuit layer PHRL side, providing a second bonding layer on the circuit layer OMAL substrate, and bonding the first bonding layer and the second bonding layer using either or both of the surface activation bonding method and the hydrophilic bonding method. In particular, a bonding method in which copper (Cu) is used as the conductor in both the first and second bonding layers, and the copper is bonded to each other, is called Cu-Cu (copper-copper) direct bonding.

[0471] The transistor 100 is provided on a substrate 101 and includes a conductive layer 131 that functions as a gate, an insulating layer 161 and an insulating layer 111 that functions as a gate insulating film, a semiconductor region 171 that includes a part of the substrate 101, and a low-resistance region 172a and a low-resistance region 172b that include a part of the substrate and function as a source region or drain region.

[0472] Furthermore, the semiconductor region 171, the low-resistance region 172a, and the low-resistance region 172b, each included in the transistor 100 shown in Figure 34, are formed by providing an element isolation layer 102 on the substrate 101. It can also be said that the element isolation layer 102 is provided to separate the multiple transistors formed on the substrate 101. The element isolation layer 102 can be formed, for example, using the LOCOS (Local Oxidation of Silicon) method, the STI (Shallow Trench Isolation) method, or the mesa isolation method.

[0473] Furthermore, the transistor 100 shown in Figure 34 may, as an example, have a convex shape in the semiconductor region 171 (part of the substrate 101) where the channel is formed, as shown in the schematic cross-sectional view of Figure 35. Figure 35 is a schematic cross-sectional view of the transistor 100 in the channel width direction. The side and top surfaces of the semiconductor region 171 are covered by a conductive layer 131 via an insulating layer 161. The conductive layer 131 may be made of a material that adjusts the work function. Such a transistor 100 is also called a fin-type transistor because it utilizes the convex portion of the semiconductor substrate. It may also have an insulating layer that is in contact with the upper part of the convex portion and functions as a mask for forming the convex portion. In addition, although the case of forming the convex portion by processing a part of the semiconductor substrate is shown here, a semiconductor film having a convex shape may be formed by processing an SOI substrate.

[0474] Furthermore, in Figure 35, a conductive layer 136 is provided so as to be in contact with the conductive layer 131 and to fill the opening formed in the insulating layer 112. The conductive layer 136 will function as a contact plug or wiring, as described later.

[0475] Note that the transistor 100 shown in Figures 34 and 35 is just one example, and its structure is not limited to that; any appropriate transistor can be used depending on the circuit configuration or driving method.

[0476] The CDVZ computing unit may be provided with a wiring layer having an interlayer film, wiring, and a plug. Furthermore, multiple wiring layers may be provided depending on the design. Also, in this specification, the wiring and the plug connected to the wiring may be a single integrated unit. That is, there may be cases where a part of the conductive layer functions as wiring, and cases where a part of the conductive layer functions as a plug.

[0477] For example, on the transistor 100, insulating layers 112, 181, and 113 are sequentially stacked as interlayer films. A conductive layer 132 is embedded in the insulating layer 112. A conductive layer 133 is embedded in the insulating layer 181 and the insulating layer 113. The conductive layers 132 and 133 function as contact plugs or wiring.

[0478] Furthermore, the insulating layer, which functions as an interlayer film, may also function as a planarizing film that covers the uneven shape beneath it. For example, the upper surface of the insulating layer 112 may be planarized by a planarizing treatment using chemical mechanical polishing (CMP) to improve its flatness.

[0479] Wiring layers may be provided on the insulating layer 113 and the conductive layer 133. For example, in Figure 34, insulating layers 182, 114, 115, and 116 are sequentially laminated on the insulating layer 113 and the conductive layer 133. Furthermore, conductive layers 134 are formed on insulating layers 182, 114, and 115. The conductive layer 134 functions as a contact plug or wiring.

[0480] An insulating layer 281 is provided on the insulating layer 116. Preferably, contact plugs or wiring for connecting to an upper circuit (for example, a circuit element included in a circuit included in the circuit layer OMAL) are embedded in the insulating layer 116 and the insulating layer 281.

[0481] For example, conductive layers 132, 133, 134, and 136 can be made from materials applicable to conductive layers 232 to 237, which will be described later.

[0482] Next, we will describe an example of the configuration of the arithmetic cells included in the circuit layer OMAL shown in Figure 34.

[0483] In the circuit layer OMAL of Figure 34, transistors M1p and M2p are each formed on the insulating layer 281. The resistive switching element MRp is formed on the insulating layer 284. The insulating layer 284 is located above the insulating layer 281. Therefore, it can be said that the resistive switching element MRp is located above transistors M1p and M2p.

[0484] Furthermore, it is preferable that each of the insulating layers 181, 182, 281, and 284 shown in Figure 34 functions as a barrier insulating film that suppresses the permeation of impurities such as water and hydrogen. Therefore, insulating layers 181, 182, 281, and 284 are designed to suppress the permeation of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (for example, N ２ O, NO, or NO ２ It is preferable to use an insulating material that has the function of suppressing the diffusion of impurities such as copper atoms and copper atoms (i.e., the above impurities do not easily permeate). Alternatively, it is preferable to use an insulating material that has the function of suppressing the diffusion of oxygen (e.g., either or both oxygen atoms and oxygen molecules) (i.e., the above oxygen does not easily permeate). For materials that can be applied to insulating layer 181, insulating layer 182, insulating layer 281, and insulating layer 284, refer to the description of the insulating layer of the transistor constituent materials.

[0485] Furthermore, a conductive layer 237, which functions as wiring WCLp, is connected to either the source or drain electrode of transistor M1p via conductive layers 234, 235, and 236. The other source or drain electrode of transistor M1p is connected via conductive layer 234 to a region of conductive layer 235 that functions as the first terminal of the resistive element MRp. Conductive layers 234 and 236 each function as contact plugs. In addition, a portion of conductive layer 233 functions as the gate electrode of transistor M1p.

[0486] Furthermore, a conductive layer 237, which functions as wiring VWE, is connected to either the source or drain electrode of transistor M2p via conductive layers 234, 235, and 236. The other source or drain electrode of transistor M2p is connected via conductive layer 234 to a region of conductive layer 235 that functions as the second terminal of the resistive switching element MRp. In addition, a portion of conductive layer 233 functions as the gate electrode of transistor M2p.

[0487] Furthermore, the gate electrodes of transistors M1p and M2p, for example, extend as a conductive layer 233 along the front-to-back direction in Figure 34.

[0488] The conductive layer 234 is provided so as to be embedded in the openings formed in the insulating layers 213, 283, 214, and 284, which will be described later. In addition, the insulating layer 215 and the conductive layer 235 are provided on the conductive layer 234 and on the insulating layer 284. In particular, the conductive layer 235 is provided so as to be embedded in the openings formed in the insulating layer 215. Layer 220 is provided on the conductive layer 235. In addition, the insulating layer 285 is provided on the side surface of layer 220, on the insulating layer 215, and on the conductive layer 235, and the insulating layer 216 is provided on the insulating layer 285. The conductive layer 236 is provided so as to be embedded in the openings formed in the insulating layer 285 and the insulating layer 216. In addition, the insulating layer 217 is provided on the insulating layer 216. The conductive layer 237 is provided on layer 220 and on the conductive layer 236. In particular, the conductive layer 237 is provided so as to be embedded in the openings formed in the insulating layer 217. Furthermore, an insulating layer 286 is provided on both the insulating layer 217 and the conductive layer 237.

[0489] Furthermore, insulating layers 215 to 217 can be made of materials applicable to insulating layer 213 or insulating layer 214, as described later. Insulating layers 284 to 286 can be made of materials applicable to insulating layer 281 or insulating layer 283, as described later. Conductive layers 235 to 237 can be made of materials applicable to conductive layer 232, conductive layer 233, or conductive layer 234 included in transistor 200, as described later.

[0490] Layer 220 includes a conductive layer 221, an insulating layer 222, a conductive layer 223, and a conductive layer 224. Furthermore, the conductive layer 221, the insulating layer 222, the conductive layer 223, and the conductive layer 224 are provided on the conductive layer 235 in this order.

[0491] The conductive layer 221 is a free layer in the MTJ element and can be the layer FL in Figure 2. The insulating layer 222 is a tunnel insulating layer in the MTJ element and can be the layer TIS in Figure 2. The conductive layer 223 is a fixed layer in the MTJ element and can be the layer RL in Figure 2. Therefore, for the materials applicable to each of the conductive layer 221, insulating layer 222, and conductive layer 223, please refer to the description in Figure 2.

[0492] The conductive layer 224 is provided as a hard mask for forming the conductive layer 221, the insulating layer 222, and the conductive layer 223. The conductive layer 224 can be made of a material that can be used for the conductive layer 232, for example. The conductive layer 224 may also function as the terminal OT shown in Figure 2.

[0493] Furthermore, when a back gate is provided in one or more of the transistors M1p to M3p and M1n to M3n, it is preferable not to provide a conductive layer near the back gate in order to avoid the formation of parasitic capacitance with the back gate.

[0494] It is preferable that each of the transistors M1p to M3p and M1n to M3n is an OS transistor in which an oxide semiconductor, a type of metal oxide, is used in the semiconductor layer where the channel is formed. Since oxide semiconductors have a band gap of 2 eV or more, the off-current is significantly low. Therefore, the power consumption of the arithmetic circuit can be reduced. Therefore, the power consumption of the arithmetic unit CDVZ, including the arithmetic cells IMp and IMn, can be reduced.

[0495] Furthermore, OS transistors operate stably even in high-temperature environments and exhibit minimal characteristic fluctuations. For example, the off-current hardly increases even in high-temperature environments. Specifically, the off-current hardly increases even in environments between room temperature (e.g., 25°C) and 200°C. Also, the on-current does not easily decrease even in high-temperature environments. In addition, the arithmetic cell shown in Figure 34 can hold the first data, thus also functioning as a memory device. For this reason, the arithmetic cell operates stably even in high-temperature environments, resulting in high reliability.

[0496] In particular, by using indium oxide for the oxide semiconductor mentioned above, that is, by making each of transistors M1p to M3p and transistors M1n to M3n I / O transistors, it is possible to create transistors with low off-current and high on-current. This can sometimes lead to the realization of a computing device that combines high reliability and fast operating speed.

[0497] <<Transistor Configuration Example 1>> Next, we will explain a specific configuration example of a transistor called a GL structure (also known as a TGSA (Trench Gate Self Align or Top Gate Self Align) structure) that can be applied to transistors M1p and M2p shown in Figure 34. Transistor 200 shown in Figures 36A and 36B is an example of a GL structure transistor that can be applied to transistors M1p and M2p in Figure 34.

[0498] In particular, Figure 36A shows a schematic cross-sectional view of transistor 200 in the channel length direction, and Figure 36B shows a schematic cross-sectional view of transistor 200 in the channel width direction.

[0499] As shown in Figures 36A and 36B, the transistor 200 includes, for example, a semiconductor layer 251a, a semiconductor layer 251b, a conductive layer 231, a conductive layer 232a, a conductive layer 232b, a conductive layer 233, an insulating layer 212, insulating layers 261 to 264, insulating layers 281 to 283, and insulating layers 212 to 214. However, the transistor 200 may not have all of the above-mentioned components. For example, although the conductive layer 231 functions as a back gate electrode in the transistor 200, the transistor 200 can also be configured without the conductive layer 231, as shown in transistors M1p and M2p in Figure 34.

[0500] The conductive layer 231 (conductive layer 231a and conductive layer 231b) and the insulating layer 212 are arranged on top of the substrate (not shown). In particular, it is preferable that the conductive layer 231 is embedded in the insulating layer 212. Specifically, it is preferable that the conductive layer 231a is provided in contact with the bottom surface and side wall of an opening provided in the insulating layer 212. It is also preferable that the conductive layer 231b is provided so as to be embedded in a recess formed in the conductive layer 231a. In the transistor 200 shown in Figures 36A and 36B, the height of the upper surface of the conductive layer 231b is approximately the same as the height of the upper surface of the conductive layer 231a and the height of the upper surface of the insulating layer 212.

[0501] The insulating layer 212, for example, functions as a planarizing film that flattens steps caused by plugs and the like, similar to the insulating layer 112. Therefore, the insulating layer 212 can be made of a material that functions as a planarizing film, similar to the insulating layer 112.

[0502] Furthermore, by using a material with a low dielectric constant for the insulating layer 212, parasitic capacitance between wirings can be reduced. For example, silicon oxide, silicon oxynitride, silicon oxide nitride, or silicon nitride can be used for the insulating layer 212. Alternatively, for example, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, or porous silicon oxide can be used for the insulating layer 212. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, or porous silicon oxide are particularly preferred because they can easily form regions containing oxygen that is desorbed by heating. Alternatively, for example, resin can be used for the insulating layer 212. The material used for the insulating layer 212 may also be an appropriate combination of the insulating materials described above.

[0503] In this specification, "oxide-nitride" refers to a material whose composition contains more oxygen than nitrogen, and "nitride oxide" refers to a material whose composition contains more nitrogen than oxygen. For example, "silicon oxynitride" refers to a material whose composition contains more oxygen than nitrogen, and "silicon nitride oxide" refers to a material whose composition contains more nitrogen than oxygen.

[0504] Furthermore, the semiconductor layer 251 and the conductive layer 233 are arranged in a region that overlaps with the conductive layer 231. The semiconductor layer 251b is arranged on top of the semiconductor layer 251a. The conductive layers 232a and 232b are arranged on top of the semiconductor layer 251b, spaced apart from each other. The insulating layer 213 is arranged on top of the conductive layers 232a and 232b. In particular, the insulating layer 213 has an opening formed in the region between the conductive layers 232a and 232b. The conductive layer 233 is arranged within this opening. The insulating layer 264 is arranged between the semiconductor layer 251b, the conductive layer 232a, the conductive layer 232b, and the insulating layer 213, and the conductive layer 233. Here, as shown in Figures 36A and 36B, it is preferable that the upper surface of the conductive layer 233 substantially coincides with the upper surface of the insulating layer 264 and the insulating layer 213. In the following, conductive layers 231a and 231b may be collectively referred to as conductive layer 231. Also, semiconductor layers 251a and 251b may be collectively referred to as semiconductor layer 251. Furthermore, conductive layers 232a and 232b may be collectively referred to as conductive layer 232.

[0505] Furthermore, as shown in Figure 36A, a low-resistance region 271a may be formed at and near the interface of the semiconductor layer 251b with the conductive layer 232a. Similarly, a low-resistance region 271b may be formed at and near the interface of the semiconductor layer 251b with the conductive layer 232b. In this case, region 271a functions as either a source region or a drain region, and region 271b functions as either a source region or a drain region. In addition, a channel-forming region is formed in the region sandwiched between region 271a and region 271b.

[0506] For the semiconductor layer 251, it is preferable to use a metal oxide that functions as an oxide semiconductor and includes a channel formation region. In particular, indium oxide, as described in Embodiment 4, is preferred as the metal oxide. In addition to indium oxide, various other metal oxides that form the channel formation region of the transistor 200 will also be described below.

[0507] As for the metal oxide that forms the channel formation region of the transistor 200, it is preferable that its band gap is larger than that of silicon (typically 1.1 eV). For example, it is preferable that the band gap of the metal oxide forming the channel formation region be 2 eV or more, preferably 2.5 eV or more. Specifically, for example, in the case of the transistor 200 shown in Figures 36A and 36B, it is preferable to use a metal oxide that functions as an oxide semiconductor for the semiconductor layer 251.

[0508] Metal oxide structures can be classified into single-crystal structures and other structures (non-single-crystal structures). Examples of non-single-crystal structures include CAAC (c-axis aligned crystalline) structures, polycrystalline structures, nanocrystalline structures, a-like (amorphous-like) structures, and amorphous structures. The structure of the metal oxide in one aspect of the present invention is not particularly limited, and any of the above structures may be used. However, using crystalline metal oxides such as CAAC structures and nc structures is preferable because it allows for the creation of highly reliable semiconductor devices.

[0509] Furthermore, it is preferable that the above metal oxide contains at least indium. It may also contain indium and zinc. In addition to these, it may also contain element M. Element M can be one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. In particular, element M can be one or more of aluminum, gallium, yttrium, or tin. It is even more preferable that element M contains one or both of gallium and tin.

[0510] As the above metal oxides, indium oxide (also called indium oxide, IO), gallium oxide (also called gallium oxide), zinc oxide (also called zinc oxide), indium zinc oxide (In-Zn oxide), indium tin oxide, indium tungsten oxide, indium titanium oxide, indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide, indium gallium tin oxide, gallium zinc oxide, aluminum zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, indium titanium zinc oxide, indium gallium zinc oxide (In-Ga-Zn oxide, also called IGZO), indium gallium tin zinc oxide, indium gallium aluminum zinc oxide, etc. can be used. Alternatively, indium tin oxide, gallium tin oxide, aluminum tin oxide, etc. containing silicon can be used.

[0511] As described above, the metal oxide preferably contains indium. Specifically, it is preferable to use indium oxide as the metal oxide. Crystalline indium oxide is particularly preferable.

[0512] Metal oxides can be suitably formed using sputtering or ALD (Advanced Laser Deposition). When metal oxides are formed by sputtering, films with high crystallinity or high film density can be formed. When metal oxides are formed using ALD, atoms can be deposited layer by layer, resulting in film formation with fewer defects such as pinholes, excellent coverage, and the ability to form films at low temperatures. Furthermore, it is preferable to perform an impurity removal treatment after the formation of the metal oxide to remove impurities (typically water, hydrogen, carbon, nitrogen, etc.) from the metal oxide film. Examples of impurity removal treatments include plasma treatment and heat treatment. Microwave plasma treatment is an example of plasma treatment.

[0513] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less. Microwave plasma processing refers to processing using a device that has a power supply that generates high-density plasma using microwaves, for example. Microwave plasma processing can also be called microwave-excited high-density plasma processing.

[0514] In the transistor 200, a configuration is shown in which two semiconductor layers, semiconductor layer 251a and semiconductor layer 251b, are stacked in the region where the channel is formed (hereinafter also referred to as the channel formation region) and in its vicinity. However, the present invention is not limited to this. For example, a single-layer structure of semiconductor layer 251b or a stacked structure of three or more layers may be provided. Furthermore, each of semiconductor layer 251a and semiconductor layer 251b may have a stacked structure of two or more layers.

[0515] The conductive layer 233 functions as the first gate electrode of the transistor (sometimes referred to as the top gate electrode or front gate electrode), and as described above, the conductive layers 232a and 232b function as the source electrode or drain electrode, respectively. As described above, the conductive layer 233 is formed to be embedded in the opening of the insulating layer 213 and in the region sandwiched between the conductive layers 232a and 232b. Here, the arrangement of the conductive layer 233, conductive layer 232a, and conductive layer 232b is formed in a self-aligned manner with respect to the opening of the insulating layer 213. In other words, in the transistor 200, the first gate electrode can be positioned in a self-aligned manner between the source electrode and the drain electrode. Therefore, since the conductive layer 233 can be formed without providing a positional margin, the occupied area of ​​the transistor 200 can be reduced. This makes it possible to increase the density of arithmetic cells in the arithmetic unit.

[0516] The transistor 200 can be formed by first forming an island-shaped laminate on an insulating layer 262 (described later), including an insulating layer 263 (described later), a semiconductor layer 251, and conductive layers that will become conductive layers 232a and 232b; then stacking insulating layers 282 and 213 (collectively referred to here as the interlayer film) above the island-shaped laminate and above the insulating layer 262 in that order; and then forming an opening in the region of the interlayer film that overlaps the island-shaped laminate, and providing an insulating layer 264 and a conductive layer 233 in that order in the opening. In particular, it is preferable to form the conductive layers 232a and 232b simultaneously by forming the opening in the interlayer film. In this specification, a transistor structure in which, after the formation of the island-shaped laminate and the interlayer film, an opening reaching the island-shaped laminate is provided in the interlayer film, and a conductive layer that will become the first gate electrode of the transistor is provided to fill the opening is referred to as the GL structure. This type of structure is sometimes also called a TGSA structure.

[0517] In Figures 36A and 36B, the conductive layer 233 is shown as a two-layer structure. Here, it is preferable that the conductive layer 233 has a conductive layer 233a and a conductive layer 233b disposed on top of the conductive layer 233a. For example, it is preferable that the conductive layer 233a is arranged to enclose the bottom and sides of the conductive layer 233b. In this case, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the conductive layer 233a.

[0518] It is preferable to use a conductive material for the conductive layer 233a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen. Furthermore, by having the function of suppressing the diffusion of oxygen in the conductive layer 233a, it is possible to suppress the oxidation of the conductive layer 233b by oxygen contained in the insulating layer 213, etc., which reduces the conductivity. As a conductive material that has the function of suppressing the diffusion of oxygen, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc.

[0519] Furthermore, it is preferable to use a conductive layer with high conductivity for the conductive layer 233b. For example, the conductive layer 233b can be made of a conductive material mainly composed of tungsten, copper, or aluminum. The conductive layer 233b may also be in a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0520] For conductive layers 232a and 232b, it is preferable to use conductive materials that are resistant to oxidation or conductive materials that have a function to suppress the diffusion of oxygen. Examples of such conductive materials include conductive materials containing nitrogen and conductive materials containing oxygen. This makes it possible to suppress a decrease in the conductivity of conductive layers 232a and 232b. When conductive materials containing metal and nitrogen are used as conductive layers 232a and 232b, conductive layers 232a and 232b become conductive layers having at least a metal and nitrogen. For example, as materials to be applied to conductive layers 232a and 232b, conductive materials that are resistant to oxidation or conductive materials that have a function to suppress the diffusion of oxygen can be selected from the materials that can be applied to conductive layers 233a and 233b respectively as described above.

[0521] Conductive layers 234a and 234b can be made of conductive materials mainly composed of tungsten, copper, or aluminum. Furthermore, conductive layers 234a and 234b can have a laminated structure having multiple layers. In particular, it is preferable that the laminated structure consists of a conductive material having the function of suppressing the permeation of impurities such as water and hydrogen, and a highly conductive material, which are laminated together.

[0522] Furthermore, the conductive layer 231 may function as a second gate electrode (sometimes referred to as a bottom gate electrode or back gate electrode). In this case, by independently changing the potential applied to the conductive layer 231, separate from the potential applied to the conductive layer 233, the threshold voltage V of the transistor 200 can be controlled. ｔｈ This can be controlled. In particular, by applying a negative potential to the conductive layer 231, the V of the transistor 200 can be controlled. ｔｈThis makes it possible to increase the voltage and decrease the off-current. Therefore, applying a negative potential to the conductive layer 231 reduces the drain current when the potential applied to the conductive layer 233 is 0V compared to when no potential is applied.

[0523] The conductive layer 231 should be larger than the channel formation region in the semiconductor layer 251. In particular, as shown in Figure 36B, it is preferable that the conductive layer 231 extends as wiring even in the region outside the edge that intersects with the channel width direction of the semiconductor layer 251. That is, it is preferable that the conductive layer 231 and the conductive layer 233 are superimposed on the outside of the side surface in the channel width direction of the semiconductor layer 251, with an insulating layer in between.

[0524] As shown in Figure 36A, the conductive layer 233 preferably has a conductive layer 233a provided inside the insulating layer 264 and a conductive layer 233b provided so as to be embedded inside the conductive layer 233a. Although Figures 36A and 36B show the conductive layer 233 as a two-layer laminated structure, the present invention is not limited thereto. For example, the conductive layer 233 may be a single-layer structure or a laminated structure of three or more layers.

[0525] For the conductive layer 231 and conductive layer 233, for example, materials applicable to conductive layer 233a and conductive layer 233b described above can be selected and used.

[0526] As shown in Figures 36A and 36B, the transistor 200 preferably includes an insulating layer 211, an insulating layer 281 disposed on the insulating layer 211, an insulating layer 212 disposed on the insulating layer 281, a conductive layer 231 disposed so as to be embedded in the insulating layer 212, an insulating layer 261 disposed on the insulating layer 212 and the conductive layer 231, an insulating layer 262 disposed on the insulating layer 261, and an insulating layer 263 disposed on the insulating layer 262. It is preferable that a semiconductor layer 251a is disposed on the insulating layer 263.

[0527] Furthermore, as shown in Figures 36A and 36B, it is preferable that an insulating layer 282 is placed between the insulating layer 262, insulating layer 263, semiconductor layer 251a, semiconductor layer 251b, conductive layer 232a, and conductive layer 232b, and the insulating layer 213. Here, as shown in Figures 36A and 36B, it is preferable that the insulating layer 282 is in contact with the side surface of the insulating layer 264, the top and side surface of the conductive layer 232a, the top and side surface of the conductive layer 232b, the semiconductor layer 251a, the semiconductor layer 251b, the side and top surface of the insulating layer 263, and the top surface of the insulating layer 262.

[0528] Furthermore, insulating layer 264 functions as a first gate insulating film in transistor 200. In addition, insulating layers 261 to 263 function as second gate insulating films. For these gate insulating films, for example, silicon oxide, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or silicon oxide with vacancies can be used. In addition, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO) can be used. ３ ) or (Ba, Sr)TiO ３ An insulating layer containing a so-called high-k material such as (BST) can be used in a single layer or a multilayer configuration. Furthermore, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the above insulating layer material. Alternatively, these insulating layers may be subjected to nitriding treatment.

[0529] Preferably, insulating layers 283 and 214, which function as interlayer films, are arranged on the transistor 200. Here, it is preferable that the insulating layer 283 is arranged in contact with the upper surfaces of the conductive layer 233, the insulating layer 264, and the insulating layer 213. In this case, it is preferable that the upper surface of the insulating layer 213 is flattened.

[0530] It is preferable that a conductive layer 234 (conductive layer 234a and conductive layer 234b) is provided, which connects to the transistor 200 and functions as a plug. For this reason, the conductive layer 234 is provided in contact with the inner wall of the opening of the insulating layer 282, insulating layer 213, insulating layer 283, and insulating layer 214. In particular, a first conductive layer of the conductive layer 234 may be provided in contact with the inner wall, and a second conductive layer of the conductive layer 234 may be provided on the side surface of the first conductive layer. Here, the height of the upper surface of the conductive layer 234 and the height of the upper surface of the insulating layer 214 can be made to be approximately the same.

[0531] Specifically, for example, a first conductive layer of conductive layer 234a is provided in contact with one inner wall of two openings in insulating layer 214, insulating layer 283, insulating layer 213 and insulating layer 282, and a second conductive layer of conductive layer 234a is formed in contact with its side surface. A conductive layer 232a is located in a part of the bottom of the opening, and conductive layer 234a is in contact with conductive layer 232a. Similarly, for example, a first conductive layer of conductive layer 234b is provided in contact with the other inner wall of two openings in insulating layer 214, insulating layer 283, insulating layer 213 and insulating layer 282, and a second conductive layer of conductive layer 234b is formed in contact with its side surface. A conductive layer 232b is located in a part of the bottom of the opening, and conductive layer 234b is in contact with conductive layer 232b.

[0532] Although the transistor 200 shows a configuration in which a first conductive layer and a second conductive layer of the conductive layer 234 are stacked, the present invention is not limited thereto. For example, the conductive layer 234 may be provided as a single layer or as a stacked structure of three or more layers. When a structure has a stacked structure, an ordinal number may be assigned to distinguish it according to the order of formation.

[0533] As shown in Figure 36B, in the region of the semiconductor layer 251b that does not overlap with the conductive layer 232, in other words, in the channel formation region of the semiconductor layer 251, the side surface of the semiconductor layer 251 is covered by the conductive layer 233. This makes it easier to apply the electric field of the conductive layer 233, which functions as the first gate electrode, to the side surface of the semiconductor layer 251, and as a result, the channel formation region of the semiconductor layer 251 can be electrically surrounded by the electric field of the conductive layer 233. Therefore, the on-current of the transistor 200 can be increased and the frequency characteristics can be improved.

[0534] For example, the insulating layer 213 preferably has a lower dielectric constant than the insulating layer 262. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance between wirings can be reduced. Therefore, as a material with a low dielectric constant, the insulating layer 213 can be made from a material that can be used for the insulating layer 212.

[0535] <<Transistor Configuration Example 2>> In the schematic cross-sectional view of Figure 34, which shows an example of the configuration of a computing device that is a semiconductor device according to one aspect of the present invention, transistors M1p and M2p are described as having a GL structure. However, the structures of transistors M1p and M2p according to one aspect of the present invention are not limited to this. As an alternative to the GL structure, transistors M1p and M2p according to one aspect of the present invention can be, for example, the structure of a vertical channel transistor described below.

[0536] Figures 37A to 37C show examples of the configuration of a vertical channel transistor. In a vertical channel transistor, the source electrode and drain electrode are located at different heights, and the current flowing through the semiconductor layer flows in the height direction. In other words, the channel length direction can be said to have a component in the height direction (vertical direction).

[0537] The transistors shown in Figures 37A to 37C may also be called VFETs (Vertical Field Effect Transistors), vertical transistors, or vertical channel transistors, in addition to being vertical channel transistors. Furthermore, in this specification, in vertical channel transistors, one of the source electrode or drain electrode located at the bottom may be referred to as the bottom electrode. Also, the other of the source electrode or drain electrode located at the top may be referred to as the top electrode.

[0538] In particular, Figure 37A shows a schematic plan view of an example of a vertical channel type transistor 300, and Figures 37B and 37C show schematic cross-sectional views of the transistor 300. Figure 37B is a schematic cross-sectional view along the dashed line A1-A2 shown in Figure 37A, and Figure 37C is a schematic cross-sectional view along the dashed line A3-A4 shown in Figure 37A. Figure 37B shows a selection of transistors included in the circuit layer OMAL. Figure 38 shows a schematic perspective view of the transistor 300 and its surrounding wiring as shown in Figures 37A to 37C.

[0539] The transistor 300 shown in Figures 37A to 37C and Figure 38 includes, as an example, a conductive layer 331 that functions as wiring or an electrode, a conductive layer 332 that functions as wiring or an electrode, a semiconductor layer 351 that includes a channel formation region of the transistor 300, an insulating layer 361 that functions as a gate insulating film of the transistor 300, a conductive layer 333 that functions as the gate of the transistor 300, and a conductive layer 334 that functions as wiring.

[0540] The conductive layer 331 is provided above the insulating layer 311, which functions as an interlayer film. Furthermore, since the conductive layer 331 functions as wiring, it extends along the dashed line A3-A4 in the schematic plan view of Figure 37A.

[0541] For example, the conductive layer 331 can be a conductive layer applicable to transistors M1p and M2p as described above. The same applies to conductive layers 332 to 334, which will be described later.

[0542] On the insulating layer 311 and the conductive layer 331, an insulating layer 312 and a conductive layer 332, which function as an interlayer film, are formed in this order. In Figure 37B, the insulating layer 312 has a three-layer structure consisting of two barrier insulating films that suppress the diffusion of impurities, and an interlayer film sandwiched between these barrier insulating films. Preferably, the barrier insulating films have a function to suppress the diffusion of oxygen to prevent oxidation of the conductive layer 331 or the conductive layer 332. Furthermore, since the conductive layer 332 functions as wiring, it extends along the dashed line A1-A2 in the schematic pl...

Claims

It comprises a first cell, a second cell, and a first drive circuit. Each of the first and second cells comprises a first transistor, a second transistor, a third transistor, and a resistive switching element. The first drive circuit has a first input terminal, a second input terminal, and a first output terminal. The resistive switching element comprises a conductive layer and a magnetic tunnel junction element. The conductive layer has a first region that functions as a first terminal, a second region that functions as a second terminal, and a region that is in contact with the free layer of the magnetic tunnel junction element on the path of the current flowing between the first region and the second region. The fixed layer of the magnetic tunnel junction element has a region that functions as a third terminal, The source or drain of the first transistor is electrically connected to the first terminal. Either the source or the drain of the second transistor is electrically connected to the second terminal. Either the source or the drain of the third transistor is electrically connected to the third terminal. The source or drain of the first transistor of the first cell is electrically connected to the first input terminal. The source or drain of the first transistor of the second cell is electrically connected to the second input terminal. The first drive circuit has the function of outputting a signal corresponding to the difference between the first current flowing through the first input terminal and the second current flowing through the second input terminal to the first output terminal. Semiconductor equipment. 　 In claim 1, The gates of the first transistors in the first cell and the second cell are electrically connected to the first wiring. The gates of the second transistors in the first and second cells are electrically connected to the second wiring. The gates of the third transistors in the first and second cells are electrically connected to the third wiring. Semiconductor equipment. 　 In claim 2, Each of the first transistor, the second transistor, and the third transistor has an oxide containing indium in its channel-forming region. Semiconductor equipment. 　 Claim 3, comprising a second drive circuit, The second drive circuit comprises a shift register, a selector, a first sequence circuit, and a second sequence circuit. The shift register has a second output terminal, The selector has a third input terminal, a third output terminal, and a fourth output terminal. The first sequential circuit has a fourth input terminal, a fifth output terminal, and a first control terminal. The second sequential circuit has a fifth input terminal, a sixth output terminal, and a second control terminal. The second output terminal is electrically connected to the third input terminal. The third output terminal is electrically connected to the first control terminal, The fifth output terminal is electrically connected to the fifth input terminal, The sixth output terminal and the fourth output terminal are electrically connected to the first wiring. The selector has the function of making the third input terminal conductive between the third output terminal and one of the fourth output terminals, and non-conductive between the third input terminal and the other of the third output terminal and the fourth output terminal. The first sequential circuit has the function of holding first information input to the fourth input terminal, and the function of outputting the first information as a signal to the fifth output terminal in response to a control signal input to the first control terminal. The second sequential circuit has the function of holding the second information input to the fifth input terminal, and the function of outputting the second information as a signal to the sixth output terminal in response to a control signal input to the second control terminal. Semiconductor equipment. 　 In claim 4, the transistor included in the second drive circuit has an oxide containing indium in the channel forming region. Semiconductor equipment. 　 It comprises a first cell, a second cell, and a first drive circuit. Each of the first and second cells includes a first to fourth transistor and a three-terminal resistive switching element including a magnetic tunnel junction element. The resistance change element has a first terminal through which read current and write current flow, a second terminal through which the write current flows, and a third terminal through which the read current flows. The first drive circuit has a first input terminal, a second input terminal, and a first output terminal. The source or drain of the first transistor and the source or drain of the fourth transistor are electrically connected to the first terminal. Either the source or the drain of the second transistor is electrically connected to the second terminal. Either the source or the drain of the third transistor is electrically connected to the third terminal. The source or drain of the first transistor in the first cell and the source or drain of the fourth transistor in the second cell are electrically connected to the first input terminal. The other source or drain of the first transistor in the second cell and the other source or drain of the fourth transistor in the first cell are electrically connected to the second input terminal. The first drive circuit has the function of outputting a signal corresponding to the difference between the first current flowing through the first input terminal and the second current flowing through the second input terminal to the first output terminal. Semiconductor equipment. 　 In claim 6, The gates of the first transistors in the first cell and the second cell are electrically connected to the first wiring. The gates of the second transistors in the first and second cells are electrically connected to the second wiring. The gates of the third transistors in the first and second cells are electrically connected to the third wiring. The gates of the fourth transistors in the first and second cells are electrically connected to the fourth wiring. Semiconductor equipment. 　 In claim 7, It has a second drive circuit, The aforementioned second drive circuit includes a shift register, a selector, a first sequence circuit, a second sequence circuit, a first switch circuit, a second switch circuit, and a switch. The shift register has a second output terminal, The selector has a third input terminal, a third output terminal, and a fourth output terminal. The first sequential circuit has a fourth input terminal, a fifth output terminal, and a first control terminal. The second sequential circuit has a fifth input terminal, a sixth output terminal, and a second control terminal. The first switch circuit has a fourth terminal, a fifth terminal, and a third control terminal. The second switch circuit has a sixth terminal, a seventh terminal, and a fourth control terminal. The switch has an eighth terminal, The second output terminal is electrically connected to the third input terminal. The third output terminal is electrically connected to the first control terminal and the second control terminal. The fifth output terminal is electrically connected to the fourth terminal, The sixth output terminal is electrically connected to the sixth terminal, The fourth output terminal and the fifth terminal are electrically connected to the first wiring. The eighth terminal and the seventh terminal are electrically connected to the fourth wiring. The third control terminal and the fourth control terminal are electrically connected to the fifth wiring. The shift register has the function of outputting a first control signal from the second output terminal, The selector has the function of making the third input terminal conductive between the third output terminal and one of the fourth output terminals, and non-conductive between the third input terminal and the other of the third output terminal and the fourth output terminal. The first sequential circuit has the function of holding first information input to the fourth input terminal, and the function of outputting the first information as a first signal to the fifth output terminal in response to the first control signal input to the first control terminal. The second sequential circuit has the function of holding the second information input to the fifth input terminal, and the function of outputting the second information as a second signal to the sixth output terminal in response to the first control signal input to the second control terminal. The first switch circuit has the function of making the connection between the fourth terminal and the fifth terminal conductive or non-conductive in response to the second control signal input to the third control terminal. The second switch circuit has the function of making the connection between the sixth terminal and the seventh terminal conductive or non-conductive in response to the second control signal input to the fourth control terminal. Semiconductor equipment. 　 In claim 8, Each of the first switch circuit and the second switch circuit has a three-state buffer circuit, In the first switch circuit, the input terminal of the three-state buffer circuit is electrically connected to the fourth terminal, the output terminal of the three-state buffer circuit is electrically connected to the fifth terminal, and the enable terminal of the three-state buffer circuit is electrically connected to the third control terminal. In the second switch circuit, the input terminal of the three-state buffer circuit is electrically connected to the sixth terminal, the output terminal of the three-state buffer circuit is electrically connected to the seventh terminal, and the enable terminal of the three-state buffer circuit is electrically connected to the fourth control terminal. Semiconductor equipment. 　 In any one of claims 6 to 9, Each of the first transistor, the second transistor, the third transistor, and the fourth transistor has an oxide containing indium in its channel-forming region. Semiconductor equipment.

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