Reconfigurable interconnection circuit for multi-core processor, implementation method, and chip

Abstract

The present application relates to the technical field of chips, and discloses a reconfigurable interconnection circuit for a multi-core processor, an implementation method, and a chip. The circuit comprises: a multi-master multi-slave routing arbitration architecture and an interconnection component, wherein a multi-core processor is connected to the multi-master multi-slave routing arbitration architecture, and the multi-master multi-slave routing arbitration architecture is connected to an embedded FPGA by means of the interconnection component. The multi-master multi-slave routing arbitration architecture is used for performing identification and routing arbitration on data transmission inside the multi-core processor or between the multi-core processor and the embedded FPGA, and allocating corresponding interconnection resources for the data transmission, wherein the interconnection resources are implemented on the basis of the interconnection component. The interconnection component is used for managing and transmitting communication between interfaces connected by the interconnection component, wherein the interfaces are interfaces on the multi-core processor side and / or interfaces on the embedded FPGA side. The present application realizes real-time, reliable and efficient interconnection between a multi-core processor and an embedded FPGA, and can reduce the requirements for hardware resources and reduce the size of a system on a chip.

Description

Reconfigurable interconnect circuits, implementation methods and chips for multi-core processors Technical Field

[0001] This application belongs to the field of chip technology, and in particular relates to a reconfigurable interconnect circuit, implementation method and chip for multi-core processors. Background Technology

[0002] Single-core processors suffer from performance bottlenecks when handling complex tasks, making multi-core processors a solution for enhancing computing power. By integrating multiple CPU cores, multi-core processors achieve higher parallel processing capabilities and stronger computing performance. In System-on-Chip (SoC) design, multi-core processors can be tightly integrated with embedded Field-Programmable Gate Arrays (FPGAs) to form a heterogeneous computing platform. In this platform, the multi-core processor performs general-purpose computing tasks, while the embedded FPGA is used for specific hardware acceleration tasks. Their collaborative operation improves system performance and efficiency. A key challenge is achieving communication and interconnection between the multi-core processor and the embedded FPGA. Summary of the Invention

[0003] This application aims to address at least one of the technical problems existing in the related art. To this end, this application proposes a reconfigurable interconnect circuit, implementation method, and chip for multi-core processors. By dynamically allocating interconnect resources through routing arbitration, a reconfigurable interconnect circuit is formed, realizing real-time, reliable, and efficient interconnection between multi-core processors and embedded FPGAs. This can reduce the demand for hardware resources and reduce the size of the system-on-a-chip.

[0004] In a first aspect, this application provides a reconfigurable interconnect circuit for multi-core processors, the circuit comprising:

[0005] A multi-master, multi-slave routing arbitration structure and interconnect components are provided. A multi-core processor is connected to the multi-master, multi-slave routing arbitration structure, and the multi-master, multi-slave routing arbitration structure is connected to an embedded FPGA through the interconnect components.

[0006] The multi-master multi-slave routing arbitration structure is used to identify and route the data transmission within the multi-core processor or between the multi-core processor and the embedded FPGA, and to allocate corresponding interconnect resources for the data transmission. The interconnect resources are implemented based on the interconnect components.

[0007] The interconnect component is used to manage and transmit communication between the interfaces connected to the interconnect component, wherein the interface is the interface on the multi-core processor side and / or the interface on the embedded FPGA side.

[0008] The multi-master multi-slave routing arbitration structure or the interconnection component adopts an island-type interconnection architecture, and the interconnection resources under the island-type interconnection architecture include global interconnection resources and local interconnection resources;

[0009] The global interconnection resources include interconnection channels and switch boxes, and the local interconnection resources include connection boxes, wherein...

[0010] The interconnection channel is composed of a preset number of interconnection segments, which are used to realize signal transmission between logic function blocks;

[0011] The switch box includes a preset number of programmable switches for switching between different interconnecting segments;

[0012] The connection box includes an input connection module and an output connection module, which are used to realize signal transmission between logic function blocks and interconnection channels.

[0013] In the above technical solution, the reconfigurable interconnect circuit for multi-core processors includes a multi-master multi-slave routing arbitration structure and interconnect components. The multi-master multi-slave routing arbitration structure is used to identify and arbitrate data transmission between the multi-core processor and the embedded FPGA, and to allocate interconnect resources based on the interconnect components. The interconnect components manage and transmit communication between the multi-core processor and the embedded FPGA interface. By dynamically allocating interconnect resources through routing arbitration, a reconfigurable interconnect circuit is formed, realizing real-time, reliable and efficient interconnection between the multi-core processor and the embedded FPGA. This can reduce the demand for hardware resources and reduce the size of the system-on-a-chip. The multi-master multi-slave routing arbitration structure or interconnect components are islanded interconnect architectures, and the interconnect resources are divided into global interconnect resources and local interconnect resources. The global interconnect resources include interconnect channels and switch boxes, which are used to transmit signals between logic function blocks, and the programmable switches in the switch boxes control the direction and path of signal transmission. Local interconnect resources, including connection boxes, enable signal transmission between logic function blocks and interconnect channels. Through the connection and expansion of logic function blocks, a complete interconnect circuit function is formed, meeting the user's interconnection needs. The island-type interconnect architecture allows for the expansion of more processors or peripherals through multi-master multi-slave routing arbitration structures and interconnect components, adapting to different communication needs. Different types of interconnect channels and switch boxes help to utilize hardware resources more effectively, reduce the size of reconfigurable interconnect circuits for multi-core processors, and thus reduce the size of the system-on-a-chip.

[0014] According to one embodiment of this application, the types of interconnect components include slave interconnect components, master interconnect components, storage interconnect components, system application interconnect components, and control interconnect components, wherein,

[0015] The slave interconnect component is used to interconnect at least one processor in a multi-core processor with an embedded FPGA, wherein the at least one processor acts as a slave and the embedded FPGA acts as a master.

[0016] The host interconnect component is used to interconnect at least one processor in a multi-core processor with an embedded FPGA, wherein the at least one processor acts as the host and the embedded FPGA acts as the slave.

[0017] The storage interconnect component is used to interconnect storage resources;

[0018] The system application interconnection component is used to realize the interconnection of system-level applications;

[0019] The control interconnection component is used to transmit control signals.

[0020] In the above technical solution, the interconnect components include slave interconnect components, master interconnect components, storage interconnect components, system application interconnect components, and control interconnect components. Different types of interconnect components cooperate to realize data transmission and control signal transmission between the multi-core processor and the embedded FPGA, or between the multi-core processor and other resources. The processor in the multi-core processor and the instantiated programmable logic device in the embedded FPGA can be configured as a master or slave, improving data transmission efficiency. Different types of interconnect components can adapt to different communication needs. By dynamically allocating interconnect resources, the demand for hardware resources can be effectively reduced, the size of the reconfigurable interconnect circuit can be reduced, and thus the size of the system-on-a-chip can be reduced.

[0021] According to one embodiment of this application, the embedded FPGA as a host includes at least one programmable logic device instantiated from the embedded FPGA as a host.

[0022] In the above technical solution, the embedded FPGA instantiates at least one programmable logic device as the host. The FPGA as the host can communicate and exchange data with other parts of the system-on-a-chip, thereby improving the data processing capability and response speed of the embedded FPGA.

[0023] According to one embodiment of this application, the embedded FPGA as a slave device includes at least one programmable logic device instantiated from the embedded FPGA as a slave device.

[0024] In the above technical solution, the embedded FPGA instantiates at least one programmable logic device as a slave, which can respond to requests from a multi-core processor or other host. As a slave, the embedded FPGA can execute specific tasks or requests initiated by the host, so that the host can effectively use the embedded FPGA.

[0025] According to one embodiment of this application, the host interconnect component is further used to realize interconnection between processors in the multi-core processor, wherein at least one processor acts as a host and at least another processor acts as a slave.

[0026] In the above technical solution, the host interconnect component supports communication within the multi-core processor, allowing communication between different processors without the need for external devices, thereby improving the communication efficiency between processors and enhancing the data processing capabilities of the multi-core processor.

[0027] According to one embodiment of this application, the host interconnect component is further configured to realize interconnection between at least one processor of the multi-core processor and the embedded FPGA and at least another processor, wherein at least one processor of the multi-core processor acts as a host, and at least one programmable logic device instantiated by the embedded FPGA and the at least another processor act as slaves.

[0028] In the above technical solution, the host interconnect component can be used to realize the interconnection between the host and the slave within the multi-core processor, and can also be used to use at least one programmable logic device instantiated from the embedded FPGA as a slave. That is, the host interconnect component can manage the communication within the multi-core processor and the communication between the multi-core processor and external devices (such as embedded FPGAs), so that the multi-core processor can use the embedded FPGA more effectively and realize closer cooperation between processors within the multi-core processor.

[0029] According to one embodiment of this application, the type of the interface includes at least one of the following: AMBA general interface, AMBA high-performance interface, AMBA_ACP interface, and CTRL_IO_SIG interface.

[0030] In the above technical solution, the reconfigurable interconnect circuit for multi-core processors uses multiple interface types, including at least one of the following: AMBA general-purpose interface, AMBA high-performance interface, AMBA_ACP interface, and CTRL_IO_SIG interface. The AMBA general-purpose interface supports communication between the multi-core processor and the embedded FPGA in either a master or slave role. The AMBA high-performance interface improves data transmission rate through FIFO buffering. The ACP interface achieves cache coherency and can be used to optimize accelerator memory access. The CTRL_IO_SIG interface is used to transmit control signals. By configuring different interfaces, the interface can be dynamically selected according to communication requirements, improving data transmission efficiency. The design of multiple interface types and interconnect components allows the reconfigurable interconnect circuit for multi-core processors to adapt to different communication needs, effectively reducing the demand for hardware resources and the size of the reconfigurable interconnect circuit for multi-core processors, thereby reducing the size of the system-on-a-chip (SoC).

[0031] According to one embodiment of this application, all interfaces on the multi-core processor side, except for the accelerated consistency interface, are connected to the multi-master multi-slave routing arbitration structure, and then connected to the embedded FPGA through the interconnect component.

[0032] In the above technical solution, all interfaces on the multi-core processor side, except for the accelerated consistency interface, are connected to the multi-master multi-slave routing arbitration structure, and then connected to the embedded FPGA through interconnect components. Interconnect resources are dynamically allocated through routing arbitration, forming a reconfigurable interconnect circuit, realizing the interconnection between the multi-core processor and the embedded FPGA. This can reduce the demand for hardware resources and reduce the size of the system-on-a-chip. The accelerated consistency interface is not connected to the multi-master multi-slave routing arbitration structure, avoiding possible additional contention and waiting time, and improving the data transmission efficiency between the multi-core processor and the embedded FPGA.

[0033] According to one embodiment of this application, the accelerated coherence interface on the multi-core processor side is directly connected to the system application interconnect component in the interconnect component, and the system application interconnect component is a coherence control unit within the accelerated processor.

[0034] In the above technical solution, the accelerated coherence interface on the multi-core processor side is directly connected to the system application interconnect component in the interconnect component. This component is the coherence control unit inside the accelerated processor, which can simplify the data transmission path and improve the data transmission efficiency between the multi-core processor and the embedded FPGA.

[0035] According to one embodiment of this application, the interface on the embedded FPGA side includes at least one of the following: host AMBA general interface, slave AMBA general interface, host AMBA high-performance interface, slave AMBA_ACP interface and CTRL_IO_SIG interface;

[0036] The slave interconnect component is connected to the host AMBA general interface, the host interconnect component is connected to the slave AMBA general interface, the storage interconnect component is connected to the host AMBA high-performance interface, the system application interconnect component is connected to the slave AMBA_ACP interface, and the control interconnect component is connected to the CTRL_IO_SIG interface.

[0037] In the above technical solution, the slave interconnect component is connected to the host AMBA general interface, the host interconnect component is connected to the slave AMBA general interface, the storage interconnect component is connected to the host AMBA high-performance interface, the system application interconnect component is connected to the slave AMBA_ACP interface, and the control interconnect component is connected to the CTRL_IO_SIG interface. This illustrates the interface configuration on the embedded FPGA side and its connection method with different interconnect components, realizing communication and data transmission between the multi-core processor and the embedded FPGA, which can meet the data transmission needs in different application scenarios.

[0038] According to one embodiment of this application, allocating corresponding interconnection resources for the data transmission includes: determining the connection relationship of interconnection segments in the interconnection component and the jump relationship between interconnection segments based on the number of interfaces, interface types, and circuit application requirements of the multi-master multi-slave routing arbitration structure; generating a reconfigurable configuration file, wherein the reconfigurable configuration file is used to configure the on or off of the programmable switch in the switch box and the input connection module and output connection module in the connection box.

[0039] In the above technical solution, based on the number of interfaces, interface types, and circuit application requirements of the multi-master multi-slave routing arbitration structure, the connection relationship of interconnection segments in the interconnection component and the jump relationship between interconnection segments are determined, a reconfigurable configuration file is generated, and corresponding interconnection resources are allocated for data transmission according to the reconfigurable configuration file. This enables the reconfigurable interconnection circuit for multi-core processors to adapt to different data transmission requirements and improves the flexibility of the reconfigurable interconnection circuit for multi-core processors.

[0040] According to one embodiment of this application, the local interconnection resource further includes: an input cross-connection module, which is used to realize signal interconnection between logic units and to connect the input pins of the logic function block to each logic unit;

[0041] The logic unit comprises the logic function block.

[0042] In the above technical solution, the local interconnection resources also include an input cross-interconnection module, which can be used to realize signal interconnection between logic units and to connect the input pins of logic function blocks to each logic unit, thereby enabling interconnection between multi-core processors and embedded FPGAs.

[0043] According to one embodiment of this application, the horizontal and vertical channels of the embedded FPGA-side programmable interconnect provide the global interconnect resources, which interact with the local interconnect resources and the multi-core processor-side interconnect bus via signal exchange.

[0044] The signal output from the multi-core processor side is sent to the interconnect component through the local interconnect resource and processed by the corresponding logic unit; alternatively, the signal output from the multi-core processor side is sent to the adjacent logic unit for processing through the horizontal channel.

[0045] In the above technical solution, the horizontal and vertical channels of the programmable interconnect on the embedded FPGA side provide global interconnect resources. The global interconnect resources interact with the interconnect bus on the multi-core processor side through local interconnect resources. The signal output on the multi-core processor side is sent to the interconnect component through the local interconnect resources and processed by the corresponding logic unit, or sent to the adjacent logic unit through the horizontal channel for processing. Through the global and local interconnect resources, the interconnection between the multi-core processor and the embedded FPGA is realized, which improves the flexibility of the reconfigurable interconnect circuit for multi-core processors.

[0046] According to one embodiment of this application, the interconnection segments include long interconnection segments, short interconnection segments, local interconnection segments, and direct-connection segments. The long interconnection segments are used to meet the signal path requirements between logic functional blocks that are far apart. The short interconnection segments are used to realize the interconnection between adjacent logic functional blocks. The local interconnection segments are used to realize signal sharing and feedback between logic units within each logic functional block. The direct-connection segments are used for signal transmission between adjacent logic functional blocks.

[0047] In the above technical solution, the design of the interconnection segment adopts a multi-level combined interconnection system, including long interconnection segments, short interconnection segments, local interconnection segments and direct connection segments, to meet the interconnection requirements of different distances and complexities, adapt to the layout and signal transmission of different logical functional blocks in the multi-master multi-slave routing arbitration structure and interconnection components, and improve the flexibility of reconfigurable interconnection circuits for multi-core processors.

[0048] According to one embodiment of this application, the interconnection channel is a one-way channel or a two-way channel.

[0049] In the above technical solution, the interconnection channel is either a unidirectional channel or a bidirectional channel. By selecting different interconnection channels, various signal transmission requirements can be adapted to improve the data transmission efficiency of reconfigurable interconnection circuits for multi-core processors.

[0050] According to one embodiment of this application, the switch box is implemented by combining a bidirectional interconnection switch and a unidirectional interconnection switch.

[0051] In the above technical solution, the switch box is implemented by combining bidirectional interconnection switches and unidirectional interconnection switches. By selecting different interconnection switches, it can adapt to various signal transmission requirements and improve the data transmission efficiency of reconfigurable interconnection circuits for multi-core processors.

[0052] According to one embodiment of this application, the topology type of the programmable switch in the switch box includes at least one of subset interconnection, global interconnection, and vertical interconnection.

[0053] In the above technical solution, the topology type of the programmable switch in the switch box includes at least one of subset interconnection, global interconnection and vertical interconnection. By reasonably selecting and applying the topology type of the programmable switch in the switch box, the flexibility and scalability of the reconfigurable interconnect circuit for multi-core processors can be improved.

[0054] According to one embodiment of this application, the parameters of the multi-master multi-slave routing arbitration structure or interconnection component include: the number of routing wires that can be connected to the input or output of each logical function block, the number of other routing wires that can be connected to each routing wire, the length of the routing segment, the mode of the routing switch, the electrical design of the wires and programmable switches, and the number of routing segments for each channel.

[0055] In the above technical solution, the parameters of the multi-master multi-slave routing arbitration structure or interconnection component include the number of routing wires that can be connected to the input or output of each logical function block, the number of other routing wires that can be connected to each routing wire, the length of the routing segment, the mode of the routing switch, the electrical design of the routing wires and programmable switches, and the number of routing segments in each channel. These parameters together determine the configuration of the data transmission path of the reconfigurable interconnection circuit for multi-core processors, enabling dynamic adjustment of the routing path according to different data transmission requirements, adapting to different application scenarios, and helping to utilize hardware resources more effectively.

[0056] According to one embodiment of this application, the programmable switch is implemented using a multiplexer and a tri-state buffer.

[0057] In the above technical solution, the programmable switch is implemented using a multiplexer and a tri-state buffer, which improves the flexibility and control capability of the programmable switch. It can be dynamically adjusted according to real-time data transmission requirements and routing decisions, thereby improving the flexibility of reconfigurable interconnect circuits for multi-core processors.

[0058] According to one embodiment of this application, the multi-master multi-slave routing arbitration structure includes an AMBA bus matrix, which is used to connect all AMBA bus interfaces of the multi-core processor.

[0059] In the above technical solution, the multi-master multi-slave routing arbitration structure includes an AMBA bus matrix for connecting all AMBA bus interfaces of the multi-core processor. By centrally connecting all AMBA bus interfaces of the multi-core processor, the efficiency of data transmission is improved, the use of hardware resources is optimized, and the flexibility of reconfigurable interconnect circuits for multi-core processors is enhanced.

[0060] Secondly, this application provides a method for implementing reconfigurable interconnect circuits for multi-core processors, the method comprising:

[0061] Based on interconnection requirements, interconnection parameters on the multi-core processor side, and interconnection parameters on the embedded FPGA side, the code for the reconfigurable interconnection circuit for the multi-core processor is generated.

[0062] Generate an FPGA configuration file based on the code;

[0063] The FPGA configuration file is downloaded to the embedded FPGA to form the reconfigurable interconnect circuit for multi-core processors.

[0064] In the above technical solution, based on interconnection requirements, interconnection parameters on the multi-core processor side, and interconnection parameters on the embedded FPGA side, code for the reconfigurable interconnection circuit for multi-core processors is generated, and the code is converted into an FPGA configuration file. The FPGA configuration file is then downloaded to the embedded FPGA, thus realizing a reconfigurable interconnection circuit for multi-core processors. This improves the flexibility of implementing a reconfigurable interconnection circuit for multi-core processors, and the implemented reconfigurable interconnection circuit for multi-core processors can meet different interconnection requirements, enhancing the scalability and adaptability of the reconfigurable interconnection circuit for multi-core processors.

[0065] According to one embodiment of this application, the interconnect parameters on the multi-core processor side include at least one of the following: number of CPU cores, data bit width of each CPU, number of master and slave CPUs, access address space of each CPU, CPU interface type, number of interfaces of the multi-master multi-slave routing arbitration structure, and interface type of the multi-master multi-slave routing arbitration structure.

[0066] The interconnect parameters on the embedded FPGA side include at least one of the following: number of embedded FPGA master and slave, AMBA bus interface type, number of interconnect component signals, interconnect component type, and quantity of each type of interconnect component.

[0067] In the above technical solution, based on interconnection requirements, at least one of the following is generated: number of CPU cores, data bit width of each CPU, number of CPU masters and slaves, access address space of each CPU, CPU interface type, number of interfaces and interface types of the multi-master multi-slave routing arbitration structure, and at least one of the following: number of embedded FPGA masters and slaves, AMBA bus interface type, number of interconnection component signals, interconnection component type, and quantity of each type of interconnection component. This improves the flexibility of implementing reconfigurable interconnection circuits for multi-core processors, and the implemented reconfigurable interconnection circuits for multi-core processors can meet different interconnection requirements, enhancing the scalability and adaptability of reconfigurable interconnection circuits for multi-core processors.

[0068] According to one embodiment of this application, generating the code for the reconfigurable interconnect circuit for the multi-core processor based on interconnect requirements, interconnect parameters on the multi-core processor side, and interconnect parameters on the embedded FPGA side includes:

[0069] Based on interconnection requirements, determine the data transmission within the multi-core processor or between the multi-core processor and the embedded FPGA;

[0070] Based on the interconnect parameters on the multi-core processor side and the interconnect parameters on the embedded FPGA side, code for the reconfigurable interconnect circuit for the multi-core processor is generated for the data transmission.

[0071] In the above technical solution, based on interconnection requirements, the data transmission within the multi-core processor or between the multi-core processor and the embedded FPGA is determined. Based on the interconnection parameters on the multi-core processor side and the interconnection parameters on the embedded FPGA side, code for a reconfigurable interconnection circuit for the multi-core processor is generated for data transmission. This enables the implementation of the corresponding reconfigurable interconnection circuit for the multi-core processor, enhancing the scalability and adaptability of the reconfigurable interconnection circuit for the multi-core processor.

[0072] Thirdly, this application provides a chip that includes a multi-core processor and an embedded FPGA, and further includes reconfigurable interconnect circuitry for the multi-core processor as described in the first aspect above.

[0073] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0074] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0075] Figure 1 is a schematic diagram of the structure of a reconfigurable interconnect circuit for multi-core processors provided in some embodiments of this application;

[0076] Figure 2 is a schematic diagram of interconnect resources under an islanded interconnect architecture provided in some embodiments of this application;

[0077] Figure 3 is a schematic diagram of a switch box provided in some embodiments of this application;

[0078] Figure 4 is a schematic diagram of a connection box provided in some embodiments of this application;

[0079] Figure 5 is a schematic diagram of the configuration interconnection resources provided in some embodiments of this application;

[0080] Figure 6 is a schematic diagram of the interconnection channel structure provided in some embodiments of this application;

[0081] Figure 7 is a schematic diagram of a programmable switch topology provided in some embodiments of this application;

[0082] Figure 8 is a schematic diagram of the structure of a bidirectional interconnection switch provided in some embodiments of this application;

[0083] Figure 9 is a schematic diagram of the structure of a unidirectional interconnection switch provided in some embodiments of this application;

[0084] Figure 10 is a schematic diagram of a multi-master multi-slave routing arbitration structure or interconnection component provided in some embodiments of this application;

[0085] Figure 11 is a schematic diagram of a programmable switch structure provided in some embodiments of this application;

[0086] Figure 12 is a schematic diagram of a multiplexer provided in some embodiments of this application;

[0087] Figure 13 is a schematic diagram of an AMBA bus matrix provided in some embodiments of this application;

[0088] Figure 14 is a flowchart illustrating a method for implementing a reconfigurable interconnect circuit for a multi-core processor according to some embodiments of this application.

[0089] Figure labeling: 10: Reconfigurable interconnect circuit for multi-core processors; 101: Multi-master multi-slave routing arbitration structure; 1011: AMBA bus matrix; 102: Interconnect component; 1021: Slave interconnect component; 1022: Master interconnect component; 1023: Storage interconnect component; 1024: System application interconnect component; 1025: Control interconnect component. Detailed Implementation

[0090] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0091] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0092] With ever-increasing computing demands, the performance bottleneck of single-core processors in handling complex tasks has made multi-core processors a key technology for improving computing power. Multi-core processors, by integrating multiple CPU cores, can achieve higher parallel processing capabilities and stronger computing performance. However, the performance of a multi-core processor depends not only on the processing power of the cores, but also on the efficiency of inter-core communication, which directly affects data transfer speed, system latency, and overall system performance.

[0093] In multi-core processors, inter-core communication typically employs two methods: pipelining and shared memory. In pipelining mode, data is transferred between different cores via private caches. For example, after CPU0 processes data, it passes it to CPU1, which then passes it to CPU2, and so on. While this method allows for continuous task processing, data transfer across core caches introduces significant latency. On the other hand, while inter-core data transfer based on shared memory is possible, its performance is limited because accessing shared memory consumes far more clock cycles than accessing private caches.

[0094] In System-on-Chip (SoC) design, multi-core processors can be tightly integrated with embedded Field Programmable Gate Arrays (FPGAs) to form a heterogeneous computing platform. The multi-core processor is responsible for performing general computing tasks, while the embedded FPGA can be used for specific hardware acceleration tasks. The two work together to improve system performance and efficiency. Embedded FPGAs can also be called eFPGAs. How to achieve communication and interconnection between multi-core processors and eFPGAs is a problem that needs to be solved.

[0095] The reconfigurable interconnect circuit, implementation method, and chip for multi-core processors provided in this application will be described in detail below with reference to the accompanying drawings and through specific embodiments and application scenarios.

[0096] Figure 1 is a schematic diagram of a reconfigurable interconnect circuit for multi-core processors provided in some embodiments of this application. As shown in Figure 1, the reconfigurable interconnect circuit 10 for multi-core processors includes: a multi-master multi-slave routing arbitration structure 101 and an interconnect component 102. The multi-core processor is connected to the multi-master multi-slave routing arbitration structure 101, and the multi-master multi-slave routing arbitration structure 101 is connected to an embedded FPGA through the interconnect component 102.

[0097] The multi-master multi-slave routing arbitration structure 101 is used to identify and route arbitration of data transmission within the multi-core processor or between the multi-core processor and the embedded FPGA, and to allocate corresponding interconnection resources for the data transmission. The interconnection resources are implemented based on the interconnection component 102.

[0098] The interconnect component 102 is used to manage and transmit communication between the interfaces connected to the interconnect component, wherein the interface is the interface on the multi-core processor side and / or the interface on the embedded FPGA side.

[0099] The multi-master multi-slave routing arbitration structure or the interconnection component adopts an island-type interconnection architecture, and the interconnection resources under the island-type interconnection architecture include global interconnection resources and local interconnection resources;

[0100] The global interconnection resources include interconnection channels and switch boxes, and the local interconnection resources include connection boxes, wherein...

[0101] The interconnection channel is composed of a preset number of interconnection segments, which are used to realize signal transmission between logic function blocks;

[0102] The switch box includes a preset number of programmable switches for switching between different interconnecting segments;

[0103] The connection box includes an input connection module and an output connection module, which are used to realize signal transmission between logic function blocks and interconnection channels;

[0104] The complete interconnect circuit function required by the user is formed by connecting and expanding the functions implemented by multiple logic function blocks.

[0105] Understandably, the multi-master multi-slave routing arbitration structure 101 allows multiple master devices (such as multiple processors) and multiple slave devices (such as embedded FPGAs or other devices) to transmit data, and identifies, arbitrates, and makes routing decisions for these data transmission requests, so that data can be transmitted between devices through the correct path, and allocates interconnect resources based on interconnect components for data transmission.

[0106] Interconnect component 102 connects multi-master multi-slave routing arbitration structure 101 and embedded FPGA, and is used to manage and transmit communication between the interfaces connected to the interconnect component.

[0107] Optionally, the communication between the interfaces can be communication between the interface on the multi-core processor side and the interface on the embedded FPGA side, or communication between the interfaces on the multi-core processor side, or communication between the interfaces on the embedded FPGA side.

[0108] Interconnect component 102 manages and transmits communication between its connected interfaces, thereby realizing the interconnect resources allocated by the multi-master multi-slave routing arbitration structure 101. This enables the connection relationships between different interfaces and interconnect segments, as well as the jump relationships between interconnect segments, which can meet different computing needs and application scenarios.

[0109] The multi-master multi-slave routing arbitration structure 101 identifies, arbitrates, and makes routing decisions for data transmission. The interconnect component 102 manages and transmits communication between the interfaces connected to the interconnect component based on the routing decisions of the multi-master multi-slave routing arbitration structure 101, thereby realizing the corresponding interconnect resources. The multi-master multi-slave routing arbitration structure 101 and the interconnect component 102 together form a reconfigurable interconnect circuit, enabling real-time, reliable, and efficient interconnection between multi-core processors and embedded FPGAs.

[0110] It should be noted that the multi-master multi-slave routing arbitration structure 101 identifies and arbitrates data transmission based on the address space. That is, when a data transmission request occurs, the multi-master multi-slave routing arbitration structure determines the data transmission address based on the destination address or source address of the transmission request, and further determines the routing path and allocates the corresponding interconnection resources, thereby realizing real-time, reliable and efficient interconnection between multi-core processors and embedded FPGAs.

[0111] As shown in Figure 1, in the system-on-a-chip, the multi-master multi-slave routing arbitration structure 101 and the interconnect component 102 act as switches to enable communication between the multi-core processor and the embedded FPGA.

[0112] Optionally, the interface communicates based on the Advanced Microcontroller Bus Architecture (AMBA) protocol and can be called an AMBA interface.

[0113] The AMBA protocol includes Advanced High-performance Bus (AHB), Advanced Peripheral Bus (APB), and Advanced eXtensible Interface (AXI), which can be used to implement connections between processors, memory, and peripherals with different performance and power consumption requirements.

[0114] Within a processor system (a multi-core processor system), AMBA is used within the APU to connect the processor cores to the SCU, cache memory, or OCM, as well as various interconnects within the FPGA. These connections complement the connections at the CPU-eFPGA boundary.

[0115] In some embodiments, the reconfigurable interconnect circuit for multi-core processors may include multiple interconnect components 102 with different functions. Some interconnect components 102 are directly connected to the embedded FPGA for data exchange between the central processing unit (CPU) in the multi-core processor and the embedded FPGA. The CPU can be simply referred to as a processor, and the multi-core processor includes at least one processor. Other interconnect components 102 are used for connections between CPUs or within the embedded FPGA. The connections between interconnect components 102 can also be based on the AMBA protocol, enabling data to be transferred between interconnect components, thereby allowing the SoC to achieve efficient data processing to adapt to various complex computing needs.

[0116] Figure 2 is a schematic diagram of interconnection resources under an islanded interconnection architecture provided in some embodiments of this application. As shown in Figure 2, the islanded multi-master multi-slave routing arbitration structure includes interconnection channels, switch boxes, connection boxes, input cross-connection modules, and logical function blocks (also called logical function modules or logical clusters) composed of multiple logical units, and also includes IP function modules. An IP function module (Intellectual Property Core) refers to a pre-designed and verified integrated circuit design module with specific functions. A logical function block can also be represented as a Configurable Logic Block (CLB). Multiple Configurable Logic Blocks constitute programmable logic resources.

[0117] In an islanded interconnect architecture, the multi-master multi-slave routing arbitration structure or interconnect components are divided into several independent functional units, namely "islands". The islands are divided into global interconnect resources and local interconnect resources to support signal transmission and logic control within the SoC.

[0118] The global interconnection resources include interconnection channels and switch boxes (SBs). Interconnection channels enable signal transmission between logic function blocks via preset interconnection segments. The switch box includes a preset number of programmable switches. Figure 3 is a schematic diagram of a switch box provided in some embodiments of this application. The switch box is used to enable switching between different interconnection segments, and to perform path selection and switching control between different interconnection segments, thereby managing the direction and routing of signal transmission.

[0119] Interconnect channels are composed of a predetermined number of regularly connected units. The vast majority of signal transmission between logic functional blocks is achieved through these interconnect units, including long and short interconnect segments. Short interconnect segments are used to interconnect adjacent logic functional blocks, while long interconnect segments are used to meet the signal path requirements between logic functional blocks that are far apart. The number, direction, length, composition ratio, and distribution of interconnect channels affect the circuit's delay characteristics and signal quality, and directly determine the routing efficiency and resource utilization of the embedded FPGA.

[0120] Local interconnect resources include connection boxes (CBs), which contain input connection modules and output connection modules. These are used to implement signal transmission between logic function blocks and interconnect channels, and also to connect interconnect segments and programmable logic resources. Figure 4 is a schematic diagram of a connection box provided in some embodiments of this application.

[0121] Interconnect segments in the chip layout are actually horizontal or vertical metal lines. These metal lines are bidirectional, but since all interconnect segments are connected by interconnect switches in the SB, the direction of the switch circuit in the interconnect resource determines the direction of the interconnect segment.

[0122] In some embodiments, the local interconnection resource further includes: an input cross-connection module, which is used to realize signal interconnection between logic units and to connect the input pins of the logic function block to each logic unit;

[0123] The logic unit comprises the logic function block.

[0124] The input cross-connect module is used to realize signal interconnection between logic units and connect the input pins of logic function blocks to the corresponding logic units. Specifically, it may include the allocation and sharing of input pin connections, cascading between logic units, and feedback of output signals.

[0125] In the above technical solution, the reconfigurable interconnect circuit for multi-core processors includes a multi-master multi-slave routing arbitration structure and interconnect components. The multi-master multi-slave routing arbitration structure is used to identify and arbitrate data transmission between the multi-core processor and the embedded FPGA, and to allocate interconnect resources based on the interconnect components. The interconnect components manage and transmit communication between the multi-core processor and the embedded FPGA interface. By dynamically allocating interconnect resources through routing arbitration, a reconfigurable interconnect circuit is formed, realizing real-time, reliable and efficient interconnection between the multi-core processor and the embedded FPGA. This can reduce the demand for hardware resources and reduce the size of the system-on-a-chip. The multi-master multi-slave routing arbitration structure or interconnect components are islanded interconnect architectures, and the interconnect resources are divided into global interconnect resources and local interconnect resources. The global interconnect resources include interconnect channels and switch boxes, which are used to transmit signals between logic function blocks, and the programmable switches in the switch boxes control the direction and path of signal transmission. Local interconnect resources, including connection boxes, enable signal transmission between logic function blocks and interconnect channels. By connecting and expanding the functions implemented by logic function blocks, complete application circuit functions required by users can be formed, satisfying users' interconnection needs. The island-type interconnect architecture allows for the expansion of more processors or peripherals through multi-master multi-slave routing arbitration structures and interconnect components, adapting to different communication needs. Different types of interconnect channels and switch boxes help to utilize hardware resources more effectively, reduce the size of reconfigurable interconnect circuits for multi-core processors, and thus reduce the size of system-on-a-chip.

[0126] In one embodiment of this application, the interconnection component 102 includes a slave interconnection component 1021, a host interconnection component 1022, a storage interconnection component 1023, a system application interconnection component 1024, and a control interconnection component 1025, wherein...

[0127] The slave interconnection component 1021 is used to interconnect at least one processor in a multi-core processor with an embedded FPGA, wherein the at least one processor acts as a slave and the embedded FPGA acts as a master.

[0128] The host interconnect component 1022 is used to interconnect at least one processor in a multi-core processor with an embedded FPGA, wherein the at least one processor acts as a host and the embedded FPGA acts as a slave.

[0129] The storage interconnect component 1023 is used to interconnect storage resources;

[0130] The system application interconnection component 1024 is used to realize the interconnection of system-level applications;

[0131] The control interconnection component 1025 is used to transmit control signals.

[0132] As shown in Figure 1, the slave interconnect component 1021 is used to interconnect at least one CPU in the multi-core processor as a slave and the eFPGA as a master. That is, through the slave interconnect component 1021, the CPU in the multi-core processor can respond to the request of the eFPGA and execute the corresponding task. The master interconnect component 1022 is used to interconnect at least one CPU in the multi-core processor as a master and the eFPGA as a slave. That is, through the master interconnect component 1022, the multi-core processor can control the eFPGA and send instructions and data to it. The storage interconnect component 1023 is used to interconnect storage resources, that is, to manage the access of the multi-core processor and the eFPGA to storage resources (such as memory, hard disk, etc.) and realize data storage and retrieval. The system application interconnect component 1024 is used to interconnect system-level applications, such as for data exchange and communication between different applications. The control interconnect component 1025 is used to transmit control signals and manage the control signals (such as synchronization signals, interrupt signals, etc.) between the multi-core processor and the FPGA to ensure stable operation of the SoC.

[0133] Different types of interconnect components collaborate to enable communication and data transfer between multi-core processors and embedded FPGAs or with other resources, adapting to different computing needs and application scenarios.

[0134] In some embodiments, the embedded FPGA as a host includes at least one programmable logic device instantiated from the embedded FPGA as a host.

[0135] In some embodiments, the embedded FPGA as a slave device includes at least one programmable logic device instantiated from the embedded FPGA as a slave device.

[0136] eFPGA is an FPGA embedded in a SoC. Instantiation refers to creating an instance of a specific hardware design, which can be a logic module, a processor core, or any other predefined hardware structure. Programmable logic devices are hardware components whose internal logic can be reconfigured after manufacturing. In embedded FPGAs, programmable logic devices typically consist of programmable logic units (such as lookup tables, flip-flops, etc.) and programmable resources (such as switch boxes, wiring resources, etc.).

[0137] When an embedded FPGA acts as the host, the embedded FPGA instantiates at least one programmable logic device as the host. That is, the FPGA can actively initiate communication requests and control data transmission or logic processing. As the host, the FPGA can directly communicate and exchange data with other parts of the SoC.

[0138] When an embedded FPGA acts as a slave device, the embedded FPGA instantiates at least one programmable logic device as a slave device to respond to requests from the CPU or other host. As a slave device, the embedded FPGA can execute specific tasks or requests initiated by the host, enabling the host to effectively utilize the embedded FPGA.

[0139] In some embodiments, the host interconnect component 1022 is also used to realize interconnection between processors in the multi-core processor, with at least one processor acting as a host and at least another processor acting as a slave.

[0140] Understandably, the host interconnect component 1022 can be used to interconnect at least one processor in a multi-core processor as the host and the embedded FPGA as the slave. It can also be used to interconnect at least one processor within a multi-core processor as the host and at least another processor as the slave. In other words, the host interconnect component 1022 can support communication within a multi-core processor, allowing communication between different CPUs without the need for external devices, thereby improving the communication efficiency within the multi-core processor, reducing communication latency, and improving the processing power of the SoC.

[0141] In some embodiments, the host interconnect component 1022 is further configured to implement interconnection between at least one processor of the multi-core processor and the embedded FPGA and at least another processor, wherein at least one processor of the multi-core processor acts as a host, and at least one programmable logic device instantiated by the embedded FPGA and the at least another processor act as slaves.

[0142] It is understandable that the host interconnect component 1022 can be used to realize the interconnection between the host and slave within the multi-core processor, and can also be used to communicate with at least one programmable logic device instantiated in the eFPGA as a slave. That is, the host interconnect component can manage the communication within the multi-core processor and the communication between the multi-core processor and the eFPGA at the same time, so that the multi-core processors and the embedded FPGA can cooperate more closely to meet the corresponding computing needs and application scenarios.

[0143] In the above technical solution, the interconnect components include slave interconnect components, master interconnect components, storage interconnect components, system application interconnect components, and control interconnect components. Different types of interconnect components cooperate to realize data transmission and control signal transmission between the multi-core processor and the embedded FPGA, or between the multi-core processor and other resources. The processor in the multi-core processor and the instantiated programmable logic device in the embedded FPGA can be configured as a master or slave, improving data transmission efficiency. Different types of interconnect components can adapt to different communication needs. By dynamically allocating interconnect resources, the demand for hardware resources can be effectively reduced, the size of the reconfigurable interconnect circuit can be reduced, and thus the size of the system-on-a-chip can be reduced.

[0144] In one embodiment of this application, the type of the interface includes at least one of the following: AMBA general interface, AMBA high-performance interface, AMBA_ACP interface, and CTRL_IO_SIG interface.

[0145] The AMBA universal interface is a standardized interface used to connect various components in a multi-core processor and an eFPGA, supporting basic data transfer and communication needs and suitable for a variety of different devices and application scenarios. In some embodiments, the AMBA universal interface is designed as a 32-bit or 64-bit data bus for low-to-medium speed data communication between the multi-core processor and the eFPGA. The interface is transparent, meaning data is directly transferred from one device to another without additional buffering. Two AMBA universal interfaces are configured to enable bidirectional communication: one interface allows the CPU to control communication as a master, while the other allows the PL (Programmable Logic Device, instantiated from the eFPGA) to control communication as a master. This allows the CPU and eFPGA to act as master or slave as needed in different scenarios, thereby improving the flexibility and communication efficiency of the SoC.

[0146] The AMBA high-performance interface is designed to meet the demands of high-performance computing, providing higher data transfer rates and lower latency. In some embodiments, the AMBA high-performance interface features a FIFO (First-In-First-Out) buffer, allowing for batch read and write operations, thereby further improving data transfer efficiency. It supports high-speed data communication between eFPGAs and multi-core processors, with a data bus width of 32 bits or 64 bits to accommodate different data transfer requirements.

[0147] The AMBA_ACP interface is an interface designed for accelerators that supports cache coherency protocols, allowing accelerators to directly access SoC memory and maintain consistency with the processor cache. This can be used to improve data processing efficiency and reduce latency.

[0148] The CTRL_IO_SIG interface is used to pass control signals between multi-core processors and eFPGAs, and can be used to achieve synchronous operation between SoC components and correct data transmission control.

[0149] In the above technical solution, the reconfigurable interconnect circuit for multi-core processors uses multiple interface types, including at least one of the following: AMBA general-purpose interface, AMBA high-performance interface, AMBA_ACP interface, and CTRL_IO_SIG interface. The AMBA general-purpose interface supports communication between the multi-core processor and the embedded FPGA in either a master or slave role. The AMBA high-performance interface improves data transmission rate through FIFO buffering. The ACP interface achieves cache coherency and can be used to optimize accelerator memory access. The CTRL_IO_SIG interface is used to transmit control signals. By configuring different interfaces, the interface can be dynamically selected according to communication requirements, improving data transmission efficiency. The design of multiple interface types and interconnect components allows the reconfigurable interconnect circuit for multi-core processors to adapt to different communication needs, effectively reducing the demand for hardware resources and the size of the reconfigurable interconnect circuit for multi-core processors, thereby reducing the size of the system-on-a-chip (SoC).

[0150] In one embodiment of this application, all interfaces on the multi-core processor side, except for the accelerated consistency interface, are connected to the multi-master multi-slave routing arbitration structure, and then connected to the embedded FPGA through the interconnect component.

[0151] The Accelerator Coherency Port (ACP) is a dedicated interface for high-speed cache-coherent access between multi-core processors and embedded FPGAs. It supports all standard read and write transactions without requiring additional consistency management.

[0152] Understandably, the ACP interface already has the ability to handle consistent transactions, so there is no need for additional consistency management through a multi-master multi-slave routing arbitration structure. It also avoids the additional contention and waiting time that may occur in a multi-master multi-slave routing arbitration structure, which can improve the data transmission efficiency between multi-core processors and embedded FPGAs.

[0153] In the above technical solution, all interfaces on the multi-core processor side, except for the accelerated consistency interface, are connected to the multi-master multi-slave routing arbitration structure, and then connected to the embedded FPGA through interconnect components. Interconnect resources are dynamically allocated through routing arbitration, forming a reconfigurable interconnect circuit, realizing the interconnection between the multi-core processor and the embedded FPGA. This can reduce the demand for hardware resources and reduce the size of the system-on-a-chip. The accelerated consistency interface is not connected to the multi-master multi-slave routing arbitration structure, avoiding possible additional contention and waiting time, and improving the data transmission efficiency between the multi-core processor and the embedded FPGA.

[0154] In one embodiment of this application, the accelerated coherence interface on the multi-core processor side is directly connected to the system application interconnect component in the interconnect component, and the system application interconnect component is a coherence control unit within the accelerated processor.

[0155] The System Coherency Unit (SCU) within the Accelerated Processing Unit (APU) is used to maintain cache coherency within the multi-core processor.

[0156] Understandably, the accelerated consistency interface is directly connected to the consistency control unit within the accelerated processor. This connection method allows the accelerated consistency interface to be directly connected to the system application interconnect component in the interconnect component instead of the multi-master multi-slave routing arbitration structure. This simplifies the data transmission path and improves the data transmission efficiency between the multi-core processor and the embedded FPGA.

[0157] In the above technical solution, the accelerated coherence interface on the multi-core processor side is directly connected to the system application interconnect component in the interconnect component. This component is the coherence control unit inside the accelerated processor, which can simplify the data transmission path and improve the data transmission efficiency between the multi-core processor and the embedded FPGA.

[0158] In one embodiment of this application, the interface on the embedded FPGA side includes at least one of the following: host AMBA general interface, slave AMBA general interface, host AMBA high-performance interface, slave AMBA_ACP interface and CTRL_IO_SIG interface;

[0159] The slave interconnect component is connected to the host AMBA general interface, the host interconnect component is connected to the slave AMBA general interface, the storage interconnect component is connected to the host AMBA high-performance interface, the system application interconnect component is connected to the slave AMBA_ACP interface, and the control interconnect component is connected to the CTRL_IO_SIG interface.

[0160] On the embedded FPGA side, the host AMBA general-purpose interface is used for communication when the embedded FPGA acts as the host and the processor acts as the slave. The host AMBA high-performance interface is used to implement high-speed data transmission, the slave AMBA_ACP interface is used to connect high-speed data transmission that supports cache coherency, and the CTRL_IO_SIG interface is used to transmit control signals and input / output signals.

[0161] The master interconnect component connects to the slave AMBA general interface, allowing the embedded FPGA to act as a slave in response to processor requests. The storage interconnect component connects to the master AMBA high-performance interface for high-speed data transfer of storage resources. The system application interconnect component connects to the slave AMBA_ACP interface for high-speed data transfer in system-level applications. The control interconnect component connects to the CTRL_IO_SIG interface for transmitting control signals and input / output signals.

[0162] Table 1

[0163] Table 1 is an interface description table provided in some embodiments of this application. As shown in Table 1, in some embodiments, the interface types also include AHB_HP interface and AHB_GP interface. When the interface name in Table 1 starts with M, the processor is the master and the embedded FPGA is the slave. When the interface name in Table 1 starts with S, the processor is the slave and the embedded FPGA is the master.

[0164] The AHB_HP interface implements a high-bandwidth data path from the FPGA bus host to the OCM and DDR memory, featuring two read / write communication FIFO buffers. The memory interconnect component connects the high-speed AXI_HP interface to two DDR memory interfaces or the OCM. The AXI_HP interface has a 32-bit or 64-bit data host interface, each independently programmable, capable of automatically scaling unaligned 32-bit transfers to 64-bit. The AXI_HP interface also features a programmable write command threshold, supports cross-domain operations at asynchronous clock frequencies, and includes read / write FIFOs. Command and communication data FIFO fill counts are visible to the FPGA, allowing the eFPGA to dynamically monitor and manage data.

[0165] The AHB_GP interface is a direct-connect interface. Unlike the AHB_HP interface, the AHB_GP interface lacks additional buffering. Therefore, its performance is primarily limited by the host interface and slave interconnect. The AHB_GP interface is more suitable for general-purpose rather than high-performance tasks. Each AHB_GP interface can support multiple peripherals. The AHB_GP interface supports 32-bit or 64-bit data bus width, with a 12-bit bus interface ID width and a 6-bit slave interface ID width. Both the host and slave interfaces can accept one 8-read and one 8-write operation.

[0166] In the above technical solution, the slave interconnect component is connected to the host AMBA general interface, the host interconnect component is connected to the slave AMBA general interface, the storage interconnect component is connected to the host AMBA high-performance interface, the system application interconnect component is connected to the slave AMBA_ACP interface, and the control interconnect component is connected to the CTRL_IO_SIG interface. This illustrates the interface configuration on the embedded FPGA side and its connection method with different interconnect components, realizing communication and data transmission between the multi-core processor and the embedded FPGA, which can meet the data transmission needs in different application scenarios.

[0167] In one embodiment of this application, allocating corresponding interconnection resources for the data transmission includes: determining the connection relationship of interconnection segments in the interconnection component and the jump relationship between interconnection segments based on the number of interfaces, interface types and circuit application requirements of the multi-master multi-slave routing arbitration structure, and generating a reconfigurable configuration file. The reconfigurable configuration file is used to configure the on or off of the programmable switch in the switch box and the input connection module and output connection module in the connection box.

[0168] Understandably, in a multi-master, multi-slave routing arbitration structure, efficient data transmission requires the allocation of corresponding interconnect resources. This allocation process is determined based on the number and type of interfaces in the multi-master, multi-slave routing arbitration structure, as well as the circuit application requirements. Due to the complexity of the interface logic between the processor and the embedded FPGA, a large number of interfaces and dedicated interconnect resources are needed to implement data transmission. Therefore, in some embodiments, a multi-level combined interconnect structure is used to design the connection relationships of interconnect segments in the interconnect components and the jump relationships between interconnect segments.

[0169] In a multi-master, multi-slave routing arbitration structure, the number of interfaces determines the number of channels that can transmit data, while the interface type determines the type of data transmitted. Circuit application requirements, i.e., different application scenarios, have different data transmission needs, including data transmission rate, latency, and bandwidth. These requirements directly affect the allocation and configuration of interconnect resources.

[0170] Interconnect segments are the foundation of interconnect components. They connect different logical functional blocks within the interconnect components. By determining the connection relationships between interconnect segments, data transmission paths are formed, enabling efficient data transmission. Within an interconnect component, data may need to hop between multiple interconnect segments. The hopping relationships determine the data routing path in the interconnect circuit and how path selection is performed through interconnect components such as switch boxes. After determining the connection relationships of interconnect segments within the interconnect component and the hopping relationships between interconnect segments, a reconfigurable configuration file can be generated.

[0171] Figure 5 is a schematic diagram of the configuration interconnection resources provided in some embodiments of this application. As shown in Figure 5, the multi-master multi-slave routing arbitration structure or interconnection components adopt an islanded interconnection architecture. The interconnection resources under the islanded interconnection architecture include global interconnection resources and local interconnection resources. The global interconnection resources include interconnection channels and switch boxes. The interconnection channels are composed of a preset number of interconnection segments and are used to realize signal transmission between logic function blocks. The switch boxes include a preset number of programmable switches and are used to realize switching between different interconnection segments. The local interconnection resources include connection boxes, including input connection modules and output connection modules. The input connection modules and output connection modules are not shown in Figure 5 and can be implemented using programmable switches. The connection boxes are used to realize signal transmission between logic function blocks and interconnection channels. Among them, the reconfigurable configuration file is used to configure the programmable switches in the switch boxes and the input connection modules and output connection modules in the connection boxes to be turned on or off.

[0172] In the above technical solution, based on the number of interfaces, interface types, and circuit application requirements of the multi-master multi-slave routing arbitration structure, the connection relationship of interconnection segments in the interconnection component and the jump relationship between interconnection segments are determined, a reconfigurable configuration file is generated, and corresponding interconnection resources are allocated for data transmission according to the reconfigurable configuration file. This enables the reconfigurable interconnection circuit for multi-core processors to adapt to different data transmission requirements and improves the flexibility of the reconfigurable interconnection circuit for multi-core processors.

[0173] In one embodiment of this application, the horizontal and vertical channels of the embedded FPGA-side programmable interconnect provide the global interconnect resources, which interact with the local interconnect resources and the multi-core processor-side interconnect bus via signals.

[0174] The signal output from the multi-core processor side is sent to the interconnect component through the local interconnect resource and processed by the corresponding logic unit; alternatively, the signal output from the multi-core processor side is sent to the adjacent logic unit for processing through the horizontal channel.

[0175] The embedded FPGA-side programmable interconnects, including horizontal and vertical channels, provide global interconnect resources that allow signals to be transmitted between different logic units. These global interconnect resources include interconnect channels and switch boxes. The interconnect channels are used to transmit signals between logic functional blocks, while the switch boxes contain programmable switches to control the direction and path of signal transmission, thereby enabling flexible signal routing.

[0176] Signal outputs from the multi-core processor can be sent to interconnect components via local interconnect resources, and these signals can also be sent directly to adjacent logic units for processing via horizontal channels, thereby reducing data transmission latency.

[0177] Local interconnect resources include a connection box and an input cross-connect module. The connection box includes input connection modules and output connection modules, used to realize signal transmission between logic function blocks and interconnect channels. The input cross-connect module realizes signal interconnection between logic units. This module can also connect the input pins of the logic function block to each logic unit. It should be noted that multiple logic units constitute a logic function block.

[0178] In the above technical solution, the horizontal and vertical channels of the programmable interconnect on the embedded FPGA side provide global interconnect resources. The global interconnect resources interact with the interconnect bus on the multi-core processor side through local interconnect resources. The signal output on the multi-core processor side is sent to the interconnect component through the local interconnect resources and processed by the corresponding logic unit, or sent to the adjacent logic unit through the horizontal channel for processing. Through the global and local interconnect resources, the interconnection between the multi-core processor and the embedded FPGA is realized, which improves the flexibility of the reconfigurable interconnect circuit for multi-core processors.

[0179] In one embodiment of this application, the interconnection channel is a one-way channel or a two-way channel.

[0180] Figure 6 is a schematic diagram of the interconnection channel provided in some embodiments of this application. As shown in Figure 6(a), in a unidirectional channel, the direction of signal transmission is determined at the end of the connection by a unidirectional inverter or buffer. Signals can only be transmitted from terminals A and C to terminals B and D respectively; the reverse direction is not possible. As shown in Figure 6(b), at the end of a bidirectional channel connection, the direction of signal transmission is usually selected by a bidirectional selector. The bidirectional selector is often implemented by a buffer or a tri-state buffer. Terminals A and B in the figure can achieve bidirectional signal transmission through configuration.

[0181] In the above technical solution, the interconnect channel is either a unidirectional channel or a bidirectional channel. By selecting different interconnect channels, various data transmission requirements can be adapted to improve the data transmission efficiency of reconfigurable interconnect circuits for multi-core processors.

[0182] In one embodiment of this application, the topology type of the programmable switch in the switch box includes at least one of subset interconnection, global interconnection, and vertical interconnection.

[0183] Figure 7 is a schematic diagram of a programmable switch topology provided in some embodiments of this application. As shown in Figure 7, the programmable switch topology types include at least one of subset interconnection, global interconnection, and vertical interconnection.

[0184] Subset interconnection refers to the configuration of programmable switches to connect specific circuit elements or modules, thereby forming a small, localized subset of connections. This connection method is suitable for scenarios where local communication is required between circuit modules to achieve specific functions.

[0185] Global interconnect refers to programmable switches being configured to allow for extensive, global connections between circuit elements or modules. This type of connection is typically used to implement complex circuit functions and system-level integration.

[0186] Vertical interconnect refers to connections between different layers or different circuit boards, allowing signals to be transmitted between different layers. This type of connection is typically achieved through vias, conductive pillars, or other vertical connection structures.

[0187] By appropriately selecting and applying the topology type of the programmable switches in the switch box, it is possible to achieve switching between different interconnection segments, path selection and switching control between different interconnection segments, thereby managing the direction and route of signal transmission.

[0188] In the above technical solution, the topology type of the programmable switch in the switch box includes at least one of subset interconnection, global interconnection and vertical interconnection. By reasonably selecting and applying the topology type of the programmable switch in the switch box, the flexibility and scalability of the reconfigurable interconnect circuit for multi-core processors can be improved.

[0189] In one embodiment of this application, the switch box is implemented by combining a bidirectional interconnection switch and a unidirectional interconnection switch.

[0190] Figure 8 is a schematic diagram of the structure of a bidirectional interconnecting switch provided in some embodiments of this application. As shown in Figure 8, the interconnecting segments in the horizontal (x) direction can transmit signals from left to right or from right to left; the interconnecting segments in the vertical (y) direction can transmit signals from top to bottom or from bottom to top. If the bidirectional interconnecting switch shown in Figure 8 is used in SB, then the interconnecting segments it drives are bidirectional.

[0191] Figure 9 is a schematic diagram of the structure of a unidirectional interconnection switch provided in some embodiments of this application. As shown in Figure 9, the unidirectional interconnection switch only allows signals to flow in one direction, and is suitable for scenarios where signal transmission has a clear directionality.

[0192] By combining bidirectional and unidirectional interconnect switches, the transmission path can be flexibly configured to adapt to different signal transmission requirements.

[0193] In some embodiments, the number of interconnect switches and the switching relationships are configured as follows: the connectivity (Fc) between function block (CLB) pins and interconnects is set to 10%, meaning that 10% of the interconnects passing through a CLB pin have a switch leading to that input pin; the number of other interconnect segments (Fs) that an interconnect segment can connect to at its end is at least 3, covering left, right, and forward directions. Logic function blocks allow direct data exchange between the inputs and outputs of logic units, i.e., adding direct-connect signals. By utilizing these flexibility and considering all the options offered by multi-level programmable interconnects, placement and routing tools can achieve high routing success rates even with low Fc and Fs values.

[0194] In the above technical solution, the switch box is implemented by combining bidirectional interconnection switches and unidirectional interconnection switches. By selecting different interconnection switches, various signal transmission requirements can be adapted to improve the data transmission efficiency of reconfigurable interconnection circuits for multi-core processors.

[0195] In one embodiment of this application, the interconnection segments include long interconnection segments, short interconnection segments, local interconnection segments, and direct-connection segments. The long interconnection segments are used to meet the signal path requirements between logic functional blocks that are far apart. The short interconnection segments are used to realize the interconnection between adjacent logic functional blocks. The local interconnection segments are used to realize signal sharing and feedback between logic units within each logic functional block. The direct-connection segments are used for signal transmission between adjacent logic functional blocks.

[0196] Understandably, long interconnect segments are used to meet the signal path requirements between logic functional blocks that are far apart. In reconfigurable interconnect circuits for multi-core processors, logic functional blocks may be distributed in different locations, and long interconnect segments can span a large spatial distance, enabling signals to be accurately transmitted to the target logic functional block. Short interconnect segments are used to enable the flow of large amounts of signals and rapid interconnection between adjacent logic functional blocks. Because adjacent logic functional blocks are relatively close in space, short interconnect segments can reduce signal transmission delay and power consumption, thereby improving data transmission efficiency. Local interconnect segments are used to enable signal sharing and feedback between logic units within each logic functional block, helping to enhance the signal processing capabilities within the logic functional block. Straight-through segments are used for signal transmission between adjacent logic functional blocks, reducing signal transmission delay and power consumption.

[0197] In this embodiment, the interconnection segments adopt a multi-level combined interconnection system, namely "long line-short line-local interconnection line-straight connection line", which provides different types of rich interconnection resources to meet the interconnection needs of different applications, and can efficiently and flexibly realize user circuits.

[0198] Creating a good interconnect architecture involves many complex trade-offs. It includes enough programmable switches and interconnect segments to enable the majority of circuits to be implemented, achieving good routing efficiency; however, too many interconnect segments and programmable switches waste space. Short interconnect segments are used for short connections to reduce capacitance and layout area, while long interconnect segments can be used for longer connections to avoid additional delays caused by multiple programmable switches.

[0199] In the above technical solution, the design of the interconnection segment adopts a multi-level combined interconnection system, including long interconnection segments, short interconnection segments, local interconnection segments and direct connection segments, to meet the interconnection requirements of different distances and complexities, adapt to the layout and signal transmission of different logical functional blocks in the multi-master multi-slave routing arbitration structure and interconnection components, and improve the flexibility of reconfigurable interconnection circuits for multi-core processors.

[0200] In one embodiment of this application, the parameters of the multi-master multi-slave routing arbitration structure or interconnection component include: the number of routing wires that can be connected to the input or output of each logical function block, the number of other routing wires that can be connected to each routing wire, the length of the routing segment, the mode of the routing switch, the electrical design of the routing wires and programmable switches, and the number of routing segments for each channel.

[0201] The number of routing wires that each logic function block's inputs or outputs can connect to determines how many routing wires the logic function block can connect to, thus affecting signal transmission capability and flexibility. The number of other routing wires that each routing wire can connect to involves the cross-connection capability between routing wires, affecting signal routing selection and flow management on different paths. The length of the routing segment affects signal transmission delay and signal integrity, directly impacting circuit layout and wiring in physical design. The mode of the routing switch determines the configuration of the signal transmission path, including unidirectional or bidirectional transmission, and how path selection is performed via the switch box.

[0202] Figure 10 is a schematic diagram of a multi-master multi-slave routing arbitration structure or interconnection component provided in some embodiments of this application. Taking Figure 10 as an example, the number of routing wires that can be connected to the input or output of each logical function block is 3, the number of other routing wires that can be connected to each routing wire is 3, and the number of routing segments in each channel is 4.

[0203] Figure 11 is a schematic diagram of a programmable switch structure provided in some embodiments of this application. As shown in Figure 11, the eFPGA can use transmission transistors controlled by SRAM cells to connect interconnects. Although transmission transistors can provide the smallest area, this structure introduces a quadratic increase in delay when multiple transmission transistors are connected in series, which makes this structure slow when implementing large FPGAs.

[0204] In some embodiments, the programmable switch is implemented using a multiplexer and a tri-state buffer. To reduce latency by increasing area, the eFPGA uses a multiplexer composed of transmission transistors, with the multiplexer output buffered by a tri-state buffer.

[0205] A multiplexer (MUX) is a logic circuit with multiple input lines and one output line that selects one of multiple inputs as the output based on a selection signal. In reconfigurable interconnect circuits, the MUX is used to select the signal path that should be activated.

[0206] Figure 12 is a schematic diagram of a multiplexer provided in some embodiments of this application. This structure features a small transmission tube size and a large buffer size, allowing for a trade-off between area and driving capability. It possesses superior electrical characteristics, reduces area, and increases speed. This application can use the multiplexer shown in Figure 12 as the basic implementation structure of a programmable switch.

[0207] A tri-state buffer is a buffer that can exist in three states: high, low, and high impedance (disabled). The high impedance state allows other parts of the circuit to take over the bus, enabling multiple devices to share the same communication path without interfering with each other. In reconfigurable interconnect circuits, tri-state buffers are used to disable a path when signal transmission is not needed, or to coordinate access when multiple devices share the same bus.

[0208] Programmable switches implemented using multiplexers and tri-state buffers improve the flexibility and control of multi-master multi-slave routing arbitration structures or interconnect components, enabling dynamic adjustments based on real-time data transmission requirements and routing decisions.

[0209] In the above technical solution, the parameters of the multi-master multi-slave routing arbitration structure or interconnection component include the number of routing wires that can be connected to the input or output of each logical function block, the number of other routing wires that can be connected to each routing wire, the length of the routing segment, the mode of the routing switch, the electrical design of the routing wires and programmable switches, and the number of routing segments in each channel. These parameters together determine the configuration of the data transmission path of the reconfigurable interconnection circuit for multi-core processors, enabling dynamic adjustment of the routing path according to different data transmission requirements, adapting to different application scenarios, and helping to utilize hardware resources more effectively.

[0210] In one embodiment of this application, the multi-master multi-slave routing arbitration structure includes an AMBA bus matrix 1011, which is used to connect all AMBA bus interfaces of the multi-core processor.

[0211] Figure 13 is a schematic diagram of an AMBA bus matrix provided in some embodiments of this application. As shown in Figure 13, in some embodiments, the multi-master multi-slave routing arbitration structure further includes an AMBA bus matrix 1011, which is used to connect all AMBA bus interfaces of the multi-core processor. In a multi-core processor, different processors may need to access the same resources, such as memory or peripherals. The AMBA bus matrix provides a shared communication path, and by centrally managing the AMBA bus interfaces, resource allocation and flow control are achieved, optimizing the overall performance of the reconfigurable interconnect circuit for multi-core processors.

[0212] In the above technical solution, the multi-master multi-slave routing arbitration structure includes an AMBA bus matrix for connecting all AMBA bus interfaces of the multi-core processor. By centrally connecting all AMBA bus interfaces of the multi-core processor, the efficiency of data transmission is improved, the use of hardware resources is optimized, and the flexibility of reconfigurable interconnect circuits for multi-core processors is enhanced.

[0213] Figure 14 is a flowchart illustrating a method for implementing a reconfigurable interconnect circuit for a multi-core processor according to some embodiments of this application. As shown in Figure 14, the method for implementing the reconfigurable interconnect circuit for a multi-core processor includes steps 1410, 1420, and 1430.

[0214] Step 1410: Generate the code for the reconfigurable interconnect circuit for the multi-core processor based on the interconnect requirements, the interconnect parameters on the multi-core processor side, and the interconnect parameters on the embedded FPGA side.

[0215] The complete interconnect circuit functionality required by the user is formed by connecting and expanding the functions implemented by multiple logic function blocks. Interconnection requirements reflect the complete interconnect circuit functionality needed by the user, and based on the interconnection requirements, it can be determined which logic function blocks need to be connected and expanded.

[0216] In some embodiments, the interconnect parameters on the multi-core processor side include at least one of the following: number of CPU cores, data bit width per CPU, number of master and slave CPUs, access address space per CPU, CPU interface type, number of interfaces in the multi-master multi-slave routing arbitration structure, and interface type of the multi-master multi-slave routing arbitration structure.

[0217] The interconnect parameters on the embedded FPGA side include at least one of the following: number of embedded FPGA master and slave, AMBA bus interface type, number of interconnect component signals, interconnect component type, and quantity of each type of interconnect component.

[0218] In some embodiments, generating the code for the reconfigurable interconnect circuit for the multi-core processor based on interconnect requirements, interconnect parameters on the multi-core processor side, and interconnect parameters on the embedded FPGA side includes:

[0219] Based on interconnection requirements, determine the data transmission within the multi-core processor or between the multi-core processor and the embedded FPGA;

[0220] Based on the interconnect parameters on the multi-core processor side and the interconnect parameters on the embedded FPGA side, code for the reconfigurable interconnect circuit for the multi-core processor is generated for the data transmission.

[0221] Understandably, the code for reconfigurable interconnect circuits for multi-core processors is generated based on at least one of the following interconnect requirements: number of CPU cores, data bit width per CPU, number of CPU masters and slaves, access address space per CPU, CPU interface type, number of interfaces in the multi-master multi-slave routing arbitration structure, and interface type of the multi-master multi-slave routing arbitration structure; at least one of the following embedded FPGA master and slaves, AMBA bus interface type, number of interconnect component signals, interconnect component type, and quantity of each interconnect component type. The purpose is to ensure that the generated code can meet the communication and data transmission requirements of multi-core processors and embedded FPGAs. The generated code defines in detail the structure, function, and interconnection relationship of the multi-master multi-slave routing arbitration structure and interconnect components in the reconfigurable interconnect circuit for multi-core processors.

[0222] Step 1420: Generate the FPGA configuration file based on the code.

[0223] Based on the code generated in step 1410, a configuration file for the FPGA is created. The configuration file contains information that will be downloaded to the embedded FPGA for configuration. The generation of the configuration file may involve code compilation, synthesis, and optimization to ensure that the configuration file can be correctly understood and executed by the embedded FPGA.

[0224] Step 1430: Download the FPGA configuration file to the embedded FPGA to form the reconfigurable interconnect circuit for multi-core processors.

[0225] The FPGA configuration file generated in step 1420 is downloaded to the embedded FPGA, enabling it to implement the preset reconfigurable interconnect circuit for multi-core processors according to the instructions in the configuration file.

[0226] In the above technical solution, based on interconnection requirements, interconnection parameters on the multi-core processor side, and interconnection parameters on the embedded FPGA side, code for the reconfigurable interconnection circuit for multi-core processors is generated, and the code is converted into an FPGA configuration file. The FPGA configuration file is then downloaded to the embedded FPGA, thus realizing a reconfigurable interconnection circuit for multi-core processors. This improves the flexibility of implementing a reconfigurable interconnection circuit for multi-core processors, and the implemented reconfigurable interconnection circuit for multi-core processors can meet different interconnection requirements, enhancing the scalability and adaptability of the reconfigurable interconnection circuit for multi-core processors.

[0227] This application also provides a chip, which includes a multi-core processor and an embedded FPGA, and further includes a reconfigurable interconnect circuit for the multi-core processor. For an understanding of the reconfigurable interconnect circuit for the multi-core processor, please refer to the description in the foregoing embodiments, which will not be repeated here.

[0228] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0229] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0230] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the related technology, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0231] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

[0232] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0233] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A reconfigurable interconnect circuit for multi-core processors, characterized in that, include: A multi-master, multi-slave routing arbitration structure and interconnect components are provided. A multi-core processor is connected to the multi-master, multi-slave routing arbitration structure, and the multi-master, multi-slave routing arbitration structure is connected to an embedded field-programmable gate array (FPGA) through the interconnect components. The multi-master multi-slave routing arbitration structure is used to identify and route the data transmission within the multi-core processor or between the multi-core processor and the embedded FPGA, and to allocate corresponding interconnect resources for the data transmission. The interconnect resources are implemented based on the interconnect components. The interconnect component is used to manage and transmit communication between the interfaces connected to the interconnect component, wherein the interface is the interface on the multi-core processor side and / or the interface on the embedded FPGA side. The multi-master multi-slave routing arbitration structure or the interconnection component adopts an island-type interconnection architecture, and the interconnection resources under the island-type interconnection architecture include global interconnection resources and local interconnection resources; The global interconnection resources include interconnection channels and switch boxes, and the local interconnection resources include connection boxes, wherein... The interconnection channel is composed of a preset number of interconnection segments, which are used to realize signal transmission between logic function blocks; The switch box includes a preset number of programmable switches for switching between different interconnecting segments; The connection box includes an input connection module and an output connection module, which are used to realize signal transmission between logic function blocks and interconnection channels.

2. The reconfigurable interconnect circuit for multi-core processors according to claim 1, characterized in that, The interconnection components include slave interconnection components, master interconnection components, storage interconnection components, system application interconnection components, and control interconnection components, wherein... The slave interconnect component is used to interconnect at least one processor in a multi-core processor with an embedded FPGA, wherein the at least one processor acts as a slave and the embedded FPGA acts as a master. The host interconnect component is used to interconnect at least one processor in a multi-core processor with an embedded FPGA, wherein the at least one processor acts as the host and the embedded FPGA acts as the slave. The storage interconnect component is used to interconnect storage resources; The system application interconnection component is used to realize the interconnection of system-level applications; The control interconnection component is used to transmit control signals.

3. The reconfigurable interconnect circuit for multi-core processors according to claim 2, characterized in that, The embedded FPGA as the host includes at least one programmable logic device instantiated from the embedded FPGA as the host.

4. The reconfigurable interconnect circuit for multi-core processors according to claim 2, characterized in that, The embedded FPGA as a slave device includes at least one programmable logic device instantiated from the embedded FPGA as a slave device.

5. The reconfigurable interconnect circuit for multi-core processors according to claim 2, characterized in that, The host interconnect component is also used to realize the interconnection between processors in the multi-core processor, with at least one processor acting as the host and at least another processor acting as the slave.

6. The reconfigurable interconnect circuit for multi-core processors according to claim 2, characterized in that, The host interconnect component is also used to realize the interconnection between at least one processor of the multi-core processor and the embedded FPGA and at least another processor, wherein at least one processor of the multi-core processor acts as the host, and at least one programmable logic device instantiated by the embedded FPGA and the at least another processor act as slaves.

7. The reconfigurable interconnect circuit for multi-core processors according to claim 1, characterized in that, The types of the interfaces include at least one of the following: Advanced Microcontroller Bus Architecture (AMBA) general interface, AMBA high-performance interface, AMBA_ACP interface, and CTRL_IO_SIG interface.

8. The reconfigurable interconnect circuit for multi-core processors according to claim 1, characterized in that, All interfaces on the multi-core processor side, except for the accelerated consistency interface, are connected to the multi-master multi-slave routing arbitration structure, and then connected to the embedded FPGA through the interconnect component.

9. The reconfigurable interconnect circuit for multi-core processors according to claim 2, characterized in that, The accelerated coherence interface on the multi-core processor side is directly connected to the system application interconnect component in the interconnect component, which is a coherence control unit within the accelerated processor.

10. The reconfigurable interconnect circuit for multi-core processors according to claim 2, characterized in that, The interfaces on the embedded FPGA side include at least one of the following: host AMBA general interface, slave AMBA general interface, host AMBA high-performance interface, slave AMBA_ACP interface and CTRL_IO_SIG interface; The slave interconnect component is connected to the host AMBA general interface, the host interconnect component is connected to the slave AMBA general interface, the storage interconnect component is connected to the host AMBA high-performance interface, the system application interconnect component is connected to the slave AMBA_ACP interface, and the control interconnect component is connected to the CTRL_IO_SIG interface.

11. The reconfigurable interconnect circuit for multi-core processors according to claim 1, characterized in that, The allocation of corresponding interconnection resources for the data transmission includes: determining the connection relationship of interconnection segments in the interconnection component and the jump relationship between interconnection segments according to the number of interfaces, interface type and circuit application requirements of the multi-master multi-slave routing arbitration structure, and generating a reconfigurable configuration file. The reconfigurable configuration file is used to configure the on or off of the programmable switch in the switch box and the input connection module and output connection module in the connection box.

12. The reconfigurable interconnect circuit for multi-core processors according to claim 1, characterized in that, The local interconnection resources also include: an input cross-connection module, which is used to realize signal interconnection between logic units and to connect the input pins of the logic function block to each logic unit; The logic unit comprises the logic function block.

13. The reconfigurable interconnect circuit for multi-core processors according to any one of claims 1-12, characterized in that, The horizontal and vertical channels of the embedded FPGA-side programmable interconnect provide the global interconnect resources, which interact with the local interconnect resources and the multi-core processor-side interconnect bus through the local interconnect resources. The signal output from the multi-core processor side is sent to the interconnect component through the local interconnect resource and processed by the corresponding logic unit; alternatively, the signal output from the multi-core processor side is sent to the adjacent logic unit for processing through the horizontal channel.

14. The reconfigurable interconnect circuit for multi-core processors according to claim 1, characterized in that, The interconnection segments include long interconnection segments, short interconnection segments, local interconnection segments, and direct interconnection segments. The long interconnection segments are used to meet the signal path requirements between logic functional blocks that are far apart. The short interconnection segments are used to realize the interconnection between adjacent logic functional blocks. The local interconnection segments are used to realize signal sharing and feedback between logic units within each logic functional block. The direct interconnection segments are used for signal transmission between adjacent logic functional blocks.

15. The reconfigurable interconnect circuit for multi-core processors according to claim 1, characterized in that, The interconnection channel can be a one-way channel or a two-way channel.

16. The reconfigurable interconnect circuit for multi-core processors according to claim 1, characterized in that, The switch box is implemented by combining bidirectional interconnection switches and unidirectional interconnection switches.

17. The reconfigurable interconnect circuit for multi-core processors according to claim 1, characterized in that, The topology types of the programmable switches in the switch box include at least one of the following: subset interconnection, global interconnection, and vertical interconnection.

18. The reconfigurable interconnect circuit for multi-core processors according to claim 1, characterized in that, The parameters of the multi-master multi-slave routing arbitration structure or interconnection component include: the number of routing wires that can be connected to the input or output of each logical function block, the number of other routing wires that can be connected to each routing wire, the length of the routing segment, the mode of the routing switch, the electrical design of the wires and programmable switches, and the number of routing segments for each channel.

19. The reconfigurable interconnect circuit for multi-core processors according to claim 1, characterized in that, The programmable switch is implemented using a multiplexer and a tri-state buffer.

20. The reconfigurable interconnect circuit for multi-core processors according to any one of claims 1-12 and 14-19, characterized in that, The multi-master multi-slave routing arbitration structure includes an AMBA bus matrix, which is used to connect all AMBA bus interfaces of the multi-core processor.

21. A method for implementing a reconfigurable interconnect circuit for a multi-core processor as described in any one of claims 1 to 20, characterized in that, include: Based on interconnection requirements, interconnection parameters on the multi-core processor side, and interconnection parameters on the embedded FPGA side, the code for the reconfigurable interconnection circuit for the multi-core processor is generated. Generate an FPGA configuration file based on the code; The FPGA configuration file is downloaded to the embedded FPGA to form the reconfigurable interconnect circuit for multi-core processors.

22. The method according to claim 21, characterized in that, The interconnect parameters on the multi-core processor side include at least one of the following: number of CPU cores, data bit width of each CPU, number of CPU master and slave, access address space of each CPU, CPU interface type, number of interfaces of the multi-master multi-slave routing arbitration structure, and interface type of the multi-master multi-slave routing arbitration structure. The interconnect parameters on the embedded FPGA side include at least one of the following: number of embedded FPGA master and slave, AMBA bus interface type, number of interconnect component signals, interconnect component type, and quantity of each type of interconnect component.

23. The method according to claim 21, characterized in that, The step of generating the code for the reconfigurable interconnect circuit for the multi-core processor based on interconnect requirements, interconnect parameters on the multi-core processor side, and interconnect parameters on the embedded FPGA side includes: Based on interconnection requirements, determine the data transmission within the multi-core processor or between the multi-core processor and the embedded FPGA; Based on the interconnect parameters on the multi-core processor side and the interconnect parameters on the embedded FPGA side, code for the reconfigurable interconnect circuit for the multi-core processor is generated for the data transmission.

24. A chip, characterized in that, It includes multi-core processors and embedded FPGAs, and further includes reconfigurable interconnect circuitry for multi-core processors as claimed in any one of claims 1 to 20.

Images