Chip packaging method, chip packaging module and electronic device

Abstract

Provided in the present application are a chip packaging method, a chip packaging module and an electronic device. The method comprises: forming, on a wafer, a first package layer in which a first pad layer, at least one first line layer and a second pad layer that are in electrical connection layer by layer are embedded, wherein a first side of the first package layer is in contact with the wafer, the first pad layer is formed on the first side of the first package layer, the second pad layer is formed on a second side of the first package layer and exposed from the second side of the first package layer, and the line width of a line in the first line layer is less than or equal to 2 μm; forming, on the second side of the first package layer, a second package layer in which a third pad layer and at least one second line layer that are in electrical connection layer by layer are embedded, wherein the third pad layer is electrically connected to the second pad layer, and the minimum line width of a line in the second line layer is greater than the minimum line width of the line in the first line layer; and removing the wafer, which is in contact with the first side of the first package layer, so as to expose the first pad layer, and electrically connecting a chip to the first pad layer, so as to obtain a chip packaging module.

Description

Chip packaging methods, chip packaging modules and electronic devices Technical Field

[0001] This application relates to the field of chip packaging technology, and in particular to a chip packaging method, a chip packaging module, and an electronic device. Background Technology

[0002] With the development of microelectronics technology, increasing integration has become a crucial way to overcome chip performance bottlenecks. A significant direction for current chip technology advancement is integration in chip packaging. However, some chip packaging solutions, while improving integration, suffer from high manufacturing costs and process complexity. Therefore, a new technological solution is urgently needed to reduce chip packaging costs and process complexity. Summary of the Invention

[0003] This application provides a chip packaging method, a chip packaging module, and an electronic device.

[0004] According to a first aspect of the embodiments of this application, a chip packaging method is provided, comprising:

[0005] A first package layer is formed on a wafer, which has a first pad layer, at least one first circuit layer and a second pad layer embedded in it through successive electrical connections. The first package layer includes a first side and a second side opposite to each other along the thickness direction. The first side of the first package layer is in contact with the wafer. The first pad layer is formed on the first side of the first package layer. The second pad layer is formed on the second side of the first package layer and exposed from the second side of the first package layer. The linewidth of the circuit in the first circuit layer is less than or equal to 2 μm.

[0006] On the second side of the first encapsulation layer, a second encapsulation layer is formed, which is embedded with a third pad layer and at least one second circuit layer that are electrically connected layer by layer. The third pad layer is electrically connected to the second pad layer, and the minimum line width of the circuit in the second circuit layer is greater than the minimum line width of the circuit in the first circuit layer.

[0007] The wafer that is in contact with the first side of the first packaging layer is at least partially removed to expose the first pad layer, and the chip is electrically connected to the first pad layer to obtain a chip packaging module.

[0008] According to a second aspect of the embodiments of this application, a chip packaging module is provided, which is obtained by packaging using the method described in any one of the first aspects.

[0009] According to a third aspect of the embodiments of this application, a chip packaging module is provided, comprising:

[0010] chip;

[0011] The first packaging layer includes a first side and a second side opposite to each other along the thickness direction, and is embedded with a first pad layer, at least one first circuit layer and a second pad layer that are electrically connected layer by layer. The first pad layer is located on the first side of the first packaging layer and is electrically connected to the chip, and the second pad layer is located on the second side of the first packaging layer.

[0012] The second encapsulation layer has embedded a third pad layer and at least one second circuit layer that are electrically connected layer by layer, wherein the third pad layer is electrically connected to the second pad layer.

[0013] Wherein, the line width of the lines in the first line layer is less than or equal to 2µm, and the minimum line width of the lines in the second line layer is greater than the minimum line width of the lines in the first line layer.

[0014] According to a fourth aspect of the embodiments of this application, an electronic device is provided, including: a chip packaging module as described in any one of the second or third aspects.

[0015] The technical solution in this application embodiment can form a first packaging layer on a wafer, which is embedded with a first pad layer, at least one first circuit layer and a second pad layer that are electrically connected layer by layer. The first packaging layer includes a first side and a second side that are opposite to each other along the thickness direction. The first side of the first packaging layer is in contact with the wafer. The first pad layer is formed on the first side of the first packaging layer, and the second pad layer is formed on the second side of the first packaging layer and exposed from the second side of the first packaging layer. The line width of the circuit in the first circuit layer is less than or equal to 2 μm. Then, on the second side of the first packaging layer, a second packaging layer is formed, which is embedded with a third pad layer and at least one second circuit layer that are electrically connected layer by layer. The third pad layer is electrically connected to the second pad layer. The minimum line width of the circuit in the second circuit layer is greater than the minimum line width of the circuit in the first circuit layer. Then, at least part of the wafer that is in contact with the first side of the first packaging layer is removed to expose the first pad layer, and the chip is electrically connected to the first pad layer to effectively obtain a chip packaging module. Therefore, through the above technical solution, on the one hand, this application can effectively achieve chip packaging and obtain chip packaging modules without using through-silicon via (TSV) technology, thus reducing manufacturing costs and effectively reducing process complexity compared to related technical solutions using TSV technology; on the other hand, by setting the linewidth of the lines in the first circuit layer to less than or equal to 2µm and making the minimum linewidth of the lines in the second circuit layer greater than the minimum linewidth of the lines in the first circuit layer, the linewidth of the lines in the first circuit layer can be kept small, which facilitates the realization of high-density lines and interconnections and is beneficial to improving the integration of the chip packaging module; furthermore, since this chip packaging solution electrically connects the chip to the first pad layer after the first and second packaging layers are fabricated and connected, compared to the case where the chip is electrically connected to the first pad layer first, it is beneficial to avoid the situation where the chip is scrapped due to the damage of either the first or second packaging layer, thus further reducing process costs and ensuring the yield of the final chip packaging module. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0017] Figure 1 shows a schematic diagram of the structure of a chip packaging module obtained by a chip packaging scheme in the related technology.

[0018] Figure 2 shows a schematic diagram of some examples of chip packaging modules in this application.

[0019] Figure 3 shows a flowchart of some examples of chip packaging methods in this application.

[0020] Figure 4 shows some optional flowcharts for step S104 in this application.

[0021] Figure 5 shows some optional flowcharts for step S1042 in this application.

[0022] Figures 6a to 6i illustrate some optional fabrication processes of the chip packaging module in this application.

[0023] Figure 7 shows a schematic block diagram of some examples of electronic devices in this application.

[0024] Explanation of reference numerals in the attached figures: 100, Chip packaging module; 1, First packaging layer; 10, Wafer; 11, First pad layer; 111, First pad; 12, First circuit layer; 13, Second pad layer; 131, Second pad; 2, Second packaging layer; 21, Third pad layer; 211, Third pad; 22, Second circuit layer; 23, Fourth pad layer; 231, Fourth pad; 24, Electrical connection block; 201, First molding compound dielectric layer; 202, Second molding compound dielectric layer; 203, Third molding compound dielectric layer; 3, Chip; 4, Conductive block; 5, Protective layer; 200, Electronic device. Detailed Implementation

[0025] To enable those skilled in the art to better understand the technical solutions in the embodiments of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art should fall within the protection scope of the embodiments of this application.

[0026] With the development of microelectronics technology, increasing integration has become an important way to overcome chip performance bottlenecks. A key direction for current chip technology advancement is integration in chip packaging. However, some chip packaging solutions, while improving integration, have high manufacturing costs and complex processes.

[0027] For example, in related 2.5D or 3D packaging technologies, one way to integrate chips using different process technologies is to improve integration density through a silicon interposer (SI) adapter. During the packaging process, the SI interposer serves as a connection layer between the chip and the packaging substrate. For instance, taking the CoWoS (Chip on Wafer on Substrate) technology as an example, when using a SI interposer for chip packaging, the chip is typically soldered to a circuit layer formed on one side of the SI interposer, and through-silicon vias (TSVs) are used to electrically connect the circuit layer formed on the SI interposer to the circuit layer of the packaging substrate on the other side of the SI interposer. For example, Figure 1 shows a schematic diagram of a chip packaging module obtained from a chip packaging scheme in related technologies. The example in Figure 1 can be a stacked structure obtained from the CoWoS (Chip on Wafer on Substrate) technology. As shown in Figure 1, chips a and b are connected to a circuit layer formed on the upper surface of a silicon interposer via solder. This circuit layer includes interconnect metal lines of various sizes fabricated using wafer-level manufacturing processes. The final interconnection is then electrically connected to the lower surface of the silicon interposer via through-silicon vias (TSVs) within the silicon interposer, and finally interconnected with the circuitry of the packaging substrate via solder. However, due to the characteristics of TSV technology in such a silicon interposer, and the fact that the aspect ratio of TSVs generally exceeds 10:1, the manufacturing technology is extremely difficult, resulting in high manufacturing costs and complex processes.

[0028] However, the CoWoS technology, including but not limited to the one shown in Figure 1, uses a silicon interposer. Due to the characteristics of through-silicon vias (TSVs), the overall manufacturing cost is high, and the process complexity is also high. Furthermore, while CoWoS technology can utilize silicon interposers to achieve the need for high-density metal interconnects, and this process technology is compatible with the wafer manufacturing process, the chip is integrated with the silicon interposer in the CoWoS solution, and then shipped as a module to downstream packaging plants for soldering to the packaging substrate. If damage occurs in this module due to process deviations in the silicon interposer itself (such as defects in TSVs) or open / short circuits in the interconnects, the chip will be scrapped as well, further increasing the overall process cost. Moreover, due to this process architecture, it is difficult to ensure product yield, thus significantly increasing the cost of packaging integration.

[0029] In view of this, this application provides a chip packaging solution to at least partially improve the above-mentioned problems. It should be understood that the chip packaging solution of this application does not use through-silicon vias (TSVs), which can at least partially avoid the defects of the technical solution shown in Figure 1, effectively reduce the manufacturing cost and process complexity of the chip packaging module, and effectively improve the integration of the obtained chip packaging module.

[0030] The specific implementation of the technical solutions of the embodiments of this application is described below with reference to the accompanying drawings. It should be noted that, for ease of illustration, the structures in the various drawings are not necessarily drawn to scale. The various drawings are not intended to limit the embodiments of this application.

[0031] Here, we will first briefly introduce the main structure of the chip packaging module 100 obtained by the embodiment of this application, so as to facilitate the detailed description of the chip packaging method below. As shown in the example in Figure 2, the chip packaging module 100 prepared by the preparation method of the first aspect of this application includes: a chip 3, a first packaging layer 1, and a second packaging layer 2. The first packaging layer 1 includes a first side and a second side opposite to each other along the thickness direction, and is embedded with a first pad layer 11, at least one first circuit layer 12, and a second pad layer 13 that are electrically connected layer by layer. The first pad layer 11 is located on the first side of the first packaging layer 1 and is electrically connected to the chip 3, and the second pad layer 13 is located on the second side of the first packaging layer 1. The second packaging layer 2 is embedded with a third pad layer 21 and at least one second circuit layer 22 that are electrically connected layer by layer. The third pad layer 21 is electrically connected to the second pad layer 13. The linewidth of the circuit in the first circuit layer is less than or equal to 2 μm, and the minimum linewidth of the circuit in the second circuit layer 22 is greater than the minimum linewidth of the circuit in the first circuit layer 12.

[0032] It should be understood that the type of chip 3 is not limited in this application, and it can be any chip. For example, it can include, but is not limited to, processor chips (such as, but not limited to, GPU (Graphics Processing Unit), CPU (Central Processing Unit), MCU (Micro Control Unit), DSP (Digital Signal Processor), FPGA (Field Programmable Gate Array), etc.), memory chips (such as, but not limited to, HBM (High Bandwidth Memory) chips, ROM (Read-Only Memory) chips, RAM (Random Access Memory) chips, FLASH memory chips, EEPROM (Electrically Erasable Programmable Read-Only Memory) chips, EPROM (Erasable Programmable Read-Only Memory) chips), system-on-a-chip (also known as system on chip, or SoC), etc.), or it can be other analog circuit chips or digital circuit chips. This application does not limit the number of chips 3; one or more chips 3 may be electrically connected to the first pad layer 11. As shown in the example in Figure 2, the first pad layer 11 is electrically connected to two chips 3.

[0033] Optionally, as shown in Figure 2, the first pad layer 11 may include multiple first pads 111, which can be used to electrically connect with different pads of the chip 3. Optionally, as shown in Figure 2, the second pad layer 13 includes multiple second pads 131, and the third pad layer 21 includes multiple third pads 211. The multiple second pads 131 can be electrically connected to the multiple third pads 211 respectively. It should be noted that the number of first pads 111 can be designed as needed, and the shape and size of each pair of multiple first pads 111 can be the same or different, which is not limited here. The number of second pads 131 can be designed as needed, which is not limited here, and the shape and size of each pair of multiple first pads 111 can be the same or different. The number of third pads 211 can be designed as needed, and the shape and size of each pair of multiple third pads 211 can be the same or different, which is not limited here.

[0034] It should be understood, in conjunction with Figure 2, that in the first encapsulation layer 1 and the second encapsulation layer 2 obtained in this application, the first encapsulation layer 1 can be regarded as a silicon interposer, and does not require the use of through-silicon via (TSV) technology; the second encapsulation layer 2 can be regarded as an encapsulation substrate. Clearly, this solution differs significantly from the CoWoS technology solution shown in Figure 1 in both the chip packaging process and the product structure.

[0035] Figure 3 shows a flowchart of a chip packaging method for some examples of this application. Referring to Figure 3, the chip packaging method includes steps S102, S104, and S106, specifically:

[0036] S102: A first package layer is formed on a wafer, which is embedded with a first pad layer, at least one first circuit layer and a second pad layer that are electrically connected layer by layer. The first package layer includes a first side and a second side that are opposite each other along the thickness direction. The first side of the first package layer is in contact with the wafer. The first pad layer is formed on the first side of the first package layer. The second pad layer is formed on the second side of the first package layer and exposed from the second side of the first package layer. The line width of the circuit in the first circuit layer is less than or equal to 2 μm.

[0037] When understanding the relevant content of step S102, you can also refer to the schematic diagram in Figure 6a.

[0038] The chip packaging method of this application can first form a first packaging layer 1 on a wafer 10. Optionally, the wafer 10 here can refer to a silicon wafer. The wafer can be of any size as needed, for example, including but not limited to 6-inch wafers, 8-inch wafers, 12-inch wafers, etc.

[0039] The first encapsulation layer 1 can be formed using any suitable encapsulation material. Optionally, the first encapsulation layer 1 can be formed using an encapsulation material suitable for subsequent wafer-level manufacturing processes. For example, in some optional embodiments, the material of the first encapsulation layer 1 can be SiO2, i.e., silicon dioxide. That is, in step S102 of this application, forming the first encapsulation layer on the wafer can be forming the first encapsulation layer 1 in the form of a SiO2 layer on wafer 10. For example, at least one of the following processes, including but not limited to PECVD (Plasma-Enhanced Chemical Vapor Deposition), HDPCVD (High-Density Plasma Chemical Vapor Deposition), and LPCVD (Low-Pressure Chemical Vapor Deposition), can be used to grow SiO2 on wafer 10 to form the first encapsulation layer 1 in the form of a SiO2 layer.

[0040] It should be understood that the first packaging layer 1 in the form of a SiO2 layer can, on the one hand, serve as an insulating layer to effectively meet some insulation requirements between the subsequently formed layer structures (i.e., the first pad layer 11, at least one first circuit layer 12, and the second pad layer 13); on the other hand, by adopting the first packaging layer 1 in the form of a SiO2 layer, it is easier to make the linewidth of the lines therein less than or equal to 2µm when forming the first circuit layer 12, thereby improving the integration of the packaged chip module.

[0041] One or more first circuit layers 12 can be embedded in the first encapsulation layer 1. Optionally, the first encapsulation layer 1 can have 1 to 10 first circuit layers 12 embedded. Of course, more first circuit layers 12 can be provided as needed. For example, in the example of Figure 2, the first encapsulation layer 1 has 2 first circuit layers 12 embedded.

[0042] The first pad layer 11 in this application may include multiple first pads 111, the specific number of which can be designed as needed. It should be understood that when there are multiple first circuit layers 12, the circuit structures between each first circuit layer 12 may have approximately the same circuit structure, or they may all have completely different circuit structures. This application does not limit the circuit structure in each first circuit layer 12; it can be designed according to actual needs. The second pad layer 13 in this application may include multiple second pads 131, the specific number of which can be designed as needed. The first packaging layer 1 formed on the wafer 10 includes a first side and a second side opposite each other along the thickness direction. The first side of the first packaging layer 1 contacts the wafer 10. The first pad layer 11 is formed on the first side of the first packaging layer 1 and can subsequently be used for electrical connection with the chip. The second pad layer 13 is formed on the second side of the first packaging layer 1 and exposed from the second side of the first packaging layer 1, and can subsequently be used for electrical connection with the third pad layer 21.

[0043] Optionally, as shown in FIG6a, an opening can be made on the second side of the first packaging layer 1 by any physical or chemical process to expose the first pad layer 11.

[0044] In this application, the first pad layer 11, at least one first circuit layer 12, and the second pad layer 13 are electrically connected layer by layer. For example, if there are two first circuit layers 12 between the first side and the second side of the first package layer 1 opposite each other along the thickness direction, then the first pad layer 11 and the first first circuit layer 12 are electrically connected, and the second first circuit layer 12 is electrically connected to the second pad layer 13. Other cases can be understood by analogy to this example, and will not be elaborated here.

[0045] It is understood that the electrical connection between the first pad layer 11 and the first circuit layer 12 can mean that at least the first pad 111 in the first pad layer 11 is electrically connected to at least a portion of the circuitry in the first circuit layer 12. The electrical connection between the first circuit layer 12 and the second pad layer 13 can mean that at least a portion of the circuitry in the first circuit layer 12 is electrically connected to at least a portion of the circuitry in the second circuit layer 13. The electrical connection between the first circuit layer 12 and the second pad layer 13 can mean that at least a portion of the circuitry in the first circuit layer 12 is electrically connected to at least the second pad 131 in the second pad layer 13.

[0046] Optionally, the first pad layer 11, at least one first circuit layer 12, and the second pad layer 13 can be electrically connected layer by layer by setting an electrical connection structure between adjacent layers. The electrical connection structure is not specifically limited here.

[0047] In this application, the first pad layer 11, at least one first circuit layer 12, and the second pad layer 13 can be fabricated using any feasible method. In some optional embodiments, the first pad layer 11, at least one first circuit layer 12, and the second pad layer 13, which are electrically connected layer by layer, can be formed by wafer-level manufacturing processes. It should be understood that wafer-level manufacturing processes in this application can easily produce high-density interconnect traces, making it easier to make the linewidth of the first circuit layer 12 2µm, thereby improving the integration of the packaged chip module.

[0048] Furthermore, since wafer-level manufacturing processes do not involve transistor manufacturing in this step, but only circuit manufacturing and interconnection, convenience can be guaranteed, which helps to reduce the difficulty of the process.

[0049] Optionally, the first pad layer 11, at least one first circuit layer 12, and the second pad layer 13 can be made of at least one of copper and aluminum. Alternatively, they can be made of other metals or other feasible conductive materials.

[0050] For example, in some alternative examples, when aluminum is used, the aluminum layer can be made using processes such as sputtering or vapor deposition. When copper is used, a titanium-copper seed metal layer can be sputtered, and then a copper layer can be grown on the seed metal layer by electroplating. Finally, the process is carried out according to the damascus process.

[0051] Optionally, the linewidth of the lines in the first circuit layer 12 of this application can be between 100 nm and 2 μm. This linewidth range can be achieved relatively easily using wafer-level manufacturing processes. In some embodiments, the linewidth in the first circuit layer 12 can be between 100 nm and 1 μm. Such a linewidth range allows for better integration of the chip packaging module.

[0052] S104: On the second side of the first encapsulation layer, a second encapsulation layer is formed, which is embedded with a third pad layer and at least one second circuit layer that are electrically connected layer by layer. The third pad layer is electrically connected to the second pad layer. The minimum line width of the circuit in the second circuit layer is greater than the minimum line width of the circuit in the first circuit layer.

[0053] When understanding the relevant content of step S104, you can also refer to the schematic diagrams in Figures 6b to 6g.

[0054] In step S102, the linewidth of the lines in the first line layer 12 is set to be less than or equal to 2µm. Then, in step S104, the minimum linewidth of the lines in the second line layer 22 is made greater than the minimum linewidth of the lines in the first line layer 12. This ensures that the linewidth of the lines in the first line layer 12 is small, which facilitates the realization of high-density lines and interconnections and is beneficial to improving the integration of the chip packaging module.

[0055] One or more second circuit layers 22 can be embedded in the second encapsulation layer 2. Optionally, the second encapsulation layer 2 can have 1 to 10 layers of second circuit layers 22 embedded. Of course, more layers of second circuit layers 22 can be provided as needed. For example, in the example of Figure 2, the second encapsulation layer 2 has 3 layers of second circuit layers 22 embedded.

[0056] It should be understood that when there are multiple second circuit layers 22, the circuit structures between each second circuit layer 22 can be roughly the same or completely different. This application does not limit the circuit structure in each second circuit layer 22, and it can be designed according to actual needs. The third pad layer 21 in this application may include multiple third pads 211, and the specific number can be designed as needed.

[0057] In this application, the third pad layer 21 and at least one second circuit layer 22 are electrically connected layer by layer. For example, if the second package layer 2 has three second circuit layers 22 embedded in it, then the third pad layer 21 is electrically connected to the first circuit layer 12, and the second circuit layer 22 is electrically connected to the third circuit layer 22. Other cases can be understood by analogy to this example, and will not be elaborated here.

[0058] It is understood that the electrical connection between the third pad layer 21 and the second circuit layer 22 can mean that at least the third pad 211 in the third pad layer 21 is electrically connected to at least a portion of the circuitry in the second circuit layer 22. Similarly, the electrical connection between the second circuit layer 22 and the second circuit layer 22 can mean that at least a portion of the circuitry in the second circuit layer 22 is electrically connected to at least a portion of the circuitry in the second circuit layer 22.

[0059] Optionally, the third pad layer 21 and at least one second circuit layer 22 can be made of at least one of copper and aluminum. Alternatively, they can be made of other metals or other feasible conductive materials.

[0060] Optionally, the second encapsulation layer 2 in this application can be a molding medium layer. It can be made of any suitable molding material, including but not limited to at least one of epoxy molding compound (EMC), polyimide (PI), etc. The second encapsulation layer 2 in the form of a molding medium layer has good performance, is easy to manufacture, and has low process complexity.

[0061] Optionally, step S104 in this application can be implemented using a different manufacturing process than step S102. For example, step S102 uses a wafer-level manufacturing process, while step S104 may not use a wafer-level manufacturing process.

[0062] This application does not limit the specific implementation of step S104. In some optional embodiments, referring to the flowchart shown in FIG4, step S104 includes steps S1042, S1044, S1046 and S1048, specifically:

[0063] S1042: A conductive component is formed on a second pad layer exposed from the second side of the first encapsulation layer, and a first molding dielectric layer is formed on the second side of the first encapsulation layer to expose the conductive component.

[0064] The first molding dielectric layer 201 in this application can be made of any molding material. Optionally, the material of the first molding dielectric layer 201 can be epoxy molding compound (EMC). EMC material has the advantages of low cost, convenient molding operation, high production efficiency, good high temperature resistance, good electrical insulation, and good heat dissipation, which can effectively meet the molding performance requirements. Furthermore, EMC material can also meet the requirements for circuit fabrication. Optionally, the first molding dielectric layer 201 can also be made of polyimide (PI). Alternatively, other materials that meet the requirements can also be used.

[0065] Optionally, the first encapsulating medium layer 201 can be manufactured using an injection mold through an injection molding process. Injection molding processes may include, but are not limited to, C-mold injection molding or T-mold injection molding.

[0066] The conductive components in this application can be made of any conductive material, such as metals, including but not limited to at least one of titanium, copper, aluminum, silver, etc. (single metal or multi-metal stack), or an alloy of at least two of them.

[0067] Optionally, conductive components can be formed on the second pad layer 13 exposed from the second side of the first packaging layer 1 using at least one of sputtering, vapor deposition, or electroplating processes. Forming conductive components using this process eliminates the need for soldering to establish an electrical connection with the second pad layer 13, thus avoiding the instability of the packaging structure caused by soldering. This improves the reliability of the chip packaging module and effectively reduces packaging costs.

[0068] This application does not limit the specific structure of the conductive component. For example, optionally, the second pad layer 13 includes a plurality of second pads 131, the third pad layer 21 includes a plurality of third pads 211, and the conductive component may include a plurality of conductive blocks 4. In some optional embodiments, as shown in the flowchart of FIG5, the above step S1042 includes steps S1042A and S1042B, specifically:

[0069] S1042A: A plurality of conductive blocks 4 are correspondingly formed on a plurality of second pads 131 of the second pad layer 13, such that the ends of the conductive blocks 4 away from the second pads 131 extend beyond the second side of the first encapsulation layer 1.

[0070] For example, the relevant content of step S1042A can be understood by referring to the schematic diagram in Figure 6b.

[0071] Optionally, the end of the conductive block 4 furthest from the second pad 131 extends 5µm to 100µm beyond the second side of the first encapsulation layer 1. As shown in Figure 6b, H1 in Figure 6b indicates the distance between the end of the conductive block 4 furthest from the second pad 131 and the second side of the first encapsulation layer 1, where 5µm ≤ H1 ≤ 100µm. This range helps ensure a stable electrical connection between the conductive block 4 and the prepared third pad 211, thereby electrically connecting the second pad 131 and the third pad 211 through the conductive block 4. Of course, specific values ​​can be selected as needed. In some examples, H1 can be 5µm, 10µm, 20µm, 30µm, 40µm, 50µm, 60µm, 70µm, 80µm, 90µm, 100µm, etc.

[0072] Multiple conductive blocks 4 can be formed in any manner. For example, some feasible implementations include forming a full metal layer on the second side of the first packaging layer 1 using at least one of sputtering, vapor deposition, or electroplating processes, and then etching the metal layer to retain the desired portion of the metal layer that connects to the second pads 131 to form the conductive blocks 4. In other embodiments, the metal layer can also be deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), or other methods.

[0073] Optionally, the conductive block 4 can be made of at least one of titanium, copper, aluminum, silver, etc. (a single metal or a multi-metal stack), or an alloy of at least two. For example, taking a single metal as an example, the conductive block 4 can be a copper block. For example, taking a multi-metal stack as an example, the conductive block 4 can be a titanium-copper metal stack. For example, taking an alloy as an example, the conductive block 4 can be a titanium-copper alloy.

[0074] S1042B: A first molding dielectric layer 201 covering a plurality of conductive blocks 4 is formed on the second side of the first encapsulation layer 1, and the first molding dielectric layer 201 is ground so that at least a portion of the plurality of conductive blocks 4 is exposed.

[0075] For example, the relevant content of step S1042B can be understood by referring to the schematic diagrams in Figures 6c and 6d.

[0076] Optionally, the prepared chip packaging module structure (including wafer 10, first packaging layer 1, conductive blocks 4, etc.) can be placed entirely within the mold cavity of a wafer-level or panel-level injection mold, and then injection molded using a molding compound (such as EMC plastic, etc.) (e.g., C-mold or T-mold injection molding process, etc.) to obtain a first molding dielectric layer 201 covering the second side of the first packaging layer 1 and the multiple conductive blocks 4. In this way, the multiple conductive blocks 4 can be encapsulated by the first molding dielectric layer 201.

[0077] Subsequently, the surface of the first molding compound 201 away from the second pad 131 can be polished, so that at least a portion of the multiple conductive blocks 4 are exposed after polishing. This polishing process can be performed simultaneously with the polishing of the first molding compound 201 and the conductive blocks 4, or the conductive blocks 4 can be left unpolished; the operation can be carried out according to the actual situation.

[0078] Based on this, the optional embodiments of steps S1042A to S1042B in this application can effectively prepare the first molding dielectric layer 201 and the conductive component including multiple conductive blocks 4, and effectively expose the multiple conductive blocks 4 through the first molding dielectric layer 201 to facilitate the subsequent preparation of multiple third pads 211 of the third pad layer 21, so as to electrically connect the second pad layer 13 and the third pad layer 21 through the conductive blocks 4.

[0079] S1044: A third pad layer is formed in the first molding dielectric layer to connect with the exposed conductive component, so that the third pad layer is electrically connected to the second pad layer through the conductive component.

[0080] For example, the relevant content of step S1044 can be understood by referring to the schematic diagram in Figure 6e.

[0081] The third pad layer 21 can be made of at least one of the metals selected from copper and aluminum. Alternatively, it can be made of other metals or other feasible conductive materials.

[0082] This application does not limit the specific implementation of step S1044. For example, based on the optional embodiments of steps S1042A to S1042B above, the third pad layer 21 may include a plurality of third pads 211, and a plurality of conductive blocks 4 may be used to electrically connect a plurality of second pads 131 and a plurality of third pads 211 accordingly. Optionally, step S1044 includes: forming a plurality of third pads 211 of the third pad layer 21 correspondingly on the exposed plurality of conductive blocks 4, so that the plurality of third pads 211 of the third pad layer 21 are electrically connected to the plurality of second pads 131 of the second pad layer 13 respectively through the plurality of conductive blocks 4.

[0083] Multiple third pads 211 can be formed in any manner. For example, some feasible implementations include forming a full-layer metal layer on the side of the first molding compound 201 exposed by sputtering, vapor deposition, electroplating, or other processes, and then etching the metal layer to retain the portion of the metal layer that is connected to the conductive blocks 4 to form the third pads 211. In other embodiments, the metal layer can also be deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), or other methods.

[0084] It should be understood that in the above optional solutions, the third pad 211 can be directly formed on the conductive block 4, and the conductive block 4 is also directly formed on the second pad 131. Thus, when the third pad 211 is electrically connected to the second pad 131 through the conductive block 4, the electrical connection can be made stable without the need for soldering. Therefore, the drawbacks of unstable packaging structure caused by soldering can be avoided, thereby improving the reliability of the chip packaging module and effectively reducing the packaging cost.

[0085] S1046: Multiple layers of second molding dielectric layers are sequentially formed on the first molding dielectric layer, and a second circuit layer is formed between every two adjacent layers of second molding dielectric layers, and the third pad layer and the obtained at least one second circuit layer are electrically connected layer by layer.

[0086] For example, the relevant content of step S1046 can be understood by referring to the schematic diagram in Figure 6f.

[0087] The second molding medium layer 202 in this application can be made of any molding material. Optionally, the material of the second molding medium layer 202 can be epoxy molding compound (EMC). Optionally, the second molding medium layer 202 can also be made of polyimide (PI). Alternatively, other materials that meet the requirements can be used.

[0088] Optionally, the second encapsulating medium layer 202 can be manufactured using an injection mold through an injection molding process. Injection molding processes may include, but are not limited to, C-mold injection molding or T-mold injection molding.

[0089] In this application, a second circuit layer 22 is formed between every two adjacent second molding dielectric layers 202, which can be fabricated sequentially according to their positions. For example, the first second molding dielectric layer 202 can be fabricated first, followed by the second circuit layer 22, and then the second second molding dielectric layer 202. Other cases can be deduced similarly.

[0090] Optionally, the third pad layer 21 and the resulting at least one second circuit layer 22 can be electrically connected layer by layer, which can be achieved by setting an electrical connection structure between adjacent layers. The electrical connection structure is not specifically limited here.

[0091] S1048: A second encapsulation layer is formed based on a first molding dielectric layer and multiple layers of second molding dielectric layers.

[0092] After the first molding dielectric layer 201 and the multilayer second molding dielectric layer 202 are prepared, the first molding dielectric layer 201 and the multilayer second molding dielectric layer 202 can be used as part of the second encapsulation layer 2, thereby facilitating the formation of the second encapsulation layer 2. For example, this can also be understood in conjunction with the example in Figure 6g.

[0093] For example, in some cases, the second encapsulation layer 2 may consist of a first molding dielectric layer 201 and multiple layers of second molding dielectric layers 202. In other cases, the second encapsulation layer 2 may consist of a first molding dielectric layer 201, multiple layers of second molding dielectric layers 202, and other encapsulation structure layers (such as the third molding dielectric layer 203 described below) (as shown in the example of Figure 6g). The configuration can be as needed, and no specific limitations are imposed here.

[0094] Based on this, through the optional implementation of steps S1042 to S1048 above, on the one hand, a second packaging layer 2 embedded with a third pad layer 21 and at least one second circuit layer 22 with progressively interconnected layers can be effectively prepared, and the multiple third pads 211 of the third pad layer 21 can be effectively connected to the multiple second pads 131 of the second pad layer 13. On the other hand, the above optional technical solution is a sequential superposition of the preparation processes of multiple second pads 131, multiple conductive blocks 4, and multiple third pads 211, which makes the electrical connection between multiple second pads 131 and multiple conductive blocks 4, and the electrical connection between multiple conductive blocks 4 and multiple third pads 211 more stable and the electrical connection performance better. Moreover, the electrical connection can be formed without relying on solder, so that the interface between the first packaging layer 1 and the second packaging layer 2 can be avoided. Therefore, the disadvantages of unstable packaging structure caused by soldering can be avoided, thereby improving the reliability of the chip packaging module and effectively reducing the packaging cost.

[0095] In some optional embodiments, the first molding dielectric layer 201 and the second molding dielectric layer 202 can be formed using the same molding material. This results in a more uniform overall structure and properties of the formed second encapsulation layer 2, and better encapsulation stability.

[0096] For example, the first encapsulation medium layer 201 and the second encapsulation medium layer 202 can both be made of epoxy resin molding compound (EMC plastic) so that the second encapsulation layer 2 has good overall high temperature resistance, good electrical insulation, good heat dissipation, and good encapsulation performance.

[0097] It is understood that the second circuit layer 22 embedded in the second encapsulation layer 2 to be formed in this application can be one layer or multiple layers. Regarding steps S1046 and S1048, several optional embodiments for different situations will be described below.

[0098] In some optional embodiments, if the second encapsulation layer 2 to be formed is embedded with a second circuit layer 22, then: step S1046 may include steps S1046A2 to S1046A4, specifically:

[0099] S1046A2: At least one electrical connection block 24 is formed on the third pad layer 21, and a first second molding compound layer 202 is formed on the first molding compound layer 201 to cover the third pad layer 21 and the electrical connection block 24 formed on the third pad layer 21. The first second molding compound layer 202 is polished so that the electrical connection block 24 formed on the third pad layer 21 is exposed.

[0100] Therefore, the first layer of the second molding medium layer 202 can be prepared through this step S1046A2.

[0101] In this application, the electrical connection block 24 is used to electrically connect two adjacent layers. According to the actual circuit design requirements, a suitable number of electrical connection blocks 24 can be formed at appropriate locations on the third pad layer 21 (e.g., on any one or more third pads 211) for subsequent electrical connection between the third pad layer 21 and the adjacent second line layer 22.

[0102] The electrical connection block 24 can be formed in any manner. For example, some feasible implementations include forming a full metal layer on the third pad layer 21 using at least one of sputtering, vapor deposition, or electroplating processes, and then etching the metal layer to retain some desired portions to form the electrical connection block 24. The retained electrical connection block 24 is electrically connected to at least one third pad 211 of the third pad layer 21. In other embodiments, the metal layer can also be deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), or other methods.

[0103] Optionally, the chip packaging module structure prepared up to this step can be placed entirely within the mold cavity of a wafer-level or panel-level injection mold, and then injection molded using a molding compound (such as EMC plastic) (e.g., C-mold or T-mold injection molding process) to obtain a first second molding compound layer 202 that covers the side of the first molding compound layer 201 away from the first packaging layer 1. In this way, the third pad layer 21 and the electrical connection blocks 24 formed on the third pad layer 21 can also be covered by the first second molding compound layer 202.

[0104] Next, the surface of the first layer of the second molding compound 202 that is away from the third pad layer 21 can be ground, so that the ground first layer of the second molding compound 202 exposes the electrical connection block 24 formed on the third pad layer 21. This grinding process can be performed simultaneously with the grinding of the second molding compound 202 and the electrical connection block 24, or the grinding of the electrical connection block 24 can be omitted, depending on the actual situation.

[0105] S1046A4: On the first layer second molding dielectric layer 202, a first layer second circuit layer 22 electrically connected to the electrical connection block 24 formed on the third pad layer 21 is formed, and a second layer second molding dielectric layer 202 covering the first layer second circuit layer 22 is formed.

[0106] Thus, the first layer of the second circuit layer 22 and the second layer of the second molding dielectric layer 202 can be prepared sequentially through this step S1046A4.

[0107] The second circuit layer 22 can be formed in any manner. For example, some feasible implementations include forming a full metal layer on the first second molding dielectric layer 202 using at least one process such as sputtering, vapor deposition, or electroplating, and then etching the metal layer to retain some necessary portions to form the first second circuit layer 22. The retained first second circuit layer 22 is electrically connected to the electrical connection block 24 formed on the third pad layer 21. In other embodiments, the metal layer can also be deposited using methods such as physical vapor deposition (PVD) or chemical vapor deposition (CVD).

[0108] Optionally, the second circuit layer 22 can be made of at least one of the metals selected from copper and aluminum. Alternatively, it can be made of other metals or other feasible conductive materials.

[0109] Then, the chip packaging module structure prepared up to this step can be placed in the mold cavity of a wafer-level or panel-level injection mold, and then injection molded using a molding compound (such as EMC plastic, etc.) (such as C-mold or T-mold injection molding process, etc.) to obtain a second layer second molding dielectric layer 202 covering the first layer second circuit layer 22.

[0110] Based on this, the present application, by including the above steps S1046A2 to S1046A4, can effectively form multiple layers of second molding dielectric layers 202 sequentially on the first molding dielectric layer 201, and effectively form a second circuit layer 22 between each two adjacent layers of second molding dielectric layers 202, and make the third pad layer 21 and the obtained at least one layer of second circuit layer 22 electrically connected layer by layer, thereby facilitating the preparation of the second encapsulation layer 2.

[0111] Optionally, based on steps S1046A2 to S1046A4, in step S1048, the second encapsulation layer 2 can be composed of a first molding dielectric layer 201 and two second molding dielectric layers 202. This is suitable for situations where a fourth pad layer 23 is not required (see below).

[0112] In some optional embodiments, the chip packaging scheme of this application embodiment can also embed a fourth pad layer 23 in the second packaging layer 2. The fourth pad layer 23 can be adapted to the need for wiring between the second packaging layer 2 and other external circuit structures. Optionally, step S1046A4 may include: forming a first-layer second circuit layer 22 on the first-layer second molding dielectric layer 202, which is electrically connected to the electrical connection block 24 formed on the third pad layer 21; forming at least one electrical connection block 24 on the first-layer second circuit layer 22; and forming a second-layer second molding dielectric layer 202 that covers the first-layer second circuit layer 22 and the electrical connection block 24 formed on the first-layer second circuit layer 22. The chip packaging method of this application further includes: grinding the second molding dielectric layer 202 to expose the electrical connection block 24 formed on the first second circuit layer 22; forming a fourth pad layer 23 electrically connected to the electrical connection block 24 formed on the first second circuit layer 22 on the formed second molding dielectric layer 202, and forming a third molding dielectric layer 203 covering the fourth pad layer 23, with an opening in the third molding dielectric layer 203 to expose at least a portion of the fourth pad layer 23. Based on this, step S1048 may include: forming a second packaging layer 2 based on the first molding dielectric layer 201, the multiple layers of second molding dielectric layers 202, and the third molding dielectric layer 203.

[0113] Based on this, through the above optional embodiments, a fourth pad layer 23 electrically connected to the second circuit layer 22 can be embedded in the obtained second packaging layer 2. At least a portion of the fourth pad layer 23 is exposed through the opening, so that the connection lines can be exposed from the other side of the module for connection. This satisfies the requirement that the packaged chip packaging module 100 is electrically connected to other external circuit structures (such as circuit boards, other chips, electronic devices, etc.) through the fourth pad layer 23. It can realize double-sided electrical connection of the lines in the chip packaging module (i.e., the packaged lines are electrically connected to the chip 3 and other circuit structures respectively), so as to facilitate the use of the chip packaging module 100.

[0114] Optionally, the opening in the third molding dielectric layer 203 can be on the side of the third molding dielectric layer 203 away from the first packaging layer 1, so that the fourth pad layer 23 is exposed from this side through the opening. This can meet the need for electrical connection between the side of the second packaging layer 2 away from the first packaging layer 1 and other external circuit structures (such as circuit boards, other chips, electronic devices, etc.), and can realize double-sided electrical connection of the circuit in the chip packaging module, so as to facilitate the use of the chip packaging module 100.

[0115] It should be understood that the electrical connection block 24 and its optional formation methods, grinding treatment, etc. have been explained in the previous text and can be understood by referring to the previous text. Similar content will not be repeated here.

[0116] Optionally, the fourth pad layer 23 may include multiple fourth pads 231, the number of which can be set according to actual needs. The electrical connection between the fourth pad layer 23 and the second circuit layer 22 may mean that at least a portion of the fourth pads 231 of the fourth pad layer 23 are electrically connected to at least a portion of the circuitry in the second circuit layer 22. The electrical connection blocks 24 formed on the second circuit layer 22 may be designed as one or more as needed, and the specific connection positions can also be set as needed, without any limitations.

[0117] The third molding medium layer 203 in this application can be made of any molding material. Optionally, the material of the third molding medium layer 203 can be epoxy molding compound (EMC). Optionally, the third molding medium layer 203 can also be made of polyimide (PI). Alternatively, other materials that meet the requirements can be used.

[0118] Optionally, the third encapsulating medium layer 203 can be manufactured using an injection mold through an injection molding process. Injection molding processes may include, but are not limited to, C-mold injection molding or T-mold injection molding.

[0119] Optionally, the third molding dielectric layer 203, the first molding dielectric layer 201, and the second molding dielectric layer 202 can be formed using the same molding dielectric material. This results in a more uniform overall structure and properties of the formed second encapsulation layer 2, and better encapsulation stability. For example, the first molding dielectric layer 201, the second molding dielectric layer 202, and the third molding dielectric layer 203 can all be made of epoxy molding compound (EMC plastic) to ensure that the second encapsulation layer 2 has good overall high-temperature resistance, good electrical insulation, good heat dissipation, and good encapsulation performance.

[0120] For example, after forming the electrical connection block 24 on the first second circuit layer 22, the entire chip packaging module structure prepared up to this step can be placed in the mold cavity of a wafer-level or panel-level injection mold, and then injection molded using a molding compound (such as EMC plastic, etc.) (e.g., C-mold or T-mold injection molding process, etc.) to obtain a second second molding dielectric layer 202 covering the first second circuit layer 22 and the electrical connection block 24 formed thereon. Then, the surface of the second second molding dielectric layer 202 away from the first packaging layer 1 can be polished, so that the polished second second molding dielectric layer 202 exposes the electrical connection block 24 formed on the first second circuit layer 22. This polishing process can be performed simultaneously with the polishing of the second molding dielectric layer 202, or the electrical connection block 24 can be left unpolished, depending on the actual situation. After exposing the electrical connection block 24 formed on the first second circuit layer 22, the entire chip packaging module structure prepared up to this step can be placed in the mold cavity of a wafer-level or panel-level injection mold, and then injection molded using a molding compound (e.g., C-mold or T-mold injection molding process) to obtain the third molding dielectric layer 203. Afterwards, an opening can be made in the third molding dielectric layer 203 using any physical or chemical process to expose the fourth pad layer 23. It should be understood that the above process is merely an example and is not intended to limit the embodiments of this application.

[0121] In some alternative embodiments, if the second encapsulation layer 2 to be formed is embedded with two second circuit layers 22, then: step S1046 may include steps S1046B2 to S1046B6, specifically:

[0122] S1046B2: At least one electrical connection block 24 is formed on the third pad layer 21, and a first second molding compound layer 202 is formed on the first molding compound layer 201 to cover the third pad layer 21 and the electrical connection block 24 formed on the third pad layer 21. The first second molding compound layer 202 is ground so that the electrical connection block 24 formed on the third pad layer 21 is exposed.

[0123] Therefore, the first second molding dielectric layer 202 can be prepared through step S1046B2. Step S1061B2 can be understood by referring to step S1046A2, as they are similar and will not be described again here.

[0124] S1046B4: On the first second molding dielectric layer 202, a first second circuit layer 22 is formed that is electrically connected to the electrical connection block 24 formed on the third pad layer 24. At least one electrical connection block 24 is formed on the first second circuit layer 22, and a second second molding dielectric layer 202 is formed that covers the first second circuit layer 22 and the electrical connection block 24 formed on the first second circuit layer 22. The second second molding dielectric layer 202 is then polished so that the electrical connection block 24 formed on the first second circuit layer 22 is exposed.

[0125] Thus, the first layer of the second circuit layer 22 and the second layer of the second encapsulation dielectric layer 202 can be prepared sequentially through this step S1046B4.

[0126] S1046B6: On the second second molding dielectric layer 202, a second second circuit layer 22 electrically connected to the electrical connection block 24 formed on the first second circuit layer 22 is formed, and a third second molding dielectric layer 202 covering the second second circuit layer 22 is formed, thereby obtaining a total of 2 second circuit layers 22 and 3 second molding dielectric layers 202.

[0127] Thus, through step S1046B6, the second circuit layer 22 and the third molding dielectric layer 202 can be prepared sequentially, resulting in a total of 2 second circuit layers 22 and 3 second molding dielectric layers 202.

[0128] Based on this, the present application, by including the above steps S1046B2 to S1046B6, can effectively form multiple layers of second molding dielectric layers 202 sequentially on the first molding dielectric layer 201, and effectively form a second circuit layer 22 between each two adjacent layers of second molding dielectric layers 202, and make the third pad layer 21 and the obtained at least one layer of second circuit layer 22 electrically connected layer by layer, thereby facilitating the preparation of the second encapsulation layer 2.

[0129] Optionally, based on steps S1046B2 to S1046B6, in step S1048, the second encapsulation layer 2 can be composed of a first molding dielectric layer 201 and three second molding dielectric layers 202. This is suitable for cases where a fourth pad layer 23 is not required (see below).

[0130] In some optional embodiments, the chip packaging scheme of this application embodiment can also embed a fourth pad layer 23 in the second packaging layer 2. The fourth pad layer 23 can be adapted to the need for wiring between the second packaging layer 2 and other external circuit structures. Optionally, step S1046B6 may include: forming a second second circuit layer 22 on the second second molding dielectric layer 202, which is electrically connected to the electrical connection block 24 formed on the first second circuit layer 22; forming at least one electrical connection block 24 on the second second circuit layer 22; and forming a third second molding dielectric layer 202 that covers the second second circuit layer 22 and the electrical connection block 24 formed on the second second circuit layer 22. The chip packaging method of this application further includes: grinding the third second molding dielectric layer 202 to expose the electrical connection block 24 formed on the second second circuit layer 22; forming a fourth pad layer electrically connected to the electrical connection block 24 formed on the second second circuit layer 22 on the formed third second molding dielectric layer 202; and forming a third molding dielectric layer 203 covering the fourth pad layer 23, with an opening in the third molding dielectric layer 203 to expose at least a portion of the fourth pad layer 23. Based on this, step S1048 may include: forming a second packaging layer 2 based on the first molding dielectric layer 201, the three second molding dielectric layers 202, and the third molding dielectric layer 203.

[0131] Based on this, through the above optional embodiments, a fourth pad layer 23 electrically connected to the second circuit layer 22 can be embedded in the obtained second packaging layer 2. At least a portion of the fourth pad layer 23 is exposed through the opening, so that the connection lines can be exposed from the other side of the module for connection. This satisfies the requirement that the packaged chip packaging module 100 is electrically connected to other external circuit structures (such as circuit boards, other chips, electronic devices, etc.) through the fourth pad layer 23. It can realize double-sided electrical connection of the lines in the chip packaging module (that is, the packaged lines can be electrically connected to the chip 3 and other circuit structures respectively), so as to facilitate the use of the chip packaging module 100.

[0132] It should be understood that the relevant content regarding the third molding dielectric layer 203 and the fourth pad 231 has been explained similarly in the previous text, and can be understood by referring to the previous content. Similar content will not be repeated here.

[0133] In some alternative embodiments, if the second encapsulation layer 2 to be formed is embedded with n second circuit layers 22, where n≥3, then: S1046 may include steps S1046C2~S1046C8, specifically:

[0134] S1046C2: At least one electrical connection block 24 is formed on the third pad layer 21, and a first second molding compound layer 202 is formed on the first molding compound layer 201 to cover the third pad layer 21 and the electrical connection block 24 formed on the third pad layer 21. The first second molding compound layer 202 is ground so that the electrical connection block 24 formed on the third pad layer 21 is exposed.

[0135] Therefore, the first second molding dielectric layer 202 can be prepared through step S1046C2. Step S1061C2 can be understood by referring to step S1046A2, as they are similar and will not be described again here.

[0136] S1046C4: On the first second molding dielectric layer 202, a first second circuit layer 22 is formed that is electrically connected to the electrical connection block 24 formed on the third pad layer 21. At least one electrical connection block 24 is formed on the first second circuit layer 22, and a second second molding dielectric layer 202 is formed that covers the first second circuit layer 22 and the electrical connection block 24 formed on the first second circuit layer 22. The second second molding dielectric layer 202 is then polished so that the electrical connection block 24 formed on the first second circuit layer 22 is exposed.

[0137] Thus, the first layer of the second circuit layer 22 and the second layer of the second encapsulation dielectric layer 202 can be prepared sequentially through this step S1046C4.

[0138] S1046C6: Repeat the following steps in sequence to obtain the second circuit layer 22 of the 2nd to n-1th layers and the second molding dielectric layer 202 of the 3rd to nth layers: "On the second molding dielectric layer 202 of the ith layer, form the second circuit layer 22 of the ith layer, which is electrically connected to the electrical connection block 24 formed on the second circuit layer 22 of the i-1th layer, form at least one electrical connection block 24 on the second circuit layer 22 of the ith layer, and form the second molding dielectric layer 202 of the i+1th layer that covers the second circuit layer 22 of the ith layer and the electrical connection block 24 formed on the second circuit layer 22 of the ith layer, and then grind the second molding dielectric layer 202 of the i+1th layer so that the electrical connection block 24 formed on the second circuit layer 22 of the ith layer is exposed, 2≤i≤n-1.

[0139] Therefore, through step S1046C6, the second circuit layer 22, the third molding dielectric layer 202, the fourth molding dielectric layer 202, ..., the (n-1)th second circuit layer 22, and the nth second molding dielectric layer 202 can be prepared sequentially.

[0140] S1046C8: On the nth second molding dielectric layer 202, an nth second circuit layer 22 is formed that is electrically connected to the electrical connection block 24 formed on the (n-1)th second circuit layer 22, and an (n+1)th second molding dielectric layer 202 is formed that covers the nth second circuit layer 22, thereby obtaining a total of nth second circuit layer 22 and n+1th second molding dielectric layer 202.

[0141] Therefore, through step S1046C8, the nth second circuit layer 22 and the (n+1)th second molding dielectric layer 202 can be prepared successively, thus obtaining a total of n second circuit layers 22 and n+1 second molding dielectric layers 202.

[0142] Based on this, the present application, by including the above steps S1046C2 to S1046C8, can effectively form multiple layers of second plastic encapsulation dielectric layers 202 sequentially on the first plastic encapsulation dielectric layer 201, and effectively form a second circuit layer 22 between each two adjacent layers of second plastic encapsulation dielectric layers 202, and make the third pad layer 21 and the obtained at least one layer of second circuit layer 22 electrically connected layer by layer, thereby facilitating the preparation of the second encapsulation layer 2.

[0143] Optionally, based on steps S1046C2 to S1046C8, in step S1048, the second encapsulation layer 2 can be composed of the first molding dielectric layer 201 and the n+1th second molding dielectric layer 202. This is suitable for cases where the fourth pad layer 23 is not required (see below).

[0144] In some optional embodiments, the chip packaging scheme of this application embodiment can also embed a fourth pad layer 23 in the second packaging layer 2. The fourth pad layer 23 can be adapted to the need for wiring between the second packaging layer 2 and other external circuit structures. Optionally, step S1046C8 may include: forming an nth layer of second molding dielectric layer 202 that is electrically connected to an electrical connection block 24 formed on the (n-1)th layer of second molding dielectric layer 22; forming at least one electrical connection block 24 on the nth layer of second molding dielectric layer 22; and forming an (n+1)th layer of second molding dielectric layer 202 that covers the nth layer of second molding dielectric layer 22 and the electrical connection block 24 formed on the nth layer of second molding dielectric layer 22. The chip packaging method of this application further includes: grinding the (n+1)th second molding dielectric layer 202 to expose the electrical connection block 24 formed on the nth second circuit layer 22; forming a fourth pad layer 23 electrically connected to the electrical connection block 24 formed on the (n+1)th second molding dielectric layer 202, and forming a third molding dielectric layer 203 covering the fourth pad layer 23, with an opening in the third molding dielectric layer 203 to expose at least a portion of the fourth pad layer 23. Based on this, step S1048 may include: forming a second packaging layer 2 based on the first molding dielectric layer 201, the multiple layers of second molding dielectric layers 202, and the third molding dielectric layer 203.

[0145] Based on this, through the above optional embodiments, a fourth pad layer 23 electrically connected to the nth second circuit layer 22 can be embedded in the obtained second packaging layer 2. At least part of the fourth pad layer 23 is exposed through the opening, so that the connection lines can be exposed from the other side of the module for connection. This satisfies the requirement that the packaged chip packaging module 100 is electrically connected to other external circuit structures (such as circuit boards, other chips, electronic devices, etc.) through the fourth pad layer 23. It can realize double-sided electrical connection of the lines in the chip packaging module (that is, the packaged lines can be electrically connected to the chip 3 and other circuit structures respectively), so as to facilitate the use of the chip packaging module 100.

[0146] It should be understood that the relevant content regarding the third molding dielectric layer 203 and the fourth pad 231 has been explained similarly in the previous text, and can be understood by referring to the previous content. Similar content will not be repeated here.

[0147] For example, we can understand this by referring to the example in Figure 6g. In this example, n=3, three second circuit layers and four second molding dielectric layers 202 are prepared, and one third molding dielectric layer 203 is also prepared, thus forming a second encapsulation layer 2 including one first molding dielectric layer 201, four second molding dielectric layers 202 and one third molding dielectric layer 203.

[0148] Optionally, the thickness of the second encapsulation layer 2 formed in this application can be in the range of 200um to 500um, so that the second encapsulation layer 2 has better structural stability and facilitates the implementation of subsequent steps. For example, H2 in Figure 6g shows the thickness of the second encapsulation layer 2, where 200um ≤ H2 ≤ 500um. Within the above range, it can be selected as needed, such as 200um, 250um, 300um, 350um, 400um, 450um, 500um, etc.

[0149] It should be understood, in conjunction with Figure 2, that in the first encapsulation layer 1 and the second encapsulation layer 2 obtained through the above steps, the first encapsulation layer 1 can be considered as a silicon interposer, without relying on through-silicon via (TSV) technology, and the second encapsulation layer 2 can be considered as an encapsulation substrate. Clearly, this solution differs significantly from the CoWoS technology solution shown in Figure 1.

[0150] Optionally, the second encapsulation layer 2 in this application (which may include a first molding dielectric layer 201 and a second molding dielectric layer 202, and may further include a third molding dielectric layer 203) can be made of EMC material, which is beneficial for achieving more balanced warpage, better mechanical strength, and better heat dissipation performance of the second encapsulation layer 2 of the chip packaging module 100. Furthermore, the second encapsulation layer 2, using EMC material, can serve as an insulating layer for the second circuit layer 22, resulting in better insulation. Moreover, using EMC material makes this solution easier to use with wafer-level / panel-level packaging technology, facilitating wafer-level or panel-level circuit integration. The addition of this feature also facilitates the removal of the wafer 10 in the subsequent step S106.

[0151] It should be noted that the thickness of any two layers among the first molding dielectric layer 201, the multilayer second molding dielectric layer 202, and the third molding dielectric layer 203 can be the same or all different, depending on the design requirements. In this application, the thickness of the second encapsulation layer 2 and the thickness of the first encapsulation layer 1 can be the same or different, depending on the requirements.

[0152] S106: At least partially remove the wafer that is in contact with the first side of the first packaging layer, expose the first pad layer, and electrically connect the chip to the first pad layer to obtain a chip packaging module.

[0153] When understanding the relevant content of step S106, you can also refer to the schematic diagrams in Figures 6h to 6i.

[0154] The wafer 10 can be completely removed, or only a portion of the wafer 10 on the multiple first pads 111 of the first pad layer 11 can be removed, as long as the multiple first pads 111 of the first pad layer 11 are exposed.

[0155] Optionally, the chip 3 can be electrically connected to the first pad layer 11 by soldering to obtain the chip package module 100.

[0156] Optionally, in the actual implementation of step S106, for ease of operation, the semi-finished product obtained in step S104 can be flipped over for further processing of wafer 10 (as shown in Figure 6h and its example description). For example, a grinding and polishing process can be used to remove wafer 10 (wafer 10 can be completely removed, or only a portion of wafer 10 can be removed). Taking wafer 10 as a silicon wafer as an example, since the silicon wafer and the material used in the first packaging layer 1 (e.g., SiO2) are different, wafer 10 can be easily removed with the assistance of processes such as grinding, etching, chemical mechanical polishing (CMP), and dry etching.

[0157] Optionally, the thickness of the second encapsulation layer 2 can be in the range of 200um to 500um, so that the thickness rigidity can support the first encapsulation layer 1 between the second encapsulation layer 2 and the wafer 10, thereby facilitating the removal of the wafer 10 and ensuring structural stability.

[0158] For example, referring to Figure 2 or Figure 6h, an example is shown where the entire wafer 10 is removed, exposing multiple first pads 111 of the first pad layer 11. This demonstrates that the first packaging layer 1 and the second packaging layer are well integrated, and the first circuit layer 12 embedded in the first packaging layer 1 retains high-density interconnect lines with a linewidth of less than 2µm. In this optional example, the first packaging layer 1 can be considered a silicon interposer without relying on through-silicon via (TSV) technology, and the second packaging layer 2 can be considered a packaging substrate. It can also be seen that the first packaging layer 1 and the second packaging layer 2 are sequentially stacked manufacturing processes. The second pad layer 13 of the first packaging layer 1 and the third pad layer 21 of the second packaging layer 2 are not electrically connected by solder. Therefore, there is no solder interface between the first packaging layer 1 and the second packaging layer 2, which offers significant advantages for the packaging process, saving process costs and improving the reliability of the resulting chip packaging module 100.

[0159] Based on this, and based on the technical solutions of steps S102 to S106 in the embodiments of this application, a first packaging layer can be formed on a wafer, which includes a first pad layer, at least one first circuit layer, and a second pad layer with progressively interconnected layers. The first packaging layer includes a first side and a second side opposite to each other along the thickness direction. The first side of the first packaging layer is in contact with the wafer. The first pad layer is formed on the first side of the first packaging layer, and the second pad layer is formed on the second side of the first packaging layer and exposed from the second side of the first packaging layer. The linewidth of the circuit in the first circuit layer is less than or equal to 2 μm. Then, on the second side of the first packaging layer, a second packaging layer is formed, which includes a third pad layer with progressively interconnected layers and at least one second circuit layer. The third pad layer is electrically connected to the second pad layer. The minimum linewidth of the circuit in the second circuit layer is greater than the minimum linewidth of the circuit in the first circuit layer. After that, at least part of the wafer in contact with the first side of the first packaging layer is removed to expose the first pad layer, and the chip is electrically connected to the first pad layer to effectively obtain a chip packaging module. Therefore, through the above technical solution, on the one hand, this application can effectively achieve chip packaging and obtain chip packaging modules without using through-silicon via (TSV) technology, thus reducing manufacturing costs and effectively reducing process complexity compared to related technical solutions using TSV technology; on the other hand, by setting the linewidth of the lines in the first circuit layer to less than or equal to 2µm and making the minimum linewidth of the lines in the second circuit layer greater than the minimum linewidth of the lines in the first circuit layer, the linewidth of the lines in the first circuit layer can be kept small, which facilitates the realization of high-density lines and interconnections and is beneficial to improving the integration of the chip packaging module; furthermore, since this chip packaging solution electrically connects the chip to the first pad layer after the first and second packaging layers are fabricated and connected, compared to the case where the chip is electrically connected to the first pad layer first, it is beneficial to avoid the situation where the chip is scrapped due to the damage of either the first or second packaging layer, thus further reducing process costs and ensuring the yield of the final chip packaging module.

[0160] In some alternative embodiments, the first shape dimension of the first encapsulation layer 1 in the direction perpendicular to its thickness is the same as the second shape dimension of the second encapsulation layer 2 in the direction perpendicular to its thickness.

[0161] Therefore, the shape dimensions of the first encapsulation layer 1 and the second encapsulation layer 2 perpendicular to the thickness direction can be equal. For example, if both the first encapsulation layer 1 and the second encapsulation layer 2 are rectangular or approximately rectangular, then the shape dimensions perpendicular to their thickness direction can also be considered as their shape dimensions in the length and width directions. Assuming the thickness is Z, the length is X, and the width is Y, then the first shape dimension and the second shape dimension being the same can mean that the XY dimensions of the first encapsulation layer 1 and the XY dimensions of the second encapsulation layer 2 are the same. For example, to illustrate this more easily, the first shape dimension of the first encapsulation layer 1 can be a rectangle with a length × width of 5mm × 5mm, then the second shape dimension of the second encapsulation layer 2 can also be a rectangle with a length × width of 5mm × 5mm, in which case the first shape dimension and the second shape dimension are the same. This principle applies to other regular or irregular shapes.

[0162] The packaging method used in this solution allows for the integration of the second packaging layer 2 and the first packaging layer 1 before connecting the chip 3. This is equivalent to facilitating the integration of the silicon interposer and the packaging substrate before connecting the chip. Therefore, unlike the CoWoS technology in Figure 1, which requires integrating the chip and silicon interposer together before shipping the module to the downstream packaging plant for soldering to the packaging substrate, this avoids the problems common in the CoWoS technology: process deviations in the silicon interposer itself (e.g., defects in through-silicon vias, TSVs) or short circuits in interconnects leading to chip failure, high process costs, and low product yield. Based on this, this solution allows for the connection of the chip 3 only when both the first and second packaging layers 1 and 2 are undamaged. This effectively prevents the chip 3 from being scrapped due to damage to either the first or second packaging layer 1 or 2, thus reducing process costs and ensuring a high yield of the final chip packaging module 100.

[0163] In some alternative embodiments, the first encapsulation layer 1 and the second encapsulation layer 2 are integrally cut to ensure that the first shape and the second shape are the same. Thus, by integrally cutting, it can be effectively ensured that the first shape of the first encapsulation layer 1 and the second shape of the second encapsulation layer 2 are the same.

[0164] Optionally, when integrally cutting the first packaging layer 1 and the second packaging layer 2, it can be done after at least a portion of the wafer 10 has been removed.

[0165] In other embodiments, the first shape dimension of the first encapsulation layer 1 in the direction perpendicular to its thickness is smaller than the second shape dimension of the second encapsulation layer 2 in the same direction. This reduces the volume of the first encapsulation layer 1, thereby reducing the volume and weight of the chip packaging module 100. For example, if the first shape dimension of the first encapsulation layer 1 is a rectangle with a length × width of 3mm × 3mm, then the second shape dimension of the second encapsulation layer 2 can be a rectangle with a length × width of 5mm × 5mm. This principle applies to both regular and irregular shapes. For example, such a structure can be obtained by adding a process, such as first cutting the first encapsulation layer 1 and then cutting the second encapsulation layer.

[0166] In some optional embodiments, the chip packaging method of this application further includes: forming a protective layer 5 covering at least a portion of the chip 3 on a first side of the first packaging layer 1 along the thickness direction. (This can also be understood in conjunction with the schematic diagram in FIG6i.)

[0167] Based on this, the protective layer 5 can physically protect at least part of the chip 3 to achieve electrical and environmental isolation. While providing electrical insulation, it also isolates the chip from external water, oxygen, and other adverse environmental factors, which is conducive to the normal operation of the chip 3, effectively ensuring its lifespan, effectively improving the reliability of the packaged chip module 100, and improving the performance of the chip 3 and the packaged chip module 100.

[0168] Optionally, the protective layer 5 can completely cover the chip 3. Obviously, this provides more comprehensive protection for the chip 3 and better improves the performance of the chip 3 and the chip packaging module 100.

[0169] The protective layer 5 can be made of any material, such as an epoxy resin molding compound, an inorganic oxide system, or an organic polyimide (PI) material. Alternatively, it can be made of other materials when required.

[0170] It should be understood that, based on the technical solution of this application, there is no need for substantial equipment investment in silicon interposers. Currently, leading domestic and international wafer foundries have invested significant human and material resources to enter the field of advanced packaging. However, the optional technical solution of this application only utilizes some wafer manufacturing process technologies to perfectly inherit the high-density, small-size circuit characteristics of wafer manufacturing processes, enabling the foundation for high-speed, low-latency inter-chip communication. From the product architecture characteristics of the final chip packaging module 100, this technical solution achieves the same high-speed, low-latency performance comparable to the CoWoS technology solution with the same interconnect density, but at only one-tenth the processing cost. Therefore, it can significantly reduce the cost of chip packaging manufacturing solutions.

[0171] It should be understood that the above description is only some optional embodiments of the chip packaging scheme of this application, and is not a limitation on the embodiments of this application.

[0172] To facilitate a further understanding of the chip packaging scheme of the application embodiments, the overall process of an example chip packaging scheme will be described below with reference to Figures 6a to 6i. This example can be used to manufacture the chip packaging module 100 shown in Figure 2.

[0173] As shown in Figure 6a, a first packaging layer 1 is formed on a wafer 10, which includes a first pad layer 11, at least one first circuit layer 12 (e.g., multiple first circuit layers 12), and a second pad layer 13 with sequentially interconnected layers. The first packaging layer 1 includes a first side and a second side opposite to each other along the thickness direction. The first side of the first packaging layer 1 is in contact with the wafer 10. The first pad layer 11 is formed on the first side of the first packaging layer 1, and the second pad layer 13 is formed on the second side of the first packaging layer 1 and exposed from the second side of the first packaging layer 1. The linewidth of the circuits in the first circuit layer 12 is less than or equal to 2 μm. The first pad layer 11 includes multiple first pads 111, and the second pad layer 13 includes multiple second pads 131. The first packaging layer 1 may embed multiple first circuit layers 12. The first packaging layer 1 is a SiO2 layer formed on the wafer 10. The first pad layer 11, at least one first circuit layer 12, and second pad layer 13 are formed by wafer-level manufacturing processes.

[0174] As shown in Figure 6b, a plurality of conductive blocks 4 are correspondingly formed on a plurality of second pads 131 exposed from the second side of the first encapsulation layer 1, such that the ends of the conductive blocks 4 away from the second pads 131 extend beyond the second side of the first encapsulation layer 1, and the extension distance H1 satisfies 5um≤H1≤100um.

[0175] As shown in Figure 6c, a first molding dielectric layer 201 covering multiple conductive blocks 4 is formed on the second side of the first encapsulation layer 1; the first molding dielectric layer 201 is made of EMC material.

[0176] As shown in Figure 6d, the first molding dielectric layer 201 is ground to expose at least a portion of the plurality of conductive blocks 4.

[0177] As shown in Figure 6e, a plurality of third pads 211 of the third pad layer 21 are correspondingly formed on the exposed plurality of conductive blocks 4, so that the plurality of third pads 211 of the third pad layer 21 are electrically connected to the plurality of second pads 131 of the second pad layer 13 through the plurality of conductive blocks 4.

[0178] As shown in Figure 6f, the second encapsulation layer 2 to be formed has n layers of second circuit layers 22 embedded, where n ≥ 3 (this can be understood as n = 3 in the figure). At least one electrical connection block 24 is formed on the third pad layer 21. A first layer of second plastic encapsulation dielectric layer 202 is formed on the first plastic encapsulation dielectric layer 201, covering the third pad layer 21 and the electrical connection block 24 formed on the third pad layer 21. The first layer of second plastic encapsulation dielectric layer 202 is ground to expose the electrical connection block 24 formed on the third pad layer 21. On the first layer of second plastic encapsulation dielectric layer 202, a connection with the third pad layer 21 is formed. Electrically connected blocks 24 formed on disk layer 21 are electrically connected to the first layer of second circuit layer 22. At least one electrical connected block 24 is formed on the first layer of second circuit layer 22, and a second layer of second molding dielectric layer 202 is formed covering the first layer of second circuit layer 22 and the electrical connected blocks 24 formed on the first layer of second circuit layer 22. The second layer of second molding dielectric layer 202 is then polished so that the electrical connected blocks 24 formed on the first layer of second circuit layer 22 are exposed. The following steps are then repeated sequentially to obtain the second to n-1 layers of second circuit layer 22 and the third to n layers of second molding dielectric layer 202: "In On the i-th second molding dielectric layer 202, an i-th second circuit layer 22 is formed that is electrically connected to the electrical connection block 24 formed on the (i-1)-th second circuit layer 22. At least one electrical connection block 24 is formed on the i-th second circuit layer 22, and an (i+1)-th second molding dielectric layer 202 is formed that covers the i-th second circuit layer 22 and the electrical connection block 24 formed on the i-th second circuit layer 22. The (i+1)-th second molding dielectric layer 202 is then polished so that the electrical connection block 24 formed on the i-th second circuit layer 22 is exposed, 2≤i≤n-1”; on the n-th second... On the molding dielectric layer 202, an nth second circuit layer 22 is formed, electrically connected to the electrical connection block 24 formed on the (n-1)th second circuit layer 22. At least one electrical connection block 24 is formed on the nth second circuit layer 22, and an (n+1)th second molding dielectric layer 202 is formed covering the nth second circuit layer 22 and the electrical connection block 24 formed on the nth second circuit layer 22, thus obtaining a total of n second circuit layers 22 and n+1 second molding dielectric layers 202 (as shown in the example where n=3, a total of 3 second circuit layers 22 and 4 second molding dielectric layers 202 are obtained); the second molding dielectric layer 202 is made of EMC material. (It should be understood that, for ease of understanding, the areas of each molding dielectric layer are roughly shown with dashed lines in each schematic diagram. In addition, the second encapsulation layer 2 to be formed can also embed 1 or 2 second circuit layers 22, the specific implementation method has been explained above, and will not be repeated here with a separate example.)

[0179] As shown in Figure 6g, the (n+1)th second molding dielectric layer 202 is ground to expose the electrical connection block 24 formed on the nth second circuit layer 22. A fourth pad layer 23 electrically connected to the electrical connection block 24 formed on the nth second circuit layer 22 is formed on the (n+1)th second molding dielectric layer 202, and a third molding dielectric layer 203 covering the fourth pad layer 23 is formed. An opening is made in the third molding dielectric layer 203 to expose at least a portion of the fourth pad layer 23. A second encapsulation layer 2 is formed based on the first molding dielectric layer 201, the multiple layers of second molding dielectric layers 202 and third molding dielectric layers 203. The third molding dielectric layer 203 is made of EMC material. The thickness H2 of the second encapsulation layer 2 ranges from 200um to 500um.

[0180] As shown in Figure 6h, the module structure obtained in the step shown in Figure 6g is flipped over, and the wafer 10 is removed to expose the multiple first pads 111 of the first pad layer 11.

[0181] As shown in Figure 6i, at least one chip 3 is electrically connected to multiple first pads 111 of the first pad layer 11 (as shown in Figure 6i, two chips 3 can be used as an example, and they are electrically connected by solder), and then a protective layer 5 covering the chip 3 is made to obtain the chip packaging module 100.

[0182] It should be understood that the examples shown in Figures 6a to 6i are not intended to limit the embodiments of this application in any way. In addition, the descriptions are relatively concise and can be understood in conjunction with the relevant descriptions of the preceding embodiments.

[0183] According to a second aspect of the embodiments of this application, a chip packaging module 100 is provided, which is packaged by the chip packaging method of the first aspect described above.

[0184] It should be understood that since the chip packaging module 100 of the second aspect is obtained through the chip packaging method of the first aspect described above, the chip packaging module 100 does not rely on the through-silicon via (TSV) process, thus resulting in lower manufacturing costs and lower manufacturing process complexity. Furthermore, since the linewidth of the lines in the first circuit layer 12 is set to be less than or equal to 2µm, and the minimum linewidth of the lines in the second circuit layer 22 is greater than the minimum linewidth of the lines in the first circuit layer 12, the linewidth of the lines in the first circuit layer 12 can be kept small, which facilitates the realization of high-density lines and interconnections, resulting in a higher integration level of the chip packaging module 100. In addition, the chip packaging module 100 obtained by this chip packaging method helps to avoid the situation where chip 3 is scrapped due to damage to either the first packaging layer 1 or the second packaging layer 2, thereby further reducing process costs and achieving a better yield of the resulting chip packaging module 100.

[0185] According to a third aspect of the embodiments of this application, referring to FIG2, a chip packaging module 100 is provided, comprising: a chip 3, a first packaging layer 1, and a second packaging layer 2; the first packaging layer 1 includes a first side and a second side opposite to each other along the thickness direction, and is embedded with a first pad layer 11, at least one first circuit layer 12, and a second pad layer 13 electrically connected layer by layer, the first pad layer 11 being located on the first side of the first packaging layer 1 and electrically connected to the chip 3, and the second pad layer 13 being located on the second side of the first packaging layer 1; the second packaging layer 2 is embedded with a third pad layer 21 electrically connected layer by layer and at least one second circuit layer 22, the third pad layer 21 being electrically connected to the second pad layer 13; wherein, the linewidth of the circuit in the first circuit layer is less than or equal to 2µm, and the minimum linewidth of the circuit in the second circuit layer 22 is greater than the minimum linewidth of the circuit in the first circuit layer 12.

[0186] Based on this, the chip packaging module 100 in this application does not rely on the through-silicon via (TSV) process, thus resulting in lower manufacturing costs and lower process complexity. Furthermore, since the linewidth of the lines in the first circuit layer 12 is set to be less than or equal to 2µm, and the minimum linewidth of the lines in the second circuit layer 22 is greater than the minimum linewidth of the lines in the first circuit layer 12, the linewidth of the lines in the first circuit layer 12 can be kept small, which facilitates the realization of high-density circuits and interconnections, resulting in a high integration level of the chip packaging module 100. In addition, the chip packaging module 100 is less likely to suffer from the situation where chip 3 is scrapped due to the failure of either the first packaging layer 1 or the second packaging layer 2, which is conducive to further reducing process costs, and the chip packaging module 100 can also have a better yield.

[0187] Optionally, referring to FIG2, the first pad layer 11 may include a plurality of first pads 111, the second pad layer 13 may include a plurality of second pads 131, and the third pad layer 21 may include a plurality of third pads 211.

[0188] It should be understood that the contents of the first pad layer 11, the first circuit layer 12, the second pad layer 13, the third pad layer 21, the second circuit layer 22, and the fourth pad layer 23 have been explained in the previous text and can be understood in conjunction with the previous text, so they will not be repeated here.

[0189] Optionally, the linewidth of the lines in the first line layer 12 of this application can be from 100nm to 2µm. Such a linewidth range can effectively improve the integration density of the chip packaging module.

[0190] Optionally, the linewidth of the lines in the first line layer 12 of this application can be from 100nm to 1µm. Such a linewidth range can effectively improve the integration density of the chip packaging module.

[0191] In some optional embodiments, the first encapsulation layer 1 is a SiO2 layer.

[0192] Based on this, the first packaging layer 1 in the form of a SiO2 layer can, on the one hand, serve as an insulating layer to effectively meet some insulation requirements between the various layer structures (i.e., the first pad layer 11, at least one first line layer 12, and the second pad layer 13); on the other hand, by adopting the first packaging layer 1 in the form of a SiO2 layer, it is easier to make the line width of the first line layer 12 less than or equal to 2 μm when forming the first line layer 12, thereby achieving high-density lines and improving the integration of the chip packaging module 100.

[0193] In some alternative embodiments, the second encapsulation layer 2 is a plastic encapsulation dielectric layer. The second encapsulation layer 2 in the form of a plastic encapsulation dielectric layer has good performance, is easy to manufacture, and has low process complexity.

[0194] In some alternative embodiments, the material of the encapsulating medium layer is epoxy molding compound (EMC material) and / or polyimide.

[0195] The molding dielectric layer (i.e., the second encapsulation layer 2) uses EMC material, which offers advantages such as low cost, convenient molding operation, high production efficiency, good high-temperature resistance, good electrical insulation, and good heat dissipation, effectively meeting the performance requirements of molding. Furthermore, EMC material also meets the requirements for circuit fabrication. Using EMC material helps to achieve more balanced warpage, better mechanical strength, and better heat dissipation in the second encapsulation layer 2 of the chip packaging module 100. In addition, the second encapsulation layer 2, using EMC material, can serve as an insulating layer for the second circuit layer 22, providing better insulation. Moreover, using EMC material makes this solution easier to use with wafer-level / panel-level packaging technology, facilitating wafer-level or panel-level circuit integration.

[0196] In some optional embodiments, referring to FIG2, the thickness H2 of the second encapsulation layer 2 is between 200um and 500um. This thickness range allows the second encapsulation layer 2 to have good structural stability. Within the above range, it can be selected as needed, for example, 200um, 250um, 300um, 350um, 400um, 450um, 500um, etc.

[0197] In this application, the number of first circuit layers 12 can be set as needed, and no limitation is made here. In some optional embodiments, the first encapsulation layer 1 is embedded with 1 to 10 first circuit layers 12. For example, in the example of FIG2, the first encapsulation layer 1 is embedded with 2 first circuit layers 12.

[0198] In this application, the number of second circuit layers 22 can be set as needed, and no limitation is made here. In some optional embodiments, the second encapsulation layer 2 has 1 to 10 second circuit layers 22 embedded. For example, in the example of FIG2, the second encapsulation layer 2 has 3 second circuit layers 22 embedded.

[0199] In some optional embodiments, at least one electrical connection block 24 is provided between each adjacent pair of the third pad layer 21 and at least one second circuit layer 22, and the adjacent pairs of layers are electrically connected through the at least one electrical connection block 24. Thus, a stable electrical connection between the adjacent pairs of layers can be achieved through the electrical connection block 24.

[0200] In some alternative embodiments, the first shape dimension of the first encapsulation layer 1 in the direction perpendicular to its thickness is the same as the second shape dimension of the second encapsulation layer 2 in the direction perpendicular to its thickness.

[0201] This structural design facilitates the integration of the second packaging layer 2 and the first packaging layer 1 during the manufacturing of the chip packaging module 100, followed by the connection of the chip 3. Essentially, it allows for the integration of the silicon interposer with the packaging substrate before connecting the chip. Therefore, unlike the CoWoS technology in Figure 1, which requires integrating the chip and silicon interposer together before shipping the module to the downstream packaging plant for soldering to the packaging substrate, this avoids the problems common in the CoWoS technology: process deviations in the silicon interposer itself (e.g., defects in through-silicon vias, TSVs) or short circuits in interconnects leading to chip failure, high process costs, and low product yield. Consequently, during the manufacturing of the chip packaging module 100, the connection of the chip 3 can be performed only after ensuring that neither the first packaging layer 1 nor the second packaging layer 2 is damaged. This reduces the likelihood of damage to either the first packaging layer 1 or the second packaging layer 2 causing chip failure, thus lowering process costs and ensuring a higher yield for the chip packaging module 100.

[0202] In some alternative embodiments, the first shape dimension of the first encapsulation layer 1 in the direction perpendicular to its thickness is smaller than the second shape dimension of the second encapsulation layer 2 in the direction perpendicular to its thickness. This reduces the volume of the first encapsulation layer 1, thereby reducing the volume and weight of the chip packaging module 100.

[0203] In some alternative embodiments, referring to FIG2, the chip packaging module 100 further includes a protective layer 5 covering at least a portion of the chip 3.

[0204] Based on this, the protective layer 5 can physically protect at least part of the chip 3 to achieve electrical and environmental isolation. While providing electrical insulation, it also isolates the chip from external water, oxygen, and other adverse environmental factors, which is conducive to the normal operation of the chip 3, effectively ensuring its lifespan, effectively improving the reliability of the packaged chip module 100, and improving the performance of the chip 3 and the packaged chip module 100.

[0205] Optionally, referring to Figure 2, the protective layer 5 can completely cover the chip 3. Obviously, this provides more comprehensive protection for the chip 3 and better improves the performance of the chip 3 and the chip packaging module 100.

[0206] The protective layer 5 can be made of any material, such as an epoxy resin molding compound, an inorganic oxide system, or an organic polyimide (PI) material. Alternatively, it can be made of other materials when required.

[0207] In some optional embodiments, as shown in FIG2, the second encapsulation layer 2 is further embedded with a fourth pad layer 23, which is exposed to the outside of the second encapsulation layer 2 through an opening on the second encapsulation layer 2, and the third pad layer, at least one second circuit layer and the fourth pad layer 23 are electrically connected layer by layer.

[0208] Based on this, the fourth pad layer 23 can meet the electrical connection requirements between the chip packaging module 100 and other external circuit structures (such as circuit boards, other chips, electronic devices, etc.), and can realize the double-sided electrical connection of the circuits in the chip packaging module (that is, the packaged circuits can be electrically connected to the chip 3 and other circuit structures respectively), so as to facilitate the use of the chip packaging module 100.

[0209] Optionally, as shown in FIG2, the fourth pad layer 23 may include a plurality of fourth pads 231.

[0210] In some optional embodiments, the chip packaging module 100 further includes a conductive component; the second side of the first packaging layer 1 is attached to the second packaging layer 2 to form a plurality of receiving slots, and the second pad layer 13 and the third pad layer 21 are at least partially located in the receiving slots; the conductive component seamlessly fills at least one receiving slot and electrically connects the second pad layer 13 and the third pad layer 21.

[0211] Based on this, the stability of the electrical connection between the second pad layer 13 and the third pad layer 21 can be effectively guaranteed by the conductive components, improving the electrical connection performance. Furthermore, the electrical connection can be formed without relying on solder, thus avoiding the presence of a solder interface between the first packaging layer 1 and the second packaging layer 2. Therefore, the drawbacks of unstable packaging structure caused by soldering can be avoided, thereby improving the reliability of the chip packaging module 100 and effectively reducing the packaging cost.

[0212] In some optional embodiments, the second pad layer 13 includes a plurality of second pads 131, the third pad layer 21 includes a plurality of third pads 211, and the conductive component includes a plurality of conductive blocks 4; the plurality of second pads 131 are at least partially located in their corresponding receiving grooves, and the plurality of third pads 211 are at least partially located in their corresponding receiving grooves; the plurality of conductive blocks 4 are seamlessly filled in their corresponding receiving grooves and electrically connect the second pads 131 and the third pads 211 located in the receiving grooves.

[0213] Based on this, the conductive block 4 can effectively ensure the stability of the electrical connection between the second pad 131 of the second pad layer 13 and the third pad 211 of the third pad layer 21, improve the electrical connection performance, and form an electrical connection without relying on solder. This avoids the appearance of a solder interface between the first packaging layer 1 and the second packaging layer 2, thus avoiding the drawbacks of unstable packaging structure caused by soldering. This can improve the reliability of the chip packaging module 100 and effectively reduce the packaging cost.

[0214] It should be understood that the various optional embodiments of the chip packaging module 100 in the third aspect have also been described in detail in the aforementioned chip packaging method embodiments in the first aspect. Therefore, they can also be understood in conjunction with the content in the aforementioned chip packaging method embodiments in the first aspect.

[0215] According to the fourth aspect of the embodiments of this application, as shown in FIG7, an electronic device 200 is provided, including: the chip packaging module 100 provided in the aforementioned second or third aspect.

[0216] Optionally, the electronic device 200 can be any electronic device, including but not limited to mobile phones, computers, etc. It should be understood that the above are merely illustrative applications and do not constitute any limitation on the embodiments of this application.

[0217] It is understood that the above descriptions of various aspects of the embodiments of this application are merely optional exemplary descriptions of the technical solutions of the embodiments of this application, and are not intended to limit the embodiments of this application in any way.

[0218] The optional embodiments of the present application have been described in detail above with reference to the accompanying drawings. However, the embodiments of the present application are not limited thereto. It should be noted that, for the convenience of explaining the embodiments of the present application, the various drawings of the embodiments of the present application are not necessarily drawn to scale, and are only used to facilitate the explanation of the technical solution, and are not intended to limit the embodiments of the present application in any way. Within the scope of the technical concept of the embodiments of the present application, various simple modifications can be made to the technical solutions of the embodiments of the present application. The various technical features included in the different embodiments of the present application can be combined in any suitable manner. In order to avoid unnecessary repetition, the various possible combinations will not be described separately in the embodiments of the present application. However, these simple modifications and combinations should also be regarded as the content disclosed in the embodiments of the present application, and all fall within the protection scope of the embodiments of the present application.

[0219] The term "comprising" and its variations as used herein are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". It should be noted that the concepts of "first", "second", etc., mentioned in this application are only used to distinguish different devices, modules, or units, and are not intended to limit the order of functions performed by these devices, modules, or units or their interdependencies. It should be noted that the modifications "a" and "a plurality" mentioned in this application are illustrative rather than restrictive, and those skilled in the art should understand that, unless explicitly indicated in the context, they should be understood as "one or more".

[0220] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of this application, and are not intended to limit them; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

A chip packaging method, comprising: A first package layer is formed on a wafer, which has a first pad layer, at least one first circuit layer and a second pad layer embedded in it through successive electrical connections. The first package layer includes a first side and a second side opposite to each other along the thickness direction. The first side of the first package layer is in contact with the wafer. The first pad layer is formed on the first side of the first package layer. The second pad layer is formed on the second side of the first package layer and exposed from the second side of the first package layer. The linewidth of the circuit in the first circuit layer is less than or equal to 2 μm. On the second side of the first encapsulation layer, a second encapsulation layer is formed, which is embedded with a third pad layer and at least one second circuit layer that are electrically connected layer by layer. The third pad layer is electrically connected to the second pad layer, and the minimum line width of the circuit in the second circuit layer is greater than the minimum line width of the circuit in the first circuit layer. The wafer that is in contact with the first side of the first packaging layer is at least partially removed to expose the first pad layer, and the chip is electrically connected to the first pad layer to obtain a chip packaging module. According to the method of claim 1, wherein, The first pad layer, at least one first circuit layer, and the second pad layer, which are electrically interconnected layer by layer, are formed by wafer-level manufacturing processes. According to the method of claim 1, wherein, The formation of the first encapsulation layer on the wafer includes: forming a first encapsulation layer in the form of a SiO2 layer on the wafer. According to the method of claim 1, wherein, The second packaging layer, formed on the second side of the first packaging layer, includes a third pad layer and at least one second circuit layer embedded therein, which are electrically interconnected layer by layer. A conductive component is formed on a second pad layer exposed from a second side of the first encapsulation layer, and a first molding dielectric layer is formed on a second side of the first encapsulation layer to expose the conductive component. A third pad layer is formed in the first molding dielectric layer to connect with the exposed conductive component, so that the third pad layer is electrically connected to the second pad layer through the conductive component; Multiple layers of second molding media are sequentially formed on the first molding media layer, and a second circuit layer is formed between every two adjacent layers of second molding media layers, and the third pad layer and the obtained at least one second circuit layer are electrically connected layer by layer. The second encapsulation layer is formed based on the first molding medium layer and the multilayer second molding medium layer. The method according to claim 4, wherein, The second pad layer includes a plurality of second pads, the third pad layer includes a plurality of third pads, and the conductive component includes a plurality of conductive blocks; The step of forming a conductive component on a second pad layer exposed from a second side of a first encapsulation layer, and forming a first molding compound layer on a second side of the first encapsulation layer to expose the conductive component, includes: forming a plurality of conductive blocks correspondingly on a plurality of second pads of the second pad layer, such that the ends of the conductive blocks away from the second pads extend beyond the second side of the first encapsulation layer; forming a first molding compound layer on a second side of the first encapsulation layer to cover the plurality of conductive blocks; and grinding the first molding compound layer so that at least a portion of the plurality of conductive blocks is exposed by the first molding compound layer. The step of forming a third pad layer in the first molding dielectric layer that is connected to the exposed conductive component, so that the third pad layer is electrically connected to the second pad layer through the conductive component, includes: forming a plurality of third pads of the third pad layer correspondingly on a plurality of exposed conductive blocks, so that the plurality of third pads of the third pad layer are electrically connected to a plurality of second pads of the second pad layer through the plurality of conductive blocks respectively. The method according to claim 4, wherein, If the second encapsulation layer to be formed has one second circuit layer embedded in it, then: The step of sequentially forming multiple layers of second molding dielectric layers on the first molding dielectric layer, and forming a second circuit layer between every two adjacent layers of second molding dielectric layers, and electrically connecting the third pad layer and the resulting at least one second circuit layer layer by layer, includes: At least one electrical connection block is formed on the third pad layer, and a first second plastic encapsulation layer is formed on the first plastic encapsulation layer to cover the third pad layer and the electrical connection block formed on the third pad layer. The first second plastic encapsulation layer is ground to expose the electrical connection block formed on the third pad layer. On the first second molding dielectric layer, a first second circuit layer is formed that is electrically connected to the electrical connection block formed on the third pad layer, and a second second molding dielectric layer is formed that covers the first second circuit layer. The method according to claim 6, wherein, The method of forming a first-layer second circuit layer electrically connected to an electrical connection block formed on the third pad layer on the first-layer second molding dielectric layer, and forming a second-layer second molding dielectric layer covering the first-layer second circuit layer, includes: forming a first-layer second circuit layer electrically connected to an electrical connection block formed on the third pad layer on the first-layer second molding dielectric layer; forming at least one electrical connection block on the first-layer second circuit layer; and forming a second-layer second molding dielectric layer covering the first-layer second circuit layer and the electrical connection block formed on the first-layer second circuit layer. The method further includes: grinding the second molding compound layer to expose the electrical connection block formed on the first second circuit layer; forming a fourth pad layer electrically connected to the electrical connection block formed on the first second circuit layer on the formed second molding compound layer; and forming a third molding compound layer covering the fourth pad layer, with an opening in the third molding compound layer to expose at least a portion of the fourth pad layer. The step of forming the second encapsulation layer based on the first molding medium layer and the multilayer second molding medium layer includes: forming the second encapsulation layer based on the first molding medium layer, the multilayer second molding medium layer and the third molding medium layer. The method according to claim 4, wherein, If the second encapsulation layer to be formed has two second circuit layers embedded in it, then: The step of sequentially forming multiple layers of second molding dielectric layers on the first molding dielectric layer, and forming a second circuit layer between every two adjacent layers of second molding dielectric layers, and electrically connecting the third pad layer and the resulting at least one second circuit layer layer by layer, includes: At least one electrical connection block is formed on the third pad layer, and a first second plastic encapsulation layer is formed on the first plastic encapsulation layer to cover the third pad layer and the electrical connection block formed on the third pad layer. The first second plastic encapsulation layer is ground to expose the electrical connection block formed on the third pad layer. On the first second molding dielectric layer, a first second circuit layer is formed that is electrically connected to the electrical connection block formed on the third pad layer. At least one electrical connection block is formed on the first second circuit layer, and a second second molding dielectric layer is formed that covers the first second circuit layer and the electrical connection block formed on the first second circuit layer. The second second molding dielectric layer is then polished so that the electrical connection block formed on the first second circuit layer is exposed. On the second second molding dielectric layer, a second second circuit layer electrically connected to the electrical connection block formed on the first second circuit layer is formed, and a third second molding dielectric layer covering the second second circuit layer is formed, thereby obtaining a total of 2 second circuit layers and 3 second molding dielectric layers. The method according to claim 8, wherein, The method of forming a second circuit layer electrically connected to an electrical connection block formed on the second circuit layer of the first layer on the second molding dielectric layer, and forming a third molding dielectric layer covering the second circuit layer, includes: forming a second circuit layer electrically connected to an electrical connection block formed on the second circuit layer of the first layer on the second molding dielectric layer; forming at least one electrical connection block on the second circuit layer; and forming a third molding dielectric layer covering the second circuit layer and the electrical connection block formed on the second circuit layer. The method further includes: grinding the third second molding compound layer to expose the electrical connection block formed on the second second circuit layer; forming a fourth pad layer electrically connected to the electrical connection block formed on the second second circuit layer on the formed third second molding compound layer, and forming a third molding compound layer covering the fourth pad layer, with an opening in the third molding compound layer to expose at least a portion of the fourth pad layer; The step of forming the second encapsulation layer based on the first molding medium layer and the multilayer second molding medium layer includes: forming the second encapsulation layer based on the first molding medium layer, three layers of second molding medium layer and a third molding medium layer. The method according to claim 4, wherein, If the second encapsulation layer to be formed has n second circuit layers embedded, where n≥3, then: The step of sequentially forming multiple layers of second molding dielectric layers on the first molding dielectric layer, and forming a second circuit layer between every two adjacent layers of second molding dielectric layers, and electrically connecting the third pad layer and the resulting at least one second circuit layer layer by layer, includes: At least one electrical connection block is formed on the third pad layer, and a first second plastic encapsulation layer is formed on the first plastic encapsulation layer to cover the third pad layer and the electrical connection block formed on the third pad layer. The first second plastic encapsulation layer is ground to expose the electrical connection block formed on the third pad layer. On the first second molding dielectric layer, a first second circuit layer is formed that is electrically connected to the electrical connection block formed on the third pad layer. At least one electrical connection block is formed on the first second circuit layer, and a second second molding dielectric layer is formed that covers the first second circuit layer and the electrical connection block formed on the first second circuit layer. The second second molding dielectric layer is then polished so that the electrical connection block formed on the first second circuit layer is exposed. The following steps are then repeated sequentially to obtain the second circuit layers 2 to n-1 and the second molding dielectric layers 3 to n: On the second molding dielectric layer 1, an 1st second circuit layer is formed that is electrically connected to the electrical connection block formed on the 1st-1st second circuit layer; at least one electrical connection block is formed on the 1st second circuit layer; and an 1+1th second molding dielectric layer is formed that covers the 1st second circuit layer and the electrical connection block formed on the 1st second circuit layer; then the 1+1th second molding dielectric layer is ground so that the electrical connection block formed on the 1st second circuit layer is exposed, 2≤i≤n-1; On the nth second molding dielectric layer, an nth second circuit layer is formed that is electrically connected to the electrical connection block formed on the (n-1)th second circuit layer, and an (n+1)th second molding dielectric layer is formed that covers the nth second circuit layer, thereby obtaining a total of n second circuit layers and n+1 second molding dielectric layers. The method according to claim 10, wherein, The method of forming an nth second circuit layer on the nth second molding dielectric layer that is electrically connected to the electrical connection block formed on the (n-1)th second circuit layer, and forming an (n+1)th second molding dielectric layer that covers the nth second circuit layer, includes: forming an nth second circuit layer on the nth second molding dielectric layer that is electrically connected to the electrical connection block formed on the (n-1)th second circuit layer; forming at least one electrical connection block on the nth second circuit layer; and forming an (n+1)th second molding dielectric layer that covers the nth second circuit layer and the electrical connection block formed on the nth second circuit layer. The method further includes: grinding the (n+1)th second molding dielectric layer to expose the electrical connection block formed on the nth second circuit layer; forming a fourth pad layer electrically connected to the electrical connection block formed on the nth second circuit layer on the (n+1)th second molding dielectric layer, and forming a third molding dielectric layer covering the fourth pad layer, with an opening in the third molding dielectric layer to expose at least a portion of the fourth pad layer; The step of forming the second encapsulation layer based on the first molding medium layer and the multilayer second molding medium layer includes: forming the second encapsulation layer based on the first molding medium layer, the multilayer second molding medium layer and the third molding medium layer. The method according to claim 5, wherein, The end of the conductive block furthest from the second pad extends 5µm to 100µm beyond the second side of the first encapsulation layer. The method according to any one of claims 4-12, wherein, The formation of a conductive component on the second pad layer exposed from the second side of the first encapsulation layer includes: A conductive component is formed on the second pad layer exposed from the second side of the first encapsulation layer by at least one of sputtering, vapor deposition, or electroplating processes. The method according to any one of claims 4-12, wherein, The first molding media layer and the second molding media layer are formed using the same molding material. The method according to claim 14, wherein, The molding compound is epoxy resin molding compound and / or polyimide. The method according to any one of claims 1-12, wherein, The first shape dimension of the first encapsulation layer in the direction perpendicular to its thickness is the same as the second shape dimension of the second encapsulation layer in the direction perpendicular to its thickness. The method according to claim 16, wherein, The first encapsulation layer and the second encapsulation layer are integrally cut and formed so that the first shape and the second shape are the same. The method according to any one of claims 1-12, wherein, The method further includes forming a protective layer covering at least a portion of the chip on a first side of the first encapsulation layer along its thickness direction. A chip packaging module, wherein the chip packaging module is packaged by any one of claims 1-18. A chip packaging module, comprising: chip; The first packaging layer includes a first side and a second side opposite to each other along the thickness direction, and is embedded with a first pad layer, at least one first circuit layer and a second pad layer that are electrically connected layer by layer. The first pad layer is located on the first side of the first packaging layer and is electrically connected to the chip, and the second pad layer is located on the second side of the first packaging layer. The second encapsulation layer has embedded a third pad layer and at least one second circuit layer that are electrically connected layer by layer, wherein the third pad layer is electrically connected to the second pad layer. Wherein, the line width of the lines in the first line layer is less than or equal to 2µm, and the minimum line width of the lines in the second line layer is greater than the minimum line width of the lines in the first line layer. The chip packaging module according to claim 20, wherein, The chip packaging module satisfies at least one of the following conditions: The first encapsulation layer is a SiO2 layer; The second encapsulation layer is a plastic encapsulation dielectric layer; The thickness of the second encapsulation layer is between 200µm and 500µm; The first encapsulation layer is embedded with 1 to 10 first circuit layers; The second encapsulation layer is embedded with 1 to 10 second circuit layers; At least one electrical connection block is provided between each two adjacent layers in the third pad layer and at least one second circuit layer, and the two adjacent layers are electrically connected through the at least one electrical connection block. The first shape dimension of the first encapsulation layer in the direction perpendicular to its thickness is the same as the second shape dimension of the second encapsulation layer in the direction perpendicular to its thickness. The first shape dimension of the first encapsulation layer in the direction perpendicular to its thickness is smaller than the second shape dimension of the second encapsulation layer in the direction perpendicular to its thickness. The chip packaging module also includes a protective layer covering at least a portion of the chip; The second encapsulation layer is further embedded with a fourth pad layer, which is exposed to the outside of the second encapsulation layer through an opening on the second encapsulation layer, and the third pad layer, at least one second circuit layer and the fourth pad layer are electrically connected layer by layer. The chip packaging module according to claim 21, wherein, The material of the encapsulating medium layer is epoxy molding compound and / or polyimide. The chip packaging module according to any one of claims 20-22, wherein, The chip packaging module also includes conductive components; The second side of the first encapsulation layer is attached to the second encapsulation layer to form a plurality of receiving grooves, and the second pad layer and the third pad layer are at least partially located within the receiving grooves; The conductive component is seamlessly filled into at least one receiving groove and electrically connects the second pad layer and the third pad layer. The chip packaging module according to claim 23, wherein, The second pad layer includes a plurality of second pads, the third pad layer includes a plurality of third pads, and the conductive component includes a plurality of conductive blocks; The plurality of second pads are at least partially located in their corresponding receiving slots, and the plurality of third pads are at least partially located in their corresponding receiving slots; The plurality of conductive blocks are seamlessly filled into their corresponding receiving slots, and the second and third pads located in the receiving slots are electrically connected. An electronic device, comprising: The chip packaging module as described in any one of claims 19-24.

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