Display substrate, preparation method therefor, and display apparatus

Abstract

A display substrate and a display apparatus. The display substrate comprises a plurality of circuit units. Each circuit unit comprises a pixel driving circuit, the pixel driving circuit at least comprising a first transistor (T1), a third transistor (T3), and a fifth transistor (T5). A second electrode of the first transistor (T1) is connected to a top gate electrode of the third transistor (T3). A second electrode of the fifth transistor (T5) is connected to a first electrode of the third transistor (T3). The pixel driving circuit further comprises a first capacitor (C1) and a sixth transistor (T6). The first capacitor (C1) at least comprises a third electrode plate (13) and a fourth electrode plate (14). The third electrode plate (13) is connected to the second electrode of the first transistor (T1). The fourth electrode plate (14) is connected to a first electrode of the sixth transistor (T6), and a second electrode of the sixth transistor (T6) is connected to a second electrode of the third transistor (T3).

Description

Display substrate and its preparation method, display device Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, specifically to a display substrate and its preparation method, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] On one hand, this disclosure provides a display substrate including multiple circuit units, at least one of which includes a pixel driving circuit. The pixel driving circuit includes at least a first transistor, a third transistor, and a fifth transistor. The first electrode of the first transistor is connected to a reference signal line, and the second electrode of the first transistor is connected to the top gate electrode of the third transistor. The first electrode of the fifth transistor is connected to a first power line, and the second electrode of the fifth transistor is connected to the first electrode of the third transistor. A first capacitor and a sixth transistor are further disposed between the top gate electrode of the third transistor and the second electrode of the third transistor. The first capacitor includes at least a third plate and a fourth plate. The orthographic projection of the fourth plate on the display substrate plane at least partially overlaps with the orthographic projection of the third plate on the display substrate plane. The third plate is connected to the second electrode of the first transistor through a first node electrode, and the fourth plate is connected to the first electrode of the sixth transistor through a second node electrode. The second electrode of the sixth transistor is connected to the second electrode of the third transistor through a third node electrode.

[0005] In an exemplary embodiment, the pixel driving circuit further includes a fourth transistor, the first electrode of which is connected to a data signal line, and the second electrode of which is connected to the top gate electrode of the third transistor.

[0006] In an exemplary embodiment, the fourth transistor includes at least a fourth active layer, the data signal line is connected to a first region of the fourth active layer, the first node electrode is connected to a second region of the fourth active layer and the third electrode plate through a via, and the third electrode plate and the top gate electrode of the third transistor are disposed on the same layer and are an integral structure interconnected with each other.

[0007] In an exemplary embodiment, the third transistor includes at least a third active layer, the fifth transistor includes at least a fifth active layer, and the sixth transistor includes at least a sixth active layer. The first power line is connected to the first region of the fifth active layer, and the second region of the fifth active layer is connected to the first region of the third active layer. The third node electrode is connected to the second region of the sixth active layer via a via, and also to the second region of the third active layer and the bottom gate electrode of the third transistor via a via. The second node electrode is connected to the first region of the sixth active layer via a via. The fourth electrode plate and the second node electrode are disposed on the same layer and are an integral structure interconnected with each other.

[0008] In an exemplary embodiment, the pixel driving circuit further includes a second transistor, the first electrode of which is connected to the initial signal line, and the second electrode of which is connected to the third node electrode.

[0009] In an exemplary embodiment, the display substrate includes a plurality of conductive layers disposed on a substrate in a direction perpendicular to the display substrate, wherein the first node electrode, the second node electrode and the third node electrode are disposed in the same conductive layer.

[0010] In an exemplary embodiment, the pixel driving circuit further includes a second capacitor, wherein the ratio of the capacitance value of the first capacitor to the capacitance value of the second capacitor is 0.95 to 1.05.

[0011] In an exemplary embodiment, the pixel driving circuit further includes a second capacitor, which includes at least a first electrode plate and a second electrode plate stacked together. The orthographic projection of the second electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the first electrode plate on the display substrate plane. The orthographic projection of the third electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the second electrode plate on the display substrate plane. A fourth electrode plate is connected to the second electrode plate. The second electrode plate and the third electrode plate form a first sub-capacitor. The third electrode plate and the fourth electrode plate form a second sub-capacitor. The first sub-capacitor and the second sub-capacitor connected in parallel form the first capacitor. The first electrode plate and the second electrode plate form the second capacitor.

[0012] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate includes a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially disposed on a substrate, wherein a first electrode plate is disposed in the first conductive layer, a second electrode plate is disposed in the second conductive layer, a third electrode plate is disposed in the third conductive layer and a fourth electrode plate is disposed in the fourth conductive layer.

[0013] In an exemplary embodiment, the pixel driving circuit further includes a second capacitor, which includes at least a first electrode plate, a second electrode plate, and a fifth electrode plate stacked together. The orthographic projection of the second electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the first electrode plate on the display substrate plane. The orthographic projection of the third electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the second electrode plate on the display substrate plane. The orthographic projection of the fifth electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the fourth electrode plate on the display substrate plane. The fourth electrode plate is connected to the second electrode plate, and the fifth electrode plate is connected to the first electrode plate. The second electrode plate and the third electrode plate form a first sub-capacitor, and the third electrode plate and the fourth electrode plate form a second sub-capacitor. The first sub-capacitor and the second sub-capacitor connected in parallel form the first capacitor. The first electrode plate and the second electrode plate form a third sub-capacitor, and the fourth electrode plate and the fifth electrode plate form a fourth sub-capacitor. The third sub-capacitor and the fourth sub-capacitor connected in parallel form the second capacitor.

[0014] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer sequentially disposed on a substrate. The first electrode plate is disposed in the first conductive layer, the second electrode plate is disposed in the second conductive layer, the third electrode plate is disposed in the third conductive layer, the fourth electrode plate is disposed in the fourth conductive layer, and the fifth electrode plate is disposed in the fifth conductive layer.

[0015] In an exemplary embodiment, the pixel driving circuit further includes a second capacitor, which includes at least a first electrode plate, a second electrode plate, and a sixth electrode plate stacked together. The orthographic projection of the second electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the first electrode plate on the display substrate plane. The orthographic projection of the sixth electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the second electrode plate on the display substrate plane. The orthographic projection of the third electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the sixth electrode plate on the display substrate plane. A fourth electrode plate is connected to the first electrode plate and the sixth electrode plate respectively. The sixth electrode plate and the third electrode plate form a first sub-capacitor. The third electrode plate and the fourth electrode plate form a second sub-capacitor. The first sub-capacitor and the second sub-capacitor connected in parallel form the first capacitor. The first electrode plate and the second electrode plate form a third sub-capacitor. The second electrode plate and the sixth electrode plate form a fourth sub-capacitor. The third sub-capacitor and the fourth sub-capacitor connected in parallel form the second capacitor.

[0016] In an exemplary embodiment, the pixel driving circuit further includes a second capacitor, which includes at least a first electrode plate, a second electrode plate, a fifth electrode plate, and a sixth electrode plate stacked on top of each other. The orthographic projection of the second electrode plate onto the display substrate plane at least partially overlaps with the orthographic projection of the first electrode plate onto the display substrate plane. The orthographic projection of the sixth electrode plate onto the display substrate plane at least partially overlaps with the orthographic projection of the second electrode plate onto the display substrate plane. The orthographic projection of the third electrode plate onto the display substrate plane at least partially overlaps with the orthographic projection of the sixth electrode plate onto the display substrate plane. The orthographic projection of the fifth electrode plate onto the display substrate plane overlaps with the orthographic projection of the fourth electrode plate onto the display substrate plane. The orthographic projections on the plane at least partially overlap; the fourth electrode is connected to the first electrode and the sixth electrode respectively, the fifth electrode is connected to the second electrode, the sixth electrode and the third electrode form a first sub-capacitor, the third electrode and the fourth electrode form a second sub-capacitor, and the first sub-capacitor and the second sub-capacitor connected in parallel form the first capacitor; the first electrode and the second electrode form a third sub-capacitor, the second electrode and the sixth electrode form a fourth sub-capacitor, the fourth electrode and the fifth electrode form a fifth sub-capacitor, and the third sub-capacitor, the fourth sub-capacitor and the fifth sub-capacitor connected in parallel form the second capacitor.

[0017] In an exemplary embodiment, the pixel driving circuit further includes a second capacitor, which includes at least a second electrode plate, a fifth electrode plate, and a sixth electrode plate stacked together. The orthographic projection of the sixth electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the second electrode plate on the display substrate plane. The orthographic projection of the third electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the sixth electrode plate on the display substrate plane. The orthographic projection of the fifth electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the fourth electrode plate on the display substrate plane. The fourth electrode plate is connected to the sixth electrode plate, and the fifth electrode plate is connected to the second electrode plate. The sixth electrode plate and the third electrode plate form a first sub-capacitor, and the third electrode plate and the fourth electrode plate form a second sub-capacitor. The first sub-capacitor and the second sub-capacitor connected in parallel form the first capacitor. The second electrode plate and the sixth electrode plate form a fourth sub-capacitor, and the fourth electrode plate and the fifth electrode plate form a fifth sub-capacitor. The fourth sub-capacitor and the fifth sub-capacitor connected in parallel form the second capacitor.

[0018] On the other hand, this disclosure also provides a display device including the aforementioned display substrate.

[0019] In another aspect, this disclosure also provides a display substrate including multiple circuit units, at least one circuit unit including a pixel driving circuit, the pixel driving circuit including at least a first transistor, a third transistor and a fifth transistor, the first electrode of the first transistor being connected to a reference signal line, the second electrode of the first transistor being connected to the top gate electrode of the third transistor, the first electrode of the fifth transistor being connected to a first power supply line, and the second electrode of the fifth transistor being connected to the first electrode of the third transistor; the display substrate is configured to display corresponding display content, the display content including multiple display frames, at least one display frame including a reset phase, a threshold compensation phase, a data writing phase and a light emission phase performed sequentially, the pixel driving circuit further including a sixth transistor, the sixth transistor being disposed between the top gate electrode of the third transistor and the second electrode of the third transistor, the sixth transistor being configured to be disconnected during the data writing phase.

[0020] In an exemplary embodiment, the pixel driving circuit further includes a second transistor, a fourth transistor, a first capacitor, and a second capacitor. The first terminal of the second transistor is connected to an initial signal line, and the second terminal of the second transistor is connected to the second terminal of the third transistor, the second terminal of the sixth transistor, and the first terminal of the light-emitting device. The first terminal of the fourth transistor is connected to a data signal line, and the second terminal of the fourth transistor is connected to the second terminal of the first transistor, the top gate electrode of the third transistor, and the first terminal of the first capacitor. The first terminal of the sixth transistor is connected to the second terminal of the first capacitor and the second terminal of the second capacitor, and the first terminal of the second capacitor is connected to a capacitor power supply line.

[0021] In an exemplary embodiment, the pixel driving circuit further includes a second transistor, a fourth transistor, a seventh transistor, a first capacitor, and a second capacitor. The first terminal of the fourth transistor is connected to a data signal line, and the second terminal of the fourth transistor is connected to the second terminal of the first transistor, the top gate electrode of the third transistor, and the first terminal of the first capacitor. The first terminal of the second capacitor is connected to a capacitor power supply line. The first terminal of the sixth transistor is connected to the second terminal of the first capacitor and the second terminal of the second capacitor. The second terminal of the sixth transistor is connected to the second terminal of the third transistor and the first terminal of the seventh transistor. The first terminal of the second transistor is connected to an initial signal line. The second terminal of the second transistor is connected to the second terminal of the seventh transistor and the first terminal of the light-emitting device, or the second terminal of the second transistor is connected to the second terminal of the third transistor, the second terminal of the sixth transistor, and the first terminal of the seventh transistor.

[0022] In an exemplary embodiment, the pixel driving circuit further includes a second transistor, a fourth transistor, a seventh transistor, a first capacitor, and a second capacitor. The first terminal of the second transistor is connected to an initial signal line, the first terminal of the fourth transistor is connected to a data signal line, the second terminal of the second transistor is connected to the second terminal of the third transistor, the first terminal of the seventh transistor, the second terminal of the first capacitor, and the second terminal of the second capacitor, respectively. The second terminal of the seventh transistor is connected to the first terminal of the light-emitting device, the first terminal of the sixth transistor is connected to the second terminal of the first transistor and the top gate electrode of the third transistor, respectively. The second terminal of the sixth transistor is connected to the second terminal of the fourth transistor and the first terminal of the first capacitor, respectively. The first terminal of the second capacitor is connected to a capacitor power supply line.

[0023] In an exemplary embodiment, the pixel driving circuit further includes a second transistor, a fourth transistor, an eighth transistor, a first capacitor, and a second capacitor. The first terminal of the second transistor is connected to the initial signal line, and the second terminal of the second transistor is connected to the second terminal of the third transistor, the second terminal of the sixth transistor, and the first terminal of the light-emitting device, respectively. The first terminal of the fourth transistor is connected to the data signal line.

[0024] The second terminal of the fourth transistor is connected to the second terminal of the first transistor, the top gate electrode of the third transistor, and the first terminal of the first capacitor, respectively. The first terminal of the sixth transistor is connected to the second terminal of the first capacitor and the second terminal of the second capacitor, respectively. The first terminal of the second capacitor is connected to the second terminal of the eighth transistor, and the first terminal of the eighth transistor is connected to the capacitor power supply line. Alternatively, the second terminal of the fourth transistor is connected to the top gate electrode of the third transistor and the first terminal of the first capacitor, respectively. The first terminal of the sixth transistor is connected to the second terminal of the first capacitor and the second terminal of the eighth transistor, respectively. The first terminal of the eighth transistor is connected to the second terminal of the second capacitor, and the first terminal of the second capacitor is connected to the capacitor power supply line.

[0025] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0026] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0027] Figure 1 is a schematic diagram of a display device;

[0028] Figure 2 is a schematic diagram of a planar structure of a display substrate;

[0029] Figure 3 is a schematic cross-sectional view of a display substrate;

[0030] Figure 4 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0031] Figure 5A is a driving timing diagram of the pixel driving circuit shown in Figure 4;

[0032] Figure 5B is another driving timing diagram of the pixel driving circuit shown in Figure 4;

[0033] Figure 6 is a schematic diagram of the planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0034] Figure 7 is a schematic diagram of the structure of a first capacitor and a second capacitor according to an exemplary embodiment of this disclosure;

[0035] Figure 8 is a schematic diagram of the first conductive layer pattern after it is formed according to an embodiment of the present disclosure;

[0036] Figures 9A and 9B are schematic diagrams of the second conductive layer pattern after it has been formed according to an embodiment of the present disclosure;

[0037] Figures 10A and 10B are schematic diagrams of the semiconductor layer pattern formed according to an embodiment of the present disclosure;

[0038] Figures 11A and 11B are schematic diagrams of the formation of the third conductive layer pattern according to an embodiment of the present disclosure;

[0039] Figure 12 is a schematic diagram of the fourth insulating layer pattern after being formed according to an embodiment of the present disclosure;

[0040] Figures 13A and 13B are schematic diagrams of the fourth conductive layer pattern after it is formed according to an embodiment of the present disclosure;

[0041] Figure 14 is a schematic diagram of the first planarization layer pattern after it is formed according to an embodiment of the present disclosure;

[0042] Figures 15A and 15B are schematic diagrams of the fifth conductive layer pattern after it is formed according to an embodiment of the present disclosure;

[0043] Figure 16 is a schematic diagram of the planar structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0044] Figure 17 is a schematic diagram of the structure of another first capacitor and a second capacitor in an exemplary embodiment of the present disclosure;

[0045] Figure 18 is a schematic diagram of the structure of another first capacitor and second capacitor according to an exemplary embodiment of the present disclosure;

[0046] Figure 19 is a schematic diagram of the structure of another first capacitor and second capacitor according to an exemplary embodiment of the present disclosure;

[0047] Figure 20 is a schematic diagram of the structure of another first capacitor and second capacitor according to an exemplary embodiment of the present disclosure;

[0048] Figure 21 is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0049] Figure 22 is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0050] Figure 23 is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0051] Figure 24 is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0052] Figure 25 is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure.

[0053] Explanation of reference numerals in the attached figures: 10—Substrate; 11—First electrode plate; 12—Second electrode plate; 13—Third electrode plate; 14—Fourth electrode plate; 15—Fifth electrode plate; 16—Sixth electrode plate; 21—First active layer; 22—Second active layer; 23—Third active layer; 24—Fourth active layer; 25—Fifth active layer; 26—Sixth active layer; 31—First gate electrode; 34—Fourth gate electrode; 36—Sixth gate electrode; 37—Third bottom gate electrode; 41—First node electrode; 42—Second node electrode; 43—Third node electrode; 44—Data connection electrode; 51—First scan signal line; 52—Second scan signal line; 53—Third scan signal line; 54—First emission control line; 55—Second emission control line; 56—Reference signal line; 57—Initial signal line; 58—First power connection line; 59—Second power connection line; 61—First power line; 62—Second power line; 63—Data signal line; 64—Anode connection electrode; 65—Reference connection line; 66—Initial connection line; 71—First insulating layer; 72—Second insulating layer; 73—Third insulating layer; 74—Fourth insulating layer; 75—First planarization layer; 101—Driver structure layer; 102—Light-emitting structure layer; 103—Encapsulation structure layer. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of this disclosure clearer, embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0055] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0056] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0057] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0058] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0059] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0060] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0061] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0062] In this specification, "parallel" refers to two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" refers to two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0063] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0064] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons, and may have minor deformations due to tolerances, and may include chamfers, curved edges, and other variations. The term "approximately" in this disclosure means that the limits are not strictly defined, and the values ​​are within the allowable range of process and measurement errors.

[0065] Figure 1 is a schematic diagram of a display device. As shown in Figure 1, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple light-emitting signal lines (E1 to Eo). n, m, and o can be natural numbers. The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel driving circuit, which is connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, provide clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and provide clock signals, emission stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply the data voltage corresponding to the grayscale value to data signal lines D1 to Dn in unit rows. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal. The LED driver can generate transmit signals to be provided to LED signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from the timing controller. For example, an LED driver can sequentially provide transmit signals with cutoff level pulses to LED signal lines E1 to Eo. For example, the LED driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal.

[0066] Figure 2 is a schematic diagram of a planar structure of a display substrate. As shown in Figure 2, the display substrate may include multiple pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting device. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is connected to a scan signal line, a light-emitting signal line, and a data signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting device under the control of the scan signal line and the light-emitting signal line. The light-emitting device in each sub-pixel is connected to the pixel driving circuit of its respective sub-pixel. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of its respective sub-pixel.

[0067] In an exemplary embodiment, the first sub-pixel P1 can be a red sub-pixel (R) emitting red light, the second sub-pixel P2 can be a green sub-pixel (G) emitting green light, and the third sub-pixel P3 can be a blue sub-pixel (B) emitting blue light. In an exemplary embodiment, the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels can be arranged horizontally side by side, vertically side by side, or in a triangular arrangement, etc., which are not limited herein.

[0068] In an exemplary embodiment, a pixel unit may include four sub-pixels, which may be arranged in a horizontal, vertical, or square manner, etc., and this disclosure does not limit the arrangement.

[0069] Figure 3 is a cross-sectional schematic diagram of a display substrate, illustrating the structure of three sub-pixels. As shown in Figure 3, on a plane perpendicular to the display substrate, the display substrate may include a driving structure layer 101 disposed on a substrate 10, a light-emitting structure layer 102 disposed on the side of the driving structure layer 101 away from the substrate 10, and an encapsulation structure layer 103 disposed on the side of the light-emitting structure layer 102 away from the substrate 10. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which are not limited herein.

[0070] In an exemplary embodiment, on a plane parallel to the display substrate, the driving structure layer 101 may include multiple circuit units. Each circuit unit may include a pixel driving circuit, as well as scan signal lines, light emission control lines, data signal lines, and a first power supply line connected to the pixel driving circuit. The pixel driving circuit may include at least multiple transistors and a storage capacitor. The light emission structure layer 102 may include multiple light-emitting devices. Each light-emitting device may include at least an anode, a pixel definition layer, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit in the corresponding circuit unit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of the corresponding color under the driving of the anode and cathode. The encapsulation structure layer 103 may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers, forming an inorganic / organic / inorganic material stacked structure, which can ensure that external moisture cannot enter the light emission structure layer 102.

[0071] An exemplary embodiment of this disclosure provides a display substrate including a plurality of circuit units, at least one of which includes a pixel driving circuit. The pixel driving circuit includes at least a first transistor, a third transistor, and a fifth transistor. The first electrode of the first transistor is connected to a reference signal line, and the second electrode of the first transistor is connected to the top gate electrode of the third transistor. The first electrode of the fifth transistor is connected to a first power supply line, and the second electrode of the fifth transistor is connected to the first electrode of the third transistor. A first capacitor and a sixth transistor are further disposed between the top gate electrode of the third transistor and the second electrode of the third transistor. The first capacitor includes at least a third plate and a fourth plate. The orthographic projection of the fourth plate on the display substrate plane at least partially overlaps with the orthographic projection of the third plate on the display substrate plane. The third plate is connected to the second electrode of the first transistor through a first node electrode, and the fourth plate is connected to the first electrode of the sixth transistor through a second node electrode. The second electrode of the sixth transistor is connected to the second electrode of the third transistor through a third node electrode.

[0072] The display substrate provided in the exemplary embodiments of this disclosure may include a display area, a bonding area on one side of the display area, and a border area on other sides of the display area in a plane parallel to the display substrate. In a plane perpendicular to the display substrate, the display substrate may include a driving structure layer disposed on a substrate, a light-emitting structure layer disposed on the side of the driving structure layer away from the substrate, and an encapsulation structure layer disposed on the side of the light-emitting structure layer away from the substrate. The driving structure layer of the display area may include multiple circuit units constituting multiple cell rows and multiple cell columns. At least one circuit unit may include a pixel driving circuit configured to output a corresponding current to a connected light-emitting device. The light-emitting structure layer of the display area may include multiple light-emitting units. At least one light-emitting unit may include a light-emitting device connected to the pixel driving circuit of the corresponding circuit unit. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the connected pixel driving circuit.

[0073] In exemplary embodiments, the circuit unit referred to in this disclosure refers to a region divided according to the pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to the light-emitting device. In exemplary embodiments, the position of the orthographic projection of the light-emitting unit on the substrate may correspond to the position of the orthographic projection of the circuit unit on the substrate, or the position of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position of the orthographic projection of the circuit unit on the substrate.

[0074] In an exemplary embodiment, a plurality of circuit units arranged sequentially along a first direction X can be referred to as a unit row, and a plurality of circuit units arranged sequentially along a second direction Y can be referred to as a unit column. The plurality of unit rows and the plurality of unit columns constitute an array of circuit units, with the first direction X intersecting the second direction Y. In an exemplary embodiment, the first direction X can be referred to as the unit row direction, and the second direction Y can be referred to as the unit column direction.

[0075] The following examples illustrate the display substrate of this embodiment.

[0076] Figure 4 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure. As shown in Figure 4, the pixel driving circuit of the exemplary embodiment of the present disclosure can be a 6T2C structure, including 6 transistors (first transistor T1 to sixth transistor T6) and 2 storage capacitors (first capacitor C1 and second capacitor C2). The pixel driving circuit is connected to 10 signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, first light emission signal line EM1, second light emission signal line EM2, initial signal line INIT, reference signal line REF, data signal line DATA, first power supply line VDD and capacitor power supply line VAR).

[0077] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the second terminal of the first transistor T1, the second terminal of the fourth transistor T4, the top gate electrode of the third transistor T3, and the first terminal of the first capacitor C1. The second node N2 is connected to the first terminal of the sixth transistor T6, the second terminal of the first capacitor C1, and the second terminal of the second capacitor C2. The third node N3 is connected to the second terminal of the second transistor T2 and the second terminal of the sixth transistor T6.

[0078] In an exemplary embodiment, the first terminal of the first capacitor C1 is connected to the first node N1, and the second terminal of the first capacitor C1 is connected to the second node N2. The first terminal of the second capacitor C2 is connected to the capacitor power line VAR, and the second terminal of the second capacitor C2 is connected to the second node N2.

[0079] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the first scan signal line S1, the first electrode of the first transistor T1 is connected to the reference signal line REF, and the second electrode of the first transistor T1 is connected to the first node N1.

[0080] In an exemplary embodiment, the gate electrode of the second transistor T2 is connected to the second scan signal line S2, the first electrode of the second transistor T2 is connected to the initial signal line INIT, and the second electrode of the second transistor T2 is connected to the third node N3.

[0081] In an exemplary embodiment, the top gate electrode of the third transistor T3 is connected to the first node N1, the bottom gate electrode of the third transistor T3 is connected to the second terminal of the third transistor T3, the first terminal of the third transistor T3 is connected to the second terminal of the fifth transistor T5, and the second terminal of the third transistor T3 is connected to the third node N3.

[0082] In an exemplary embodiment, the gate electrode of the fourth transistor T4 is connected to the third scan signal line S3, the first electrode of the fourth transistor T4 is connected to the data signal line DATA, and the second electrode of the fourth transistor T4 is connected to the first node N1.

[0083] In an exemplary embodiment, the gate electrode of the fifth transistor T5 is connected to the first light-emitting signal line EM1, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first electrode of the third transistor T3.

[0084] In an exemplary embodiment, the gate electrode of the sixth transistor T6 is connected to the second light-emitting signal line EM2, the first electrode of the sixth transistor T6 is connected to the second node N2, and the second electrode of the sixth transistor T6 is connected to the third node N3.

[0085] In an exemplary embodiment, the light-emitting device EL can be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or it can be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode). The first electrode of the light-emitting device is connected to the third node N3, and the second electrode of the light-emitting device is connected to the second power line VSS.

[0086] In an exemplary embodiment, the six transistors in the pixel driving circuit can be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the processing difficulty of the display substrate, and improve the product yield.

[0087] In an exemplary embodiment, the six transistors of the pixel driving circuit can be oxide transistors. The active layer of the oxide transistors can be oxide semiconductor. Oxide transistors have advantages such as low leakage current. By using a display substrate with oxide transistors, low-frequency driving can be achieved, power consumption can be reduced, and display quality can be improved.

[0088] In some possible implementations, the six transistors in the pixel driving circuit can be P-type transistors, and the active layer of the P-type transistors can be made of low-temperature polysilicon (LTPS). In other possible implementations, the second transistor T2 can be a P-type transistor, and the other transistors can be N-type transistors, which can optimize the layout space, reduce signal capacitance, and improve brightness uniformity. In still other possible implementations, the fourth transistor T4 can be a P-type transistor, and the other transistors can be N-type transistors, which can improve the data signal writing efficiency and facilitate the achievement of high refresh rates, such as 240Hz. In yet another possible implementation, the first transistor T1 can be a P-type transistor, and the other transistors can be N-type transistors, which can improve the charging efficiency of the first node N1 and facilitate the achievement of high refresh rates.

[0089] In an exemplary embodiment, the first power line VDD can be configured to provide a constant first power signal to the pixel driving circuit, and the second power line VSS can be configured to provide a constant second power signal to the light-emitting device, wherein the voltage of the first power signal is greater than the voltage of the second power signal. The reference signal line REF, the initial signal line INIT, and the capacitor power line VAR can be configured to provide a constant reference voltage signal, an initial voltage signal, and a capacitor voltage signal to the pixel driving circuit, respectively.

[0090] In an exemplary embodiment, in the pixel driving circuit of this disclosure, the capacitor power line VAR can provide a separate constant voltage signal, or it can be shared with the first power line VDD, the second power line VSS, the reference signal line REF, or the initial signal line INIT. That is, the capacitor power line VAR can provide a first power signal, a second power signal, a reference voltage signal, or an initial voltage signal.

[0091] Figure 5A is a timing diagram of a pixel driving circuit shown in Figure 4. As shown in Figure 5A, the first transistor T1 to the sixth transistor T6 in the pixel driving circuit are all N-type transistors. The operation of the pixel driving circuit can include:

[0092] The first stage, A1, can be called the reset stage. The signals of the first scan signal line S1, the second scan signal line S2, and the second light-emitting signal line EM2 are high-level signals, while the signals of the third scan signal line S3 and the first light-emitting signal line EM1 are low-level signals, which turns on the first transistor T1, the second transistor T2, and the sixth transistor T6, while turning off the other transistors.

[0093] The first transistor T1 is turned on, providing the reference signal from the reference signal line REF to the first node N1, resetting (initializing) the first node N1. The potential of the first node N1 is Vref, where Vref is the voltage of the reference signal. The second transistor T2 is turned on, providing the initial signal from the initial signal line INIT to the third node N3. The sixth transistor T6 is turned on, connecting the second node N2 and the third node N3, resetting the second node N2 and the third node N3. The potentials of the second node N2 and the third node N3 are Vinit, where Vinit is the voltage of the initial signal.

[0094] The second stage, A2, can be called the threshold compensation stage. The signals of the first scan signal line S1, the first light emission signal line EM1, and the second light emission signal line EM2 are high-level signals, while the signals of the second scan signal line S2 and the third scan signal line S3 are low-level signals, which turns on the first transistor T1, the fifth transistor T5, and the sixth transistor T6, while turning off the other transistors.

[0095] The continuous conduction of the first transistor T1 keeps the potential of the first node N1 at Vref. The conduction of the fifth transistor T5 allows the first power signal provided by the first power line VDD to be supplied to the first terminal of the third transistor T3. The conduction of the sixth transistor T6 connects the second node N2 and the third node N3. Therefore, the potential of the second node N2 and the third node N3 is Vref-Vth, where Vth is the threshold voltage of the third transistor T3.

[0096] The third stage, A3, can be called the data writing stage. The signals of the second scan signal line S2 and the third scan signal line S3 are high-level signals, while the signals of the first scan signal line S1, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are low-level signals, which turns on the second transistor T2 and the fourth transistor T4, while turning off the other transistors.

[0097] The fourth transistor T4 turns on, allowing the data signal output from the data signal line DATA to be supplied to the first node N1. The potential of the first node N1 is Vdata, which is the voltage of the data signal. After voltage division, the potential difference across the first capacitor C1 (i.e., the potential difference between the first node N1 and the second node N2) ΔC1 is [C2 / C1+C2](Vdata-Vref)+Vth. The second transistor T2 turns on, causing the initial signal to reset the third node N3. The potential of the third node N3 is Vinit. Since the sixth transistor T6 is turned off in this stage, the first node N1 and the third node N3 are isolated. Not only will the writing of the data signal not affect the third node N3, but the potential of the third node N3 will not affect the writing of the data signal.

[0098] In some possible implementations, the signal of the second scan signal line S2 in this stage can be a low-level signal, the second transistor T2 is turned off, and the potential of the third node N3 is Vref-Vth.

[0099] The fourth stage, A4, can be called the light-emitting stage. The signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are high-level signals, while the signals of the first scan signal line S1, the second scan signal line S2, and the third scan signal line S3 are low-level signals, turning on the fifth transistor T5 and the sixth transistor T6, while turning off the other transistors.

[0100] The fifth transistor T5 turns on, allowing the first power signal provided by the first power line VDD to be supplied to the first terminal of the third transistor T3. The sixth transistor T6 turns on, connecting the second node N2 and the third node N3, making the potential jumps across the first capacitor C1 consistent. Therefore, the potential difference ΔC1 across the first capacitor C1 remains unchanged, and thus the driving current of the third transistor T3 is:

[0101] I = K(Vgs - Vth) 2 =K(ΔC1-Vth) 2 =K[C2 / C1+C2](Vdata-Vref) 2 .

[0102] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the light-emitting device EL, K is a constant related to the process and design, and Vgs is the voltage difference between the top gate electrode and the second electrode of the third transistor T3.

[0103] As can be seen from the derivation of the above current formula, during the light-emitting stage, the driving current of the third transistor T3 in each pixel driving circuit is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product, and improving the display effect of the entire display product.

[0104] The pixel driving circuit provided in this exemplary embodiment provides a sixth transistor T6, which serves as an isolation transistor, between the first node N1 and the third node N3. The sixth transistor T6 is turned on during the reset phase, threshold compensation phase, and light emission phase, but turned off during the data writing phase, thus isolating the first node N1 and the third node N3. Not only does the writing of the data signal not affect the third node N3, but the potential of the third node N3 also does not affect the writing of the data signal. This effectively avoids problems such as mutual interference between threshold compensation and data writing, effectively avoids the influence on the gate-source voltage of the driving transistor, effectively reduces the variation in the output current of the pixel driving circuit, effectively reduces the variation in light emission brightness, and effectively improves the display effect and display quality.

[0105] Figure 5B is another driving timing diagram of the pixel driving circuit shown in Figure 4. As shown in Figure 5B, the operation of the pixel driving circuit can include a display frame B1 and at least one holding frame B2. The operation of the display frame B1 is basically the same as that shown in Figure 5, including a reset stage, a threshold compensation stage, a data writing stage, and a light emission stage. In the holding frame B2 stage, the signal of the second scan signal line S2 is switched to a high-level signal and a low-level signal in sequence. The second transistor T2 is turned on and off multiple times, and the third node N3 is reset multiple times. Other transistors remain in the off state.

[0106] The pixel driving circuit disclosed herein can not only eliminate the influence of voltage changes of the light-emitting device on the pixel driving circuit by setting the second transistor T2 to be turned on and off multiple times during the holding frame stage, and reset the third node N3 multiple times, but also bias the third transistor T3 to maintain the brightness during the light-emitting stage.

[0107] Figure 6 is a schematic diagram of the planar structure of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the planar structure of the pixel driving circuit in three circuit units in a unit row. Figure 7 is a schematic diagram of the structure of a first capacitor and a second capacitor according to an exemplary embodiment of the present disclosure, and is a cross-sectional view along direction AA in Figure 6. As shown in Figures 6 and 7, in a direction parallel to the display substrate, the display substrate may include circuit units constituting multiple unit rows and multiple unit columns. At least one circuit unit may include a pixel driving circuit, which is connected to at least the first scan signal line 51, the second scan signal line 52, the third scan signal line 53, the first light emission signal line 54, the second light emission signal line 55, the reference signal line 56, the initial signal line 57, the first power supply line 61, the second power supply line 62, and the data signal line 63.

[0108] In an exemplary embodiment, the first scan signal line 51, the second scan signal line 52, and the third scan signal line 53 are configured to provide a first scan signal, a second scan signal, and a third scan signal to the pixel driving circuit, respectively. The first light emission signal line 54 and the second light emission signal line 55 are configured to provide a first light emission control signal and a second light emission control signal to the pixel driving circuit, respectively. The reference signal line 56 and the initial signal line 57 are configured to provide a reference signal and an initial signal to the pixel driving circuit, respectively. The first power supply line 61 and the second power supply line 62 are configured to provide a first power signal and a second power signal to the pixel driving circuit, respectively. The data signal line 63 is configured to provide a data signal to the pixel driving circuit. The multiple signal lines connected to the pixel driving circuit can be located within corresponding circuit units.

[0109] In an exemplary embodiment, the shapes of the first scan signal line 51, the second scan signal line 52, the third scan signal line 53, the first light emission signal line 54, the second light emission signal line 55, the reference signal line 56, and the initial signal line 57 can be straight lines or broken lines extending along the first direction X, and the shapes of the first power line 61, the second power line 62, and the data signal line 63 can be straight lines or broken lines extending along the second direction Y.

[0110] In this disclosure, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In the following description, "A extends along direction B" refers to "the main body of A extends along direction B".

[0111] In an exemplary embodiment, the pixel driving circuit may include at least a first capacitor, a second capacitor, and a plurality of oxide transistors. The plurality of oxide transistors may include a first transistor T1 as a reference transistor, a second transistor T2 as a reset transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a light-emitting control transistor, and a sixth transistor T6 as an isolation transistor.

[0112] In an exemplary embodiment, in at least one circuit unit, the first transistor T1, the fourth transistor T4, and the fifth transistor T5 may be disposed on the side opposite to the second direction Y of the third transistor T3, and the second transistor T2 may be disposed on the side of the fourth transistor T4 away from the third transistor T3. The second transistor T2 and the sixth transistor T6 may be disposed on the side of the third transistor T3 in the second direction Y, and the second transistor T2 may be disposed on the side of the sixth transistor T6 away from the third transistor T3.

[0113] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the first scan signal line 51, the first terminal of the first transistor T1 is connected to the reference signal line 56, and the second terminal of the first transistor T1 is connected to the top gate electrode of the third transistor T3 and the second terminal of the fourth transistor T4, respectively. The gate electrode of the second transistor T2 is connected to the second scan signal line 52, the first terminal of the second transistor T2 is connected to the initial signal line 57, and the second terminal of the second transistor T2 is connected to the second terminals of the third transistor T3 and the sixth transistor T6, respectively. The first terminal of the third transistor T3 is connected to the second terminal of the fifth transistor T5, the gate electrode of the fourth transistor T4 is connected to the third scan signal line 53, and the first terminal of the fourth transistor T4 is connected to the data signal line 63. The gate electrode of the fifth transistor T5 is connected to the first light-emitting signal line 54, the first terminal of the fifth transistor T5 is connected to the first power supply line 61, the gate electrode of the sixth transistor T6 is connected to the second light-emitting signal line 55, and the first terminal of the sixth transistor T6 is connected to the second power supply line 62.

[0114] In an exemplary embodiment, in at least one circuit unit, the third scan signal line 53 may be disposed on the side opposite to the second direction Y of the third transistor T3, the first scan signal line 51 may be disposed on the side of the third scan signal line 53 away from the third transistor T3, the reference signal line 56 may be disposed on the side of the first scan signal line 51 away from the third transistor T3, and the first light-emitting signal line 54 may be disposed on the side of the reference signal line 56 away from the third transistor T3. The second light-emitting signal line 55 may be disposed on the side of the third transistor T3 in the second direction Y, the second scan signal line 52 may be disposed on the side of the second light-emitting signal line 55 away from the third transistor T3, and the initial signal line 57 may be disposed on the side of the second scan signal line 52 away from the third transistor T3.

[0115] In an exemplary embodiment, the first capacitor and the second capacitor may include a first electrode plate 11, a second electrode plate 12, a third electrode plate 13, and a fourth electrode plate 14 stacked together. The orthographic projection of the second electrode plate 12 onto the substrate at least partially overlaps with the orthographic projection of the first electrode plate 11 onto the substrate, and the first electrode plate 11 and the second electrode plate 12 form the second capacitor of the pixel driving circuit. The orthographic projection of the third electrode plate 13 onto the substrate at least partially overlaps with the orthographic projection of the second electrode plate 12 onto the substrate, and the second electrode plate 12 and the third electrode plate 13 form the first sub-capacitor. The orthographic projection of the fourth electrode plate 14 onto the substrate at least partially overlaps with the orthographic projection of the third electrode plate 13 onto the substrate, and the third electrode plate 13 and the fourth electrode plate 14 form the second sub-capacitor. The first sub-capacitor and the second sub-capacitor connected in parallel form the first capacitor of the pixel driving circuit.

[0116] In an exemplary embodiment, at least one circuit unit may further include a first node electrode 41 having a first node potential in the pixel driving circuit, a second node electrode 42 having a second node potential in the pixel driving circuit, and a third node electrode 43 having a third node potential in the pixel driving circuit. The third electrode plate 13 can be connected to the second electrode of the first transistor T1 and the second electrode of the fourth transistor T4 via the first node electrode 41. The fourth electrode plate 14 can be connected to the first electrode of the sixth transistor T6 via the second node electrode 42. The second electrode of the sixth transistor T6 can be connected to the second electrode of the third transistor T3 via the third node electrode 43. Here, the first node potential refers to the potential of the first node N1 in the pixel driving circuit, the second node potential refers to the potential of the second node N2 in the pixel driving circuit, and the third node potential refers to the potential of the third node N3 in the pixel driving circuit.

[0117] In an exemplary embodiment, a sixth transistor T6, which serves as an isolation transistor, can be disposed between the second node electrode 42 and the third node electrode 43. The first electrode of the sixth transistor T6 is connected to the second node electrode 42, and the second electrode of the sixth transistor T6 is connected to the third node electrode 43.

[0118] In an exemplary embodiment, the first transistor T1 may include at least a first active layer 21, the second transistor T2 may include at least a second active layer 22, the third transistor T3 may include at least a third active layer 23, the fourth transistor T4 may include at least a fourth active layer 24, the fifth transistor T5 may include at least a fifth active layer 25, and the sixth transistor T6 may include at least a sixth active layer 26. The second regions of the first active layer 21 and the second regions of the fourth active layer 24 may be interconnected, the second regions of the second active layer 22 and the second regions of the sixth active layer 26 may be interconnected, the first region of the third active layer 23 and the second region of the fifth transistor T5 may be interconnected, the reference signal line 56 may be connected to the first region of the first active layer 21, the initial signal line 57 may be connected to the first region of the second active layer 22, the data signal line 63 may be connected to the first region of the fourth active layer 24, and the first power supply line 61 may be connected to the first region of the fifth transistor T5.

[0119] In an exemplary embodiment, in at least one circuit unit, the first node electrode 41 can be disposed between the fourth electrode plate 14 and the third scan signal line 53. The first node electrode 41 can be connected to the third electrode plate 13 and the second region of the first active layer 21 and the second region of the fourth active layer 24 that are interconnected through vias. The top gate electrode of the third electrode plate 13 and the third transistor T3 can be disposed on the same layer and are an integral structure interconnected. Therefore, the third electrode plate 13 has a first node potential.

[0120] In an exemplary embodiment, in at least one circuit unit, the second node electrode 42 can be disposed between the fourth electrode plate 14 and the second light-emitting signal line 55. The second node electrode 42 can be connected to the first region of the sixth active layer 26 through a via. The fourth electrode plate 14 and the second node electrode 42 can be disposed on the same layer and are an integral structure connected to each other. Therefore, the fourth electrode plate 14 has a second node potential.

[0121] In an exemplary embodiment, in at least one circuit unit, the third node electrode 43 may be disposed on one side of the fourth electrode plate 14 in the first direction X or on the opposite side of the first direction X. The third node electrode 43 is connected to the second region of the second active layer 22 and the second region of the sixth active layer 26 through vias, and is also connected to the second region of the third active layer 23 and the bottom gate electrode of the third transistor T3 through vias.

[0122] In an exemplary embodiment, at least one circuit unit may further include a first power connection line 58. The shape of the first power connection line 58 may be a straight line or a broken line extending along the first direction X, and it may be disposed on the side of the first light-emitting control line 54 away from the fourth electrode plate 14. The first power line 61 may be connected to the first power connection line 58 through a via. The first power connection line 58 extending along the first direction X and the first power line 61 extending along the second direction Y constitute a mesh-like interconnected structure for transmitting the first power signal.

[0123] In an exemplary embodiment, at least one circuit unit may further include a second power connection line 59. The shape of the second power connection line 59 may be a straight line or a broken line extending along the first direction X, and it may be disposed between the second scan signal line 52 and the second light emission control line 55. The second power line 62 may be connected to the second power connection line 59 through a via. The second power connection line 59 extending along the first direction X and the second power line 62 extending along the second direction Y constitute a mesh-like interconnected structure for transmitting the second power signal.

[0124] In an exemplary embodiment, in at least one cell row, a plurality of circuit cells may include at least a first circuit cell Q1, a second circuit cell Q2, and a third circuit cell Q3. The pixel driving circuit in the first circuit cell Q1 and the pixel driving circuit in the second circuit cell Q2 may be arranged in a mirror-symmetric manner with respect to the column center line. The pixel driving circuit in the first circuit cell Q1 and the pixel driving circuit in the second circuit cell Q2 may be substantially the same. The column center line may be located between two adjacent circuit cells and extend along a second direction Y to a straight line.

[0125] In some possible implementations, other symmetrical arrangements are also possible. For example, the pixel driving circuits in the first circuit unit Q1 and the third circuit unit Q3 can be arranged in a mirror-symmetrical manner with respect to the column center line. Similarly, the pixel driving circuits in the second circuit unit Q2 and the third circuit unit Q3 can be arranged in a mirror-symmetrical manner with respect to the column center line; this disclosure does not limit the scope of the embodiments.

[0126] In an exemplary embodiment, the pixel driving circuit in the first circuit unit Q1 is connected to a red light-emitting device that emits red light, the pixel driving circuit in the second circuit unit Q2 is connected to a green light-emitting device that emits green light, and the pixel driving circuit in the third circuit unit Q3 is connected to a blue light-emitting device that emits blue light. In some possible embodiments, other connection methods may also be used, which are not limited herein.

[0127] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include at least: a substrate 10, a first conductive layer disposed on the substrate 10, a first insulating layer 71 disposed on the side of the first conductive layer away from the substrate 10, a second conductive layer disposed on the side of the first insulating layer 71 away from the substrate 10, a second insulating layer 72 disposed on the side of the second conductive layer away from the substrate 10, a semiconductor layer disposed on the side of the second insulating layer 72 away from the substrate 10, a third insulating layer 73 disposed on the side of the semiconductor layer away from the substrate 10, a third conductive layer disposed on the side of the third insulating layer 73 away from the substrate 10, a fourth insulating layer 74 disposed on the side of the third conductive layer away from the substrate 10, a fourth conductive layer disposed on the side of the fourth insulating layer 74 away from the substrate 10, a first planarization layer disposed on the side of the fourth conductive layer away from the substrate 10, and a fifth conductive layer disposed on the side of the first planarization layer away from the substrate 10.

[0128] In an exemplary embodiment, the first conductive layer may include at least a first electrode 11, the second conductive layer may include at least a second electrode 12, the semiconductor layer may include at least an active layer of a plurality of oxide transistors, the third conductive layer may include at least a third electrode 13, a second scan signal line 52 and a first light emission control line 54, the fourth conductive layer may include at least a fourth electrode 14, a first node electrode 41, a second node electrode 42, a third node electrode 43, a first scan signal line 51, a third scan signal line 53, a second light emission control line 55, a reference signal line 56, an initial signal line 57, a second power connection line 59 and a first power connection line 58, and the fifth conductive layer may include at least a first power line 61 and a data signal line 63.

[0129] The following exemplary description illustrates the fabrication process of the display substrate using this exemplary embodiment. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as depositing a film layer, coating the film layer with photoresist, mask exposure, development, etching, and photoresist stripping; for organic materials, processes include coating the organic material, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching, and this disclosure does not limit the methods. A "thin film" refers to a thin film made by depositing, coating, or other processes onto a substrate using a certain material. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0130] In an exemplary embodiment, the fabrication process of the display substrate may include the following operations.

[0131] (1) Forming a first conductive layer pattern. In an exemplary embodiment, forming a first conductive layer pattern may include: depositing a first conductive thin film on a substrate, patterning the first conductive thin film using a patterning process, and forming a first conductive layer pattern on the substrate, as shown in FIG8. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0132] In an exemplary embodiment, the first conductive layer pattern of each circuit unit in the display substrate may include at least a first electrode 11 and a first electrode connecting block 11-1.

[0133] In an exemplary embodiment, the first electrode plate 11 can be rectangular in shape, and the corners of the rectangle can be chamfered, grooved, or protruded. It can be located in the middle region of the circuit unit, and the first electrode plate 11 can serve as the lower electrode plate (first end of the second capacitor).

[0134] In an exemplary embodiment, the shape of the first electrode plate connecting block 11-1 can be a strip shape extending along the second direction Y, and it can be disposed on one side of the first electrode plate 11 in the second direction Y. The first end of the first electrode plate connecting block 11-1 is connected to the first electrode plate 11, and the second end of the first electrode plate connecting block 11-1 extends in a direction away from the first electrode plate 11. The first electrode plate connecting block 11-1 is configured to be connected to the second power connection line subsequently formed.

[0135] In an exemplary embodiment, in the first direction X, the edges of the first electrode plate 11 and the first electrode plate connecting block 11-1 on the same side can be substantially flush.

[0136] In an exemplary embodiment, in at least one circuit unit, the first electrode plate 11 and the first electrode plate connecting block 11-1 can be an integral structure that is interconnected.

[0137] In an exemplary embodiment, the first conductive layer in the first circuit unit Q1 and the first conductive layer in the second circuit unit Q2 can be arranged in a mirror symmetrical manner with respect to the column center line, and the first conductive layer in the first circuit unit Q1 and the first conductive layer in the second circuit unit Q2 can be substantially the same.

[0138] (2) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: sequentially depositing a first insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; patterning the second conductive film using a patterning process to form a first insulating layer covering the first conductive layer; and a second conductive layer pattern disposed on the first insulating layer, as shown in Figures 9A and 9B, where Figure 9B is a planar schematic diagram of the second conductive layer in Figure 9A. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0139] In an exemplary embodiment, the second conductive layer pattern of each circuit unit in the display substrate may include at least a second electrode 12 and a third bottom gate electrode 37.

[0140] In an exemplary embodiment, the second electrode plate 12 can be rectangular in shape, and the corners of the rectangle can be chamfered, grooved, or protruded. It can be located in the middle region of the circuit unit. The orthographic projection of the second electrode plate 12 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 11 on the substrate. The second electrode plate 12 can simultaneously serve as the upper electrode plate (second end of the second capacitor) of the second capacitor and the lower electrode plate (second end of the first capacitor) of the first capacitor.

[0141] In an exemplary embodiment, the third bottom gate electrode 37 may be a strip shape extending along the second direction Y, and may be disposed on the side of the second electrode plate 12 away from the first electrode plate connecting block 11-1. The third bottom gate electrode 37 is configured as the bottom gate electrode of the third transistor T3.

[0142] In an exemplary embodiment, the second conductive layer in the first circuit unit Q1 and the second conductive layer in the second circuit unit Q2 can be arranged in a mirror symmetrical manner with respect to the column center line, and the second conductive layer in the first circuit unit Q1 and the second conductive layer in the second circuit unit Q2 can be substantially the same.

[0143] (3) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: depositing a second insulating film and a semiconductor film sequentially on a substrate on which the aforementioned pattern is formed, patterning the semiconductor film by a patterning process to form a second insulating layer covering the second conductive layer, and a semiconductor layer pattern disposed on the second insulating layer, as shown in Figures 10A and 10B, where Figure 10B is a planar schematic diagram of the semiconductor layer in Figure 10A.

[0144] In an exemplary embodiment, the semiconductor layer pattern of each circuit unit in the display substrate may include at least the first active layer 21 of the first transistor T1 to the sixth active layer 26 of the sixth transistor T6.

[0145] In an exemplary embodiment, in the first direction X, the first active layer 21 and the fourth active layer 24 can be disposed on one side of the third active layer 23 in the first direction X or on the opposite side of the first direction X, and the first active layer 21 can be disposed on the side of the fourth active layer 24 close to the third active layer 23. In the second direction Y, the first active layer 21, the fourth active layer 24, and the fifth active layer 25 can be disposed on the opposite side of the third active layer 23 in the second direction Y, the second active layer 22 and the sixth active layer 26 can be disposed on one side of the third active layer 23 in the second direction Y, the sixth active layer 26 can be disposed on the side of the second active layer 22 close to the third active layer 23, and the fourth active layer 24 can be disposed on the side of the first active layer 21 close to the third active layer 23.

[0146] In an exemplary embodiment, the first active layer 21, the second active layer 22, the third active layer 23 and the fifth active layer 25 can be strip-shaped extending along the second direction Y, and the fourth active layer 24 and the sixth active layer 26 can be strip-shaped extending along the first direction X.

[0147] In an exemplary embodiment, the third active layer 23 and the fifth active layer 25 can be an integral structure that is interconnected, and the integral structure of the third active layer 23 and the fifth active layer 25 can form a line shape extending along the second direction Y.

[0148] In an exemplary embodiment, the first active layer 21 and the fourth active layer 24 can be an integral structure that is interconnected, and the integral structure of the first active layer 21 and the fourth active layer 24 can form an "L" shape.

[0149] In an exemplary embodiment, the second active layer 22 and the sixth active layer 26 can be an integral structure that is interconnected, and the integral structure of the second active layer 22 and the sixth active layer 26 can form an inverted "L" shape.

[0150] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the second region 21-2 of the first active layer and the second region 24-2 of the fourth active layer may be interconnected, with the second region 21-2 of the first active layer serving as the second region 24-2 of the fourth active layer. The second region 22-2 of the second active layer and the second region 26-2 of the sixth active layer may be interconnected, with the second region 22-2 of the second active layer serving as the second region 26-2 of the sixth active layer. The first region 23-1 of the third active layer and the second region 25-2 of the fifth active layer may be interconnected, with the first region 23-1 of the third active layer serving as the second region 25-2 of the fifth active layer. The first regions 21-1 of the first active layer, 22-1 of the second active layer, 23-2 of the third active layer, 24-1 of the fourth active layer, 25-1 of the fifth active layer, and 26-1 of the sixth active layer may be individually configured.

[0151] In an exemplary embodiment, the semiconductor layer in the first circuit unit Q1 and the semiconductor layer in the second circuit unit Q2 can be arranged in a mirror-symmetric manner with respect to the column center line, and the semiconductor layer in the first circuit unit Q1 and the semiconductor layer in the second circuit unit Q2 can be substantially the same.

[0152] In an exemplary embodiment, the semiconductor layer may be an oxide layer, and the first transistor T1 to the sixth transistor T6 are all oxide transistors. In an exemplary embodiment, the semiconductor thin film may be indium gallium zinc oxide (IGZO), which has a high electron mobility.

[0153] (4) Forming a third conductive layer pattern. In an exemplary embodiment, forming a third conductive layer pattern may include: sequentially depositing a third insulating film and a third conductive film on a substrate on which the aforementioned pattern is formed; patterning the third insulating film and the third conductive film using a patterning process to form a third insulating layer disposed on a semiconductor layer, and a third conductive layer pattern disposed on the third insulating layer, as shown in Figures 11A and 11B, where Figure 11B is a planar schematic diagram of the third conductive layer in Figure 11A. In an exemplary embodiment, the third conductive layer may be referred to as a third gate metal (GATE3) layer.

[0154] In an exemplary embodiment, the third conductive layer pattern of each circuit unit in the display substrate includes at least: a third electrode plate 13, a third electrode plate connecting block 13-1, a first gate electrode 31, a fourth gate electrode 34, a sixth gate electrode 36, a second scan signal line 52, and a first light emission control line 54.

[0155] In an exemplary embodiment, the third electrode plate 13 can be rectangular in shape, and the corners of the rectangle can be chamfered, grooved, or protruded. The orthographic projection of the third electrode plate 13 on the substrate at least partially overlaps with the orthographic projections of the second electrode plate 12 and the third active layer 23 on the substrate. The third electrode plate 13 can simultaneously serve as the intermediate electrode plate (first end of the first capacitor) of the first capacitor and the top gate electrode of the third transistor T3. That is, the top gate electrode of the third transistor T3 and the third electrode plate 13 can be an integral structure that is interconnected.

[0156] In an exemplary embodiment, the third electrode plate connecting block 13-1 can be block-shaped (such as rectangular) and can be disposed on the side of the third electrode plate 13 near the fourth active layer 24. The first end of the third electrode plate connecting block 13-1 is connected to the third electrode plate 13, and the second end of the third electrode plate connecting block 13-1 extends toward the fourth active layer 24. The orthographic projection of the second end of the third electrode plate connecting block 13-1 on the substrate at least partially overlaps with the orthographic projection of the fourth active layer 24 on the substrate. The third electrode plate connecting block 13-1 is configured to be connected to the subsequently formed first node electrode.

[0157] In an exemplary embodiment, in at least one circuit unit, the third electrode plate 13 and the third electrode plate connecting block 13-1 can be an integral structure that is interconnected.

[0158] In an exemplary embodiment, an opening 13-2 may be provided on the third electrode plate 13. The shape of the opening 13-2 may be block-shaped (such as rectangular). On the one hand, the orthographic projection of the opening 13-2 on the substrate at least partially overlaps with the orthographic projection of the second region 23-2 of the third active layer on the substrate. On the other hand, the orthographic projection of the opening 13-2 on the substrate at least partially overlaps with the orthographic projection of the third bottom gate electrode 37 on the substrate. The opening 13-2 is configured to accommodate a subsequently formed fifth via. The fifth via is located within the opening 13-2 and exposes the second region of the third active layer and the third bottom gate electrode 37, so that the subsequently formed third node electrode is simultaneously connected to the second region of the third active layer and the third bottom gate electrode 37 through the fifth via.

[0159] In an exemplary embodiment, the first gate electrode 31 may be block-shaped (such as rectangular) and may be disposed on the side opposite to the second direction Y of the third electrode plate 13. The orthogonal projection of the first gate electrode 31 on the substrate at least partially overlaps with the orthogonal projection of the first active layer 21 on the substrate. The first gate electrode 31 may serve as the gate electrode of the first transistor T1.

[0160] In an exemplary embodiment, the fourth gate electrode 34 may be block-shaped (such as rectangular) and may be disposed between the third electrode plate 13 and the first gate electrode 3. The orthographic projection of the fourth gate electrode 34 on the substrate at least partially overlaps with the orthographic projection of the fourth active layer 24 on the substrate. The fourth gate electrode 34 may serve as the gate electrode of the fourth transistor T4.

[0161] In an exemplary embodiment, the sixth gate electrode 36 may be block-shaped (such as rectangular) and may be disposed on one side of the third electrode plate 13 in the second direction Y. The orthographic projection of the sixth gate electrode 36 on the substrate and the orthographic projection of the sixth active layer 26 on the substrate at least partially overlap. The sixth gate electrode 36 may serve as the gate electrode of the sixth transistor T6.

[0162] In an exemplary embodiment, the shape of the second scan signal line 52 can be a straight line or a broken line extending along the first direction X. It can be disposed on the side of the sixth gate electrode 36 away from the third electrode plate 13. The area where the second scan signal line 52 overlaps with the second active layer 22 serves as the gate electrode of the second transistor T2. The second scan signal line 52 can control the conduction or disconnection of the second transistor T2.

[0163] In an exemplary embodiment, the shape of the first light-emitting control line 54 can be a straight line or a broken line extending along the first direction X. It can be disposed on the side of the first gate electrode 31 away from the third plate 13. The area where the first light-emitting control line 54 overlaps with the fifth active layer 25 serves as the gate electrode of the fifth transistor T5. The first light-emitting control line 54 can control the conduction or disconnection of the fifth transistor T5.

[0164] In an exemplary embodiment, the third conductive layer in the first circuit unit Q1 and the third conductive layer in the second circuit unit Q2 can be arranged in a mirror symmetrical manner with respect to the column center line, and the third conductive layer in the first circuit unit Q1 and the third conductive layer in the second circuit unit Q2 can be substantially the same.

[0165] In an exemplary embodiment, the patterns of the third insulating layer and the third conductive layer can be substantially the same in this patterning process. Thus, the semiconductor layer that is shielded by the third conductive layer forms the channel region of the first transistor T1 to the sixth transistor T6, and the semiconductor layer that is not shielded by the third conductive layer is conductive, that is, the first region and the second region of the first active layer to the sixth active layer are both conductive.

[0166] (5) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming a fourth insulating layer pattern may include: depositing a fourth insulating film on a substrate on which the aforementioned pattern is formed, and patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the third conductive layer, wherein a plurality of vias are provided on the fourth insulating layer, as shown in FIG12.

[0167] In an exemplary embodiment, the plurality of vias of each circuit unit in the display substrate include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, and a thirteenth via V13.

[0168] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate is within the range of the orthographic projection of the first region of the first active layer onto the substrate. The fourth insulating layer within the first via V1 is etched away, exposing the surface of the first region of the first active layer. The first via V1 is configured to allow a subsequently formed reference signal line to be connected to the first region of the first active layer through the via.

[0169] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate lies within the range of the orthographic projections of the second region of the first active layer and the third electrode connecting block 13-1 onto the substrate. The second via V2 is a transition via, including a deep half-hole and a shallow half-hole. The fourth insulating layer in the deep half-hole is etched away, exposing the surface of the second region of the first active layer (which is also the second region of the fourth active layer). The fourth insulating layer in the shallow half-hole is etched away, exposing the surface of the third electrode connecting block 13-1. The second via V2 is configured to allow the subsequently formed first node electrode to be simultaneously connected to the second region of the first active layer and the third electrode connecting block 13-1 through this via.

[0170] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate is within the range of the orthographic projection of the first region of the second active layer onto the substrate. The fourth insulating layer within the third via V3 is etched away, exposing the surface of the first region of the second active layer. The third via V3 is configured to allow the subsequently formed initial signal line to be connected to the first region of the second active layer through the via.

[0171] In an exemplary embodiment, the orthographic projection of the fourth via V4 onto the substrate is located within the range of the orthographic projection of the second region of the second active layer (which is also the second region of the sixth active layer) onto the substrate. The fourth insulating layer within the fourth via V4 is etched away, exposing the surface of the second region of the second active layer (which is also the second region of the sixth active layer). The fourth via V4 is configured to allow the subsequently formed third node electrode to be connected to the second region of the second active layer (which is also the second region of the sixth active layer) through the via.

[0172] In an exemplary embodiment, the orthographic projection of the fifth via V5 onto the substrate lies within the range of the second region of the third active layer and the orthographic projection of the third bottom gate electrode 37 onto the substrate. The fifth via V5 is a transition via, comprising a deep half-hole and a shallow half-hole. The fourth and second insulating layers within the deep half-hole are etched away, exposing the surface of the third bottom gate electrode 37. The fourth insulating layer within the shallow half-hole is etched away, exposing the surface of the second region of the third active layer. The fifth via V5 is configured to allow the subsequently formed third node electrode to be simultaneously connected to the second region of the third active layer and the third bottom gate electrode 37 through this via.

[0173] In an exemplary embodiment, the orthographic projection of the sixth via V6 onto the substrate is within the range of the orthographic projection of the first region of the fourth active layer onto the substrate. The fourth insulating layer within the sixth via V6 is etched away, exposing the surface of the first region of the fourth active layer. The sixth via V6 is configured to allow subsequently formed data connection electrodes to be connected to the first region of the fourth active layer through the via.

[0174] In an exemplary embodiment, the orthographic projection of the seventh via V7 onto the substrate is within the range of the orthographic projection of the first region of the fifth active layer onto the substrate. The fourth insulating layer within the seventh via V7 is etched away, exposing the surface of the first region of the fifth active layer. The seventh via V7 is configured to allow a subsequently formed first power line to be connected to the first region of the fifth active layer through the via.

[0175] In an exemplary embodiment, the orthographic projection of the eighth via V8 onto the substrate is within the range of the orthographic projection of the first region of the sixth active layer onto the substrate. The fourth insulating layer within the eighth via V8 is etched away, exposing the surface of the first region of the sixth active layer. The eighth via V8 is configured to allow the subsequently formed second node electrode to be connected to the first region of the sixth active layer through the via.

[0176] In an exemplary embodiment, the orthogonal projection of the ninth via V9 on the substrate is within the range of the orthogonal projection of the first gate electrode 31 on the substrate. The fourth insulating layer in the ninth via V9 is etched away, exposing the surface of the first gate electrode 31. The ninth via V9 is configured to allow the subsequently formed first scan signal line to be connected to the first gate electrode 31 through the via.

[0177] In an exemplary embodiment, the orthogonal projection of the tenth via V10 onto the substrate is within the range of the orthogonal projection of the fourth gate electrode 34 onto the substrate. The fourth insulating layer within the tenth via V10 is etched away, exposing the surface of the fourth gate electrode 34. The tenth via V10 is configured to allow the subsequently formed third scan signal line to be connected to the fourth gate electrode 34 through the via.

[0178] In an exemplary embodiment, the orthographic projection of the eleventh via V11 onto the substrate is within the range of the orthographic projection of the sixth gate electrode 36 onto the substrate. The fourth insulating layer within the eleventh via V11 is etched away, exposing the surface of the sixth gate electrode 36. The eleventh via V11 is configured to allow the subsequently formed second light-emitting control line to be connected to the sixth gate electrode 36 through the via.

[0179] In an exemplary embodiment, the orthographic projection of the twelfth via V12 on the substrate is within the range of the orthographic projection of the second electrode plate 12 on the substrate. The fourth insulating layer and the second insulating layer in the twelfth via V12 are etched away, exposing the surface of the second electrode plate 12. The twelfth via V12 is configured to allow the subsequently formed fourth electrode plate to be connected to the second electrode plate 12 through the via.

[0180] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 on the substrate is within the range of the orthographic projection of the first electrode plate connecting block 11-1 on the substrate. The fourth insulating layer, the second insulating layer, and the first insulating layer within the thirteenth via V13 are etched away, exposing the surface of the first electrode plate connecting block 11-1. The thirteenth via V13 is configured to allow the subsequently formed capacitor power line to be connected to the first electrode plate connecting block 11-1 through the via.

[0181] (6) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the fourth conductive thin film using a patterning process to form a fourth conductive layer disposed on the fourth insulating layer, as shown in Figures 13A and 13B, where Figure 13B is a planar schematic diagram of the fourth conductive layer in Figure 13A. In an exemplary embodiment, the fourth conductive layer may be referred to as the first source / drain metal (SD1) layer.

[0182] In an exemplary embodiment, the fourth conductive layer of each circuit unit in the display substrate includes at least: a fourth electrode plate 14, a first node electrode 41, a second node electrode 42, a third node electrode 43, a data connection electrode 44, a first scan signal line 51, a third scan signal line 53, a second light emission control line 55, a reference signal line 56, an initial signal line 57, a first power connection line 58, and a second power connection line 59.

[0183] In an exemplary embodiment, the fourth electrode plate 14 can be rectangular in shape, and the corners of the rectangle can be chamfered, grooved, or protruded. The orthographic projection of the fourth electrode plate 14 on the substrate at least partially overlaps with the orthographic projection of the third electrode plate 13 on the substrate, and the fourth electrode plate 14 is connected to the second electrode plate 12 through the twelfth through hole V12. Therefore, the second electrode plate 12 and the fourth electrode plate 14 have the same potential, and the fourth electrode plate 14 can serve as the upper electrode plate (the second end of the first capacitor).

[0184] In an exemplary embodiment, the shape of the first scan signal line 51 can be a straight line or a broken line extending along the first direction X. It can be disposed between the fourth electrode plate 14 and the first light emission control line 54. The first scan signal line 51 is connected to the first gate electrode 31 through the ninth via V9, thus realizing the connection between the first scan signal line 51 and the gate electrode of the first transistor T1. The first scan signal line 51 can control the conduction or disconnection of the first transistor T1.

[0185] In an exemplary embodiment, the third scan signal line 53 can be a straight line or a broken line extending along the first direction X, and can be disposed between the fourth electrode plate 14 and the first scan signal line 51. A third scan connection block 53-1 can be disposed on the third scan signal line 53. The shape of the third scan connection block 53-1 can be block-shaped (such as rectangular), and can be disposed on the side of the third scan signal line 53 near the fourth electrode plate 14. The first end of the third scan connection block 53-1 is connected to the third scan signal line 53, and the second end of the third scan connection block 53-1 extends towards the fourth electrode plate 14 and is connected to the fourth gate electrode 34 through the tenth via V10. Thus, the connection between the third scan signal line 53 and the gate electrode of the fourth transistor T4 is realized, and the third scan signal line 53 can control the conduction or disconnection of the fourth transistor T4.

[0186] In an exemplary embodiment, the second light-emitting control line 55 can be a straight line or a broken line extending along the first direction X, and can be disposed between the fourth electrode plate 14 and the second scan signal line 52. A second light-emitting connecting block 55-1 can be disposed on the second light-emitting control line 55. The shape of the second light-emitting connecting block 55-1 can be block-shaped (such as rectangular), and can be disposed on the side of the second light-emitting control line 55 near the fourth electrode plate 14. The first end of the second light-emitting connecting block 55-1 is connected to the second light-emitting control line 55, and the second end of the second light-emitting connecting block 55-1 extends towards the fourth electrode plate 14 and is connected to the sixth gate electrode 36 through the eleventh via V11. Thus, the connection between the second light-emitting control line 55 and the gate electrode of the sixth transistor T6 is realized, and the second light-emitting control line 55 can control the conduction or disconnection of the sixth transistor T6.

[0187] In an exemplary embodiment, the reference signal line 56 can be a straight line or a broken line extending along the first direction X. It can be disposed on the side of the first light-emitting control line 54 near the fourth electrode plate 14. The reference signal line 56 is connected to the first region of the first active layer through the first via V1, thereby enabling the reference signal line 56 to write the reference signal into the first electrode of the first transistor T1.

[0188] In an exemplary embodiment, the initial signal line 57 can be a straight line or a broken line extending along the first direction X. It can be located on the side of the second scan signal line 52 away from the fourth electrode plate 14. The initial signal line 57 is connected to the first region of the second active layer through the third via V3, thus enabling the initial signal line 57 to write the initial signal into the first electrode of the second transistor T2.

[0189] In an exemplary embodiment, the first power connection line 58 can be a straight line or a broken line extending along the first direction X, and can be located on the side of the first light-emitting control line 54 away from the fourth electrode plate 14. The first power connection line 58 is connected to the first region of the fifth active layer through the seventh via V7. Since the first power connection line 58 is connected to the subsequently formed first power line, the first power line writes the first power signal into the first electrode of the fifth transistor T5.

[0190] In an exemplary embodiment, the second power connection line 59 can be a straight line or a broken line extending along the first direction X, and can be disposed between the second scan signal line 52 and the second light emission control line 55. The second power connection line 59 is connected to the first electrode plate connection block 11-1 through the thirteenth via V13. Since the first electrode plate connection block 11-1 is connected to the first electrode plate 11, and the second power connection line 59 is connected to the subsequently formed second power line, the second power line writes the second power signal into the first electrode plate 11, and the first electrode plate 11 has the second power signal potential.

[0191] In an exemplary embodiment, the second power line can be used as the capacitor power line of this disclosure, that is, the capacitor power signal in this embodiment is the second power signal.

[0192] In an exemplary embodiment, a first electrode 11 located in the first conductive layer and having a second power signal potential, and a second electrode 12 located in the second conductive layer and having a second node potential, form a second capacitor C2 of the pixel driving circuit.

[0193] In an exemplary embodiment, the first node electrode 41 can be block-shaped (e.g., rectangular) and can be disposed between the fourth electrode plate 14 and the third scan signal line 53. The first node electrode 41 is connected to both the second region of the first active layer and the third electrode plate connecting block 13-1 through the second via V2. Since the second region of the first active layer can serve as the second region of the fourth active layer, and the third electrode plate connecting block 13-1 is connected to the third electrode plate 13, and the third electrode plate 13 also serves as the top gate electrode of the third transistor T3, the first node electrode 41 achieves the interconnection between the second electrode of the first transistor T1, the bottom gate electrode of the third transistor T3, the first electrode of the fourth transistor T4, and the third electrode plate 13 (the middle electrode plate of the first capacitor), forming the first node N1 of the pixel driving circuit. The first node electrode 41 and the third electrode plate 13 have a first node potential.

[0194] In an exemplary embodiment, in the second direction Y, a first scan signal line 51, a third scan signal line 53, and a reference signal line 56 are respectively provided between the first node electrode 41 and the first light emission control line 54. Not only is the distance between the two relatively large, but the reference signal line 56 with a constant potential can effectively reduce the influence of the first light emission control line 54 on the first node N1, improve the potential stability of key nodes in the pixel driving circuit, and improve the display effect and display quality.

[0195] In an exemplary embodiment, the second node electrode 42 can be a strip extending along the second direction Y, and can be disposed between the fourth electrode plate 14 and the second light-emitting control line 55. The first end of the second node electrode 42 is connected to the fourth electrode plate 14, and the second end of the second node electrode 42 extends towards the point close to the second light-emitting control line 55 and is connected to the first region of the sixth active layer through the eighth via V8. Since the fourth electrode plate 14 is connected to the second electrode plate 12, the second node electrode 42 realizes the interconnection between the first electrode of the sixth transistor T6, the second electrode plate 12 (the lower electrode plate of the first capacitor), and the fourth electrode plate 14 (the upper electrode plate of the first capacitor), forming the second node N2 of the pixel driving circuit. The second node electrode 42, the second electrode plate 12, and the fourth electrode plate 14 have a second node potential.

[0196] In an exemplary embodiment, the first capacitor C1 is a sandwich-layer capacitor. A second electrode 12 located in the second conductive layer and having a second node potential, and a third electrode 13 located in the third conductive layer and having a first node potential, form a first sub-capacitor. A third electrode 13 located in the third conductive layer and having a first node potential, and a fourth electrode 14 located in the fourth conductive layer and having a second node potential, form a second sub-capacitor. The first and second sub-capacitors connected in parallel form the first capacitor C1 of the pixel driving circuit. In an exemplary embodiment, the capacitance value of the first capacitor C1 is the sum of the capacitance values ​​of the first and second sub-capacitors.

[0197] In an exemplary embodiment, the ratio of the capacitance value of the first capacitor C1 to the capacitance value of the second capacitor C2 can be approximately 0.95 to 1.05.

[0198] In an exemplary embodiment, the capacitance values ​​of the first capacitor C1 and the second capacitor C2 can be substantially equal, which not only saves layout space but also effectively adjusts the data range. Simulation experiments show that the data range is minimized when the ratio of the capacitance value of the first capacitor C1 to the capacitance value of the second capacitor C2 is 1:1.

[0199] In an exemplary embodiment, in order to make the capacitance values ​​of the first capacitor C1 and the second capacitor C2 substantially equal, this can be achieved by increasing the overlapping area of ​​the first electrode plate 11 and the second electrode plate 12, and decreasing the overlapping area of ​​the third electrode plate 13 and the fourth electrode plate 14.

[0200] In an exemplary embodiment, the third node electrode 43 can be a strip extending along the second direction Y, and can be disposed on one side of the fourth electrode plate 14 in the first direction X or on the opposite side of the first direction X. The third node electrode 43 is connected to the second region of the second active layer (which is also the second region of the sixth active layer) through the fourth via V4, and simultaneously connected to the second region of the third active layer and the third bottom gate electrode 37 through the fifth via V5. The third node electrode 43 realizes the interconnection between the second electrode of the second transistor T2, the second electrode of the third transistor T3, the second electrode of the sixth transistor T6, and the top gate electrode of the third transistor T3, forming the third node N3 of the pixel driving circuit. The third node electrode 43 has a third node potential. In an exemplary embodiment, the third node electrode 43 is configured to be connected to the subsequently formed anode connection electrode.

[0201] In an exemplary embodiment, the data connection electrode 44 may be a strip shape extending along the first direction X, and may be disposed on the side of the third scan signal line 53 near the fourth electrode plate 14. The first end of the data connection electrode 44 is connected to the first region of the fourth active layer through the sixth via V6, and the second end of the data connection electrode 44 extends in a direction away from the first node electrode 41. The second end of the data connection electrode 44 is configured to be connected to the subsequently formed data signal line.

[0202] In an exemplary embodiment, the fourth conductive layer in the first circuit unit Q1 and the fourth conductive layer in the second circuit unit Q2 can be arranged in a mirror-symmetrical manner with respect to the column center line, and the fourth conductive layer in the first circuit unit Q1 and the fourth conductive layer in the second circuit unit Q2 can be substantially the same.

[0203] (7) Forming a first planarization layer pattern. In an exemplary embodiment, forming a first planarization layer pattern may include: coating a first planarization film on a substrate on which the aforementioned pattern is formed, and patterning the first planarization film using a patterning process to form a first planarization layer covering the fourth conductive layer pattern, wherein a plurality of vias are provided on the first planarization layer, as shown in FIG14.

[0204] In an exemplary embodiment, the plurality of vias in each circuit unit of the display substrate includes at least: a twenty-first via V21, a twenty-second via V22, and a twenty-third via V23.

[0205] In an exemplary embodiment, the orthographic projection of the 21st via V21 on the substrate is within the range of the orthographic projection of the second power connection line 59 on the substrate. The first planarization layer within the 21st via V21 is etched away, exposing the surface of the second power connection line 59. The 21st via V21 is configured to allow a subsequently formed second power line to be connected to the second power connection line 59 through the via.

[0206] In an exemplary embodiment, the orthographic projection of the 22nd via V22 on the substrate is within the range of the orthographic projection of the data connection electrode 44 on the substrate. The first planarization layer within the 22nd via V22 is etched away, exposing the surface of the data connection electrode 44. The 22nd via V22 is configured to allow subsequently formed data signal lines to be connected to the data connection electrode 44 through the via.

[0207] In an exemplary embodiment, the orthographic projection of the 23rd via V23 on the substrate is within the range of the orthographic projection of the third node electrode 43 on the substrate. The first planarization layer within the 23rd via V23 is etched away, exposing the surface of the third node electrode 43. The 23rd via V23 is configured to allow the subsequently formed anode connection electrode to be connected to the third node electrode 43 through the via.

[0208] In an exemplary embodiment, the plurality of vias may further include: a twenty-fourth via V24, a twenty-fifth via V25, and a twenty-sixth via V26.

[0209] In an exemplary embodiment, the orthographic projection of the 24th via V24 onto the substrate may be located within the range of the orthographic projection of the first power connection line 58 in a portion of the circuit unit onto the substrate. The first planarization layer within the 24th via V24 is etched away, exposing the surface of the first power connection line 58. The 24th via V24 is configured to allow a subsequently formed first power line to be connected to the first power connection line 58 through the via.

[0210] In an exemplary embodiment, the twenty-fourth via V24 may be disposed in the third circuit unit Q3.

[0211] In an exemplary embodiment, the orthographic projection of the 25th via V25 onto the substrate may be within the range of the orthographic projection of the reference signal line 56 in a portion of the circuit unit onto the substrate. The first planarization layer within the 25th via V25 is etched away, exposing the surface of the reference signal line 56. The 25th via V25 is configured to allow subsequently formed reference connection lines to be connected to the reference signal line 56 through the via.

[0212] In an exemplary embodiment, the twenty-fifth via V25 may be disposed between the second circuit unit Q2 and the third circuit unit Q3.

[0213] In an exemplary embodiment, the orthographic projection of the 26th via V26 onto the substrate may be within the range of the orthographic projection of the initial signal line 57 in a portion of the circuit unit onto the substrate. The first planarization layer within the 26th via V26 is etched away, exposing the surface of the initial signal line 57. The 26th via V26 is configured to allow subsequently formed initial connection lines to be connected to the initial signal line 57 through the via.

[0214] In an exemplary embodiment, the twenty-sixth via V26 may be disposed between the first circuit unit Q1 and the second circuit unit Q2.

[0215] (8) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth conductive film on the substrate on which the aforementioned pattern is formed, and patterning the fifth conductive film using a patterning process to form a fifth conductive layer disposed on the first planarization layer, as shown in Figures 15A and 15B, where Figure 15B is a planar schematic diagram of the fourth conductive layer in Figure 15A. In an exemplary embodiment, the fifth conductive layer may be referred to as the second source / drain metal (SD2) layer.

[0216] In an exemplary embodiment, the fifth conductive layer of each circuit unit includes at least: a second power line 62, a data signal line 63, and an anode connection electrode 64.

[0217] In an exemplary embodiment, the shape of the second power line 62 can be a straight line or a broken line extending along the second direction Y of the main body. It can be disposed on the side of the fourth electrode plate 14 away from the third node electrode 43. The second power line 62 is connected to the second power connection line 59 through the twenty-first via V21. Thus, the second power connection line 59 extending along the first direction X and the second power line 62 extending along the second direction Y form a network connection structure for transmitting the second power signal. This can not only effectively reduce the resistance of the second power line and reduce the voltage drop of the second power signal, but also effectively improve the uniformity of the second power signal in the display substrate, effectively improve display uniformity, and improve display quality.

[0218] In an exemplary embodiment, the second power line 62 can be provided in each circuit unit, that is, the second power line 62 is a one-to-one structure, which can further reduce the resistance of the second power line and further reduce the voltage drop of the second power signal.

[0219] In an exemplary embodiment, the data signal line 63 can be a straight line extending along the second direction Y, and can be located on the side of the second power line 62 away from the fourth electrode plate 14. The data signal line 63 is connected to the data connection electrode 44 through the twenty-second via V22. Since the data connection electrode 44 is connected to the first region of the fourth active layer through the via, the data signal line 63 can write data signals to the first electrode of the fourth transistor T4.

[0220] In an exemplary embodiment, the anode connection electrode 64 can be block-shaped (e.g., rectangular). The anode connection electrode 64 is connected to the third node electrode 43 through the twenty-third via V23, and the anode connection electrode 64 is configured to be connected to the subsequently formed anode. Since the third node electrode 43 has a second node potential, the pixel driving circuit can output driving current to the light-emitting device.

[0221] In an exemplary embodiment, the second power line 62, data signal line 63, and anode connection electrode 64 in the first circuit unit Q1 and the second circuit unit Q2 can be arranged in a mirror-symmetrical manner with respect to the column center line, and the second power line 62, data signal line 63, and anode connection electrode 64 in the first circuit unit Q1 and the second circuit unit Q2 can be substantially the same.

[0222] In an exemplary embodiment, the fifth conductive layer may further include a first power line 61, a reference connection line 65, and an initial connection line 66.

[0223] In an exemplary embodiment, the shape of the first power line 61 can be a straight line or a broken line extending along the second direction Y of the main body. It can be disposed on the side of the third node electrode 43 in a part of the circuit unit away from the fourth electrode plate 14. The first power line 61 can be connected to the first power connection line 58 through the twenty-fourth via V24. Thus, the first power connection line 58 extending along the first direction X and the first power line 61 extending along the second direction Y form a network connection structure for transmitting the first power signal. This can not only effectively reduce the resistance of the first power line and reduce the voltage drop of the first power signal, but also effectively improve the uniformity of the first power signal in the display substrate, effectively improve the display uniformity, and improve the display quality.

[0224] In an exemplary embodiment, the first power line 61 can be set in the third circuit unit Q3, that is, the first power line 61 is a one-to-three structure, which can effectively reduce the number of signal lines, effectively reduce the area of ​​the circuit unit, and help improve the resolution.

[0225] In an exemplary embodiment, the reference connection line 65 can be a straight line or a broken line extending along the second direction Y of the main body. It can be disposed on the side of the data signal line 63 away from the fourth electrode plate 14 in a part of the circuit unit. The reference connection line 65 can be connected to the reference signal line 56 through the twenty-fifth via V25. Thus, the reference signal line 56 extending along the first direction X and the reference connection line 65 extending along the second direction Y form a network connection structure for transmitting reference signals. This can not only effectively reduce the resistance of the reference signal line and reduce the voltage drop of the reference signal, but also effectively improve the uniformity of the reference signal in the display substrate, effectively improve the display uniformity, and improve the display quality.

[0226] In an exemplary embodiment, the reference connection line 65 can be disposed between the data signal line 63 of the second circuit unit Q2 and the data signal line 63 of the third circuit unit Q3. That is, the reference connection line 65 is a one-to-three structure, which can effectively reduce the number of signal lines, effectively reduce the area of ​​the circuit unit, and help improve the resolution.

[0227] In an exemplary embodiment, the initial connection line 66 can be a straight line or a broken line extending along the second direction Y of the main body. It can be disposed on the side of the third node electrode 43 in a part of the circuit unit away from the fourth electrode plate 14. The initial connection line 66 can be connected to the initial signal line 57 through the twenty-sixth via V26. Thus, the initial signal line 57 extending along the first direction X and the initial connection line 66 extending along the second direction Y form a network connection structure for transmitting the initial signal. This can not only effectively reduce the resistance of the initial signal line and reduce the voltage drop of the initial signal, but also effectively improve the uniformity of the initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality.

[0228] In an exemplary embodiment, the initial connection line 66 can be disposed between the third node electrode 43 of the first circuit unit Q1 and the third node electrode 43 of the second circuit unit Q2. That is, the initial connection line 66 is a one-to-three structure, which can effectively reduce the number of signal lines, effectively reduce the area of ​​the circuit unit, and help improve the resolution.

[0229] In some possible implementations, the first power line 61, the reference connection line 65, or the initial connection line 66 can be a one-to-six structure, or a portion of the first power line 61, the reference connection line 65, and the initial connection line 66 can be a one-to-three structure, and another portion can be a one-to-six structure. This disclosure does not limit the scope of the implementation.

[0230] In some other possible implementations, at least one of the reference signal line 56, the initial signal line 57, the first power connection line 58, and the second power connection line 59 may be disposed in the first conductive layer, the second conductive layer, or the third conductive layer. Alternatively, at least one of the reference signal line 56, the initial signal line 57, the first power connection line 58, and the second power connection line 59 may be disposed in two or more conductive layers to further reduce the voltage drop. This disclosure does not limit the scope of the implementation.

[0231] In an exemplary embodiment, in the first direction X, the data signal line 63 and the first node electrode 41 are respectively disposed on both sides of the second power line 62. The second power line 62, which has a constant potential, can effectively shield the mutual influence between the data signal line 63 and the first node electrode 41, reduce the impact of data jump voltage on the first node N1, improve the potential stability of key nodes of the pixel driving circuit, and improve the display effect and display quality.

[0232] In an exemplary embodiment, in the first direction X, the data signal line 63 and the second node electrode 42 are respectively disposed on both sides of the second power line 62. The second power line 62 with a constant potential can effectively shield the mutual influence between the data signal line 63 and the second node electrode 42, reduce the influence of data jump voltage on the second node N2, improve the potential stability of key nodes of the pixel driving circuit, and improve the display effect and display quality.

[0233] In an exemplary embodiment, since a first electrode connecting block 11-1 is also provided between the data signal line 63 and the second node electrode 42, the first electrode connecting block 11-1 with a constant potential can further shield the mutual influence between the data signal line 63 and the second node electrode 42, further reduce the influence of data jump voltage on the second node N2, improve the potential stability of key nodes of the pixel driving circuit, and improve the display effect and display quality.

[0234] In an exemplary embodiment, since the data signal lines 63 in the first circuit unit Q1 and the data signal lines 63 in the second circuit unit Q2 are symmetrically arranged and located outside the circuit unit, the distance between the data signal lines 63 in the first circuit unit Q1 and the data signal lines 63 in the second circuit unit Q2 is large. This can reduce the mutual influence between the data signal lines 63 in adjacent circuit units, reduce the impact of data switching voltage on key nodes of the pixel driving circuit, and improve the display effect and display quality.

[0235] In an exemplary embodiment, since a reference connection line 65 is provided between the data signal line 63 of the second circuit unit Q2 and the data signal line 63 of the third circuit unit Q3, the reference connection line 65 with a constant potential can reduce the mutual influence between the data signal lines 63 in adjacent circuit units, reduce the impact of data jump voltage on key nodes of the pixel driving circuit, and improve the display effect and display quality.

[0236] In an exemplary embodiment, the orthographic projections of the first power line 61, the second power line 62, the data signal line 63, the reference connection line 65, and the initial connection line 66 on the substrate do not overlap with the orthographic projections of the first node electrode 41, the second node electrode 42, and the third node electrode 43 on the substrate. This can effectively reduce the parasitic capacitance of the first node N1, the second node N2, and the third node N3, reduce the impact of the signal lines on key nodes of the pixel driving circuit, and improve the display effect and display quality.

[0237] Subsequently, a second planar thin film is coated on the substrate on which the aforementioned pattern is formed. The second planar thin film is patterned using a patterning process to form a second planar layer covering the pattern of the fifth conductive layer. An anode via is provided on the second planar layer. The orthogonal projection of the anode via on the substrate is located within the range of the orthogonal projection of the anode connection electrode on the substrate. The anode via is configured to allow the anode to be formed subsequently to be connected to the anode connection electrode through the via.

[0238] At this point, the driving structure layer is fabricated on the substrate. In a plane parallel to the display substrate, the driving structure layer may include multiple circuit units. Each circuit unit may include a pixel driving circuit, as well as a first scan signal line, a second scan signal line, a third scan signal line, a first light emission control line, a second light emission control line, a reference signal line, an initial signal line, a first power supply line, and a data signal line connected to the pixel driving circuit.

[0239] In a plane perpendicular to the display substrate, the driving structure layer may include a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, a semiconductor layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fourth conductive layer, a first planarization layer, a fifth conductive layer, and a second planarization layer, sequentially disposed on the substrate. The first conductive layer may include at least a first electrode plate, the second conductive layer may include at least a second electrode plate, the semiconductor layer may include at least the active layers of the first to sixth transistors, the third conductive layer may include at least a third electrode plate, the fourth conductive layer may include at least a fourth electrode plate and multiple node electrodes, and the fifth conductive layer may include at least a first power line, a second power line, and a data signal line.

[0240] In an exemplary embodiment, the substrate can be a flexible substrate or a rigid substrate. The rigid substrate can be, but is not limited to, one or more of glass and quartz. The flexible substrate can be, but is not limited to, polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on a glass substrate. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc. The materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also called barrier layers. The material of the semiconductor layer can be amorphous silicon (a-Si).

[0241] In an exemplary embodiment, the first, second, third, and fourth insulating layers can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. The first, second, third, fourth, and fifth conductive layers can be made of metallic materials, such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), or molybdenum (Mo), or can be made of alloy materials composed of metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti. The first and second planarization layers can be made of organic materials, such as resin or polyimide.

[0242] In an exemplary embodiment, after the driving structure layer is fabricated, a light-emitting structure layer can be fabricated on the driving structure layer, and an encapsulation structure layer can be fabricated on the light-emitting structure layer, which will not be described in detail here.

[0243] With the development of display technology, consumers have increasingly higher requirements for the display effect and display quality of display products. In display substrates using oxide transistors (OTTs), OTTs have lower off-state currents, are less prone to leakage, perform well in the low-frequency range, and have relatively simpler manufacturing processes and lower costs. However, OTT display substrates suffer from problems such as the mutual interference between threshold compensation and data writing. Research has found that the source electrode of the oxide driving transistor is the third node N3. During the threshold compensation stage, the threshold voltage is compensated at the third node N3. During the data writing stage, the potentials of the first node N1 and the third node N3 interact due to coupling, thus affecting the gate-source voltage of the third transistor T3 (the driving transistor) (i.e., the difference between the potentials of the first node N1 and the third node N3).

[0244] An exemplary embodiment of this disclosure provides a display substrate in which a sixth transistor T6, serving as an isolation transistor, is disposed between a first node N1 and a third node N3. The sixth transistor T6 is turned on during the reset phase, threshold compensation phase, and light emission phase, and turned off during the data writing phase, thereby isolating the first node N1 and the third node N3. Not only does the writing of the data signal not affect the third node N3, but the potential of the third node N3 also does not affect the writing of the data signal. This effectively avoids the mutual influence between threshold compensation and data writing, effectively avoids the influence on the gate-source voltage of the driving transistor, effectively reduces the variation in the output current of the pixel driving circuit, effectively reduces the variation in the light emission brightness, and effectively improves the display effect and display quality.

[0245] This disclosure, by setting the data signal line and the first node electrode respectively on both sides of the second power line, and setting the data signal line and the second node electrode respectively on both sides of the second power line, can effectively reduce the impact of data jump voltage on the first node and the second node, improve the potential stability of key nodes of the pixel driving circuit, and improve the display effect and display quality.

[0246] This disclosure effectively reduces the parasitic capacitance of the first node N1, the second node N2, and the third node N3 by ensuring that the orthogonal projections of multiple signal lines on the substrate do not overlap with the orthogonal projections of multiple node electrodes on the substrate. This effectively reduces the impact of signal lines on key nodes of the pixel driving circuit, further reduces the variation in luminous brightness, and further improves the display effect and display quality.

[0247] This disclosure, by setting a first electrode plate in a first conductive layer, a second electrode plate in a second conductive layer, a third electrode plate in a third conductive layer, and a fourth electrode plate in a fourth conductive layer, allows the first and second electrode plates to form a second capacitor, the second and third electrode plates to form a first sub-capacitor, and the third and fourth electrode plates to form a second sub-capacitor. The first and second sub-capacitors connected in parallel constitute the first capacitor. This allows for a more compact arrangement of the pixel driving circuit while meeting design requirements, effectively improving layout space utilization, resulting in a more rational structural arrangement, simple signal line connection structure, and no complex overlap. This can effectively improve product yield and reduce production costs.

[0248] This disclosure allows the capacitance values ​​of the first and second capacitors to be substantially equal, which not only saves layout space but also effectively adjusts the data range.

[0249] This disclosure, by setting a first power connection line and a first power line, and the first power connection line and the first power line forming a network connection structure for transmitting the first power signal, can not only effectively reduce the resistance of the first power line and reduce the voltage drop of the first power signal, but also effectively improve the uniformity of the first power signal in the display substrate, effectively improve display uniformity, and improve display quality and display performance.

[0250] This disclosure, by setting a second power connection line and a second power line, and the second power connection line and the second power line forming a network connection structure for transmitting the second power signal, can not only effectively reduce the resistance of the second power line and reduce the voltage drop of the second power signal, but also effectively improve the uniformity of the second power signal in the display substrate, effectively improve display uniformity, and improve display quality and display performance.

[0251] This disclosure achieves a second power line located in a pixel (VSS in Pixel, SIP) structure by setting a second power line within the display area. This significantly reduces the width of the bezel power leads, greatly reduces the width of the left and right bezels, increases the screen-to-body ratio, and facilitates the realization of full-screen display.

[0252] This disclosure, by setting reference signal lines and reference connection lines, and forming a network connection structure for transmitting reference signals, can not only effectively reduce the resistance of reference signal lines and reduce the voltage drop of reference signals, but also effectively improve the uniformity of reference signals in the display substrate, thereby improving display uniformity, display quality, and display performance.

[0253] This disclosure, by setting an initial signal line and an initial connection line, and forming a network connection structure for transmitting the initial signal, can not only effectively reduce the resistance of the initial signal line and reduce the voltage drop of the initial signal, but also effectively improve the uniformity of the initial signal in the display substrate, thereby improving display uniformity, display quality, and display performance.

[0254] This disclosure, by setting the first power line, reference connection line, and initial connection line into a one-to-three structure, can effectively reduce the number of signal lines, effectively reduce the area of ​​the circuit unit, and help improve resolution.

[0255] This disclosure sets up a mirror image of the pixel driving circuit of some adjacent circuit units, which increases the distance between the two data signal lines of adjacent circuit units. This reduces the mutual influence between data signal lines in adjacent circuit units, reduces the impact of data switching voltage on key nodes of the pixel driving circuit, and improves the display effect and display quality.

[0256] This embodiment of the invention effectively reduces the resistance of the scan signal lines and lowers the voltage drop of the scan signal by setting multiple scan signal lines in the first source-drain metal layer, thereby improving the compensation speed and display quality.

[0257] The preparation process of this disclosure is well compatible with existing preparation processes. The process is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0258] Figure 16 is a schematic diagram of the planar structure of another display substrate according to an exemplary embodiment of the present disclosure. As shown in Figure 16, in the exemplary embodiment, the main structure of the display substrate is basically the same as the main structure shown in Figure 6. The difference is that the pixel driving circuits in the first circuit unit Q1, the second circuit unit Q2, and the third circuit unit Q3 can be basically the same. This not only improves the uniformity of the pixel driving circuit and achieves uniform design of the process and coupling capacitor, but also achieves uniform design of current distribution, effectively improving display stability and uniformity, and effectively enhancing display effect and display quality.

[0259] Figure 17 is a schematic diagram of the structure of another first capacitor and second capacitor in an exemplary embodiment of this disclosure. As shown in Figure 17, the main structure of the first capacitor and second capacitor in this embodiment is basically the same as the main structure shown in Figure 7, except that the capacitor plates of the first capacitor and the second capacitor also include a fifth plate 15.

[0260] In an exemplary embodiment, the first capacitor and the second capacitor may include a first electrode plate 11, a second electrode plate 12, a third electrode plate 13, a fourth electrode plate 14 and a fifth electrode plate 15 stacked together, with the fourth electrode plate 14 connected to the second electrode plate 12 and the fifth electrode plate 15 connected to the first electrode plate 11.

[0261] In an exemplary embodiment, the orthographic projection of the second electrode plate 12 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 11 on the substrate, and the orthographic projection of the fifth electrode plate 15 on the substrate at least partially overlaps with the orthographic projection of the fourth electrode plate 14 on the substrate. The first electrode plate 11 and the fifth electrode plate 15 may have the potential of the second power signal, and the second electrode plate 12 and the fourth electrode plate 14 may have the potential of the second node. The first electrode plate 11 and the second electrode plate 12 form a third sub-capacitor, and the fourth electrode plate 14 and the fifth electrode plate 15 form a fourth sub-capacitor. The third sub-capacitor and the fourth sub-capacitor connected in parallel form the second capacitor of the pixel driving circuit.

[0262] In an exemplary embodiment, the orthographic projection of the third electrode plate 13 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate 12 on the substrate, and the orthographic projection of the fourth electrode plate 14 on the substrate at least partially overlaps with the orthographic projection of the third electrode plate 13 on the substrate. The third electrode plate 13 may have a potential of a first node, and the second electrode plate 12 and the fourth electrode plate 14 may have potentials of a second node. The second electrode plate 12 and the third electrode plate 13 form a first sub-capacitor, and the third electrode plate 13 and the fourth electrode plate 14 form a second sub-capacitor. The first sub-capacitor and the second sub-capacitor connected in parallel form the first capacitor of the pixel driving circuit.

[0263] In an exemplary embodiment, the first electrode 11 may be disposed in the first conductive layer, the second electrode 12 may be disposed in the second conductive layer, the third electrode 13 may be disposed in the third conductive layer, the fourth electrode 14 may be disposed in the fourth conductive layer, and the fifth electrode 15 may be disposed in the fifth conductive layer. The fifth conductive layer may be disposed on the side of the first planarization layer 75 away from the substrate 10.

[0264] This embodiment effectively increases the capacitance of the second capacitor by setting a fifth electrode plate in the fifth conductive layer, making the spatial layout more reasonable.

[0265] Figure 18 is a schematic diagram of the structure of another first capacitor and second capacitor according to an exemplary embodiment of this disclosure. As shown in Figure 18, the main structure of the first capacitor and second capacitor in this embodiment is basically the same as the main structure shown in Figure 7, except that the capacitor plates of the first capacitor and the second capacitor also include semiconductor plates 16.

[0266] In an exemplary embodiment, the first capacitor and the second capacitor may include a first electrode 11, a second electrode 12, a semiconductor electrode 16, a third electrode 13 and a fourth electrode 14 stacked together, and the fourth electrode 14 may be connected to the first electrode 11 and the semiconductor electrode 16 respectively.

[0267] In an exemplary embodiment, the orthographic projection of the second electrode plate 12 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 11 on the substrate, and the orthographic projection of the semiconductor electrode plate 16 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate 12 on the substrate. The first electrode plate 11 and the semiconductor electrode plate 16 may have the potential of a second node, and the second electrode plate 12 may have the potential of a second power signal. The first electrode plate 11 and the second electrode plate 12 form a third sub-capacitor, and the second electrode plate 12 and the semiconductor electrode plate 16 form a fourth sub-capacitor. The third sub-capacitor and the fourth sub-capacitor connected in parallel form the second capacitor of the pixel driving circuit.

[0268] In an exemplary embodiment, the orthographic projection of the third electrode plate 13 on the substrate at least partially overlaps with the orthographic projection of the semiconductor electrode plate 16 on the substrate, and the orthographic projection of the fourth electrode plate 14 on the substrate at least partially overlaps with the orthographic projection of the third electrode plate 13 on the substrate. The semiconductor electrode plate 16 and the fourth electrode plate 14 may have the potential of the second node, and the third electrode plate 13 may have the potential of the first node. The third electrode plate 13 and the semiconductor electrode plate 16 form a first sub-capacitor, and the third electrode plate 13 and the fourth electrode plate 14 form a second sub-capacitor. The first sub-capacitor and the second sub-capacitor connected in parallel form the first capacitor of the pixel driving circuit.

[0269] In an exemplary embodiment, the first electrode 11 may be disposed in the first conductive layer, the second electrode 12 may be disposed in the second conductive layer, the semiconductor electrode 16 may be disposed in the semiconductor layer, the third electrode 13 may be disposed in the third conductive layer, and the fourth electrode 14 may be disposed in the fourth conductive layer.

[0270] This embodiment effectively increases the capacitance of the second capacitor by setting a semiconductor electrode in the semiconductor layer, making the spatial layout more reasonable.

[0271] Figure 19 is a schematic diagram of the structure of another first capacitor and second capacitor according to an exemplary embodiment of this disclosure. As shown in Figure 19, the main structure of the first capacitor and second capacitor in this embodiment is basically the same as the main structure shown in Figure 7. The difference is that the capacitor plates of the first capacitor and the second capacitor also include a fifth electrode plate 15 and a semiconductor electrode plate 16.

[0272] In an exemplary embodiment, the first capacitor and the second capacitor may include a first electrode 11, a second electrode 12, a semiconductor electrode 16, a third electrode 13, a fourth electrode 14, and a fifth electrode 15 stacked together. The fourth electrode 14 may be connected to the first electrode 11 and the semiconductor electrode 16 respectively, and the fifth electrode 15 may be connected to the second electrode 12.

[0273] In an exemplary embodiment, the orthographic projection of the second electrode plate 12 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 11 on the substrate, the orthographic projection of the semiconductor electrode plate 16 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate 12 on the substrate, and the orthographic projection of the fifth electrode plate 15 on the substrate at least partially overlaps with the orthographic projection of the fourth electrode plate 14 on the substrate. The first electrode plate 11, the semiconductor electrode plate 16, and the fourth electrode plate 14 may have the potential of a second node, and the second electrode plate 12 and the fifth electrode plate 15 may have the potential of a second power signal. The first electrode plate 11 and the second electrode plate 12 form a third sub-capacitor, the second electrode plate 12 and the semiconductor electrode plate 16 form a fourth sub-capacitor, and the fourth electrode plate 14 and the fifth electrode plate 15 form a fifth sub-capacitor. The third, fourth, and fifth sub-capacitors connected in parallel form the second capacitor of the pixel driving circuit.

[0274] In an exemplary embodiment, the orthographic projection of the third electrode plate 13 on the substrate at least partially overlaps with the orthographic projection of the semiconductor electrode plate 16 on the substrate, and the orthographic projection of the fourth electrode plate 14 on the substrate at least partially overlaps with the orthographic projection of the third electrode plate 13 on the substrate. The semiconductor electrode plate 16 and the fourth electrode plate 14 may have the potential of the second node, and the third electrode plate 13 may have the potential of the first node. The third electrode plate 13 and the semiconductor electrode plate 16 form a first sub-capacitor, and the third electrode plate 13 and the fourth electrode plate 14 form a second sub-capacitor. The first sub-capacitor and the second sub-capacitor connected in parallel form the first capacitor of the pixel driving circuit.

[0275] In an exemplary embodiment, the first electrode 11 may be disposed in the first conductive layer, the second electrode 12 may be disposed in the second conductive layer, the semiconductor electrode 16 may be disposed in the semiconductor layer, the third electrode 13 may be disposed in the third conductive layer, the fourth electrode 14 may be disposed in the fourth conductive layer, and the fifth electrode 15 may be disposed in the fifth conductive layer.

[0276] This embodiment effectively increases the capacitance of the second capacitor by setting a semiconductor electrode in the semiconductor layer and a fifth electrode in the fifth conductive layer, making the spatial layout more reasonable.

[0277] Figure 20 is a schematic diagram of the structure of another first capacitor and second capacitor according to an exemplary embodiment of this disclosure. As shown in Figure 20, the main structure of the first capacitor and second capacitor in this embodiment is basically the same as the main structure shown in Figure 19. The difference is that the display substrate in this embodiment does not have a first conductive layer and a first electrode plate.

[0278] In an exemplary embodiment, the first capacitor and the second capacitor may include a stacked second electrode plate 12, a semiconductor electrode plate 16, a third electrode plate 13, a fourth electrode plate 14 and a fifth electrode plate 15, wherein the fourth electrode plate 14 may be connected to the semiconductor electrode plate 16 and the fifth electrode plate 15 may be connected to the second electrode plate 12.

[0279] In an exemplary embodiment, the orthographic projection of the semiconductor electrode 16 on the substrate at least partially overlaps with the orthographic projection of the second electrode 12 on the substrate, and the orthographic projection of the fifth electrode 15 on the substrate at least partially overlaps with the orthographic projection of the fourth electrode 14 on the substrate. The semiconductor electrode 16 and the fourth electrode 14 may have the potential of the second node, and the second electrode 12 and the fifth electrode 15 may have the potential of the second power signal. The second electrode 12 and the semiconductor electrode 16 form the fourth sub-capacitor, and the fourth electrode 14 and the fifth electrode 15 form the fifth sub-capacitor. The fourth sub-capacitor and the fifth sub-capacitor connected in parallel form the second capacitor of the pixel driving circuit.

[0280] In an exemplary embodiment, the orthographic projection of the third electrode plate 13 on the substrate at least partially overlaps with the orthographic projection of the semiconductor electrode plate 16 on the substrate, and the orthographic projection of the fourth electrode plate 14 on the substrate at least partially overlaps with the orthographic projection of the third electrode plate 13 on the substrate. The semiconductor electrode plate 16 and the fourth electrode plate 14 may have the potential of the second node, and the third electrode plate 13 may have the potential of the first node. The third electrode plate 13 and the semiconductor electrode plate 16 form a first sub-capacitor, and the third electrode plate 13 and the fourth electrode plate 14 form a second sub-capacitor. The first sub-capacitor and the second sub-capacitor connected in parallel form the first capacitor of the pixel driving circuit.

[0281] In an exemplary embodiment, the second electrode 12 may be disposed in the second conductive layer, the semiconductor electrode 16 may be disposed in the semiconductor layer, the third electrode 13 may be disposed in the third conductive layer, the fourth electrode 14 may be disposed in the fourth conductive layer, and the fifth electrode 15 may be disposed in the fifth conductive layer.

[0282] This embodiment can not only effectively increase the capacitance of the second capacitor and make the spatial layout more reasonable, but also effectively reduce the number of film layers and process steps by removing the first conductive layer with low utilization, thereby reducing production costs.

[0283] The structure and its preparation process described above in this disclosure are merely illustrative examples. In the exemplary embodiments, the corresponding structure and the patterning process can be changed or added or reduced according to actual needs, and this disclosure does not limit them.

[0284] In exemplary embodiments, the display substrate of this disclosure can be applied to display devices with pixel driving circuits, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., and this disclosure does not limit it.

[0285] This disclosure also provides a display substrate. In an exemplary embodiment, the display substrate may include a plurality of circuit units, at least one of which includes a pixel driving circuit. The pixel driving circuit includes at least a first transistor, a third transistor, and a fifth transistor. The first electrode of the first transistor is connected to a reference signal line, the second electrode of the first transistor is connected to the gate electrode of the third transistor, the first electrode of the fifth transistor is connected to a first power supply line, and the second electrode of the fifth transistor is connected to the first electrode of the third transistor. The display substrate is configured to display corresponding display content, the display content including a plurality of display frames. At least one display frame includes a reset phase, a threshold compensation phase, a data writing phase, and a light emission phase performed sequentially. The pixel driving circuit further includes a sixth transistor as an isolation transistor, the sixth transistor being disposed between the gate electrode of the third transistor and the second electrode of the third transistor. The sixth transistor is configured to be turned on during the reset phase, the threshold compensation phase, and the light emission phase, and turned off during the data writing phase.

[0286] In an exemplary embodiment, the pixel driving circuit further includes a second transistor, a fourth transistor, a first capacitor, and a second capacitor. The first terminal of the second transistor is connected to an initial signal line, and the second terminal of the second transistor is connected to the second terminal of the third transistor, the second terminal of the sixth transistor, and the first terminal of the light-emitting device. The first terminal of the fourth transistor is connected to a data signal line, and the second terminal of the fourth transistor is connected to the second terminal of the first transistor, the gate electrode of the third transistor, and the first terminal of the first capacitor. The first terminal of the sixth transistor is connected to the second terminal of the first capacitor and the second terminal of the second capacitor, and the first terminal of the second capacitor is connected to a capacitor power supply line.

[0287] In an exemplary embodiment, the pixel driving circuit further includes a second transistor, a fourth transistor, a seventh transistor, a first capacitor, and a second capacitor. The first terminal of the second transistor is connected to an initial signal line. The second terminal of the second transistor is connected to the second terminal of the third transistor, the second terminal of the sixth transistor, and the first terminal of the seventh transistor. The second terminal of the seventh transistor is connected to the first terminal of the light-emitting device. The first terminal of the fourth transistor is connected to a data signal line. The second terminal of the fourth transistor is connected to the second terminal of the first transistor, the gate electrode of the third transistor, and the first terminal of the first capacitor. The first terminal of the sixth transistor is connected to the second terminal of the first capacitor and the second terminal of the second capacitor. The first terminal of the second capacitor is connected to a capacitor power supply line.

[0288] In an exemplary embodiment, the pixel driving circuit further includes a second transistor, a fourth transistor, a seventh transistor, a first capacitor, and a second capacitor. The first terminal of the fourth transistor is connected to a data signal line, and the second terminal of the fourth transistor is connected to the second terminal of the first transistor, the gate electrode of the third transistor, and the first terminal of the first capacitor. The first terminal of the second capacitor is connected to a capacitor power supply line. The first terminal of the sixth transistor is connected to the second terminal of the first capacitor and the second terminal of the second capacitor. The second terminal of the sixth transistor is connected to the second terminal of the third transistor and the first terminal of the seventh transistor. The first terminal of the second transistor is connected to an initial signal line, and the second terminal of the second transistor is connected to the second terminal of the seventh transistor and the first terminal of the light-emitting device.

[0289] In an exemplary embodiment, the pixel driving circuit further includes a second transistor, a fourth transistor, a seventh transistor, a first capacitor, and a second capacitor. The first terminal of the second transistor is connected to an initial signal line, the first terminal of the fourth transistor is connected to a data signal line, the second terminal of the second transistor is connected to the second terminal of the third transistor, the first terminal of the seventh transistor, the second terminal of the first capacitor, and the second terminal of the second capacitor, respectively. The second terminal of the seventh transistor is connected to the first terminal of the light-emitting device, the first terminal of the sixth transistor is connected to the second terminal of the first transistor and the gate electrode of the third transistor, respectively. The second terminal of the sixth transistor is connected to the second terminal of the fourth transistor and the first terminal of the first capacitor, respectively. The first terminal of the second capacitor is connected to a capacitor power supply line.

[0290] In an exemplary embodiment, the pixel driving circuit further includes a second transistor, a fourth transistor, an eighth transistor, a first capacitor, and a second capacitor. The first terminal of the second transistor is connected to an initial signal line. The second terminal of the second transistor is connected to the second terminal of the third transistor, the second terminal of the sixth transistor, and the first terminal of the light-emitting device. The first terminal of the fourth transistor is connected to a data signal line. The second terminal of the fourth transistor is connected to the second terminal of the first transistor, the gate electrode of the third transistor, and the first terminal of the first capacitor. The first terminal of the sixth transistor is connected to the second terminal of the first capacitor and the second terminal of the second capacitor. The first terminal of the second capacitor is connected to the second terminal of the eighth transistor. The first terminal of the eighth transistor is connected to a capacitor power supply line.

[0291] In an exemplary embodiment, the pixel driving circuit further includes a second transistor, a fourth transistor, an eighth transistor, a first capacitor, and a second capacitor. The first terminal of the second transistor is connected to an initial signal line, and the second terminal of the second transistor is connected to the second terminals of the third transistor, the sixth transistor, and the first terminal of the light-emitting device. The first terminal of the fourth transistor is connected to a data signal line, and the second terminal of the fourth transistor is connected to the gate electrode of the third transistor and the first terminal of the first capacitor. The first terminal of the sixth transistor is connected to the second terminal of the first capacitor and the second terminal of the eighth transistor. The first terminal of the eighth transistor is connected to the second terminal of the second capacitor, and the first terminal of the second capacitor is connected to a capacitor power supply line.

[0292] Figure 21 is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure. As shown in Figure 21, the main structure of the pixel driving circuit in this embodiment is basically the same as that shown in Figure 4. The difference is that the pixel driving circuit in this embodiment also includes a seventh transistor T7, forming a 7T2C structure.

[0293] In an exemplary embodiment, the seventh transistor T7 is an N-type transistor. The seventh transistor T7 can be disposed between the third node N3 and the light-emitting device EL. The gate electrode of the seventh transistor T7 is connected to the third light-emitting signal line EM3. The first electrode of the seventh transistor T7 is connected to the third node N3. The second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device EL.

[0294] In this embodiment, by setting a seventh transistor T7 as an isolation transistor, the seventh transistor T7 can isolate the third node N3 and the light-emitting device EL, effectively reducing the impact of the voltage across the light-emitting device EL on the third node N3, effectively reducing the change in light emission brightness, and effectively improving the display effect and display quality.

[0295] Figure 22 is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure. As shown in Figure 22, the main structure of the pixel driving circuit in this embodiment is basically the same as that shown in Figure 21, except that the second transistor T2 in the pixel driving circuit of this embodiment is connected to the fourth node N4.

[0296] In an exemplary embodiment, the pixel driving circuit may further include a fourth node N4, which is connected to the second electrode of the second transistor T2 and the second electrode of the seventh transistor T7, respectively. The gate electrode of the second transistor T2 is connected to the second scan signal line S2, the first electrode of the second transistor T2 is connected to the initial signal line INIT, and the second electrode of the second transistor T2 is connected to the fourth node N4. The gate electrode of the seventh transistor T7 is connected to the third light emission signal line EM3, the first electrode of the seventh transistor T7 is connected to the third node N3, and the second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0297] In an exemplary embodiment, during the reset phase, the second transistor T2 and the seventh transistor T7 are turned on, and the initial signal provided by the initial signal line INIT is provided to the third node N3 and the fourth node N4 to reset the third node N3 and the first electrode of the light-emitting device EL.

[0298] This embodiment can not only isolate the third node N3 and the light-emitting device EL, but also effectively improve the display effect and display quality by resetting the first electrode of the light-emitting device EL.

[0299] Figure 23 is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure. As shown in Figure 23, the main structure of the pixel driving circuit in this embodiment is basically the same as that shown in Figure 4. The difference is that the pixel driving circuit in this embodiment also includes an eighth transistor T8, forming a 7T2C structure.

[0300] In an exemplary embodiment, the eighth transistor T8 is an N-type transistor. The eighth transistor T8 can be disposed between the second capacitor C2 and the capacitor power supply line VAR. The gate electrode of the eighth transistor T8 is connected to the fourth scan signal line S4. The first electrode of the eighth transistor T8 is connected to the capacitor power supply line VAR. The second electrode of the eighth transistor T8 is connected to the first terminal of the second capacitor C2.

[0301] In this embodiment, by setting an eighth transistor T8 as a noise isolation transistor, the eighth transistor T8 is turned off during the light-emitting stage, which can effectively prevent the second capacitor C2 from dividing the potential of the second node N2 and the third node N3, improve the stability of the potential of the key node of the pixel driving circuit, effectively reduce the change of light emission brightness, and effectively improve the display effect and display quality.

[0302] Figure 24 is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure. As shown in Figure 24, the main structure of the pixel driving circuit in this embodiment is basically the same as that shown in Figure 23, except that the eighth transistor T8 in this embodiment is disposed between the second node N2 and the second capacitor C2.

[0303] This embodiment can also prevent the second capacitor C2 from dividing the potential of the second node N2 and the third node N3.

[0304] Figure 25 is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure. As shown in Figure 25, the main structure of the pixel driving circuit in this embodiment is similar to that shown in Figure 4, but the positions and connection structures of the transistors and capacitors are different.

[0305] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the second terminal of the first transistor T1, the top gate electrode of the third transistor T3, and the first terminal of the sixth transistor T6. The second node N2 is connected to the second terminal of the fourth transistor T4, the second terminal of the sixth transistor T6, and the first terminal of the first capacitor C1. The third node N3 is connected to the second terminal of the second transistor T2, the second terminal of the third transistor T3, the first terminal of the seventh transistor T7, the second terminal of the first capacitor C1, and the second terminal of the second capacitor C2.

[0306] In an exemplary embodiment, the first terminal of the first capacitor C1 is connected to the second node N2, and the second terminal of the first capacitor C1 is connected to the third node N3. The first terminal of the second capacitor C2 is connected to the capacitor power line VAR, and the second terminal of the second capacitor C2 is connected to the third node N3.

[0307] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the first scan signal line S1, the first electrode of the first transistor T1 is connected to the reference signal line REF, and the second electrode of the first transistor T1 is connected to the first node N1.

[0308] In an exemplary embodiment, the gate electrode of the second transistor T2 is connected to the second scan signal line S2, the first electrode of the second transistor T2 is connected to the initial signal line INIT, and the second electrode of the second transistor T2 is connected to the third node N3.

[0309] In an exemplary embodiment, the top gate electrode of the third transistor T3 is connected to the first node N1, the first terminal of the third transistor T3 is connected to the second terminal of the fifth transistor T5, and the second terminal of the third transistor T3 is connected to the third node N3. The third transistor T3 may also include a bottom gate electrode, which is connected to the second terminal of the third transistor T3.

[0310] In an exemplary embodiment, the gate electrode of the fourth transistor T4 is connected to the third scan signal line S3, the first electrode of the fourth transistor T4 is connected to the data signal line DATA, and the second electrode of the fourth transistor T4 is connected to the second node N2.

[0311] In an exemplary embodiment, the gate electrode of the fifth transistor T5 is connected to the first light-emitting signal line EM1, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first electrode of the third transistor T3.

[0312] In an exemplary embodiment, the gate electrode of the sixth transistor T6 is connected to the second light-emitting signal line EM2, the first electrode of the sixth transistor T6 is connected to the first node N1, and the second electrode of the sixth transistor T6 is connected to the second node N2.

[0313] In an exemplary embodiment, the gate electrode of the seventh transistor T7 is connected to the third light-emitting signal line EM3, the first electrode of the seventh transistor T7 is connected to the third node N3, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device EL.

[0314] In an exemplary embodiment, all seven transistors in the pixel driving circuit are N-type transistors.

[0315] The pixel driving circuit provided in the exemplary embodiments of this disclosure, by setting a sixth transistor T6 as an isolation transistor between the first node N1 and the second node N2, wherein the sixth transistor T6 is turned on during the reset phase and the light emission phase, and turned off during the threshold compensation phase and the data writing phase, can effectively avoid the influence on the gate-source voltage of the driving transistor, effectively reduce the change in the output current of the pixel driving circuit, effectively reduce the change in the light emission brightness, and effectively improve the display effect and display quality.

[0316] This disclosure also provides a display device, which includes the aforementioned display substrate. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator, and the embodiments of the present invention are not limited thereto.

[0317] While the embodiments disclosed herein are as described above, it should be noted that these embodiments are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the specific content shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the embodiments without departing from the scope of this disclosure.

Claims

1. A display substrate comprising a plurality of circuit units, at least one circuit unit comprising a pixel driving circuit, the pixel driving circuit comprising at least a first transistor, a third transistor and a fifth transistor, wherein a first electrode of the first transistor is connected to a reference signal line, a second electrode of the first transistor is connected to the top gate electrode of the third transistor, a first electrode of the fifth transistor is connected to a first power supply line, and a second electrode of the fifth transistor is connected to the first electrode of the third transistor; a first capacitor and a sixth transistor are further disposed between the top gate electrode of the third transistor and the second electrode of the third transistor, the first capacitor comprising at least a third plate and a fourth plate, wherein the orthographic projection of the fourth plate on the display substrate plane at least partially overlaps with the orthographic projection of the third plate on the display substrate plane, the third plate is connected to the second electrode of the first transistor through a first node electrode, the fourth plate is connected to the first electrode of the sixth transistor through a second node electrode, and the second electrode of the sixth transistor is connected to the second electrode of the third transistor through a third node electrode.

2. The display substrate according to claim 1, wherein, The pixel driving circuit further includes a fourth transistor, the first electrode of which is connected to the data signal line, and the second electrode of which is connected to the top gate electrode of the third transistor. 3.The display substrate of claim 2, wherein, The fourth transistor includes at least a fourth active layer. The data signal line is connected to the first region of the fourth active layer. The first node electrode is connected to the second region of the fourth active layer and the third electrode plate through a via. The third electrode plate and the top gate electrode of the third transistor are disposed on the same layer and are an integral structure interconnected with each other.

4. The display substrate according to claim 1, wherein, The third transistor includes at least a third active layer, the fifth transistor includes at least a fifth active layer, and the sixth transistor includes at least a sixth active layer. The first power line is connected to the first region of the fifth active layer, and the second region of the fifth active layer is connected to the first region of the third active layer. The third node electrode is connected to the second region of the sixth active layer through a via, and also to the second region of the third active layer and the bottom gate electrode of the third transistor through a via. The second node electrode is connected to the first region of the sixth active layer through a via. The fourth electrode plate and the second node electrode are disposed on the same layer and are an integral structure interconnected with each other. 5.The display substrate of claim 1, wherein, The pixel driving circuit further includes a second transistor, the first electrode of which is connected to the initial signal line, and the second electrode of which is connected to the third node electrode.

6. The display substrate according to claim 1, wherein, In a direction perpendicular to the display substrate, the display substrate includes a plurality of conductive layers disposed on the substrate, wherein the first node electrode, the second node electrode and the third node electrode are disposed in the same conductive layer.

7. The display substrate according to claim 1, wherein, The pixel driving circuit further includes a second capacitor, wherein the ratio of the capacitance value of the first capacitor to the capacitance value of the second capacitor is 0.95 to 1.

05. 8.The display substrate according to any one of claims 1 to 7, wherein The pixel driving circuit further includes a second capacitor, which includes at least a first electrode plate and a second electrode plate stacked together. The orthographic projection of the second electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the first electrode plate on the display substrate plane. The orthographic projection of the third electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the second electrode plate on the display substrate plane. The fourth electrode plate is connected to the second electrode plate. The second electrode plate and the third electrode plate form a first sub-capacitor. The third electrode plate and the fourth electrode plate form a second sub-capacitor. The first sub-capacitor and the second sub-capacitor connected in parallel form the first capacitor. The first electrode plate and the second electrode plate form the second capacitor.

9. The display substrate according to claim 8, wherein, In a direction perpendicular to the display substrate, the display substrate includes a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer disposed sequentially on a substrate, wherein a first electrode plate is disposed in the first conductive layer, a second electrode plate is disposed in the second conductive layer, a third electrode plate is disposed in the third conductive layer and a fourth electrode plate is disposed in the fourth conductive layer.

10. The display substrate according to any one of claims 1 to 7, wherein, The pixel driving circuit further includes a second capacitor, which includes at least a first electrode plate, a second electrode plate, and a fifth electrode plate stacked together. The orthographic projection of the second electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the first electrode plate on the display substrate plane. The orthographic projection of the third electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the second electrode plate on the display substrate plane. The orthographic projection of the fifth electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the fourth electrode plate on the display substrate plane. The fourth electrode plate is connected to the second electrode plate, and the fifth electrode plate is connected to the first electrode plate. The second electrode plate and the third electrode plate form a first sub-capacitor, and the third electrode plate and the fourth electrode plate form a second sub-capacitor. The first sub-capacitor and the second sub-capacitor connected in parallel form the first capacitor. The first electrode plate and the second electrode plate form a third sub-capacitor, and the fourth electrode plate and the fifth electrode plate form a fourth sub-capacitor. The third sub-capacitor and the fourth sub-capacitor connected in parallel form the second capacitor. 11.The display substrate of claim 10, wherein, In a direction perpendicular to the display substrate, the display substrate includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer sequentially disposed on a substrate, wherein a first electrode plate is disposed in the first conductive layer, a second electrode plate is disposed in the second conductive layer, a third electrode plate is disposed in the third conductive layer, a fourth electrode plate is disposed in the fourth conductive layer and a fifth electrode plate is disposed in the fifth conductive layer.

12. The display substrate according to any one of claims 1 to 7, wherein, The pixel driving circuit further includes a second capacitor, which includes at least a first electrode plate, a second electrode plate, and a sixth electrode plate stacked together. The orthographic projection of the second electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the first electrode plate on the display substrate plane. The orthographic projection of the sixth electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the second electrode plate on the display substrate plane. The orthographic projection of the third electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the sixth electrode plate on the display substrate plane. The fourth electrode is connected to the first electrode and the sixth electrode respectively. The sixth electrode and the third electrode form a first sub-capacitor, and the third electrode and the fourth electrode form a second sub-capacitor. The first sub-capacitor and the second sub-capacitor connected in parallel form the first capacitor. The first electrode and the second electrode form a third sub-capacitor, and the second electrode and the sixth electrode form a fourth sub-capacitor. The third sub-capacitor and the fourth sub-capacitor connected in parallel form the second capacitor.

13. The display substrate according to any one of claims 1 to 7, wherein, The pixel driving circuit further includes a second capacitor, which includes at least a first electrode plate, a second electrode plate, a fifth electrode plate, and a sixth electrode plate stacked together. The orthographic projection of the second electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the first electrode plate on the display substrate plane. The orthographic projection of the sixth electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the second electrode plate on the display substrate plane. The orthographic projection of the third electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the sixth electrode plate on the display substrate plane. The orthographic projection of the fifth electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the fourth electrode plate on the display substrate plane. The fourth electrode is connected to the first electrode and the sixth electrode, and the fifth electrode is connected to the second electrode. The sixth electrode and the third electrode form a first sub-capacitor, and the third electrode and the fourth electrode form a second sub-capacitor. The first sub-capacitor and the second sub-capacitor connected in parallel form the first capacitor. The first electrode and the second electrode form a third sub-capacitor, the second electrode and the sixth electrode form a fourth sub-capacitor, and the fourth electrode and the fifth electrode form a fifth sub-capacitor. The third sub-capacitor, the fourth sub-capacitor, and the fifth sub-capacitor connected in parallel form the second capacitor.

14. The display substrate according to any one of claims 1 to 7, wherein, The pixel driving circuit further includes a second capacitor, which includes at least a second electrode plate, a fifth electrode plate, and a sixth electrode plate stacked together. The orthographic projection of the sixth electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the second electrode plate on the display substrate plane. The orthographic projection of the third electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the sixth electrode plate on the display substrate plane. The orthographic projection of the fifth electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the fourth electrode plate on the display substrate plane. The fourth electrode plate is connected to the sixth electrode plate, and the fifth electrode plate is connected to the second electrode plate. The sixth electrode plate and the third electrode plate form a first sub-capacitor, and the third electrode plate and the fourth electrode plate form a second sub-capacitor. The first sub-capacitor and the second sub-capacitor connected in parallel form the first capacitor. The second electrode plate and the sixth electrode plate form a fourth sub-capacitor, and the fourth electrode plate and the fifth electrode plate form a fifth sub-capacitor. The fourth sub-capacitor and the fifth sub-capacitor connected in parallel form the second capacitor.

15. A display device comprising a display substrate as described in any one of claims 1 to 14.

16. A display substrate comprising a plurality of circuit units, at least one circuit unit comprising a pixel driving circuit, the pixel driving circuit comprising at least a first transistor, a third transistor and a fifth transistor, a first electrode of the first transistor being connected to a reference signal line, a second electrode of the first transistor being connected to the top gate electrode of the third transistor, a first electrode of the fifth transistor being connected to a first power supply line, and a second electrode of the fifth transistor being connected to the first electrode of the third transistor; the display substrate being configured to display corresponding display content, the display content comprising a plurality of display frames, at least one display frame comprising a reset phase, a threshold compensation phase, a data writing phase and a light emission phase performed sequentially, the pixel driving circuit further comprising a sixth transistor disposed between the top gate electrode of the third transistor and the second electrode of the third transistor, the sixth transistor being configured to be disconnected during the data writing phase. 17.The display substrate of claim 16, wherein, The pixel driving circuit further includes a second transistor, a fourth transistor, a first capacitor, and a second capacitor. The first terminal of the second transistor is connected to the initial signal line. The second terminal of the second transistor is connected to the second terminal of the third transistor, the second terminal of the sixth transistor, and the first terminal of the light-emitting device. The first terminal of the fourth transistor is connected to the data signal line. The second terminal of the fourth transistor is connected to the second terminal of the first transistor, the top gate electrode of the third transistor, and the first terminal of the first capacitor. The first terminal of the sixth transistor is connected to the second terminal of the first capacitor and the second terminal of the second capacitor. The first terminal of the second capacitor is connected to the capacitor power supply line. 18.The display substrate of claim 16, wherein, The pixel driving circuit further includes a second transistor, a fourth transistor, a seventh transistor, a first capacitor, and a second capacitor. The first terminal of the fourth transistor is connected to a data signal line. The second terminal of the fourth transistor is connected to the second terminal of the first transistor, the top gate electrode of the third transistor, and the first terminal of the first capacitor. The first terminal of the second capacitor is connected to a capacitor power supply line. The first terminal of the sixth transistor is connected to the second terminal of the first capacitor and the second terminal of the second capacitor. The second terminal of the sixth transistor is connected to the second terminal of the third transistor and the first terminal of the seventh transistor. The first terminal of the second transistor is connected to an initial signal line. The second terminal of the second transistor is connected to the second terminal of the seventh transistor and the first terminal of the light-emitting device, or the second terminal of the second transistor is connected to the second terminal of the third transistor, the second terminal of the sixth transistor, and the first terminal of the seventh transistor.

19. The display substrate of claim 16, wherein, The pixel driving circuit further includes a second transistor, a fourth transistor, a seventh transistor, a first capacitor, and a second capacitor. The first terminal of the second transistor is connected to the initial signal line, the first terminal of the fourth transistor is connected to the data signal line, the second terminal of the second transistor is connected to the second terminal of the third transistor, the first terminal of the seventh transistor, the second terminal of the first capacitor, and the second terminal of the second capacitor, respectively. The second terminal of the seventh transistor is connected to the first terminal of the light-emitting device, the first terminal of the sixth transistor is connected to the second terminal of the first transistor and the top gate electrode of the third transistor, respectively. The second terminal of the sixth transistor is connected to the second terminal of the fourth transistor and the first terminal of the first capacitor, respectively. The first terminal of the second capacitor is connected to the capacitor power supply line. 20.The display substrate of claim 16, wherein, The pixel driving circuit further includes a second transistor, a fourth transistor, an eighth transistor, a first capacitor, and a second capacitor. The first terminal of the second transistor is connected to the initial signal line, and the second terminal of the second transistor is connected to the second terminal of the third transistor, the second terminal of the sixth transistor, and the first terminal of the light-emitting device, respectively. The first terminal of the fourth transistor is connected to the data signal line. The second terminal of the fourth transistor is connected to the second terminal of the first transistor, the top gate electrode of the third transistor, and the first terminal of the first capacitor, respectively. The first terminal of the sixth transistor is connected to the second terminal of the first capacitor and the second terminal of the second capacitor, respectively. The first terminal of the second capacitor is connected to the second terminal of the eighth transistor, and the first terminal of the eighth transistor is connected to the capacitor power supply line. Alternatively, the second terminal of the fourth transistor is connected to the top gate electrode of the third transistor and the first terminal of the first capacitor, respectively. The first terminal of the sixth transistor is connected to the second terminal of the first capacitor and the second terminal of the eighth transistor, respectively. The first terminal of the eighth transistor is connected to the second terminal of the second capacitor, and the first terminal of the second capacitor is connected to the capacitor power supply line.

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