Power management chip, power management apparatus and display device

Abstract

Provided in the embodiments of the present disclosure are a power management chip, a power management apparatus and a display device. The power management chip comprises: a first voltage generation circuit, which is configured to output a first power voltage; and a voltage adjustment circuit, which is connected to the first voltage generation circuit, and is configured to control, in response to a measurement parameter, the first voltage generation circuit to adjust the output first power voltage.

Description

Power management chips, power management devices and display devices Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a power management chip, a power management device, and a display equipment. Background Technology

[0002] Power management integrated circuits (PMICs) are an important component of display devices, typically used to convert the voltage signal output by the power supply into the signals required to drive the display panel. Summary of the Invention

[0003] This disclosure provides a power management chip, a power management device, and a display device. The power management chip includes:

[0004] The first voltage generation circuit is configured to output a first power supply voltage;

[0005] A voltage adjustment circuit, connected to the first voltage generation circuit, is configured to control the first voltage generation circuit to adjust the output first power supply voltage in response to a detected parameter.

[0006] In one possible implementation, the detection parameters include: a temperature parameter;

[0007] The voltage adjustment circuit includes a temperature detection and control circuit; the temperature detection and control circuit is connected to the first voltage generation circuit and is configured to control the first power supply voltage output by the first voltage generation circuit to decrease in response to the temperature parameter being greater than the temperature threshold, and to control the first power supply voltage output by the first voltage generation circuit to increase in response to the temperature parameter being less than the temperature threshold.

[0008] In one possible implementation, the temperature detection and control circuit includes: a first temperature-sensitive circuit and a second temperature-sensitive circuit;

[0009] The first temperature-sensitive circuit is configured to generate a first electrical signal corresponding to a first temperature range;

[0010] The second temperature-sensitive circuit is configured to generate a second electrical signal corresponding to a second temperature range, wherein the first temperature range is greater than the second temperature range.

[0011] In one possible implementation, the first temperature-sensitive circuit includes: a first temperature-sensitive resistor, a second temperature-sensitive resistor, and a third temperature-sensitive resistor;

[0012] The first terminal of the first temperature-sensitive resistor is electrically connected to the first power supply voltage terminal, and the second terminal is electrically connected to the first terminal of the second temperature-sensitive resistor and the first terminal of the third temperature-sensitive resistor.

[0013] The second terminal of the second thermistor and the second terminal of the third thermistor are connected to ground.

[0014] In one possible implementation, the second temperature-sensitive circuit includes: a fourth temperature-sensitive resistor, a fifth temperature-sensitive resistor, and a sixth temperature-sensitive resistor;

[0015] The first terminal of the fourth thermistor is electrically connected to the second power supply voltage terminal, and the second terminal is electrically connected to the first terminal of the fifth thermistor and the second terminal of the sixth thermistor.

[0016] The second terminal of the fifth thermistor and the second terminal of the sixth thermistor are connected to ground.

[0017] In one possible implementation, the second thermistor is a negative temperature coefficient resistor; and / or, the fifth thermistor is a negative temperature coefficient resistor.

[0018] In one possible implementation, the detection parameters include: the set duration of the gate drive signal;

[0019] The voltage adjustment circuit further includes a detection circuit; the detection circuit is connected to the first voltage generation circuit and is configured to receive the gate drive signal and, in response to the set duration of the gate drive signal, control the first voltage generation circuit to adjust the output first power supply voltage.

[0020] In one possible implementation, the set duration includes: the rising edge duration of the gate drive signal;

[0021] The detection circuit is further configured to control the voltage of the first power supply voltage output by the first voltage generation circuit to increase in response to the rising edge duration of the received gate drive signal being greater than a first duration threshold, and to control the voltage of the first power supply voltage output by the first voltage generation circuit to decrease in response to the rising edge duration of the received gate drive signal being less than the first duration threshold.

[0022] In one possible implementation, the set duration includes: the duration of holding a first level of the gate drive signal; the first level is used to control the transistor in the gate drive circuit to turn on;

[0023] The detection circuit is further configured to control the voltage of the first power supply voltage output by the first voltage generation circuit to increase in response to the holding duration of the received gate drive signal being greater than a second duration threshold, and to control the voltage of the first power supply voltage output by the first voltage generation circuit to decrease in response to the holding duration of the received gate drive signal being less than the second duration threshold.

[0024] In one possible implementation, the first voltage generation circuit includes a boost converter circuit.

[0025] In one possible implementation, the first voltage generating circuit includes: a first inductor, a first capacitor, a second capacitor, a first Zener diode, and a first transistor;

[0026] The first terminal of the first transistor is electrically connected to the first boost pin terminal, and the second terminal of the first transistor is electrically connected to the second boost pin terminal;

[0027] The first terminal of the first Zener diode is electrically connected to the first boost pin and the first terminal of the first resistor, and the second terminal of the first Zener diode is electrically connected to the first terminal of the first capacitor, the first voltage output terminal, and the third boost pin.

[0028] The second end of the first inductor is electrically connected to the first boost reference signal terminal and the first end of the first capacitor;

[0029] The second terminal of the first capacitor is connected to ground.

[0030] The second terminal of the second capacitor is connected to ground.

[0031] In one possible implementation, the power management chip further includes: a second voltage generation circuit configured to output a second power supply voltage; the second power supply voltage is less than the first power supply voltage;

[0032] The voltage adjustment circuit is also connected to the second voltage generation circuit and is configured to control the second voltage generation circuit to adjust the output second power supply voltage in response to the detection parameter.

[0033] In one possible implementation, the second voltage generation circuit includes a buck converter circuit.

[0034] In one possible implementation, the second voltage generation circuit includes: a second transistor, a third transistor, a first resistor, and a third capacitor;

[0035] The control terminal of the second transistor is electrically connected to the first terminal of the first resistor, the control terminal of the third transistor, and the first buck pin terminal. The first terminal of the second transistor is grounded. The second terminal of the second transistor is electrically connected to the second terminal of the first resistor, the first terminal of the third transistor, the first terminal of the third capacitor, the second voltage output terminal, and the second buck pin terminal.

[0036] The second terminal of the third transistor is electrically connected to the second voltage input terminal;

[0037] The second terminal of the third capacitor is connected to ground.

[0038] In one possible implementation, the power management chip includes: a gamma circuit group; the gamma circuit group is configured to output multiple gamma voltages;

[0039] The gamma circuit group includes at least five gamma circuits.

[0040] In one possible implementation, the gamma circuit includes: a digital-to-analog converter, an amplifier, a gamma resistor, and a gamma capacitor;

[0041] The first terminal of the digital-to-analog converter is electrically connected to the first reference voltage terminal, and the second terminal of the digital-to-analog converter is electrically connected to the first terminal of the amplifier;

[0042] The second terminal of the amplifier is electrically connected to the gamma pin terminal;

[0043] The first end of the gamma resistor is electrically connected to the gamma pin, and the second end of the gamma resistor is electrically connected to the first end of the gamma capacitor and the gamma voltage output terminal.

[0044] The second terminal of the gamma capacitor is connected to ground.

[0045] In one possible implementation, the gamma circuit group comprises ten of the gamma circuits.

[0046] This disclosure also provides a power management device, which includes the power management chip provided in this disclosure.

[0047] This disclosure also provides a display device, which includes a display panel and a power management device, wherein the power management device is the power management device provided in this disclosure. Attached Figure Description

[0048] Figure 1 is a schematic diagram of one of the first voltage generation circuit and voltage adjustment circuit provided in the embodiments of this disclosure;

[0049] Figure 2 is a second schematic diagram of the first voltage generation circuit and voltage adjustment circuit provided in the embodiments of this disclosure;

[0050] Figure 3A is a schematic diagram of the power management chip provided in an embodiment of this disclosure;

[0051] Figure 3B is an enlarged view of the dashed frame 01 in Figure 3A;

[0052] Figure 3C is an enlarged view of the dashed frame 021 in Figure 3A;

[0053] Figure 3D is an enlarged view of the dashed frame 022 in Figure 3A;

[0054] Figure 3E is a schematic diagram of at least a portion of the detection circuit;

[0055] Figure 3F is an enlarged view of the dashed frame 03 in Figure 3A;

[0056] Figure 3G is an enlarged view of the dashed frame 04 in Figure 3A;

[0057] Figure 3H is an enlarged view of the dashed frame 05 in Figure 3A;

[0058] Figure 3I is an enlarged view of the dashed frame 06 in Figure 3A;

[0059] Figure 3J is an enlarged view of the dashed frame 07 in Figure 3A;

[0060] Figure 3K is an enlarged view of the dashed frame 08 in Figure 3A;

[0061] Figure 3L is an enlarged view of the dashed frame 09 in Figure 3A;

[0062] Figure 3M is an enlarged view of the dashed frame 010 in Figure 3A;

[0063] Figure 3N is an enlarged view of the dashed frame 011 in Figure 3A;

[0064] Figure 4 is a schematic diagram of the unlabeled power management chip corresponding to Figure 3A. Detailed Implementation

[0065] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0066] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0067] As used herein, “approximately” or “substantially the same” includes the stated value and means within an acceptable range of deviations from the specific value, as determined by a person skilled in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., limitations of the measurement system). For example, “substantially the same” may mean a difference relative to the stated value within one or more standard deviations, or within ±30%, 20%, 10%, or 5%.

[0068] In the accompanying drawings, the thicknesses of layers, films, panels, regions, etc., are enlarged for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic diagrams of idealized embodiments. Thus, deviations from the shapes shown in the drawings will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shape caused, for example, by manufacturing processes. For example, regions illustrated or described as flat may typically have rough and / or non-linear characteristics. Furthermore, sharp corners illustrated may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, nor are they intended to limit the scope of the claims.

[0069] To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0070] With the development of television and outdoor products, some power management integrated circuits no longer meet the current requirements. For example, for high-power display products with large size and dual-gate architecture, there is a risk of overheating in some areas of the display panel (such as corners where the wiring is dense in the peripheral area). The high temperature will cause the gate drive on array (GOA) circuit at that location to gradually age during long-term use, resulting in a shortened lifespan of the gate drive circuit and increased power consumption.

[0071] In view of this, the present disclosure provides a power management chip, as shown in Figures 1 and 2, including:

[0072] The first voltage generation circuit 01 is configured to output the first power supply voltage VGH;

[0073] The voltage adjustment circuit 02, connected to the first voltage generation circuit 01, is configured to control the first voltage generation circuit 01 to adjust the output first power supply voltage VGH in response to the detected parameters.

[0074] The power management chip provided in this embodiment further includes a voltage adjustment circuit 02. The voltage adjustment circuit 02 can control the first voltage generation circuit 01 to adjust the output first power supply voltage VGH in response to the detection parameters. This allows the power management chip to dynamically adjust the first power supply voltage VGH according to changes in the external environment or the output of the gate drive circuit, thereby improving the driving capability of the power management chip and extending the lifespan of the gate drive circuit.

[0075] In one possible implementation, the detection parameter includes a temperature parameter; referring to FIG2, the voltage adjustment circuit 02 includes a temperature detection control circuit 021; the temperature detection control circuit 021 is connected to the first voltage generation circuit 01 and is configured to control the first power supply voltage VGH output by the first voltage generation circuit 01 to decrease in response to the temperature parameter being greater than a temperature threshold, and to control the first power supply voltage VGH output by the first voltage generation circuit 01 to increase in response to the temperature parameter being less than a temperature threshold.

[0076] In this embodiment, the voltage adjustment circuit 02 includes a temperature detection and control circuit 021. The temperature detection and control circuit 021 and the first voltage generation circuit 01 are configured to control the first power supply voltage VGH output by the first voltage generation circuit 01 to decrease in response to a temperature parameter greater than a temperature threshold, and to control the first power supply voltage VGH output by the first voltage generation circuit 01 to increase in response to a temperature parameter less than a temperature threshold. That is, when the ambient temperature is high, the first power supply voltage VGH can be adjusted to decrease, and when the temperature is low, the first power supply voltage VGH can be adjusted to increase, thereby improving the driving capability of the power management chip. Moreover, for high-power display products such as large-size, dual-gate architecture, the temperature in some areas of the display panel (such as the corners where the wiring is dense in the peripheral area) is too high. If the first power supply voltage VGH is continuously output at a higher level, the high temperature will cause the gate drive circuit at that location to... The gate drive circuit (GOA) gradually ages over long-term use, leading to a shortened lifespan and increased power consumption. However, this embodiment of the present disclosure improves the problems of gate drive circuit aging, shortened lifespan, and high power consumption by setting a temperature detection and control circuit 021 to dynamically adjust the output of the first power supply voltage VGH.

[0077] In one possible implementation, as shown in Figures 3A and 3B, the first voltage generation circuit 01 includes a boost circuit.

[0078] In one possible implementation, referring to Figures 3A, 3B and 4, the first voltage generation circuit 01 includes: a first inductor L1, a first capacitor C1, a second capacitor C2, a first Zener diode T01, and a first transistor T1.

[0079] The first terminal of the first transistor T1 is electrically connected to the first boost pin LXP, and the second terminal of the first transistor T1 is electrically connected to the second boost pin PGNDP.

[0080] The first terminal of the first Zener diode T01 is electrically connected to the first boost pin LXP and the first terminal of the first inductor L1. The second terminal of the first Zener diode T01 is electrically connected to the first terminal of the first capacitor C1, the first voltage output terminal (i.e., the output first power supply voltage VGH), and the third boost pin terminal (i.e., the pin labeled 60).

[0081] The second terminal of the first inductor L1 is electrically connected to the first boost reference signal terminal (which can output the start signal VIN or the reference voltage VAVDD) and the first terminal of the first capacitor C1.

[0082] The second terminal of the first capacitor C1 is connected to ground.

[0083] The second terminal of the second capacitor C2 is connected to ground.

[0084] In this embodiment of the present disclosure, the first voltage generation circuit 01 includes: a first inductor L1, a first capacitor C1, a second capacitor C2, a first Zener diode T01, and a first transistor T1; thus, the first power supply voltage VGH is output.

[0085] In one possible implementation, the first inductor L1 can be 10μH; the first capacitor C1 can be 10μF; and the second capacitor C2 can be 10μF.

[0086] In one possible implementation, referring to Figures 3A and 3B, the first voltage generation circuit 01 further includes a boost regulator controller 011; the first input terminal of the boost regulator controller 011 can be electrically connected to the registers & logic control, the first output terminal of the boost regulator controller 011 can be electrically connected to the control terminal of the first transistor T1, and the second output terminal of the boost regulator controller 011 can be electrically connected to the third boost pin (i.e., the pin labeled 60); the boost regulator controller 011 can receive signals from the registers & logic control to control the first transistor T1 to turn on or off.

[0087] In one possible implementation, referring to Figures 3A and 3C, the temperature detection and control circuit 021 includes: a first temperature-sensitive circuit 0211 and a second temperature-sensitive circuit 0212;

[0088] The first temperature-sensitive circuit 0211 is configured to generate a first electrical signal corresponding to a first temperature range;

[0089] The second temperature-sensitive circuit 0212 is configured to generate a second electrical signal corresponding to a second temperature range, wherein the first temperature range is greater than the second temperature range.

[0090] In one possible implementation, as shown in FIG3C, the first temperature-sensitive circuit 0211 includes: a first temperature-sensitive resistor RN1_H, a second temperature-sensitive resistor RNTC_H, and a third temperature-sensitive resistor RN2_H.

[0091] The first terminal of the first thermistor RN1_H is electrically connected to the first power supply voltage terminal VL, and the second terminal of the first thermistor RN1_H is electrically connected to the first terminal of the second thermistor RNTC_H and the first terminal of the third thermistor RN2_H.

[0092] The second terminal of the second thermistor RNTC_H and the second terminal of the third thermistor RN2_H are connected to ground.

[0093] In this embodiment of the disclosure, by making the first temperature-sensitive circuit 0211 include: a first temperature-sensitive resistor RN1_H, a second temperature-sensitive resistor RNTC_H, and a third temperature-sensitive resistor RN2_H, the temperature signal can be output through an electrical signal to realize the detection of the external temperature.

[0094] In one possible implementation, as shown in FIG3C, the second temperature-sensitive circuit 0212 includes: a fourth temperature-sensitive resistor RN1_C, a fifth temperature-sensitive resistor RNTC_C, and a sixth temperature-sensitive resistor RN2_C.

[0095] The first terminal of the fourth thermistor RN1_C is electrically connected to the second power supply voltage terminal (which can be the same as the signal of the first power supply voltage terminal VL), and the second terminal of the fourth thermistor RN1_C is electrically connected to the first terminal of the fifth thermistor RNTC_C and the second terminal of the sixth thermistor RN2_C.

[0096] The second terminal of the fifth thermistor RNTC_C and the second terminal of the sixth thermistor RN2_C are connected to ground.

[0097] In this embodiment of the disclosure, by making the second temperature-sensitive circuit 0212 include: a fourth temperature-sensitive resistor RN1_C, a fifth temperature-sensitive resistor RNTC_C, and a sixth temperature-sensitive resistor RN2_C, the temperature signal can be output through an electrical signal to realize the detection of the external temperature.

[0098] In one possible implementation, the second thermistor RNTC_H is a negative temperature coefficient resistor; and / or, the fifth thermistor RNTC_C is a negative temperature coefficient resistor. In this embodiment of the present disclosure, the second thermistor RNTC_H and / or the fifth thermistor RNTC_C being negative temperature coefficient resistors allows the resistance values ​​of the second thermistor RNTC_H and the fifth thermistor RNTC_C to decrease as the temperature increases.

[0099] In one possible implementation, referring to Figure 3C, the second end of the first temperature-sensitive resistor RN1_H can also be electrically connected to the first temperature-sensitive pin NTC_H (i.e., pin number 8); the second end of the fourth resistor RN1_C can also be electrically connected to the second temperature-sensitive pin NTC_C (i.e., pin number 10).

[0100] In one possible implementation, referring to Figures 3A and 3C, the temperature detection and control circuit 021 further includes a temperature compensation circuit 0213. The first input terminal of the temperature compensation circuit 0213 can be electrically connected to the first temperature-sensitive pin NTC_H (i.e., pin number 8), the second input terminal of the temperature compensation circuit 0213 can be electrically connected to the second temperature-sensitive pin NTC_C (i.e., pin number 10), and the output terminal of the temperature compensation circuit 0213 can be electrically connected to the boost regulator controller 011. The temperature compensation circuit 0213 can receive the first electrical signal from the first temperature-sensitive circuit 0211 and the second electrical signal from the second temperature-sensitive circuit 0212, process them, and then send them to the boost regulator controller 011 of the first voltage generation circuit 01. Optionally, the temperature compensation circuit 0213 can be a temperature compensation chip.

[0101] In one possible implementation, the detection parameters include: the set duration of the gate drive signal Gout; referring to FIG2, the voltage adjustment circuit 02 further includes: a detection circuit 022; the detection circuit 022 is connected to the first voltage generation circuit 01 and is configured to receive the gate drive signal Gout, and in response to the set duration of the gate drive signal Gout, control the first voltage generation circuit 01 to adjust the output first power supply voltage VGH.

[0102] When the gate drive circuit ages and the output gate drive signal is insufficient to turn on the transistor, in this embodiment of the present disclosure, the voltage adjustment circuit 02 monitors the gate drive signal output by the gate drive circuit and adjusts the output first power supply voltage VGH according to the set duration of the gate drive signal, so that the drive voltage output by the gate drive circuit is always at the optimal setting, thereby reducing power consumption and extending the life of the gate drive circuit.

[0103] In one possible implementation, the set duration includes: the rising edge duration Tr of the gate drive signal Gout; the detection circuit 022 is further configured to control the voltage of the first power supply voltage VGH output by the first voltage generation circuit 01 to increase in response to the receiving gate drive signal Gout rising edge duration Tr being greater than the first duration threshold, and to control the voltage of the first power supply voltage VGH output by the first voltage generation circuit 01 to decrease in response to the receiving gate drive signal rising edge duration Tr being less than the first duration threshold.

[0104] In one possible implementation, the set duration includes: a holding duration Thold of the first level of the gate drive signal Gout; the first level is used to control the transistor in the gate drive circuit to turn on; the detection circuit 022 is further configured to control the voltage VGH of the first power supply voltage output by the first voltage generation circuit 01 to increase in response to the holding duration Thold of the received gate drive signal Gout being greater than a second duration threshold, and to control the voltage VGH of the first power supply voltage output by the first voltage generation circuit 01 to decrease in response to the holding duration of the received gate drive signal Gout being less than the second duration threshold.

[0105] In one possible implementation, as shown in Figures 3A and 3D, the detection circuit 022 may include: an optimized aging detector 011. Referring to Figure 3E, the optimized aging detector 011 may include: a resistor voltage divider circuit; the resistor voltage divider circuit includes: a first detection resistor RA1, a second detection resistor RA2, a first detection capacitor CA1, and a second detection capacitor CA2;

[0106] The first terminal of the first detection resistor RA1 is electrically connected to the first terminal of the first detection capacitor CA1 and the gate drive signal terminal (output gate drive signal Gout). The second terminal of the first detection resistor RA1 is electrically connected to the first terminal of the second detection resistor RA2, the second terminal of the first detection capacitor CA1, and the first terminal of the second detection capacitor CA2.

[0107] The second terminal of the second detection resistor RA2 is electrically connected to the detection reference voltage terminal VAref and the second terminal of the second detection capacitor CA2.

[0108] In this embodiment, the detection circuit 022 can acquire the gate drive signal Gout through a resistor divider circuit, converting the voltages of the first power supply voltage VGH to the second power supply voltage VGL corresponding to the gate drive signal Gout into a voltage range of 5V to 0V. The power management chip internally identifies the rise time Tr of the gate drive signal Gout and converts Tr into a 3.3V / 0V square wave signal. The high-level time of the square wave signal is equal to the rise time Tr. The power management chip can send the square wave signal to the microcontroller unit (MCU). The MCU calculates the rise time Tr and compares it with a first duration threshold, then sets the target first power supply voltage and writes it to the power transistor chip via I2C, thereby adjusting the output of the first power supply voltage VGH. Optionally, the optimized aging detector 011 can be an optimized aging detection chip.

[0109] In one possible implementation, as shown in Figures 3A and 3F, the power management chip further includes: a second voltage generation circuit 03 configured to output a second power supply voltage VGL; the second power supply voltage VGL being less than a first power supply voltage VGH; and a voltage adjustment circuit 02, further connected to the second voltage generation circuit 03, configured to control the second voltage generation circuit 02 to adjust the output second power supply voltage VGL in response to a detection parameter.

[0110] The power management chip provided in this embodiment further includes a second voltage generation circuit 03 and a voltage adjustment circuit 02, which are also configured to control the second voltage generation circuit 02 to adjust the output second power supply voltage VGL in response to the detection parameters. This allows the power management chip to dynamically adjust the second power supply voltage VGL according to changes in the external environment or the output of the gate drive circuit, thereby improving the driving capability of the power management chip.

[0111] In one possible implementation, as shown in Figures 3A and 3F, the second voltage generation circuit 03 is connected to the temperature detection and control circuit 021, and the detection parameters include: temperature parameters; the temperature detection and control circuit 021 is also configured to control the second voltage generation circuit 02 to adjust the output second power supply voltage VGL in response to the temperature parameters.

[0112] In one possible implementation, the second voltage generation circuit 03 includes a buck circuit.

[0113] In one possible implementation, as shown in Figures 3A and 3F, the second voltage generation circuit 03 includes: a second transistor T2, a third transistor T3, a first resistor R1, and a third capacitor C3.

[0114] The control terminal of the second transistor T2 is electrically connected to the first terminal of the first resistor R1, the control terminal of the third transistor T3, and the first buck pin CTRVGL (i.e., the pin labeled 1). The first terminal of the second transistor T2 is grounded. The second terminal of the second transistor T2 is electrically connected to the second terminal of the first resistor T2, the first terminal of the third transistor T3, the first terminal of the third capacitor C3, the second voltage output terminal (outputting the second power supply voltage signal VGL), and the second buck pin (i.e., the pin labeled 2).

[0115] The second terminal of the third transistor T3 is electrically connected to the second voltage input terminal LVGL.

[0116] The second terminal of the third capacitor C3 is connected to ground.

[0117] In one possible implementation, the resistance of the first resistor R1 can be 1kΩ; the capacitance of the third capacitor C3 can be 4.7μF.

[0118] In one possible implementation, as shown in Figures 3A and 3F, the second voltage generation circuit 03 further includes: a negative regulator controller 031; the first input terminal of the negative regulator controller 031 can be electrically connected to the temperature compensation circuit 0213, the second input terminal of the negative regulator controller 031 can be electrically connected to the registers & logic control, the first output terminal of the negative regulator controller 031 can be electrically connected to the first step-down pin CTRVGL (i.e., the pin labeled 1), and the second output terminal of the negative regulator controller 031 can be connected to the second step-down pin (i.e., the pin labeled 2); the negative regulator controller 031 can receive signals from the registers & logic control and the temperature compensation circuit 0213, and output a second power supply voltage VGL according to the signals from the registers & logic control and the temperature compensation circuit 0213.

[0119] In one possible implementation, as shown in Figures 3A and 3G, the power management chip includes: a gamma circuit group 04; the gamma circuit group 04 is configured to output multiple gamma voltages; wherein the gamma circuit group includes: at least five gamma circuits. Optionally, for example, as shown in Figures 3A and 3G, the gamma circuit group 04 includes: ten gamma circuits.

[0120] In this embodiment of the disclosure, the power management chip includes at least five gamma circuits. For conventional display products, there is no need to add an additional gamma chip (Gamma IC), thus reducing the space and cost of peripheral circuits.

[0121] In one possible implementation, as shown in Figures 3A and 3G, the gamma circuit includes: a digital-to-analog converter (D1-D10), an amplifier (F1-F10), a gamma resistor (RG1-RG10), and a gamma capacitor (CG1-CG10); optionally, the digital-to-analog converter (D1-D10) can be a 10-bit digital-to-analog converter.

[0122] The first terminal of the digital-to-analog converter (D1~D10) is electrically connected to the first reference voltage terminal VREF_O, and the second terminal of the digital-to-analog converter (D1~D10) is electrically connected to the first terminal of the amplifier (F1~F10).

[0123] The second terminal of the amplifier (F1~F10) is electrically connected to the gamma pin (pins labeled 39-48);

[0124] The first terminal of the gamma resistor (RG1~RG 10) is electrically connected to the gamma pin terminal (pin terminal numbered 39-48), and the second terminal of the gamma resistor (RG1~RG 10) is electrically connected to the first terminal of the gamma capacitor (CG1~CG 10) and the gamma voltage output terminal (GAM1~GAM 10).

[0125] The second terminal of the gamma capacitor (CG1~CG10) is connected to ground.

[0126] Optionally, the resistance values ​​of each gamma resistor can be equal, for example, all can be 0Ω; optionally, the capacitance values ​​of each gamma capacitor can be equal, for example, all can be 0.1μF.

[0127] In one possible implementation, as shown in Figures 3A and 3H, the power management chip further includes an analog voltage circuit 05, which is electrically connected to the registers and logic control, and can receive signals sent by the registers and logic control and output an analog voltage AVDD.

[0128] In one possible implementation, as shown in Figures 3A and 3H, the analog voltage circuit 05 includes: a main step-up controller 051, a first analog transistor T51, a second analog transistor T52, a third analog transistor T53, an analog Zener diode T54, an analog inductor L51, a first analog resistor R51, a second analog resistor R52, a third analog resistor R53, a first analog capacitor C51, a second analog capacitor C52, a third analog capacitor C53, a fourth analog capacitor C54, a fifth analog capacitor C55, and a sixth analog capacitor C56.

[0129] The first input of the main boost controller 051 can be connected to the registers & logic controller. The main boost controller 051 has the following electrical connections: its first output can be electrically connected to the first analog pin COMP (pin number 56); its second output can be electrically connected to the second analog pin (pin number 51); its third output can be electrically connected to the third analog pin ISO_DRVA (pin number 52); its fourth output can be electrically connected to the fourth analog pin ISO_INA (pin number 53); its fifth output can be electrically connected to the fifth analog pin LX / CS (pin number 54) and the first terminal of the first analog transistor T51; its sixth output can be electrically connected to the sixth analog pin (pin number 57); and its seventh output can be electrically connected to the control terminal of the first analog transistor T51.

[0130] The second terminal of the first analog transistor T51 can be electrically connected to the seventh analog pin PGND (i.e., the pin labeled 55); the other side of the seventh analog pin PGND (i.e., the pin labeled 55) can be grounded.

[0131] The control terminal of the second analog transistor T52 can be electrically connected to the sixth analog pin (i.e., pin number 57) and the first terminal of the second analog resistor R51. The first terminal of the second analog transistor T52 can be electrically connected to the first terminal of the first analog resistor R51 and the fifth analog pin LX / CS (i.e., pin number 54). The second terminal of the second analog transistor T52 can be electrically connected to the first terminal of the analog inductor L51 and the first terminal of the analog Zener diode T54. The second terminal of the first analog resistor R51 is grounded, and the second terminal of the second analog resistor R52 is grounded.

[0132] The control terminal of the third analog transistor T53 can be electrically connected to the third analog pin ISO_DRVA (i.e., pin number 52), the first terminal of the third analog capacitor C53, and the first terminal of the fourth analog capacitor C54. The first terminal of the third analog transistor T53 can be electrically connected to the second terminal of the analog Zener diode T54, the first terminal of the second analog capacitor C52, the second terminal of the third analog capacitor C53, and the fourth analog pin ISO_INA (i.e., pin number 53). The second terminal of the third analog transistor T53 can be electrically connected to the second terminal of the fourth analog capacitor C54, the first terminal of the fifth analog capacitor C55, the second analog pin (i.e., pin number 51), and the analog voltage output terminal (i.e., the output analog voltage VAVDD). The second terminal of the second analog capacitor C52 is grounded, and the second terminal of the fifth analog capacitor C55 is grounded.

[0133] The second terminal of the analog inductor L51 is electrically connected to the first terminal of the first analog capacitor C51; the second terminal of the first analog capacitor C51 is grounded.

[0134] The first terminal of the third analog resistor R53 can be electrically connected to the first analog pin terminal COMP (i.e., the pin terminal labeled 56), and the second terminal of the third analog resistor R53 can be electrically connected to the first terminal of the sixth analog capacitor C56; the second terminal of the sixth analog capacitor C56 is grounded.

[0135] In one possible implementation, the analog inductor L51 can be 10μH; the first analog resistor R51 can be 30mΩ; the second analog resistor R52 can be 20kΩ; the third analog resistor R53 can be 160kΩ; the first analog capacitor C51 can be 10μF; the second analog capacitor C52 can be 10μF; the third analog capacitor C53 can be 4.7nF; the fourth analog capacitor C54 can be 470pF; the fifth analog capacitor C55 can be 10μF; and the sixth analog capacitor C56 can be 470pF.

[0136] In one possible implementation, as shown in Figures 3A and 3I, the power management chip further includes a multi-voltage generation circuit group 06, which is electrically connected to the registers and logic control and can receive signals sent by the registers and logic control and output multiple voltages.

[0137] In one possible implementation, as shown in Figures 3A and 3I, the multi-voltage generation circuit group 06 may include: an input / output voltage generation circuit 061, a drop voltage generation circuit 062, a core power supply voltage generation circuit 063, and a semi-analog power supply voltage generation circuit 064; wherein, the input / output voltage generation circuit 061 is configured to generate an input / output voltage VIO; the drop voltage generation circuit 062 is configured to generate a drop voltage VDO; the core power supply voltage generation circuit 063 is configured to generate a core power supply voltage VCORE; and the semi-analog power supply voltage generation circuit 064 is configured to generate a semi-analog power supply voltage HAVDD.

[0138] The input / output voltage generation circuit 061 includes: a synchronous buck converter 1, a first buck transistor T611, a second buck transistor T612, a first buck Zener diode T613, a first buck capacitor C611, a second buck capacitor C612, and a first buck inductor L61.

[0139] The first input terminal of the synchronous buck converter 1 can be electrically connected to the registers & logic control, the first output terminal of the synchronous buck converter 1 can be electrically connected to the first buck pin VIO (i.e., the pin labeled 20), the second output terminal of the synchronous buck converter 1 can be electrically connected to the control terminal of the first buck diode T611, and the third output terminal of the synchronous buck converter 1 can be electrically connected to the control terminal of the second buck diode T612.

[0140] The first terminal of the first step-down diode T611 is electrically connected to the second step-down pin VIN12 (i.e., the pin labeled 24), and the second terminal of the first step-down diode T611 is electrically connected to the first terminal of the second step-down diode T612 and the third step-down pin LX1 (i.e., the pin labeled 22).

[0141] The second terminal of the second step-down diode T612 is electrically connected to the fourth step-down pin PGND1 (i.e., the pin labeled 21); the fourth step-down pin PGND1 (i.e., the pin labeled 21) can be grounded;

[0142] The first terminal of the first step-down Zener diode T613 can be electrically connected to the third step-down pin LX1 (i.e., the pin labeled 22) and the first terminal of the first step-down inductor L61, and the second terminal of the first step-down Zener diode T613 is grounded.

[0143] The second terminal of the first step-down inductor L61 is electrically connected to the first terminal of the second step-down capacitor C612, the input / output voltage output terminal (which can output the input / output voltage VIO), and the first step-down pin VIO (i.e., the pin labeled 20). The second terminal of the second step-down capacitor C612 is grounded.

[0144] The first terminal of the first step-down capacitor C611 is electrically connected to the first step-down input terminal (which can input the start signal VIN) and the second step-down pin terminal VIN12 (that is, the pin terminal labeled 24), and the second terminal of the first step-down capacitor C611 is grounded.

[0145] The capacitance of the first step-down capacitor C611 can be 10μF, the capacitance of the second step-down capacitor C612 can be 10μF, and the capacitance of the first step-down inductor L61 can be 10μH.

[0146] The voltage drop generation circuit 062 includes: a synchronous buck converter 2, a fourth buck transistor T621, a fifth buck transistor T622, a second buck Zener diode T623, a third buck capacitor C621, and a second buck inductor L62.

[0147] The first input terminal of the synchronous buck converter 2 can be electrically connected to the registers & logic control, the first output terminal of the synchronous buck converter 2 can be electrically connected to the fifth buck pin terminal (i.e., the pin terminal labeled 28), the second output terminal of the synchronous buck converter 2 can be electrically connected to the control terminal of the fourth buck diode T621, and the third output terminal of the synchronous buck converter 2 can be electrically connected to the control terminal of the fifth buck diode T622.

[0148] The first terminal of the fourth step-down diode T621 is electrically connected to the first terminal of the first step-down diode T611, and the second terminal of the fourth step-down diode T621 is electrically connected to the first terminal of the fifth step-down diode T622 and the sixth step-down pin terminal LX2 (i.e., the pin terminal labeled 26).

[0149] The second terminal of the fifth step-down diode T622 is electrically connected to the seventh step-down pin PGND2 (i.e., pin number 27); the seventh step-down pin PGND2 (i.e., pin number 27) can be grounded;

[0150] The first terminal of the second step-down Zener diode T623 can be electrically connected to the sixth step-down pin LX2 (i.e., the pin labeled 26) and the first terminal of the second step-down inductor L62, and the second terminal of the second step-down Zener diode T623 is grounded.

[0151] The second terminal of the second step-down inductor L62 is electrically connected to the first terminal of the third step-down capacitor C621, the voltage drop output terminal (which can output voltage drop VDD), and the fifth step-down pin terminal (i.e., the pin terminal labeled 28). The second terminal of the third step-down capacitor C621 is grounded.

[0152] The third step-down capacitor C621 can have a capacitance of 10μF, and the second step-down inductor L62 can have a capacitance of 10μH.

[0153] The core power supply voltage generation circuit 063 includes: a synchronous buck converter 3, a first core transistor T631, a second core transistor T632, a first core Zener diode T633, a first core capacitor C631, a second core capacitor C632, and a first core inductor L63.

[0154] The first input terminal of the synchronous buck converter 3 can be electrically connected to the registers & logic control, the first output terminal of the synchronous buck converter 3 can be electrically connected to the control terminal of the first core diode T631, and the second output terminal of the synchronous buck converter 3 can be electrically connected to the control terminal of the second core diode T632.

[0155] The first terminal of the first core diode T631 is electrically connected to the first core pin terminal VIN13 (i.e., the pin terminal labeled 33), and the second terminal of the first core diode T631 is electrically connected to the first terminal of the second core diode T632 and the second core pin terminal LX3 (i.e., the pin terminal labeled 31).

[0156] The second terminal of the second core diode T632 is electrically connected to the third core pin terminal PGND3 (i.e., the pin terminal labeled 30); the third core pin terminal PGND3 (i.e., the pin terminal labeled 30) can be grounded;

[0157] The first terminal of the first core Zener diode T633 can be electrically connected to the second core pin terminal LX3 (i.e., the pin terminal labeled 31) and the first terminal of the first core inductor L63, and the second terminal of the first core Zener diode T633 is grounded.

[0158] The second terminal of the first core inductor L63 is electrically connected to the first terminal of the second core capacitor C632 and the core power supply voltage output terminal (which can output the core power supply voltage VCORE). The second terminal of the second core capacitor C632 is grounded.

[0159] The first terminal of the first core capacitor C631 is electrically connected to the first core input terminal (which can input the start signal VIN) and the first core pin terminal VIN13 (that is, the pin terminal labeled 33), and the second terminal of the first core capacitor C631 is grounded.

[0160] Optionally, the capacitance of the first core capacitor C631 can be 10μF, the capacitance of the second core capacitor C632 can be 22μF, and the capacitance of the first core inductor L63 can be 10μH.

[0161] The semi-analog power supply voltage generation circuit 064 includes: a synchronous buck converter 4, a first semi-analog transistor T641, a second semi-analog transistor T642, a first semi-analog capacitor C641, a second semi-analog capacitor C642, a first semi-analog inductor L64, a first semi-analog resistor R641, and a second semi-analog resistor R642.

[0162] The first input terminal of the synchronous buck converter 4 can be electrically connected to the registers & logic control, the first output terminal of the synchronous buck converter 4 can be electrically connected to the first half-analog pin terminal (i.e., the pin terminal labeled 37), the second output terminal of the synchronous buck converter 4 can be electrically connected to the control terminal of the first half-analog diode T641, and the third output terminal of the synchronous buck converter 4 can be electrically connected to the control terminal of the second half-analog diode T642.

[0163] The first terminal of the first half-analog diode T641 is electrically connected to the second half-analog pin VIN14 (i.e., pin number 36), and the second terminal of the first half-analog diode T641 is electrically connected to the first terminal of the second half-analog diode T642 and the third half-analog pin LX4 (i.e., pin number 35).

[0164] The second terminal of the second half-analog diode T642 is electrically connected to the fourth half-analog pin PGND4 (i.e., pin number 34); the fourth half-analog pin PGND4 (i.e., pin number 34) can be grounded.

[0165] The first terminal of the first half-analog inductor L64 is electrically connected to the third half-analog pin terminal LX4 (i.e., the pin terminal labeled 35). The second terminal of the first half-analog inductor L64 is electrically connected to the first terminal of the second half-analog capacitor C642 and the first half-analog power supply voltage output terminal (which can be a half-analog power supply voltage VHAVDD). The second terminal of the second half-analog capacitor C642 is grounded.

[0166] The first terminal of the first half-analog capacitor C641 is electrically connected to the second half-analog pin VIN14 (i.e., pin number 36). The second terminal of the first half-analog capacitor C641 can be electrically connected to the first terminal of the first half-analog resistor R641 and the first terminal of the second half-analog resistor R642. The second terminal of the first half-analog resistor R641 can be connected to the second half-analog power supply voltage output terminal (which can output the start signal VIN), and the second terminal of the second half-analog resistor R642 can be connected to the third half-analog power supply voltage output terminal (which can output the analog power supply voltage VADD).

[0167] Optionally, the capacitance of the first half-analog capacitor C641 can be 10μF, the capacitance of the second half-analog capacitor C642 can be 10μF, the capacitance of the first half-analog inductor L64 can be 10μH, the capacitance of the first half-analog resistor R641 can be 0Ω, and the capacitance of the second half-analog resistor R642 can be a thermistor.

[0168] In one possible implementation, as shown in Figures 3A and 3J, the power management chip further includes: a noise reduction circuit 07; the noise reduction circuit 07 can be electrically connected to the registers and logic control, can receive from the registers and logic control, and output a noise reduction signal LVGL;

[0169] The noise reduction circuit 07 may include: an inverter switch 071, a first noise reduction inductor L71, a first noise reduction transistor T71, a first noise reduction Zener diode T72, a first noise reduction capacitor C71, and a second noise reduction capacitor C72.

[0170] The first input terminal of the inverter switch 071 can be electrically connected to the registers & logic control, the first output terminal of the inverter switch 071 can be electrically connected to the control electrode of the first noise reduction transistor T71, and the second output terminal of the inverter switch 071 can be connected to the first noise reduction pin terminal (i.e., the pin terminal labeled 3).

[0171] The first terminal of the first noise reduction transistor T71 is electrically connected to the second noise reduction pin (i.e., pin number 5), and the first terminal of the first noise reduction transistor T71 is electrically connected to the third noise reduction pin VXN (i.e., pin number 4).

[0172] The first terminal of the first noise-reducing Zener transistor T72 is electrically connected to the first terminal of the first noise-reducing inductor L71 and the third noise-reducing pin VXN (i.e., pin number 4). The second terminal of the first noise-reducing Zener transistor T72 is electrically connected to the first terminal of the first noise-reducing capacitor C71, the noise-reducing output terminal (which can output the noise-reducing voltage LVGL), and the first noise-reducing pin (i.e., pin number 3). The second terminal of the first noise-reducing inductor L71 is grounded. The second terminal of the first noise-reducing capacitor C71 is grounded.

[0173] The first terminal of the second noise reduction capacitor C72 is electrically connected to the first noise reduction input terminal (which can input the start signal VIN) and the second noise reduction pin terminal (that is, the pin terminal labeled 5), and the second terminal of the second noise reduction capacitor C72 is grounded.

[0174] The first noise reduction inductor L71 can be 10μH, the first noise reduction capacitor C71 can be 10μF, and the second noise reduction capacitor C72 can be 10μF.

[0175] In one possible implementation, as shown in Figures 3A and 3K, the power management chip further includes: a linear voltage regulator circuit 08;

[0176] The linear voltage regulator circuit 08 may include: Registers & Logic control 081, internal linear voltage regulator circuit 082, first voltage regulator capacitor C81, and second voltage regulator capacitor C82.

[0177] The first input terminal of the internal linear regulator circuit 082 can be electrically connected to the first regulator pin AVIN (i.e., pin number 7), the second input terminal of the internal linear regulator circuit 082 can be electrically connected to the second regulator pin VL (i.e., pin number 9), and the output terminal of the internal linear regulator circuit 082 can be electrically connected to the register & logic controller 081.

[0178] The first terminal of the first voltage regulator capacitor C81 is electrically connected to the second voltage regulator pin VL (i.e., the pin labeled 9), and the second terminal of the first voltage regulator capacitor C81 is grounded.

[0179] The first terminal of the second voltage regulator capacitor C82 is electrically connected to the linear regulator input terminal (which can input the start signal VIN) and the first voltage regulator pin terminal AVIN (i.e., the pin terminal labeled 7), and the second terminal of the second voltage regulator capacitor C82 is grounded.

[0180] Optionally, the capacitance of the first voltage regulator capacitor C81 can be 1μF, and the capacitance of the second voltage regulator capacitor C82 can be 10μF.

[0181] In one possible implementation, as shown in Figures 3A and 3L, the power management chip further includes: an interface logic control circuit 09;

[0182] The first input terminal of the interface logic control circuit 09 is electrically connected to the first interface pin SDA (i.e., the pin labeled 14), the second input terminal of the interface logic control circuit 09 is electrically connected to the second interface pin SCL, and the output terminal of the interface logic control circuit 09 is electrically connected to the registers & logic control.

[0183] In one possible implementation, as shown in Figures 3A and 3M, the power management chip further includes a discharge circuit 010.

[0184] The discharge circuit 010 includes: a first comparator 101, a first discharge resistor R101, a second discharge resistor R102, and a third discharge resistor R103.

[0185] The first input terminal of the first comparator 101 is electrically connected to the first discharge pin terminal VDET (i.e., the pin terminal labeled 11), the second input terminal of the first comparator 101 is connected to the reference voltage terminal (a reference voltage VREF can be input), and the output terminal of the first comparator 101 can be electrically connected to the second discharge pin terminal XAO (i.e., the pin terminal labeled 12).

[0186] The first end of the first discharge resistor R101 is electrically connected to the second discharge pin XAO (i.e., the pin labeled 12), and the second end of the first discharge resistor R101 can be electrically connected to the input / output voltage signal terminal (the input / output voltage VIO can be applied).

[0187] The first end of the second discharge resistor R102 can be electrically connected to the input / output voltage signal terminal (the input / output voltage VIO can be applied), and the second end of the second discharge resistor R102 can be electrically connected to the first end of the third discharge resistor R103 and the first discharge pin VDET (that is, the pin labeled 11); the second end of the third discharge resistor R103 is grounded.

[0188] Optionally, the resistance of the first discharge resistor R101 can be 10kΩ.

[0189] In one possible implementation, as shown in Figures 3A and 3N, the power management chip further includes a common voltage generation circuit 011;

[0190] The common voltage generation circuit 011 includes: an amplifier 111, a common voltage limiter 112, a common voltage digital-to-analog converter 113, a first common resistor R11, a first common capacitor C111, and a second common capacitor C112; optionally, the common voltage digital-to-analog converter 113 can be a 7-bit digital-to-analog converter.

[0191] The first input terminal of amplifier 111 is electrically connected to the common voltage limiter 112, the second input terminal of amplifier 111 is electrically connected to the first output terminal and the first common pin terminal (i.e., the pin terminal labeled 49), the third input terminal of amplifier 111 is electrically connected to the first input signal terminal SUPG, and the second output terminal of amplifier 111 is grounded.

[0192] Common voltage limiter 112 can be electrically connected to common voltage digital-to-analog converter 113;

[0193] The first end of the first common resistor R11 is electrically connected to the first common pin (i.e., pin number 49), the second end of the first common resistor R11 is electrically connected to the first end of the first common capacitor C111, and the common voltage output terminal (which can output the common voltage VCOM); the second end of the first common capacitor C111 is grounded.

[0194] The first terminal of the second common capacitor C112 is electrically connected to the analog power supply voltage signal terminal (which can input the analog power supply voltage VAVDD) and the second common pin terminal (i.e., the pin terminal labeled 50), and the second terminal of the second common capacitor C112 is grounded.

[0195] Optionally, the resistance of the first common resistor R11 can be 4.7Ω, the capacitance of the first common capacitor C111 can be 4.7μF, and the capacitance of the second common capacitor C112 can be 1μF.

[0196] Based on the same inventive concept, embodiments of this disclosure also provide a power management device, which includes the power management chip provided in embodiments of this disclosure.

[0197] Based on the same inventive concept, this disclosure also provides a display device, which includes a display panel and a power management device, wherein the power management device is the power management device provided in this disclosure embodiment, and the power management device can be electrically connected to the display panel.

[0198] In one possible implementation, the display panel may have a display area and a peripheral area located around the display area, wherein the peripheral area may be provided with a gate driving circuit, and the power management chip provided in this embodiment may be electrically connected to the gate driving circuit.

[0199] In some embodiments, the display device provided in this disclosure can be any product or component with display function, such as a projector, 3D printer, virtual reality device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, smartwatch, fitness wristband, or personal digital assistant. Optionally, the display device provided in this disclosure includes, but is not limited to, components such as a radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, and control chip. Optionally, the control chip is a central processing unit, digital signal processor, system-on-a-chip (SoC), etc. For example, the control chip may also include a memory, a power module, etc., and achieve power supply and signal input / output functions through additionally provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer-executable code. The hardware circuit may include conventional very-large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field-programmable gate arrays, programmable array logic, programmable logic devices, etc. Furthermore, those skilled in the art will understand that the above structure does not constitute a limitation on the display device provided in the embodiments of this disclosure. In other words, the display device provided in the embodiments of this disclosure may include more or fewer of the above components, or combine certain components, or have different component arrangements.

[0200] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0201] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations to the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.

Claims

1. A power management chip, wherein, include: The first voltage generation circuit is configured to output a first power supply voltage; A voltage adjustment circuit, connected to the first voltage generation circuit, is configured to control the first voltage generation circuit to adjust the output first power supply voltage in response to a detected parameter.

2. The power management chip as described in claim 1, wherein, The detection parameters include: temperature parameters; The voltage adjustment circuit includes a temperature detection and control circuit; the temperature detection and control circuit is connected to the first voltage generation circuit and is configured to control the first power supply voltage output by the first voltage generation circuit to decrease in response to the temperature parameter being greater than the temperature threshold, and to control the first power supply voltage output by the first voltage generation circuit to increase in response to the temperature parameter being less than the temperature threshold.

3. The power management chip of claim 2, wherein, The temperature detection and control circuit includes: a first temperature-sensitive circuit and a second temperature-sensitive circuit; The first temperature-sensitive circuit is configured to generate a first electrical signal corresponding to a first temperature range; The second temperature-sensitive circuit is configured to generate a second electrical signal corresponding to a second temperature range, wherein the first temperature range is greater than the second temperature range.

4. The power management chip as described in claim 3, wherein, The first temperature-sensitive circuit includes: a first temperature-sensitive resistor, a second temperature-sensitive resistor, and a third temperature-sensitive resistor; The first terminal of the first temperature-sensitive resistor is electrically connected to the first power supply voltage terminal, and the second terminal is electrically connected to the first terminal of the second temperature-sensitive resistor and the first terminal of the third temperature-sensitive resistor. The second terminal of the second thermistor and the second terminal of the third thermistor are connected to ground.

5. The power management chip of claim 3 or 4, wherein, The second temperature-sensitive circuit includes: a fourth temperature-sensitive resistor, a fifth temperature-sensitive resistor, and a sixth temperature-sensitive resistor; The first terminal of the fourth thermistor is electrically connected to the second power supply voltage terminal, and the second terminal is electrically connected to the first terminal of the fifth thermistor and the second terminal of the sixth thermistor. The second terminal of the fifth thermistor and the second terminal of the sixth thermistor are connected to ground.

6. The power management chip of claim 4 or 5, wherein, The second thermistor is a negative temperature coefficient resistor; And / or, the fifth thermistor is a negative temperature coefficient resistor.

7. The power management chip of any of claims 1-6, wherein, The detection parameters include: the set duration of the gate drive signal; The voltage adjustment circuit further includes a detection circuit; the detection circuit is connected to the first voltage generation circuit and is configured to receive the gate drive signal and, in response to the set duration of the gate drive signal, control the first voltage generation circuit to adjust the output first power supply voltage.

8. The power management chip of claim 7, wherein, The set duration includes: the rising edge duration of the gate drive signal; The detection circuit is further configured to control the voltage of the first power supply voltage output by the first voltage generation circuit to increase in response to the rising edge duration of the received gate drive signal being greater than a first duration threshold, and to control the voltage of the first power supply voltage output by the first voltage generation circuit to decrease in response to the rising edge duration of the received gate drive signal being less than the first duration threshold.

9. The power management chip of claim 7, wherein, The set duration includes: the duration of holding the first level of the gate drive signal; the first level is used to control the transistor in the gate drive circuit to turn on; The detection circuit is further configured to control the voltage of the first power supply voltage output by the first voltage generation circuit to increase in response to the holding duration of the received gate drive signal being greater than a second duration threshold, and to control the voltage of the first power supply voltage output by the first voltage generation circuit to decrease in response to the holding duration of the received gate drive signal being less than the second duration threshold.

10. The power management chip of any of claims 1-9, wherein, The first voltage generation circuit includes a boost circuit.

11. The power management chip of any of claims 1-10, wherein, The first voltage generation circuit includes: a first inductor, a first capacitor, a second capacitor, a first Zener diode, and a first transistor; The first terminal of the first transistor is electrically connected to the first boost pin terminal, and the second terminal of the first transistor is electrically connected to the second boost pin terminal; The first terminal of the first Zener diode is electrically connected to the first boost pin and the first terminal of the first resistor, and the second terminal of the first Zener diode is electrically connected to the first terminal of the first capacitor, the first voltage output terminal, and the third boost pin. The second end of the first inductor is electrically connected to the first boost reference signal terminal and the first end of the first capacitor; The second terminal of the first capacitor is connected to ground. The second terminal of the second capacitor is connected to ground.

12. The power management chip of any of claims 1-11, wherein, The power management chip further includes: a second voltage generation circuit configured to output a second power supply voltage; the second power supply voltage is less than the first power supply voltage; The voltage adjustment circuit is also connected to the second voltage generation circuit and is configured to control the second voltage generation circuit to adjust the output second power supply voltage in response to the detection parameter.

13. The power management chip of claim 12, wherein, The second voltage generation circuit includes a step-down circuit.

14. The power management chip of claim 12 or 13, wherein, The second voltage generation circuit includes: a second transistor, a third transistor, a first resistor, and a third capacitor; The control terminal of the second transistor is electrically connected to the first terminal of the first resistor, the control terminal of the third transistor, and the first buck pin terminal. The first terminal of the second transistor is grounded. The second terminal of the second transistor is electrically connected to the second terminal of the first resistor, the first terminal of the third transistor, the first terminal of the third capacitor, the second voltage output terminal, and the second buck pin terminal. The second terminal of the third transistor is electrically connected to the second voltage input terminal; The second terminal of the third capacitor is connected to ground.

15. The power management chip of any of claims 1-14, wherein, The power management chip includes a gamma circuit group; the gamma circuit group is configured to output multiple gamma voltages. The gamma circuit group includes at least five gamma circuits.

16. The power management chip of claim 15, wherein, The gamma circuit includes: a digital-to-analog converter, an amplifier, a gamma resistor, and a gamma capacitor; The first terminal of the digital-to-analog converter is electrically connected to the first reference voltage terminal, and the second terminal of the digital-to-analog converter is electrically connected to the first terminal of the amplifier; The second terminal of the amplifier is electrically connected to the gamma pin terminal; The first end of the gamma resistor is electrically connected to the gamma pin, and the second end of the gamma resistor is electrically connected to the first end of the gamma capacitor and the gamma voltage output terminal. The second terminal of the gamma capacitor is connected to ground.

17. The power management chip of claim 15 or 16, wherein, The gamma circuit group includes ten gamma circuits.

18. A power management device, wherein, Includes the power management chip as described in any one of claims 1-17.

19. A display device comprising a display panel and a power management apparatus, wherein, The power management device is the power management device of claim 18.

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