Display substrate and method for operating same, and display apparatus

Abstract

A display substrate and a method for operating same, and a display apparatus. The display substrate comprises a base substrate, which base substrate comprises an active area (AA) and a first border area (B1). The active area (AA) comprises a plurality of sub-pixels (Pxij) and a plurality of data lines (DL), wherein the plurality of data lines (DL) are electrically connected to the plurality of sub-pixels (Pxij). The first border area (B1) comprises a plurality of data output lines (DT) and a plurality of driving pads (PA1), wherein one end of each data output line (DT) is connected to a corresponding data line (DL), and the other end thereof is connected to a corresponding driving pad (PA1). A shielding structure (PL) comprises a first shielding structure (PL1) located in the first border area (B1), wherein the orthographic projection of at least part of the structure of the plurality of data output lines (DT) on the base substrate is within the range of the orthographic projection of the first shielding structure (PL1) on the base substrate, and in the direction perpendicular to a plane where the base substrate is located, the shielding structure (PL) is located between the data output line (DT) and the base substrate.

Description

Display substrate and its working method, display device Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, specifically to a display substrate and its working method, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] In a first aspect, embodiments of this disclosure provide a display substrate, comprising:

[0005] A substrate, the substrate including a display area and a border area surrounding the display area, the border area including a first border area located on one side of the display area;

[0006] Multiple sub-pixels are located on one side of the substrate and in the display area;

[0007] Multiple data lines are located in the display area and electrically connected to the multiple sub-pixels;

[0008] Multiple data output lines are located in the first border area and are electrically connected to the multiple data lines;

[0009] Multiple driver pads are located in the first frame area and on the side of the multiple data output lines away from the display area; each of the multiple data output lines is connected to a corresponding data line at the end closer to the display area and to a corresponding driver pad at the end away from the display area.

[0010] A shielding structure, comprising a first shielding structure located in the first border region, wherein at least a portion of the structure of at least one of the plurality of data output lines is projected onto the substrate and the orthographic projection of the first shielding structure onto the substrate is within the range of the orthographic projection of the first shielding structure onto the substrate; and in a direction perpendicular to the plane of the substrate, the shielding structure is located between the at least one data output line and the substrate.

[0011] In an exemplary embodiment, the first border region has a bend area;

[0012] In the bending region, the first shielding structure includes a plurality of shielding strips, which extend along a second direction and are spaced apart along a first direction. The plurality of digital output lines extend along the second direction and are spaced apart along the first direction. In a plane parallel to the substrate, the first direction intersects the second direction. The portion of the plurality of digital output lines located in the bending region has its orthographic projection on the substrate within the orthographic projection of the plurality of shielding strips on the substrate.

[0013] In an exemplary embodiment, the plurality of data output lines correspond one-to-one with the plurality of shielding strips, and the orthographic projection of each of the plurality of data output lines on the substrate is located within the range of the orthographic projection of the corresponding shielding strip on the substrate.

[0014] In an exemplary embodiment, the first border region has a bend area;

[0015] In the bending area, the first shielding structure is provided with a plurality of groove structures, the plurality of groove structures extend along the second direction and are arranged at intervals along the first direction, the plurality of data output lines extend along the second direction and are arranged at intervals along the first direction, at least one data output line is provided between two adjacent groove structures in the first direction, and the first direction intersects the second direction in a plane parallel to the substrate.

[0016] In an exemplary embodiment, in the bending area, a shielding strip is formed between two adjacent groove structures in the first direction. The plurality of data output lines correspond one-to-one with the plurality of shielding strips, and the orthogonal projection of the data output line on the substrate is located within the range of the orthogonal projection of the corresponding shielding strip on the substrate.

[0017] In an exemplary embodiment, the groove structure is configured as a hollow structure that penetrates the first shielding structure in a direction perpendicular to the plane of the substrate.

[0018] In an exemplary embodiment, within the same shielding strip, on the same side of the first centerline in the first direction, the distance between the edge of the shielding strip and the edge of the nearest data output line is greater than or equal to 0.3 micrometers, and the first centerline is the centerline of the shielding strip extending along the second direction.

[0019] In an exemplary embodiment, within the same groove structure, on the same side of the second centerline in the first direction, the distance between the edge of the groove structure and the edge of the nearest data output line is greater than or equal to 0.3 micrometers, and the second centerline is the centerline of the groove structure extending along the second direction.

[0020] In an exemplary embodiment, at least one of the plurality of sub-pixels includes a plurality of transistors. In a direction perpendicular to the plane of the substrate, at least one of the transistors includes: an active layer located on one side of the substrate, a gate located on the side of the active layer away from the substrate, and a source and a drain located on the side of the gate away from the substrate.

[0021] The shielding structure is disposed on the same layer as the gate of at least one of the transistors; or, in a direction perpendicular to the plane of the substrate, the shielding structure is located between the active layer of at least one of the transistors and the substrate.

[0022] In an exemplary embodiment, the display substrate further includes a shielding layer, wherein in a direction perpendicular to the plane of the substrate, in a structure where the shielding structure is located between the active layer of at least one transistor and the substrate, the shielding structure and the shielding layer are disposed in the same layer.

[0023] In an exemplary embodiment, the direction from the display area to the first border area, the first border area includes a multiplexed circuit area, a bending area and a signal access area arranged sequentially;

[0024] In the bending region, the data output line is located on the side of the source and drain that is away from the substrate.

[0025] In an exemplary embodiment, the at least one sub-pixel further includes at least one capacitor, the plurality of transistors include at least one first type transistor, the active layer includes the active layer of the at least one first type transistor, the gate includes the gate of the at least one first type transistor, the first plate of the capacitor is disposed in the same layer as the gate of the first type transistor, and in a direction perpendicular to the plane of the substrate, a second plate of the capacitor is further disposed between the gate of the first type transistor and the source and the drain.

[0026] In the structure in which the shielding structure and the gate of at least one of the transistors are disposed on the same layer, the shielding structure and the gate of the first type of transistor are disposed on the same layer, and in the signal access area, at least one of the data output lines and the second plate of the capacitor are disposed on the same layer.

[0027] In the structure where the shielding structure is located between the active layer and the substrate, the shielding structure is located between the active layer of the first type of transistor and the substrate. In the signal access area, at least one of the data output lines is disposed on the same layer as at least one of the gate of the first type of transistor and the second plate of the capacitor.

[0028] In an exemplary embodiment, in a structure in which the shielding structure and the gate of the first type of transistor are disposed on the same layer, in the multiplexing circuit region, at least one of the data output lines is disposed on the same layer as the second plate of the capacitor.

[0029] In the structure where the shielding structure is located between the active layer of the first type of transistor and the substrate, in the multiplexing circuit region, at least one of the data output lines is disposed on the same layer as at least one of the gate of the first type of transistor and the second plate of the capacitor.

[0030] In an exemplary embodiment, the plurality of transistors further includes at least one second type transistor, the active layer further includes the active layer of the at least one second type transistor, the gate further includes the gate of the at least one second type transistor, and in a direction perpendicular to the plane of the substrate, the active layer of the at least one second type transistor is located on the side of the second plate of the capacitor away from the substrate, and the gate of the second type transistor is located between the active layer of the second type transistor and the source and the drain.

[0031] In the structure in which the shielding structure and the gate of the first type of transistor are disposed on the same layer, in the signal access area, at least one of the data output lines is disposed on the same layer as at least one of the second plate of the capacitor and the gate of the second type of transistor.

[0032] In the structure where the shielding structure is located between the active layer of the first type of transistor and the substrate, in the signal access area, at least one of the data output lines is disposed on the same layer as at least one of the gate of the first type of transistor, the second plate of the capacitor, and the gate of the second type of transistor.

[0033] In an exemplary embodiment, in a structure in which the shielding structure and the gate of the first type of transistor are disposed on the same layer, in the multiplexing circuit region, at least one of the data output lines is disposed on the same layer as at least one of the second plate of the capacitor and the gate of the second type of transistor.

[0034] In the structure where the shielding structure is located between the active layer of the first type of transistor and the substrate, in the multiplexing circuit region, at least one of the data output lines is disposed on the same layer as at least one of the gate of the first type of transistor, the second plate of the capacitor, and the gate of the second type of transistor.

[0035] In an exemplary embodiment, the display substrate further includes a plurality of multiplexing circuits located in the multiplexing circuit area. The plurality of data output lines correspond one-to-one with the plurality of multiplexing circuits. Each data output line is connected to a corresponding data line through a corresponding multiplexing circuit. Each multiplexing circuit is configured to provide a signal provided by one data output line to at least two of the plurality of data lines in a time-division manner.

[0036] In the structure where the shielding structure is located between the active layer of the first type of transistor and the substrate, the orthogonal projection of the plurality of multiplexing circuits on the substrate is within the range of the orthogonal projection of the first shielding structure on the substrate, and in the direction perpendicular to the plane of the substrate, the plurality of multiplexing circuits are located on the side of the shielding structure away from the substrate.

[0037] In the structure in which the shielding structure and the gate of the first type of transistor are disposed on the same layer, the orthographic projection of the plurality of multiplexer circuits on the substrate does not overlap with the orthographic projection of the first shielding structure on the substrate, and the area corresponding to the first shielding structure and the plurality of multiplexer circuits is set as a hollow structure.

[0038] In an exemplary embodiment, the display substrate further includes:

[0039] At least two data selection lines: located in the first border area, in a direction perpendicular to the plane of the substrate, the at least two data selection lines are located on the side of the shielding structure away from the substrate;

[0040] At least one of the plurality of multiplexing circuits is electrically connected to the at least two data selection lines, and each of the multiplexing circuits is configured to provide the signal of one data output line to the at least two data lines in a time-division manner under the control of the at least two data selection lines.

[0041] In an exemplary embodiment, the number of data lines is M, the number of data output lines is k, and the number of data selection lines is z, where k = M / z, M and k are both positive integers, and z is an integer greater than or equal to 2.

[0042] Each of the multiplexing circuits is electrically connected to the adjacent z data lines and is configured to provide the signal of one data output line to the corresponding z data lines in a time-division manner under the control of the z data selection lines.

[0043] In an exemplary embodiment, the display substrate further includes multiple constant voltage signal lines, the shielding structure further includes a second shielding structure, and the border area further includes a second border area, a third border area, and a fourth border area. In a first direction, the third border area and the fourth border area are located on both sides of the display area, and in a second direction, the first border area and the second border area are located on both sides of the display area. In a direction parallel to the plane of the substrate, the first direction intersects the second direction.

[0044] The second shielding structure is located in the second frame region, the third frame region, and the fourth frame region. The multiple constant voltage signal lines are located in the third frame region and the fourth frame region. In a direction perpendicular to the plane of the substrate, at least one of the multiple constant voltage signal lines is located on the side of the second shielding structure away from the substrate.

[0045] In an exemplary embodiment, the first shielding structure and the second shielding structure are interconnected to form a ring structure surrounding the display area.

[0046] In an exemplary embodiment, the first shielding structure and the second shielding structure are an integral structure.

[0047] In an exemplary embodiment, the second shielding structure is electrically connected to one of the plurality of constant voltage signal lines. The orthographic projection of the plurality of constant voltage signal lines on the substrate is within the range of the orthographic projection of the second shielding structure on the substrate. In a direction perpendicular to the plane of the substrate, the plurality of constant voltage signal lines are located on the side of the second shielding structure away from the substrate.

[0048] Alternatively, the plurality of constant voltage signal lines may include a first type of constant voltage signal line and at least one second type of constant voltage signal line, wherein the second shielding structure is multiplexed as the first type of constant voltage signal line, and in a direction perpendicular to the plane of the substrate, the at least one second type of constant voltage signal line is located on the side of the second shielding structure away from the substrate.

[0049] In an exemplary embodiment, the bezel region includes a peripheral region surrounding the display area and an edge region surrounding the peripheral region, wherein the various constant voltage signal lines and the shielding structure are located in the peripheral region; the display substrate further includes:

[0050] A blocking structure is located in the edge region and partially surrounds the display area, and is disposed in the same layer as the shielding structure;

[0051] A plurality of first grooves are located in the edge region and are sequentially spaced apart in a direction away from the peripheral region, and partially surround the peripheral region, wherein at least one of the first grooves penetrates at least a portion of the blocking structure.

[0052] In an exemplary embodiment, the border region further includes a second border region, a third border region, and a fourth border region. In a first direction, the third border region and the fourth border region are located on both sides of the display region. In a second direction, the first border region and the second border region are located on both sides of the display region. The first direction intersects the second direction. The display substrate further includes:

[0053] Multiple gate control signal lines are located in the display area, including multiple scan signal lines; the multiple sub-pixels form multiple rows, and the scan signal lines are electrically connected to at least one row of sub-pixels; the data lines are configured to provide data signals to the corresponding sub-pixels under the control of the scan signal lines.

[0054] Multiple scan gate driving circuits are located in the third border region and the fourth border region, and each scan gate driving circuit is electrically connected to at least one scan signal line.

[0055] Multiple bonding pads are located in the first frame area. The multiple bonding pads include multiple driving pads and multiple gate driving pads. In the first direction, the multiple gate driving pads are located on both sides of the multiple driving pads.

[0056] Multiple gate drive signal lines are located in the third frame region and the fourth frame region, and extend to the first frame region, and are electrically connected to the multiple gate drive pads and the multiple scan gate drive circuits.

[0057] An integrated circuit, located in the first frame area, is bonded to and connected to the plurality of bonding pads. The integrated circuit is electrically connected to the plurality of data lines through the plurality of driving pads, and is electrically connected to the plurality of gate driving signal lines through the plurality of gate driving pads. The integrated circuit is configured to provide data signals to the plurality of data lines and to provide gate driving signals to the plurality of scan gate driving circuits through the plurality of gate driving signal lines.

[0058] The plurality of scanning gate driving circuits are configured to provide scanning timing signals to the plurality of scanning signal lines under the control of the gate driving signal. The integrated circuit is configured to output an interval signal to the plurality of scanning gate driving circuits at at least one position before and after the scanning timing signal of a frame. The plurality of scanning signal lines control the timing of the data signal received by the plurality of sub-pixels under the control of the scanning timing signal and the interval signal.

[0059] In an exemplary embodiment, during the time interval of the signal, the integrated circuit is configured to stop outputting data signals to the data lines and stop providing gate drive signals to the plurality of gate drive signal lines, and the plurality of scan gate drive circuits stop outputting scan timing signals to the plurality of scan signal lines;

[0060] The scanning timing signal of a frame corresponds to the interval signal at least one position before and after the scanning signal of that frame. The scanning timing signal of a frame and the corresponding interval signal constitute a signal of a scanning cycle. The time of the interval signal is the time of at least one blank line. The time of a blank line is equal to the time of receiving data signal of a row of sub-pixels. In one scanning cycle, the time of the interval signal is the product of the time of a blank line and the number of blank lines in the interval signal.

[0061] In one scan cycle, the time for each row of subpixels to receive data signals is: the time of one scan cycle / (the number of blank rows + the number of subpixel rows), and the time of one scan cycle is 1s / refresh rate.

[0062] Secondly, embodiments of this disclosure also provide a display device, including the display substrate described in any of the above embodiments.

[0063] Thirdly, this disclosure also provides a method for operating a display substrate, the display substrate including an integrated circuit, a plurality of scanning gate driving circuits, a plurality of sub-pixels, a plurality of data lines, and a plurality of scanning signal lines. Each of the scanning gate driving circuits is configured to be electrically connected to the integrated circuit and at least one scanning signal line. The plurality of sub-pixels form multiple rows and columns. The scanning signal lines are configured to be electrically connected to one of the scanning gate driving circuits and at least one row of sub-pixels. The data lines are configured to be electrically connected to the integrated circuit and at least one column of sub-pixels, and provide data signals from the integrated circuit to the corresponding sub-pixels under the control of the scanning signal lines. The extension directions of the plurality of data lines intersect the extension directions of the plurality of scanning signal lines. The method includes:

[0064] The integrated circuit controls the plurality of scanning gate driving circuits to provide scanning timing signals to the plurality of scanning signal lines, and outputs an interval signal to the plurality of scanning gate driving circuits at at least one position before and after the scanning timing signal of a frame; the plurality of scanning signal lines, under the control of the scanning timing signal and the interval signal, control the timing at which the plurality of sub-pixels receive the data signal.

[0065] In an exemplary embodiment, during the time interval of the signal, the integrated circuit stops outputting data signals to the data line;

[0066] Under the control of the interval signal, the plurality of scan gate drive circuits stop outputting scan timing signals to the plurality of scan signal lines.

[0067] In an exemplary embodiment, the scanning timing signal of a frame corresponds to an interval signal at least one position before and after the scanning signal of that frame, and the scanning timing signal of a frame and the corresponding interval signal constitute a signal of a scanning cycle.

[0068] The interval signal time is the time of at least one blank line. The time of one blank line is equal to the time of receiving data signals for one row of sub-pixels. In one scan cycle, the interval signal time is: the time of one blank line * the number of blank lines.

[0069] In an exemplary embodiment, the time for each row of subpixels to receive data signals in one scan cycle is: the time of one scan cycle / (the number of blank rows + the number of subpixel rows), and the time of one scan cycle is 1s / refresh rate.

[0070] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0071] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shapes and sizes of the components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0072] Figure 1 shows a schematic diagram of a display device;

[0073] Figure 2a shows a schematic diagram of a display substrate structure;

[0074] Figure 2b shows a schematic diagram of a display substrate;

[0075] Figure 3a shows a schematic diagram of the first border area of ​​a display substrate;

[0076] Figure 3b shows a partially enlarged structural diagram of the R1 position in Figure 3a;

[0077] Figure 4 is a schematic diagram of the structure of a display substrate;

[0078] Figure 5a is a schematic diagram of a cross-sectional structure along position a0-a0 in Figures 2a and 2b;

[0079] Figure 5b is a schematic diagram of a cross-sectional structure along position a0-a0 in Figures 2a and 2b;

[0080] Figure 6a shows an equivalent circuit diagram of the pixel driving circuit of a sub-pixel in the display area.

[0081] Figure 6b shows an equivalent circuit diagram of the pixel driving circuit for a sub-pixel in the display area.

[0082] Figure 6c shows an equivalent circuit diagram of the pixel driving circuit for a sub-pixel in the display area.

[0083] Figure 7 shows a schematic diagram of a water ripple pattern on a display substrate;

[0084] Figure 8a is a schematic diagram of the structure of a display substrate provided in an embodiment of the present disclosure;

[0085] Figure 8b is a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0086] Figure 8c shows a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0087] Figure 8d is a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0088] Figure 8e is a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0089] Figure 8f shows a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0090] Figure 9a is an enlarged structural schematic diagram of position H1 in Figures 8c to 8e;

[0091] Figure 9b shows a cross-sectional structure along the M0-M0 position in Figure 9a;

[0092] Figure 9c shows a cross-sectional structure along the M0-M0 position in Figure 9a;

[0093] Figure 9d shows a cross-sectional structure along the M01-M01 position in Figure 9a;

[0094] Figure 9e shows a cross-sectional structure along the M01-M01 position in Figure 9a;

[0095] Figure 9f shows a cross-sectional structure along the M01-M01 position in Figure 9a;

[0096] Figure 9g shows a schematic diagram of a cross-sectional structure along the M01-M01 position in Figure 9a;

[0097] Figure 9h shows a schematic diagram of a cross-sectional structure along the M02-M02 position in Figure 9a;

[0098] Figure 9i shows a cross-sectional structure along the M02-M02 position in Figure 9a;

[0099] Figure 10a shows a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0100] Figure 10b shows a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0101] Figure 10c shows a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0102] Figure 11a shows a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0103] Figure 11b shows a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0104] Figure 11c shows a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0105] Figure 11d shows a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0106] Figure 11e shows a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0107] Figure 11f shows a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0108] Figure 12a shows a cross-sectional structure along position M1-M1 in Figures 11b to 11c and Figures 11e to 11f.

[0109] Figure 12b shows a cross-sectional structure along position M1-M1 in Figures 11b to 11c and Figures 11e to 11f.

[0110] Figure 12c shows a cross-sectional structure along position M1-M1 in Figures 11b to 11c and Figures 11e to 11f.

[0111] Figure 12d shows a cross-sectional structure along position M1-M1 in Figures 11b to 11c and Figures 11e to 11f.

[0112] Figure 13a shows a cross-sectional structure along the M2-M2 position in Figures 11b to 11c and Figures 11e to 11f;

[0113] Figure 13b shows a cross-sectional structure along the M2-M2 position in Figures 11b to 11c and Figures 11e to 11f.

[0114] Figure 14 is a schematic diagram of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0115] The embodiments described in this disclosure can be implemented in many different forms. Those skilled in the art will readily understand that the implementation methods and content can be varied in many ways without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the contents described in the following embodiments. Unless otherwise specified, the embodiments and features described in this disclosure can be arbitrarily combined with each other.

[0116] In the accompanying drawings, the size of constituent elements, the thickness of layers, or areas may sometimes be exaggerated for clarity. Therefore, any implementation of this disclosure is not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and any implementation of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0117] The ordinal numbers such as "first," "second," and "third" in this disclosure are used to avoid confusion among the constituent elements, rather than to limit the quantity.

[0118] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships when describing the positional relationships of constituent elements with reference to the accompanying drawings. This is solely for the purpose of facilitating the description of embodiments and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately changed depending on the orientation of the described constituent elements. Therefore, the use of terms not limited to those described herein can be appropriately replaced as appropriate.

[0119] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0120] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (or drain terminal, drain connection region, or drain electrode) and the source electrode (or source terminal, source connection region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0121] In this disclosure, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" can sometimes be interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged. In this disclosure, the control electrode can be the gate electrode.

[0122] In this disclosure, "electrical connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. The "component having a certain electrical function" can be, for example, an electrode or wiring, a switching element such as a transistor, or other functional elements such as a resistor, inductor, or capacitor.

[0123] Figure 1 shows a schematic diagram of a display device. The display substrate may include a timing controller, a data signal driving circuit, a scan signal driving circuit, a light emission signal driving circuit, and a pixel array. The timing controller is connected to the data signal driving circuit, the scan signal driving circuit, and the light emission signal driving circuit. The data signal driving circuit is connected to multiple data signal lines (D1 to Dn), the scan signal driving circuit is connected to multiple scan signal lines (G1 to Gm), and the light emission signal driving circuit is connected to multiple light emission signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light emission device connected to the circuit unit. The circuit unit may include a pixel driving circuit, which may be connected to the scan signal lines, the light emission signal lines, and the data signal lines (which may be referred to as data lines). In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data signal driving circuit to the data signal driving circuit, clock signals, scan start signals, etc. of specifications suitable for the scan signal driving circuit to the scan signal driving circuit, and clock signals, transmit stop signals, etc. of specifications suitable for the light emission signal driving circuit to the light emission signal driving circuit. The data signal driving circuit can use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data signal driving circuit can sample the grayscale values ​​using a clock signal and apply the data voltage corresponding to the grayscale value to data signal lines D1 to Dn on a pixel-by-pixel basis, where n can be a natural number. The scan signal driving circuit can generate scan signals to be provided to scan signal lines G1, G2, G3, ..., Gm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan signal driving circuit can sequentially provide scan signals with conduction level pulses to scan signal lines G1 to Gm. For example, a scan signal driving circuit can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal, where m can be a natural number. A light-emitting signal driving circuit can generate transmit signals to be provided to light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from a timing controller. For example, a light-emitting signal driving circuit can sequentially provide transmit signals with cutoff level pulses to light-emitting signal lines E1 to Eo. For example, a light-emitting driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals, provided in the form of cutoff level pulses, to the next stage circuit under the control of a clock signal, where o can be a natural number.

[0124] Figure 2a shows a schematic diagram of a display panel structure. As shown in Figure 2a, the display panel may include a display area AA and a border area BB surrounding the display area AA. In some examples, the border area BB may include: a first border area (bottom border) B1 and a second border area (top border) B2 arranged opposite each other in the second direction Y, and a third border area (left border) B3 and a fourth border area (right border) B4 arranged opposite each other in the first direction X. The first border area B1 is connected to the third border area B3 and the fourth border area B4, and the second border area B2 is connected to the third border area B3 and the fourth border area B4. In some examples, the display area AA may include a plurality of regularly arranged sub-pixels Pxij, a plurality of gate control signal lines SL, and a plurality of data lines DL. The plurality of gate control signal lines SL may extend along the first direction X, and the plurality of data lines DL may extend along the second direction Y. The orthogonal projections of the plurality of gate control signal lines SL and the plurality of data lines DL on the substrate may intersect to form a plurality of sub-pixel areas, and a sub-pixel Pxij may be set in each sub-pixel area. Multiple data lines DL can be electrically connected to multiple sub-pixels Pxij, and the multiple data lines DL can be configured to provide data signals to the multiple sub-pixels Pxij. Multiple gate control signal lines SL can be electrically connected to multiple sub-pixels Pxij, and the multiple gate control signal lines SL can be configured to provide gate control signals to the multiple sub-pixels Pxij. In some examples, the gate control signals may include scan signals and emission control signals, or may include scan signals, reset control signals, and emission control signals. Sub-pixels Pxij may include pixel driving circuitry and light-emitting devices. The first frame region B1 may include bonding circuitry connecting the signal lines to an external driving device. The third frame region B3 and the fourth frame region B4 may include gate driving circuitry and a second power supply line VSS for transmitting voltage signals to the multiple sub-pixels.

[0125] Figure 3a shows a schematic diagram of the planar structure of the first frame region B1. In a plane parallel to the display substrate, the first frame region B1 may include a first fan-out area 11, a bending area 12, a second fan-out area 13, an anti-static area 15, a third fan-out area 16, and a bonding area 14 arranged sequentially along the direction away from the display area AA. The bonding area 14 may include a driver chip area 141 and a bonding electrode area 142 arranged sequentially along the direction away from the bending area 12 of the second fan-out area 13. The first fan-out area 11 may include a data fan-out line, a first power line, and a second power line VSS. The data fan-out line is located in the middle of the first fan-out area 11 and includes multiple data connection lines. The multiple data connection lines are configured to connect the data lines of the display area AA in a fan-out routing manner. The first power line is configured to connect the high-voltage power line (VDD) of the display area AA. The second power line is a low-voltage power line (VSS) located in the third frame region B3 and the fourth frame region B4. The bending area 12 may include a composite insulating layer with grooves, configured to bend the bonding area 14 to the back of the display area AA (as shown in Figure 4). The bending area 12 is provided with data connection lines, one end of which is connected to the data connection line of the first fan-out area 11, and the other end is connected to the data connection line of the second fan-out area 13. The second fan-out area 13 includes multiple data connection lines led out in a fan-out routing manner. The anti-static area 15 is provided with multiple anti-static circuits 40, which are connected to the multiple data connection lines in the second fan-out area 13. The third fan-out area 16 includes multiple data connection lines led out in a fan-out routing manner, which are connected to the multiple anti-static circuits 40 in the anti-static area 15. The driver chip area 141 can house an integrated circuit (IC) 20, configured to connect to multiple data connection lines in the third fan-out area 16. The driver chip area 141 can also have multiple driver pads and multiple input pads. Multiple input ports of the IC 20 can be electrically connected to the multiple input pads, and multiple output ports of the IC can be connected to the multiple driver pads. The input pads are used to input signals, which are converted by the IC 20 and output to the driver pads. The driver pads transmit signals (such as data signals) to the corresponding data lines DL through corresponding data output lines and corresponding data connection lines. The bonding electrode area 142 includes multiple bonding pads, configured to bond to a flexible printed circuit (FPC) 30. The bonding pads can also be electrically connected to corresponding input pads through multiple signal leads. Signals from the FPC can be transmitted to the IC 20 through the input pads.In an exemplary embodiment, an integrated circuit (IC) 20 may be bonded to the driver chip area 141, and a flexible printed circuit (FPC) 30 may be bonded to the bonding electrode area 142. In an exemplary embodiment, the integrated circuit 20 (which may be referred to as a data driving circuit) may generate driving signals required to drive sub-pixels and may provide these driving signals to the sub-pixel Pxij located in the display area AA. For example, the driving signal may be a data signal controlling the brightness of the sub-pixel. In an exemplary embodiment, the bonding electrode area 142 may be provided with pads including multiple pins, and the flexible printed circuit board 30 may be bonded to the pads.

[0126] In an exemplary embodiment, in a high PPI structure, the number of integrated circuit (IC) pins is limited. A data selector (MUX, short for multiplexer) can be used to reduce the number of IC pins, which in some cases can reduce the number of driver ICs and lower costs, as shown in Figure 3b. Figure 3b is an enlarged structural diagram of the R1 position in Figure 3a. When using MUX technology, multiple multiplexer circuits (MUX) 50 can be set in the first fan-out area 11. The integrated circuit 20 located in the bonding area 14 can be connected to the multiple multiplexer circuits 50 through multiple data select lines DT. The input terminal of the multiplexing circuit 50 can be connected to the integrated circuit 20 through the corresponding data output line DT. The output terminal of the multiplexing circuit 50 can be connected to at least two data lines DL. Each data output line DT can be composed of data connection lines located in the bending area 12, the second fan-out area 13, the third fan-out area 16, and the bonding area 14. Furthermore, each data output line DT can be connected to the corresponding multiplexing circuit 50. The multiplexing circuit 50 can be electrically connected to at least two data selection lines MUX. Each multiplexing circuit 50 is configured to provide the signal of one data output line DT to the corresponding at least two data lines DL in a time-division manner under the control of at least two data selection lines MUX. As shown in Figure 3b, the multiplexing circuit 50 may include a first multiplexed transistor MT1, a second multiplexed transistor MT2, a third multiplexed transistor MT3, a fourth multiplexed transistor MT4, a fifth multiplexed transistor MT5, and a sixth multiplexed transistor MT6. In the same multiplexing circuit 50, the first terminals of the first multiplexed transistors MT1 to MT6 are all connected to a data output line DT, and the second terminals of the first multiplexed transistors MT1 to MT6 are respectively connected to six data lines DL. The control electrodes are respectively connected to the data selection lines MUX (first data selection line MUX1 to sixth data selection line MUX6). Each multiplexer circuit 50 can be configured to provide the signal of one data output line DT to the corresponding six data lines DL in a time-division manner under the control of the six data selection lines MUX. That is, one data output line DT can provide data signals to six data lines DL, which can greatly reduce the size of the bending area 12, the second fan-out area 13, the anti-static area 15, the third fan-out area 16, and the bonding area 14, and is conducive to reducing the size of the first frame area B1.

[0127] In an exemplary embodiment, as shown in FIG4, the bending region 12 can reverse the surface of the bonding region 14, that is, the upward-facing surface of the bonding region 14 can be transformed to face downward by bending the bending region 12. In an exemplary embodiment, when the bending region 12 is bent, the bonding region 14 can overlap with the display region AA in the thickness direction of the display panel.

[0128] In an exemplary embodiment, as shown in FIG2b, a schematic diagram of another display panel structure is presented. The difference between FIG2b and FIG2a is that FIG2b does not have a bending area 12, and the bonding area 14 cannot be bent to the back of the display area AA. Other structures are the same as FIG2b. In an exemplary embodiment, the integrated circuit 20 in FIG2a and FIG2b is bonded to the first frame area B1; the integrated circuit 20 can also be bonded to the flexible circuit board 30, which can reduce the size of the first frame area B1. This structure can be called a chip-on-film (COF) film.

[0129] In exemplary embodiments, for large-size display substrates, multiple data driver ICs (also known as driver ICs or driver integrated circuits) and multiple FPCs can be provided. The multiple FPCs are respectively bound to and connected to the multiple data driver ICs. For example, four data driver ICs can be provided, each bound to one of the four FPCs. This disclosure is not limited to four ICs and four FPCs; for example, two data driver ICs and two FPCs can be provided. For small-size display substrates, one or two data driver ICs can be provided. In this disclosure, the number of data driver ICs and FPCs can be set according to the size and functional requirements of the display substrate, and this disclosure does not limit this number.

[0130] Figure 5a is a schematic cross-sectional view of the sub-pixel Pxij along the a0-a0 position in the display area AA of the display substrate shown in Figures 2a and 2b. Figure 5a illustrates the structure of a single sub-pixel in the display area as an example. In this example, it is illustrated that multiple transistors in the pixel circuit are of the same type. For example, the multiple transistors in the pixel circuit can all be low-temperature polysilicon thin-film transistors or all be oxide thin-film transistors, as shown in Figure 5a. In other examples, the multiple transistors in the pixel circuit can be both low-temperature polysilicon thin-film transistors and oxide thin-film transistors, as shown in Figure 5b. In addition, this example illustrates the integration of a mutual capacitance touch structure into the display substrate to form an FMLOC structure.

[0131] In some examples, as shown in Figure 5a, in the direction Z perpendicular to the display substrate, the display area of ​​the display substrate may include: a substrate 100, and a circuit structure layer 200, a light-emitting structure layer 300, an encapsulation structure layer 400, a touch structure layer 500, and a color filter layer 600 sequentially disposed on the substrate 100. The display structure layer may include at least the circuit structure layer 200 and the light-emitting structure layer 300. The circuit structure layer 200 may include at least pixel circuits for multiple sub-pixels, each sub-pixel's pixel circuit including multiple transistors and at least one capacitor. The light-emitting structure layer 300 may include at least light-emitting elements for multiple sub-pixels.

[0132] In some examples, Figure 5a illustrates a scenario where each sub-pixel includes a thin-film transistor 21 and a capacitor 22. In some examples, the circuit structure layer 200 of the display area may include: a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer disposed on the substrate 100. The multiple display area metal layers of the display structure layer in this example may include: a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer. A first gate insulating layer 201 may be disposed between the semiconductor layer and the first gate metal layer; a second gate insulating layer 202 may be disposed between the first gate metal layer and the second gate metal layer; an interlayer insulating layer 203 may be disposed between the second gate metal layer and the first source-drain metal layer; a passivation layer 204 and a first planarization layer 205 may be disposed between the first source-drain metal layer and the second source-drain metal layer; a second planarization layer 206 may be disposed between the second source-drain metal layer and the third source-drain metal layer; and a third planarization layer 207 may be disposed on the side of the third source-drain metal layer away from the substrate 100. The first gate insulating layer 201, the second gate insulating layer 202, the interlayer insulating layer 203, and the passivation layer 204 may be inorganic insulating layers, while the first planarization layer 205, the second planarization layer 206, and the third planarization layer 207 may be organic insulating layers. However, this embodiment is not limited to these limitations. In some examples, a buffer layer 1501 may be disposed on the side of the semiconductor layer near the substrate. This buffer layer prevents harmful substances from the substrate from penetrating the interior of the display substrate and increases the adhesion of the film layers in the display substrate to the substrate. In other examples, a bottom shielding metal layer (BSM) may be disposed on the side of the buffer layer 1501 near the substrate. This bottom shielding metal layer may be configured to at least partially cover the active layer of the thin-film transistor in the pixel circuit to prevent external light from affecting the performance of the thin-film transistor. In other examples, a passivation layer may be omitted between the first and second source-drain metal layers, and only a first planarization layer may be disposed between the first and second source-drain metal layers.

[0133] In some examples, as shown in FIG5a, the semiconductor layer of the display area may include at least the active layer 210 of the thin-film transistor 21. The active layer 210 of the thin-film transistor 21 may include a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least the gate 213 of the thin-film transistor 21 and the first electrode 221 of the capacitor 22. The orthographic projection of the gate 213 of the thin-film transistor 21 onto the substrate 100 may cover the orthographic projection of the channel region 2100 of the active layer 210 onto the substrate 100. The second gate metal layer may include at least the second electrode 222 of the capacitor 22. The orthographic projections of the second electrode 222 and the first electrode 221 of the capacitor 22 onto the substrate 100 may at least partially overlap, for example, they may coincide. The first source-drain metal layer may include at least the source 211 and the drain 212 of the thin-film transistor 21. The interlayer insulating layer 203 may have multiple vias (e.g., including a first pixel via and a second pixel via) in the display area. The interlayer insulating layer 203, the second gate insulating layer 202, and the first gate insulating layer 201 within the first pixel via can be removed, exposing at least a portion of the surface of the first region 2101 of the active layer 210. The interlayer insulating layer 203, the second gate insulating layer 202, and the first gate insulating layer 201 within the second pixel via can be removed, exposing at least a portion of the surface of the second region 2102 of the active layer 210. The source 211 of the thin-film transistor 21 can be electrically connected to the first region 2101 of the active layer 210 through the first pixel via, and the drain 212 can be electrically connected to the second region 2102 of the active layer 210 through the second pixel via. The second source-drain metal layer may include at least a first transition electrode 231. The first transition electrode 231 can be electrically connected to the drain 212 of the thin-film transistor 21 of the pixel circuit through a third pixel via formed by the passivation layer 204 and the first planarization layer 205. The third source-drain metal layer may include at least a second transition electrode 232. The second transition electrode 232 can be electrically connected to the first transition electrode 231 located in the second source-drain metal layer through a fourth pixel via formed by the second planarization layer 206. The second transition electrode 232 can be electrically connected to the first electrode 301 (e.g., anode) of the light-emitting element through a fifth pixel via formed by the third planarization layer 207. In this example, the electrical connection between the pixel circuit and the light-emitting element can be achieved through the first transition electrode 231 and the second transition electrode 232.

[0134] In some examples, the gate lines of the display area may be located, for example, in the first gate metal layer or the second gate metal layer; the data lines of the display area may be located, for example, in the second source-drain metal layer or the third source-drain metal layer; and the high-potential power lines of the display area may be located, for example, in at least one of the second and third source-drain metal layers. This embodiment is not limited in this respect. The circuit structure layer of this example may include three source-drain metal layers, which can avoid arranging too many traces in a single source-drain metal layer, thereby facilitating the realization of a narrow bezel structure.

[0135] In some examples, as shown in Figure 5a, the light-emitting structure layer 300 may include a pixel definition layer 304 and multiple light-emitting elements. For example, each light-emitting element may include a stacked first electrode 301, an organic light-emitting layer 302, and a second electrode 303. The first electrode 301 of the light-emitting element can be an anode, and the first electrode 301 can be disposed on a third planarization layer 207 and electrically connected to a second transition electrode 232 through a fifth pixel via formed in the third planarization layer 207. The pixel definition layer 304 is disposed on the first electrode 301 and the third planarization layer 207, and the pixel definition layer 304 may have multiple pixel openings, one pixel opening exposing at least a portion of the surface of a corresponding first electrode 301. At least a portion of the organic light-emitting layer 302 can be disposed within a pixel opening and connected to the corresponding first electrode 301. The second electrode 303 can be disposed on the organic light-emitting layer 302 and connected to the organic light-emitting layer 302. The organic light-emitting layer 302 can emit light of a corresponding color under the drive of the first electrode 301 and the second electrode 303. An isolation pillar layer may also be provided on the side of the pixel definition layer 304 away from the substrate 100, and the isolation pillar layer may include multiple isolation pillars (PS).

[0136] In some examples, the organic light-emitting layer 302 of the light-emitting element may include an emitting layer (EML) and one or more films selected from the following: a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 301 and the second electrode 303, the light-emitting properties of the organic material can be utilized to emit light at the required grayscale.

[0137] In some examples, the light-emitting layers of different colored light-emitting elements can be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. To reduce process complexity and improve yield, the hole injection layer and hole transport layer on one side of the light-emitting layer can be common layers, as can the electron injection layer and electron transport layer on the other side. In some examples, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer can be fabricated in a single process (single vapor deposition process or single inkjet printing process), and isolation can be achieved through surface steps of the formed film layers or through surface treatment. For example, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be formed by vapor deposition using a fine metal mask (FMM) or an open mask, or by inkjet printing.

[0138] In some examples, as shown in FIG5a, the encapsulation structure layer 40 may include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 stacked in a direction perpendicular to the substrate. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials such as silicon nitride, silicon oxide, or silicon oxynitride. Inorganic materials have high density and can prevent the intrusion of water, oxygen, etc. The second encapsulation layer 402 may be made of organic materials and may be disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that external moisture cannot enter the light-emitting element. The second encapsulation layer 402 may be made of organic materials, for example, it may be a polymer material containing a desiccant or a polymer material that can block moisture, or it may be a polymer resin to planarize the surface of the display substrate and relieve stress on the first encapsulation layer 401 and the third encapsulation layer 403. It may also include a water-absorbing material such as a desiccant to absorb water, oxygen, and other substances that have penetrated the interior. However, this embodiment is not limited in this respect. For example, the encapsulation structure layer can adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0139] In some examples, the touch structure layer of the display area may include: a plurality of first touch electrodes, a plurality of first connecting portions, a plurality of second touch electrodes, and a plurality of second connecting portions. The plurality of first touch electrodes may be arranged in the same layer, and adjacent first touch electrodes may be connected through the first connecting portions. The plurality of second touch electrodes may be arranged in the same layer, and adjacent second touch electrodes may be connected through the second connecting portions.

[0140] In some examples, as shown in FIG5a, the touch structure layer 500 of the display area may include, in the direction perpendicular to the substrate, a touch buffer layer (TBL) 501, a first touch conductive layer 511, a touch interlayer insulating layer (TLD) 502, and a second touch conductive layer 512 sequentially disposed therefrom. The touch buffer layer 501 and the touch interlayer insulating layer 502 may be inorganic insulating layers, such as SiNx layers. For example, the first touch conductive layer 511 may include a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of first connecting portions. The first touch electrodes and the first connecting portions may be an integral structure interconnected. The second touch conductive layer 512 may include a plurality of second connecting portions. The second connecting portions may be interconnected with adjacent second touch electrodes through vias formed in the touch interlayer insulating layer. However, this embodiment is not limited to this. In other examples, the first touch conductive layer may include: a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of second connecting portions, wherein the second touch electrodes and the second connecting portions may be an integral structure interconnected with each other; the second touch conductive layer may include a plurality of first connecting portions, which may be interconnected with adjacent first touch electrodes through vias formed in the interlayer insulating layer. In some examples, the first touch electrodes may be driving (Tx) electrodes, and the second touch electrodes may be sensing (Rx) electrodes. Alternatively, the first touch electrodes may be sensing (Rx) electrodes, and the second touch electrodes may be driving (Tx) electrodes. This embodiment is not limited in this respect.

[0141] In some examples, the first and second touch electrodes may be rhomboid in shape, such as a regular rhombus, a horizontally elongated rhombus, or a vertically elongated rhombus. In other examples, the first and second touch electrodes may be any one or more of triangles, squares, trapezoids, parallelograms, pentagons, hexagons, and other polygons, which are not limited to the embodiments disclosed herein.

[0142] In some examples, the first and second touch electrodes can be in the form of transparent conductive electrodes. In other examples, the first and second touch electrodes can be in the form of a metal mesh, which can be formed by multiple interwoven metal wires. The metal mesh can include multiple mesh patterns, and the mesh pattern can be a polygon composed of multiple metal wires. The metal mesh-type first and second touch electrodes have advantages such as low resistance, small thickness, and fast response speed.

[0143] In some examples, as shown in FIG5a, in a direction perpendicular to the substrate, the color filter on encapsulation (COE) 600 may include an insulating layer 601, a color filter layer, and an overcoat 602 disposed sequentially. The color filter layer includes a black matrix 610 and color filter units 611 disposed between the black matrix 610. The color filter units 611 may be, for example, red filter units, green filter units, or blue filter units.

[0144] In some examples, as shown in Figure 5b, a cross-sectional view of sub-pixel Pxij along position a0-a0 in the display area AA of the display substrate shown in Figures 2a and 2b is presented. In the direction Z perpendicular to the display panel, the display area of ​​the display substrate may include: a substrate 100, and a circuit structure layer 200, a light-emitting structure layer 300, an encapsulation structure layer 400, and a touch structure layer 500 sequentially disposed on the substrate 100. The display structure layer may include at least the circuit structure layer 200 and the light-emitting structure layer 300. The circuit structure layer 200 may include at least pixel circuits for multiple sub-pixels, each sub-pixel's pixel circuit including multiple transistors and at least one capacitor. The light-emitting structure layer 300 may include at least light-emitting elements for multiple sub-pixels.

[0145] In some examples, Figure 5b illustrates a sub-pixel comprising a first transistor 21, a second transistor 23, and a capacitor 22. The transistor types of the first transistor 21 and the second transistor 23 may be different. Specifically, the first transistor 21 may be a low-temperature polycrystalline silicon thin-film transistor, and the second transistor 23 may be an oxide thin-film transistor.

[0146] In some examples, the circuit structure layer 200 of the display area may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source / drain metal layer, and a second source / drain metal layer disposed on the substrate 100. In this example, the multiple display area metal layers of the display structure layer may include: a first gate metal layer, a second gate metal layer, a third gate metal layer, a first source / drain metal layer, and a second source / drain metal layer. A first gate insulating (GI) layer 201 may be disposed between the first semiconductor layer and the first gate metal layer, and a second gate insulating layer 202 may be disposed between the first gate metal layer and the second gate metal layer; a first interlayer insulating (ILD) layer 103 and a first buffer layer 104 may be disposed between the second gate metal layer and the second semiconductor layer, and the first buffer layer 104 may be located on the side of the first interlayer insulating layer 103 away from the substrate 100; a third gate insulating layer 105 may be disposed between the second semiconductor layer and the third gate metal layer; a second interlayer insulating layer 106 may be disposed between the third gate metal layer and the first source / drain metal layer; a passivation (PVX) layer 204 and a first planarization (PLN) layer 205 may be disposed between the first source / drain metal layer and the second source / drain metal layer, and the first planarization layer 205 may be located on the side of the passivation layer 204 away from the substrate 100; a second planarization layer 206 may be disposed on the side of the second source / drain metal layer away from the substrate 100. In this embodiment, the first gate insulating layer 201, the second gate insulating layer 202, the first interlayer insulating layer 103, the first buffer layer 104, the third gate insulating layer 105, the second interlayer insulating layer 106, and the passivation layer 204 can be inorganic insulating layers, while the first planarization layer 205 and the second planarization layer 206 can be organic insulating layers. However, this embodiment is not limited in this respect. In other examples, a second buffer layer can also be disposed on the side of the first semiconductor layer near the substrate. The second buffer layer can prevent harmful substances in the substrate from penetrating into the interior of the display panel and can also increase the adhesion of the 1502 film layer in the display panel to the substrate. In other examples, a bottom shielding metal layer (BSM) can also be disposed on the side of the second buffer layer 1502 near the substrate. The bottom shielding metal layer can be configured to at least partially cover the active layer of the transistors of the pixel circuit to avoid external light affecting the performance of the transistors. In other examples, the passivation layer can be omitted between the first source / drain metal layer and the second source / drain metal layer, and only the first planarization layer can be disposed between the first source / drain metal layer and the second source / drain metal layer. In other examples, the first buffer layer may be omitted between the second gate metal layer and the second semiconductor layer, and only the first interlayer insulating layer 103 may be provided.

[0147] In some examples, as shown in FIG5b, the first semiconductor layer of the display area may include at least: a first active layer 210 of the first transistor 21. The first active layer 210 of the first transistor 21 may include: a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least: a first gate 213 of the first transistor 21, and a first electrode 221 of the capacitor 22. The orthographic projection of the first gate 213 of the first transistor 21 onto the substrate 100 may cover the orthographic projection of the channel region 2100 of the first active layer 210 onto the substrate 100. The second gate metal layer may include at least: a second electrode 222 of the capacitor 22, and a third gate 234 of the second transistor 23. The orthographic projections of the second electrode 222 and the first electrode 221 of the capacitor 22 onto the substrate 100 may at least partially overlap, for example, they may coincide. The second semiconductor layer may include at least: a second active layer 230 of the second transistor 23. The third gate metal layer may include at least: the second gate 233 of the second transistor 23. The orthographic projection of the second gate 233 of the second transistor 23 onto the substrate 100 may partially overlap with the orthographic projection of the second active layer 230 onto the substrate 100. The orthographic projection of the third gate 234 of the second transistor 23 onto the substrate 100 may partially overlap with the orthographic projection of the second active layer 230 onto the substrate 100. The third gate 234 may be the bottom gate of the second transistor 23, and the second gate 233 may be the top gate of the second transistor 23.

[0148] In some examples, as shown in Figure 5b, the first source-drain metal layer may include at least: a first source 211 and a first drain 212 of the first transistor 21, and a second source 235 and a second drain 236 of the second transistor 23. The second interlayer insulating layer 106 may have multiple pixel vias (e.g., including a first pixel via, a second pixel via, a third pixel via, and a fourth pixel via) in the display area. The second interlayer insulating layer 106, the third gate insulating layer 105, the first buffer layer 104, the first interlayer insulating layer 103, the second gate insulating layer 202, and the first gate insulating layer 201 within the first pixel via can be removed, exposing at least a portion of the surface of the first region 2101 of the first active layer 210. The second interlayer insulating layer 106, the third gate insulating layer 105, the first buffer layer 104, the first interlayer insulating layer 103, the second gate insulating layer 202, and the first gate insulating layer 201 within the second pixel via can be removed, exposing at least a portion of the surface of the second region 2102 of the first active layer 210. The second interlayer insulating layer 106 and the third gate insulating layer 105 within the third pixel via and the fourth pixel via can be removed, exposing at least a portion of the surfaces at both ends of the second active layer 230. The first source 211 of the first transistor 21 can be electrically connected to the first region 2101 of the first active layer 210 through a first pixel via, and the first drain 212 can be electrically connected to the second region 2102 of the first active layer 210 through a second pixel via. The second source 235 of the second transistor 23 can be electrically connected to one end of the second active layer 230 through a third pixel via, and the second drain 236 of the second transistor 23 can be electrically connected to the other end of the second active layer 230 through a fourth pixel via. The second source-drain metal layer may include at least a first transition electrode 231. The first transition electrode 231 can be electrically connected to the first drain 212 of the first transistor 21 of the pixel circuit through a fifth pixel via formed by the passivation layer 204 and the first planarization layer 205. In this example, the first transition electrode 231 can be used to achieve the electrical connection between the pixel circuit and the light-emitting element.

[0149] In some examples, the gate lines of the display area may be located, for example, in the first gate metal layer and the third gate metal layer; the data lines of the display area may be located, for example, in the second source-drain metal layer; and the high-potential power lines of the display area may be located, for example, in the second source-drain metal layer. This embodiment is not limited in this respect.

[0150] In some examples, as shown in Figure 5b, the light-emitting structure layer 300 may include a pixel definition layer 134 and multiple light-emitting elements. For example, each light-emitting element may include a stacked first electrode 301, an organic light-emitting layer 302, and a second electrode 303. The first electrode 301 of the light-emitting element can be an anode, and the first electrode 301 can be disposed on the second planarization layer 206 and electrically connected to the first transition electrode 231 through a sixth pixel via formed in the second planarization layer 206. The pixel definition layer 304 is disposed on the first electrode 301 and the second planarization layer 206, and the pixel definition layer 304 may have multiple pixel openings, one pixel opening exposing at least a portion of the surface of a corresponding first electrode 301. At least a portion of the organic light-emitting layer 302 can be disposed within a pixel opening and connected to the corresponding first electrode 301. The second electrode 303 can be disposed on the organic light-emitting layer 302 and connected to the organic light-emitting layer 302. The organic light-emitting layer 302 can emit light of a corresponding color under the drive of the first electrode 301 and the second electrode 303.

[0151] In some examples, the organic light-emitting layer 302 of the light-emitting element may include an emitting layer (EML) and one or more films selected from the following: a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 301 and the second electrode 303, the light-emitting properties of the organic material can be utilized to emit light at the required grayscale.

[0152] In some examples, the light-emitting layers of different colored light-emitting elements can be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. To reduce process complexity and improve yield, the hole injection layer and hole transport layer on one side of the light-emitting layer can be common layers, as can the electron injection layer and electron transport layer on the other side. In some examples, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer can be fabricated in a single process (single vapor deposition process or single inkjet printing process), and isolation can be achieved through surface steps of the formed film layers or through surface treatment. For example, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be formed by vapor deposition using a fine metal mask (FMM) or an open mask, or by inkjet printing.

[0153] In some examples, as shown in Figure 5b, the encapsulation structure layer 400 may include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 stacked together. The first and third encapsulation layers 401 and 403 may be made of inorganic materials, such as silicon nitride, silicon oxide, or silicon oxynitride. Inorganic materials have high density, which can prevent the intrusion of water, oxygen, etc. The second encapsulation layer 402 may be disposed between the first and third encapsulation layers 401 and 403 to ensure that external moisture cannot enter the light-emitting element. The second encapsulation layer 402 may be made of organic materials, for example, it may be a polymer material containing a desiccant or a polymer material that can block moisture, or it may be a polymer resin to planarize the surface of the display panel and relieve stress on the first and third encapsulation layers 401 and 403. It may also include a desiccant or other water-absorbing material to absorb water, oxygen, and other substances that have penetrated the interior. However, this embodiment is not limited to this. For example, the encapsulation structure layer may adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0154] In some examples, the touch structure layer of the display area may include: a plurality of first touch electrodes, a plurality of first connecting portions, a plurality of second touch electrodes, and a plurality of second connecting portions. The plurality of first touch electrodes may be arranged in the same layer, and adjacent first touch electrodes may be connected through the first connecting portions. The plurality of second touch electrodes may be arranged in the same layer, and adjacent second touch electrodes may be connected through the second connecting portions.

[0155] In some examples, as shown in FIG5b, the touch structure layer 500 of the display area may include, in the direction perpendicular to the display panel, a touch buffer layer (TBL) 501, a first touch conductive layer 511, a touch interlayer insulating layer (TLD) 502, a second touch conductive layer 512, and a protective layer 503, arranged sequentially. The touch buffer layer 501 and the touch interlayer insulating layer 502 may be inorganic insulating layers, and the protective layer 503 may be an organic insulating layer. For example, the first touch conductive layer 511 may include a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of first connecting portions. The first touch electrodes and the first connecting portions may be an integral structure interconnected. The second touch conductive layer 512 may include a plurality of second connecting portions. The second connecting portions may be interconnected with adjacent second touch electrodes through vias formed in the touch interlayer insulating layer. However, this embodiment is not limited to this. In other examples, the first touch conductive layer may include: a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of second connecting portions, wherein the second touch electrodes and the second connecting portions may be an integral structure interconnected with each other; the second touch conductive layer may include a plurality of first connecting portions, which may be interconnected with adjacent first touch electrodes through vias formed in the interlayer insulating layer. In some examples, the first touch electrodes may be driving (Tx) electrodes, and the second touch electrodes may be sensing (Rx) electrodes. Alternatively, the first touch electrodes may be sensing (Rx) electrodes, and the second touch electrodes may be driving (Tx) electrodes. This embodiment is not limited in this respect.

[0156] In some examples, the first and second touch electrodes may be rhomboid in shape, such as a regular rhombus, a horizontally elongated rhombus, or a vertically elongated rhombus. In other examples, the first and second touch electrodes may be any one or more of triangles, squares, trapezoids, parallelograms, pentagons, hexagons, and other polygons, which are not limited to the embodiments disclosed herein.

[0157] In some examples, the first and second touch electrodes can be in the form of transparent conductive electrodes. In other examples, the first and second touch electrodes can be in the form of a metal mesh, which can be formed by multiple interwoven metal wires. The metal mesh can include multiple mesh patterns, and the mesh pattern can be a polygon composed of multiple metal wires. The metal mesh-type first and second touch electrodes have advantages such as low resistance, small thickness, and fast response speed.

[0158] In an exemplary embodiment, at least one sub-pixel Pxij may include a pixel driving circuit and a light-emitting element. Within the same sub-pixel Pxij, the light-emitting element is electrically connected to the pixel driving circuit and configured to emit light under the drive of the pixel driving circuit. The pixel driving circuit may include, but is not limited to, the 7T1C circuit structure shown in FIG6a and the 8T1C circuit structure shown in FIG6b and 6c. The pixel driving circuit is described in detail below with reference to FIG6a to 6c:

[0159] Figure 6a shows an equivalent circuit diagram of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In some examples, as shown in Figure 6a, the pixel driving circuit of this example may include seven transistors (i.e., first transistor T1 to seventh transistor T7) and a storage capacitor Cst. The gate of the third transistor T3 is electrically connected to the first node N1, the first terminal of the third transistor T3 is electrically connected to the second node N2, and the second terminal of the third transistor T3 is electrically connected to the third node N3. The third transistor T3 can also be referred to as a driving transistor. The gate of the fourth transistor T4 is electrically connected to the scan signal line GL, the first terminal of the fourth transistor T4 is electrically connected to the data line DL, and the second terminal of the fourth transistor T4 is electrically connected to the first terminal of the third transistor T3. The fourth transistor T4 can also be referred to as a data writing transistor. The gate of the second transistor T2 is electrically connected to the scan signal line GL. The first terminal of the second transistor T2 is electrically connected to the gate of the third transistor T3, and the second terminal of the second transistor T2 is electrically connected to the second terminal of the third transistor T3. The second transistor T2 can also be called a threshold compensation transistor. The gate of the fifth transistor T5 is electrically connected to the light emission control line EML. The first terminal of the fifth transistor T5 is electrically connected to the first power supply line VDD, and the second terminal of the fifth transistor T5 is electrically connected to the first terminal of the third transistor T3. The gate of the sixth transistor T6 is electrically connected to the light emission control line EML. The first terminal of the sixth transistor T6 is electrically connected to the second terminal of the third transistor T3, and the second terminal of the sixth transistor T6 is electrically connected to the anode of the light-emitting element EL. The fifth transistor T5 and the sixth transistor T6 can also be called light emission control transistors. The first transistor T1 is electrically connected to the gate of the third transistor T3 and is configured to reset the gate of the third transistor T3. The seventh transistor T7 is electrically connected to the anode of the light-emitting element EL and is configured to reset the anode of the light-emitting element EL. The gate of the first transistor T1 is electrically connected to the first reset control line RST1, the first terminal of the first transistor T1 is electrically connected to the first initial signal line Vinit1, and the second terminal of the first transistor T1 is electrically connected to the gate of the third transistor T3. The gate of the seventh transistor T7 is electrically connected to the second reset control line RST2, the first terminal of the seventh transistor T7 is electrically connected to the second initial signal line Vinit2, and the second terminal of the seventh transistor T7 is electrically connected to the anode of the light-emitting element EL. The first transistor T1 and the seventh transistor T7 can also be referred to as reset control transistors. The first capacitor plate of the storage capacitor Cst is electrically connected to the gate of the third transistor T3, and the second capacitor plate of the storage capacitor Cst is electrically connected to the first power supply line VDD.

[0160] In this example, the first node N1 is the connection point of the storage capacitor Cst, the first transistor T1, the third transistor T3, and the second transistor T2; the second node N2 is the connection point of the fifth transistor T5, the fourth transistor T4, and the third transistor T3; the third node N3 is the connection point of the third transistor T3, the second transistor T2, and the sixth transistor T6; and the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7, and the light-emitting element EL.

[0161] In some examples, the first power line VDD can be configured to provide a constant first voltage signal to the pixel circuit, and the second power line VSS can be configured to provide a constant second voltage signal to the pixel circuit, wherein the first voltage signal can be greater than the second voltage signal. The scan signal line GL can be configured to provide a scan signal SCAN to the pixel circuit, the data line DL can be configured to provide a data signal DATA to the pixel circuit, the light emission control line EML can be configured to provide a light emission control signal EM to the pixel circuit, the first reset control line RST1 can be configured to provide a first reset control signal to the pixel circuit, and the second reset control line RST2 can be configured to provide a second reset control signal to the pixel circuit.

[0162] In some examples, the first initial signal line Vinit1 can be configured to provide a first initial signal to the pixel circuit, and the second initial signal line Vinit2 can be configured to provide a second initial signal to the pixel circuit. For example, the first initial signal may be different from the second initial signal. The first and second initial signals can be constant voltage signals, the magnitude of which may be, for example, between the first and second voltage signals, but is not limited thereto. In other examples, the first and second initial signals may be the same.

[0163] In some examples, the first transistor T1 through the seventh transistor T7 can be either P-type or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 through the seventh transistor T7 may include both P-type and N-type transistors.

[0164] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be low-temperature polysilicon (LTPS) transistors, or oxide transistors, or a combination of LTPS and metal-oxide transistors. The active layer of the LTPS transistor is made of low-temperature polysilicon (LTPS), while the active layer of the metal-oxide transistor is made of metal-oxide semiconductor (Oxide). LTPS transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current. Integrating LTPS transistors and metal-oxide transistors onto a single display substrate forms an LTPO (Low Temperature Poly-Silicon+Oxide) display substrate. This leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0165] In an exemplary embodiment, the pixel driving circuit can also be as shown in Figures 6b and 6c; the difference between Figure 6b and Figure 6a is that an eighth transistor T8 is added, the gate of the eighth transistor T8 is connected to the second node N2, the first terminal of the eighth transistor T8 is connected to the third initial signal line Vinit3, and the gate of the eighth transistor T8 is connected to the third reset control line RST3. The difference between Figure 6c and Figure 6b is that the second terminal of the first transistor T1 is connected to the third node N3.

[0166] In an exemplary embodiment, in a display substrate using the pixel driving circuit shown in FIG. 6a, the multiple gate control signal lines SL may include a first reset control line RST1, a second reset control line RST2, a scan signal line GL, and a light emission control line EML; in a display substrate using the pixel driving circuit shown in FIG. 6b and FIG. 6c, the multiple gate control signal lines SL may include a first reset control line RST1, a second reset control line RST2, a third reset control line RST3, a scan signal line GL, and a light emission control line EML.

[0167] In an exemplary embodiment, in the pixel driving circuit shown in FIG6a, the first transistor T1 to the seventh transistor T7 are all P-type transistors; in the pixel driving circuit shown in FIG6b, the first transistor T1 and the second transistor T2 are N-type transistors, and the other transistors are all P-type transistors; in the pixel driving circuit shown in FIG6c, the second transistor T2 is an N-type transistor, and the other transistors are all P-type transistors; that is, FIG6a shows an LTPS pixel driving circuit, and FIG6b and FIG6c show LTPO pixel driving circuits. In the LTPS pixel driving circuit, the circuit structure layer 200 may include a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer disposed on the substrate 100, as shown in FIG5a; in the LTPO pixel driving circuit, the circuit structure layer 200 may include a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer disposed on the substrate 100, as shown in FIG5b.

[0168] When a display device with a display substrate is placed on a wireless charging device for charging, the display device is susceptible to electromagnetic interference, resulting in water ripples BL (water ripples are typically bright and dark ripples extending along the first direction X and rolling along the second direction Y; bright ripples BL1 and dark ripples BL2 are usually arranged alternately along the second direction Y), as shown in Figure 7. The water ripples BL generated in the display area AA are usually perpendicular to the extension direction of the data line DL. The data line DL extends along the second direction Y and is arranged along the first direction X. The water ripples BL are usually extended along the first direction X and arranged along the second direction Y. The generation of water ripples BL seriously affects the display effect and results in poor display quality.

[0169] This disclosure provides a display substrate, which may include:

[0170] A substrate, the substrate including a display area and a border area surrounding the display area, the border area including a first border area located on one side of the display area;

[0171] Multiple sub-pixels are located on one side of the substrate and in the display area;

[0172] Multiple data lines are located in the display area and electrically connected to the multiple sub-pixels;

[0173] Multiple data output lines are located in the first border area and are electrically connected to the multiple data lines;

[0174] Multiple driver pads are located in the first frame area and on the side of the multiple data output lines away from the display area; each of the multiple data output lines is connected to a corresponding data line at the end closer to the display area and to a corresponding driver pad at the end away from the display area.

[0175] A shielding structure, comprising a first shielding structure located in the first border region, wherein at least a portion of the structure of at least one of the plurality of data output lines is projected onto the substrate and the orthographic projection of the first shielding structure onto the substrate is within the range of the orthographic projection of the first shielding structure onto the substrate; and in a direction perpendicular to the plane of the substrate, the shielding structure is located between the at least one data output line and the substrate.

[0176] In the display substrate provided in this embodiment, a first shielding structure is provided in the first frame area. The orthographic projection of at least a portion of the structure of at least one data output line on the substrate is located within the range of the orthographic projection of the first shielding structure on the substrate. In the direction perpendicular to the plane of the substrate, the shielding structure is located between the data output line and the substrate. The first shielding structure can shield electromagnetic interference during wireless charging, which affects the data signal written by the data output line to the sub-pixels in the display area. It can solve the technical problem of water ripples in the display area caused by electromagnetic interference during wireless charging to a certain extent.

[0177] As shown in Figure 8a, this is a schematic diagram of the structure of a display substrate provided in an embodiment of the present disclosure. The display substrate may include:

[0178] The substrate may include a display area AA and a border area BB surrounding the display area AA. The border area BB may include a first border area B1 located on one side of the display area AA.

[0179] Multiple sub-pixels Pxij can be located on one side of the substrate and within the display area AA;

[0180] Multiple data lines DL can be located in the display area AA and electrically connected to multiple sub-pixels Pxij;

[0181] Multiple data output lines DT can be located in the first border area B1 and electrically connected to multiple data lines DL;

[0182] Multiple drive pads PA1 can be located in the first frame area B1 and on the side of multiple data output lines DT away from the display area AA; the end of each data output line DT near the display area AA is electrically connected to a corresponding data line DL, and the end away from the display area AA is connected to the corresponding drive pad PA1.

[0183] The shielding structure PL may include a first shielding structure PL1, which may be located in the first border region B1. The orthographic projection of at least a portion of the structure of at least one of the multiple data output lines DT onto the substrate may be located within the range of the orthographic projection of the first shielding structure PL1 onto the substrate. In a direction perpendicular to the plane of the substrate, the shielding structure PL may be located between the at least one data output line DT and the substrate.

[0184] In an exemplary embodiment, as shown in Figures 8a to 8f, the first border region B1 may have a bending region 12;

[0185] As shown in Figures 8c, 8d, 8e and 9a, Figure 9a is an enlarged structural schematic diagram of position H1 in Figures 8c to 8e. In the bending area 12, the first shielding structure PL1 can be provided with multiple groove structures KL. The multiple groove structures KL can extend along the second direction Y and be arranged at intervals along the first direction X. Multiple data output lines DT can extend along the second direction Y and be arranged at intervals along the first direction X. In the first direction X, at least one data output line DT can be provided between two adjacent groove structures KL. In the plane parallel to the substrate, the first direction X intersects the second direction Y.

[0186] In an exemplary embodiment, as shown in Figures 9a to 9i, Figures 9b and 9c are cross-sectional structural diagrams along the M0-M0 position in Figure 9a, Figures 9d to 9g are cross-sectional structural diagrams along the M01-M01 position in Figure 9a, and Figures 9h and 9i are cross-sectional structural diagrams along the M02-M02 position in Figure 9a. In the bending area 12, in the first direction X, a shielding strip PL11 is formed between two adjacent groove structures KL. Multiple data output lines DT correspond one-to-one with multiple shielding strips PL11. The orthogonal projection of the data output line DT on the substrate is located within the range of the orthogonal projection of the corresponding shielding strip PL11 on the substrate.

[0187] In an exemplary embodiment, as shown in Figures 9a to 9c and 9d to 9g, the groove structure KL can be configured as a hollow structure that penetrates the first shielding structure PL in the direction Z perpendicular to the plane of the substrate.

[0188] In an exemplary embodiment, as shown in Figures 9a to 9c and 9d to 9g, within the same groove structure KL, on the same side of the second centerline Q2-Q2 along the first direction X, the distance d1 between the edge of the groove structure KL and the edge of the nearest data output line DT is greater than or equal to 0.3 micrometers. The second centerline Q2-Q2 is the centerline extending from the groove structure KL along the second direction Y. For example, the value of d1 can be greater than or equal to 0.5 micrometers.

[0189] In an exemplary embodiment, as shown in Figures 9a, 9d, and 9f, in the bending region 12, the first shielding structure PL1 may include multiple shielding strips PL11. The shielding strips PL11 may extend along the second direction Y and be arranged at intervals along the first direction X. Multiple data output lines DT may extend along the second direction Y and be arranged at intervals along the first direction X. In a plane parallel to the substrate, the first direction X intersects with the second direction Y.

[0190] In an exemplary embodiment, as shown in Figures 9a, 9d, and 9f, in the bending area 12, multiple data output lines DT correspond one-to-one with multiple shielding strips PL11. The orthographic projection of each data output line DT on the substrate is within the range of the orthographic projection of the corresponding shielding strip PL11 on the substrate.

[0191] In an exemplary embodiment, as shown in Figures 9a, 9d, and 9f, within the same shielding strip PL11, on the same side of the first centerline Q1-Q1 in the first direction X, the distance d1 between the edge of the shielding strip PL11 and the edge of the nearest data output line DT is greater than or equal to 0.3 micrometers. The first centerline Q1-Q1 is the centerline of the shielding strip PL11 extending along the second direction Y. For example, the value of d1 can be greater than or equal to 0.5 micrometers.

[0192] In an exemplary embodiment, as shown in Figures 9a to 9c and Figures 9d to 9g, in the bending region 12, in the first direction X, the size d2 of the groove structure KL (i.e., the distance between two adjacent shielding strips PL11) can be greater than or equal to 2 micrometers, the size d3 of the shielding strip PL11 can be greater than or equal to 6 micrometers, and the size d4 of the data output line DT can be greater than or equal to 5 micrometers, wherein d3 = d4 + 2 * d1.

[0193] In an exemplary embodiment, the first shielding structure PL1 of the bending area 12 is provided with multiple groove structures KL, which can prevent the first shielding structure PL1 from cracking during the bending process of the bending area 12. The multiple groove structures KL are set as hollow structures that penetrate the first shielding structure PL to form multiple shielding strips PL11, which makes the first shielding structure PL1 easier to bend in the bending area 12 and avoids cracking. It can prevent the first shielding structure PL1 from being damaged to a certain extent, so that the first shielding structure PL1 can play a better shielding role and reduce the interference of electromagnetic signals on the data signal output by the data output line DT during the charging process.

[0194] In an exemplary embodiment, at least one sub-pixel Pxij among a plurality of sub-pixels may include a plurality of transistors. In a direction perpendicular to the plane of the substrate, at least one transistor may include: an active layer located on one side of the substrate, a gate located on the side of the active layer away from the substrate, and a source and a drain located on the side of the gate away from the substrate.

[0195] As shown in Figures 8b, 8d, 8e, and 9b, the shielding structure PL can be disposed in the same layer as the gate of at least one transistor; or, as shown in Figures 8a, 8c, 8f, and 9c, the shielding structure PL can be located between the active layer of at least one transistor and the substrate 100 in the direction Z perpendicular to the plane of the substrate.

[0196] In an exemplary embodiment, as shown in Figures 5a and 5b, the display substrate may further include a shielding layer BSM. In a structure where the shielding structure PL is located between the active layer of at least one transistor and the substrate in a direction Z perpendicular to the plane of the substrate, the shielding structure PL may be disposed in the same layer as the shielding layer BSM.

[0197] In an exemplary embodiment, the direction from the display area AA to the first border area B1 (i.e., the opposite direction of the second direction Y) may include a multiplexed circuit area 11, a bending area 12, and a signal access area B11 arranged sequentially.

[0198] As shown in Figures 9b and 9c, in the bending region 12, the data output line DT can be located on the side of the source and drain away from the substrate.

[0199] In an exemplary embodiment, as shown in Figures 8a to 8f, the signal access area B11 may include a second fan-out area 13, an anti-static area 15, and a third fan-out area 16. In an exemplary embodiment, the multiplexing circuit area 11 may be a first fan-out area 11.

[0200] In an exemplary embodiment, the at least one sub-pixel Pxij may further include at least one capacitor (for example, it may include a storage capacitor Cst as shown in Figures 6a to 6c), the plurality of transistors may include at least one type of transistor (in Figure 6a, all seven transistors are type of transistors, in Figure 6b, the third transistor T3 to the seventh transistor T7 are all type of transistors, and in Figure 6c, the first transistor T1, the third transistor T3 to the seventh transistor T7 are all type of transistors), the active layer may include the active layer of the at least one type of transistor, the gate may include the gate of the at least one type of transistor, the first plate of the capacitor is disposed in the same layer as the gate of the type of transistor, and in a direction perpendicular to the plane of the substrate, a second plate of the capacitor is further provided between the gate of the type of transistor and the source and drain of the first type of transistor;

[0201] As shown in Figures 8b, 8d and 8e, in the structure in which the shielding structure PL is disposed on the same layer as the gate of at least one transistor, the shielding structure PL can be disposed on the same layer as the gate of the first type of transistor, and in the signal access area B11, at least one data output line DT can be disposed on the same layer as the second plate of the capacitor.

[0202] As shown in Figures 8a, 8c, and 8f, in a structure where the shielding structure PL is located between the active layer and the substrate, the shielding structure PL can be located between the active layer of the first-type transistor and the substrate. In the signal access area B11, at least one data output line DT can be disposed on the same layer as at least one of the gate of the first-type transistor and the second plate of the capacitor. That is, the data output line DT can be disposed on the same layer as the gate of the first-type transistor, or the data output line DT can be disposed on the same layer as the second plate of the capacitor, or the data output line DT can be a double-layer structure disposed on the same layer as the gate of the first-type transistor and the second plate of the capacitor. The double-layer structure can reduce the voltage drop of the data output line DT, which is beneficial to improving display uniformity. Alternatively, multiple data output lines DT can be disposed on the same layer as the gate of the first-type transistor and the second plate of the capacitor, and alternately disposed. For example, they can be disposed alternately. In two adjacent data output lines DT, one data output line DT is disposed on the same layer as the gate of the first-type transistor, and the other data output line DT is disposed on the same layer as the second plate of the capacitor.

[0203] In an exemplary embodiment, as shown in Figures 8b, 8d and 8e, in a structure in which the shielding structure PL is disposed on the same layer as the gate of the first type of transistor, in the multiplexing circuit region 11, at least one data output line DT can be disposed on the same layer as the second plate of the capacitor.

[0204] As shown in Figures 8a, 8c, and 8f, in the shielding structure PL located between the active layer of the first type of transistor and the substrate, in the multiplexing circuit region 11, at least one data output line DT can be disposed on the same layer as at least one of the gate of the first type of transistor and the second plate of the capacitor. That is, the data output line DT can be disposed on the same layer as the gate of the first type of transistor, or the data output line DT can be disposed on the same layer as the second plate of the capacitor, or the data output line DT can be a double-layer structure disposed on the same layer as the gate of the first type of transistor and the second plate of the capacitor. The double-layer structure can reduce the voltage drop of the data output line DT, which is beneficial to improving the display uniformity.

[0205] In an exemplary embodiment, the plurality of transistors may further include at least one second type transistor, and the active layer may further include the active layer of the at least one second type transistor (as shown in Figures 6b and 6c, where the first transistor T1 in Figure 6b is a second type transistor and the second transistor T2 in Figure 6c is a second type transistor). The gate may further include the gate of the at least one second type transistor. In a direction perpendicular to the plane of the substrate, the active layer of the at least one second type transistor may be located on the side of the second plate of the capacitor away from the substrate, and the gate of the second type transistor may be located between the active layer of the second type transistor and the source and drain.

[0206] As shown in Figures 8b, 8d and 8e, in the structure where the shielding structure PL and the gate of the first type of transistor are arranged on the same layer, in the signal access area B11, at least one data output line DT can be arranged on the same layer as at least one of the second plate of the capacitor and the gate of the second type of transistor. That is, the data output line DT can be set as a double-layer structure arranged on the same layer as the second plate of the capacitor and the gate of the second type of transistor, which can reduce the voltage drop of the data output line DT.

[0207] As shown in Figures 8a, 8c, and 8f, in the structure where the shielding structure PL is located between the active layer of the first type of transistor and the substrate, in the signal access region B11, at least one data output line DT can be disposed in the same layer as at least one of the gate of the first type of transistor, the second plate of the capacitor, and the gate of the second type of transistor. That is, the data output line DT can be configured as a three-layer structure disposed in the same layer as the gate of the first type of transistor, the second plate of the capacitor, and the gate of the second type of transistor. Alternatively, the data output line DT can be configured as a two-layer structure disposed in the same layer as at least two of the gate of the first type of transistor, the second plate of the capacitor, and the gate of the second type of transistor, which can reduce the voltage drop of the data output line DT.

[0208] In an exemplary embodiment, as shown in Figures 8b, 8d and 8e, in a structure in which the shielding structure PL is disposed on the same layer as the gate of the first type of transistor, in the multiplexing circuit region 11, at least one data output line DT is disposed on the same layer as at least one of the second plate of the capacitor and the gate of the second type of transistor. That is, the data output line DT can be configured as a double-layer structure disposed on the same layer as the second plate of the capacitor and the gate of the second type of transistor, which can reduce the voltage drop of the data output line DT.

[0209] As shown in Figures 8a, 8c, and 8f, in the structure where the shielding structure PL is located between the active layer of the first type of transistor and the substrate, in the multiplexing circuit region 11, at least one data output line DT is disposed on the same layer as at least one of the gate of the first type of transistor, the second plate of the capacitor, and the gate of the second type of transistor. That is, the data output line DT can be configured as a three-layer structure disposed on the same layer as the gate of the first type of transistor, the second plate of the capacitor, and the gate of the second type of transistor, or the data output line DT can be configured as a two-layer structure disposed on the same layer as at least two of the gate of the first type of transistor, the second plate of the capacitor, and the gate of the second type of transistor, which can reduce the voltage drop of the data output line DT.

[0210] In an exemplary embodiment, as shown in Figures 8a to 8d and 8f, the display substrate may further include a plurality of multiplexing circuits 50. The plurality of multiplexing circuits 50 may be located in the multiplexing circuit area 11. A plurality of data output lines DT may correspond one-to-one with the plurality of multiplexing circuits 50. Each data output line DT is connected to a corresponding data line DL through the corresponding multiplexing circuit 50. Each multiplexing circuit 50 is configured to provide the signal provided by one data output line DT to at least two data lines DL among the plurality of data output lines DT in a time-division manner.

[0211] As shown in Figures 8a, 8c and 8f, in the structure where the shielding structure PL is located between the active layer of the first type of transistor and the substrate, the orthogonal projection of the multiple multiplexing circuits 50 on the substrate can be located within the range of the orthogonal projection of the first shielding structure PL on the substrate. In the direction perpendicular to the plane of the substrate, the multiple multiplexing circuits 50 can be located on the side of the shielding structure PL away from the substrate.

[0212] As shown in Figures 8b and 8d, in the structure in which the shielding structure PL and the gate of the first type of transistor are arranged on the same layer, the orthographic projection of the multiple multiplexing circuits 50 on the substrate does not overlap with the orthographic projection of the first shielding structure PL on the substrate, and the area corresponding to the first shielding structure PL and the multiple multiplexing circuits 50 is set as a hollow structure K11.

[0213] In an exemplary embodiment, as shown in Figures 8a to 8f, an anti-static region 15 can be provided between the second fan-out region 13 and the third fan-out region 16. The anti-static region 15 can be provided with multiple anti-static circuits 40. As shown in Figures 8a, 8c and 8f, in the structure where the shielding structure PL is located between the active layer of the first type of transistor and the substrate, the orthogonal projection of the multiple anti-static circuits 40 on the substrate can be located within the range of the orthogonal projection of the first shielding structure PL on the substrate. In the direction perpendicular to the plane of the substrate, the multiple anti-static circuits 40 can be located on the side of the shielding structure PL away from the substrate. As shown in Figures 8b, 8d and 8e, in the structure where the shielding structure PL and the gate of the first type of transistor are disposed on the same layer, the orthogonal projection of the multiple anti-static circuits 40 on the substrate does not overlap with the orthogonal projection of the first shielding structure PL on the substrate. The area corresponding to the first shielding structure PL and the multiple anti-static circuits 40 is set as a hollow structure K12.

[0214] In an exemplary embodiment, as shown in FIG8e, the multiplexing circuit area 11 does not have a structure in which multiple multiple selection circuits 50 are provided and the anti-static area 15 has a structure in which multiple anti-static circuits 40 are provided. In the structure in which the shielding structure PL and the gate of the first type of transistor are arranged on the same layer, the orthographic projection of the multiple anti-static circuits 40 on the substrate does not overlap with the orthographic projection of the first shielding structure PL on the substrate. The area corresponding to the first shielding structure PL and the multiple anti-static circuits 40 is set as a hollow structure K12. The multiplexing circuit area 11 does not have a hollow structure K11.

[0215] In an exemplary embodiment, as shown in Figures 10a to 10c, the first border region B1 may not have a bending region 12. As shown in Figures 10a and 10c, in the structure where the shielding structure PL is located between the active layer of the first type of transistor and the substrate, the area corresponding to the first shielding structure PL1 and the anti-static circuit 40 and the multiplexing circuit 50 may not have a cutout structure. As shown in Figure 10b, in the structure where the shielding structure PL and the gate of the first type of transistor are disposed on the same layer, the orthographic projection of the multiple multiplexing circuits 50 on the substrate does not overlap with the orthographic projection of the first shielding structure PL1 on the substrate. The area corresponding to the first shielding structure PL1 and the multiple multiplexing circuits 50 is set as a cutout structure K11. The orthographic projection of the multiple anti-static circuits 40 on the substrate does not overlap with the orthographic projection of the first shielding structure PL on the substrate. The area corresponding to the first shielding structure PL1 and the multiple anti-static circuits 40 is set as a cutout structure K12.

[0216] In an exemplary embodiment, as shown in Figures 8f and 10c, in a structure where the shielding structure PL is located between the active layer of the first type of transistor and the substrate, the shielding structure PL may further include a third shielding structure PL3. The third shielding structure PL3 may be located in the bonding region 14, and the first shielding structure PL1 may be connected to the third shielding structure PL3. For example, the first shielding structure PL1 and the third shielding structure PL3 may be an integrally formed structure.

[0217] In an exemplary embodiment, as shown in FIG3b, which is a schematic diagram of the multiplexing circuit 50, the display substrate may further include:

[0218] At least two data selection lines MUX: located in the first border region B1, in a direction perpendicular to the plane of the substrate, at least two data selection lines MUX are located on the side of the shielding structure PL away from the substrate.

[0219] At least one of the multiplexer circuits 50 is electrically connected to at least two data select lines MUX, and each multiplexer circuit 50 is configured to provide a signal of one data output line DT to at least two data lines DL in a time-division manner under the control of the at least two data select lines MUX.

[0220] In an exemplary embodiment, the number of data lines DL can be M, the number of data output lines DT can be k, and the number of data selection lines MUX can be z, where k = M / z, M and k are both positive integers, and z can be an integer greater than or equal to 2.

[0221] Each multiplexer circuit 50 is electrically connected to the adjacent z data lines DL, and is configured to provide the signal of one data output line DT to the corresponding z data lines DL in a time-division manner under the control of the z data selection lines MUX.

[0222] As shown in Figure 3b, the number of data selection lines MUX can be 6 (i.e., the value of z can be 6). The data selection lines MUX can include the first data selection line MUX1 to the sixth data selection line MUX6. Each multiplexing circuit 50 is electrically connected to the adjacent 6 data lines DL and is configured to provide the signal of one data output line DT to the corresponding 6 data lines DL in a time-division manner under the control of the 6 data selection lines MUX.

[0223] In an exemplary embodiment, as shown in Figures 11a to 11f, Figures 11a and 11d are schematic diagrams of the planar structure of a display substrate without a shielding structure PL, Figures 11b and 11c are schematic diagrams of the planar structure of the display substrate shown in Figure 11a after a shielding structure is provided, and Figures 11e and 11f are schematic diagrams of the planar structure of the display substrate shown in Figure 11d after a shielding structure is provided. The display substrate may also include various constant voltage signal lines HV, the shielding structure PL may also include a second shielding structure PL2, and the border area BB may also include a second border area B2, a third border area B3, and a fourth border area B4. In the first direction X, the third border area B3 and the fourth border area B4 may be located on both sides of the display area AA. In the second direction Y, the first border area B1 and the second border area B2 may be located on both sides of the display area AA. In a direction parallel to the plane of the substrate, the first direction X may intersect with the second direction Y.

[0224] The second shielding structure PL2 can be located in the second frame region B2, the third frame region B3, and the fourth frame region B4. Multiple constant voltage signal lines HV can be located in the third frame region B3 and the fourth frame region B4. In the direction perpendicular to the plane of the substrate, at least one of the multiple constant voltage signal lines HV can be located on the side of the second shielding structure PL2 away from the substrate.

[0225] In an exemplary embodiment, the constant voltage signal line HV may include a first power supply line VDD, a second power supply line VSS, a first initial signal line Vinit1, and a second initial signal line Vinit2, as shown in Figures 6a to 6c.

[0226] In an exemplary embodiment, as shown in Figures 11c, 11d, 11e, and 11f, the first shielding structure PL and the second shielding structure PL can be connected to each other to form a ring structure surrounding the display area AA.

[0227] In an exemplary embodiment, as shown in Figures 11c, 11d, 11e, and 11f, the first shielding structure PL and the second shielding structure PL can be an integral structure.

[0228] In an exemplary embodiment, as shown in Figures 11c and 11f, in a structure where the shielding structure PL is located between the active layer of the first type of transistor and the substrate, the shielding structure PL may further include a third shielding structure PL3. The third shielding structure PL3 may be located in the bonding region 14. The first shielding structure PL1 may be connected to the third shielding structure PL3 and the second shielding structure PL2. For example, the first shielding structure PL1, the third shielding structure PL3, and the second shielding structure PL2 may be an integrally formed structure. The first shielding structure PL1 shown in Figure 11b can be the same as the first shielding structure shown in Figures 8a and 8c (this structure can be that the shielding structure PL is located between the active layer of the first type of transistor and the substrate). In the structure where the multiplexing circuit region 11 is provided with a multiplexing circuit 50 and the shielding structure is arranged on the same layer as the gate of the first type of transistor, the area corresponding to the first shielding structure PL1 and the anti-static circuit 40 and the multiplexing circuit 50 can be set as a hollow structure. The shielding structure PL shown in Figure 11e can be the same as the first shielding structure shown in Figure 10a (this structure can be that the shielding structure PL is located between the active layer of the first type of transistor and the substrate). In the structure where the multiplexing circuit region 11 is provided with a multiplexing circuit 50 and the shielding structure is arranged on the same layer as the gate of the first type of transistor, the area corresponding to the first shielding structure PL1 and the anti-static circuit 40 and the multiplexing circuit 50 can be set as a hollow structure.

[0229] In an exemplary embodiment, as shown in FIG13a, which is a cross-sectional structural schematic diagram along the M2-M2 position in FIG11b to FIG11c and FIG11e to FIG11f, the second shielding structure PL2 can be electrically connected to one of the various constant voltage signal lines HV (for example, the second shielding structure PL2 can be electrically connected to the second power line VSS, and the second power line VSS can be connected to the second shielding structure PL2 in the first frame area B1). The orthogonal projection of the various constant voltage signal lines HV on the substrate can be located within the range of the orthogonal projection of the second shielding structure PL on the substrate. In the direction perpendicular to the plane of the substrate, the various constant voltage signal lines HV can be located on the side of the second shielding structure PL2 away from the substrate.

[0230] Alternatively, as shown in Figure 13b, which is a cross-sectional structural diagram along the M2-M2 position in Figures 11b to 11c and Figures 11e to 11f, the various constant voltage signal lines HV may include a first type of constant voltage signal line HV and at least one second type of constant voltage signal line HV. The second shielding structure PL2 may be reused as the first type of constant voltage signal line HV (for example, the first type of constant voltage signal line HV may be the second power line VSS, and the second power line VSS may be electrically connected to the second shielding structure PL2 in the first border area B1). In the direction perpendicular to the plane where the substrate is located, at least one second type of constant voltage signal line HV (for example, the second type of constant voltage signal line HV may include the first power line VDD, the first initial signal line Vinit1, and the second initial signal line Vinit2) may be located on the side of the second shielding structure PL away from the substrate.

[0231] In an exemplary embodiment, as shown in Figures 11a to 13b, Figures 12a to 12d are schematic diagrams of several cross-sectional structures along the M1-M1 position (which can be viewed from the M1-M1 position in the direction facing the arrow) in Figures 11b to 11c and 11e to 11f, and Figures 13a to 13b are schematic diagrams of several cross-sectional structures along the M2-M2 position (which can be viewed from the M2-M2 position in the direction facing the arrow) in Figures 11b to 11c and 11e to 11f. The border area BB can include a peripheral area BB1 surrounding the display area AA and an edge area BB2 surrounding the peripheral area BB1. Multiple constant voltage signal lines HV and a shielding structure PL can be located in the peripheral area BB1. The display area AA and the peripheral area BB1 form an encapsulation area A1. The display substrate may also include:

[0232] The blocking structure ML can be located in the edge area BB2 and partially surround the display area AA, and be set in the same layer as the shielding structure PL;

[0233] A plurality of first grooves C1 are located in the edge region BB2 and are arranged sequentially at intervals in a direction away from the peripheral region BB1, and partially surround the peripheral region BB1, wherein at least one first groove C1 penetrates at least partially the blocking structure ML.

[0234] In an exemplary embodiment, the display substrate may further include: a signal access area B11, which may be located at the edge area BB2 of the first border area B1; the orthographic projection of the blocking structure ML on the substrate 100 does not overlap with the orthographic projection of the signal access area B11 on the substrate; and the orthographic projection of the plurality of first grooves C1 on the substrate does not overlap with the orthographic projection of the signal access area B11 on the substrate.

[0235] In an exemplary embodiment, as shown in Figures 12a and 12c, at least one first groove C1 penetrates a portion of the blocking structure ML, and as shown in Figures 12b and 12d, at least one first groove C1 penetrates the blocking structure ML. Figures 13a, 12c, and 12d show the shielding structure PL located between the active layer of the first type of transistor and the substrate 100, while Figures 13b, 12a, and 12b show the shielding structure PL disposed on the same layer as the gate of the first type of transistor.

[0236] In an exemplary embodiment, as shown in Figures 12a to 12d, the display substrate may further include a plurality of inorganic film layers located on one side of the substrate 100 and an organic layer 03 covering a plurality of first grooves C1, wherein each first groove C1 penetrates at least one of the plurality of inorganic film layers.

[0237] In an exemplary embodiment, as shown in Figures 12a to 12d and Figures 13a to 13b, the organic layer 03 may include a first planarization layer 205 and a second planarization layer 206 sequentially stacked along a direction Z away from the substrate 100. The first planarization layer 205 covers a plurality of first grooves C1, and the second planarization layer 206 is located on the side of the first planarization layer 205 away from the substrate 100.

[0238] In an exemplary embodiment, as shown in FIG5, FIG12a to FIG12d, the plurality of inorganic film layers may include a first gate insulating layer 201, a second gate insulating layer 202, and an interlayer dielectric layer 203 sequentially stacked along the direction Z away from the substrate 100.

[0239] In an exemplary embodiment, as shown in Figures 12a to 12d, the inorganic film layer and the barrier structure ML between each two adjacent first grooves C1 constitute a barrier portion ZL; the plurality of inorganic film layers may further include: a buffer layer 1502 located between the gate insulating layer 201 and the barrier structure ML, and a barrier layer 1501 located between the barrier structure ML and the substrate 100 in the direction Z perpendicular to the plane of the substrate 100. In an exemplary embodiment, as shown in FIG12a, the first groove C1 can penetrate a portion of the blocking structure ML and the second gate insulating layer 202 and the interlayer insulating layer 203; as shown in FIG12b, the first groove C1 can penetrate the first gate insulating layer 201, the blocking structure ML, the second gate insulating layer 202 and the interlayer insulating layer 203; as shown in FIG12c, the first groove C1 can penetrate the buffer layer 1502, the first gate insulating layer 201, the second gate insulating layer 202 and the interlayer insulating layer 203 and a portion of the blocking structure ML; as shown in FIG12d, the first groove C1 can penetrate the blocking structure ML, the buffer layer 1502, the first gate insulating layer 201, the second gate insulating layer 202 and the interlayer insulating layer 203.

[0240] In an exemplary embodiment, as shown in Figures 9b and 9c, at least a portion of the inorganic film layer between the data output line DT and the shielding strip PL11 can be removed in the bending region 12 and filled with an organic layer 03, which can prevent the inorganic film layer from breaking during bending; for example, all the inorganic film layers between the data output line DT and the shielding strip PL11 can be removed and filled with an organic layer 03.

[0241] In an exemplary embodiment, since the plurality of first grooves C1 are located within the edge region BB2 and there is a gap between them and the encapsulation region A1, the plurality of first grooves C1 can block cracks that appear at the edge of the display substrate, preventing the cracks from extending into the encapsulation region A1. Since the plurality of first grooves C1 can block the extension of cracks, the inorganic film layer between two adjacent first grooves C1 can form a blocking part ZL, which can also be called a crack dam.

[0242] Referring to Figures 11a to 11f, it can be seen that the orthographic projection of each first groove C1 onto the substrate 01 can be an annular shape with an opening k0 (i.e., the first groove C1 does not overlap with the signal access area B11, the bending area 12, and the multiplexing circuit area 11, and the opening k0 is formed in the first border area B). For example, referring to Figures 11a to 11f, two annular first grooves C1 with openings are shown. Figures 12a to 12d show a number of five first grooves C1. The number of first grooves C1 is not limited to two or five. It can be set according to the actual product. The number of first grooves C1 at different positions in the edge area BB2 can be the same or different (for example, the number of first grooves C1 in the edge area BB2 of the second border area B2 can be the same or different from the number of first grooves C1 in the edge areas BB2 of the third border area B3 and the fourth border area B3). Each annular ring (i.e., each first groove C1) may surround the encapsulation region A1, and the orthographic projection of each opening k0 on the substrate 100 may at least partially overlap with the signal access region B11, that is, the width of each opening (the dimension along the first direction X) may be greater than the width of the signal access region B11. In an exemplary embodiment, as shown in FIG11a, the first groove C1 may be disconnected at the opening k0 position (i.e., the first groove C1 may be disconnected in the signal access region B11, the bending region 12, and the multiplexing circuit region 11), and the region outside the opening k0 of the first groove C1 may also be disconnected.

[0243] In an exemplary embodiment, as shown in Figures 13a and 13b, which are cross-sectional structural diagrams along the M2-M2 position in Figures 11b to 11c and Figures 11e to 11f, the encapsulation area A1 may include a display area AA and a peripheral area BB1 surrounding the display area AA. The border area BB may include the peripheral area BB1 and the edge area BB2. The peripheral area BB1 may be provided with peripheral circuits (e.g., GOA circuits), and the edge area BB2 may be provided with a first groove C1. In Figure 13a, T1 is one of the transistors located in the display area AA, M2 and M3 are two transistors in the peripheral area BB1, and 22-1 and 22-2 are two capacitors located in the peripheral area BB1. In the peripheral area BB1: the second power line VSS passes through the third transition electrode 233 and the fourth transition electrode 234 (the third transition electrode 233 and the fourth transition electrode 234 can be arranged on the same layer as the first transition electrode 231 in Figure 5a, or the third transition electrode 233 and the fourth transition electrode 234 can be arranged on the same layer as the first transition electrode 231 in Figure 5b) and the second electrode 303 (the second electrode 303 can be used as the second power line VSS in Figures 6a to 6c). Electrically connected, the second shielding structure PL2 extends to the first frame area B1 and is connected to the first shielding structure PL1 located in the first frame area B1; the second power line VSS can extend to the first frame area B1 and is connected to the flexible circuit board 30 in the bonding area 14. The first shielding structure PL1 can be electrically connected to the second power line VSS through a via. The shielding structure PL and the second power line VSS are electrically connected to form a double-layer structure. On the one hand, it can reduce the voltage drop of the second power line VSS and improve the display uniformity. On the other hand, the ring-shaped shielding structure PL surrounding the display area AA is set in the peripheral area BB1, which is similar to adding a reinforcing rib and can improve the strength of the peripheral area BB1 of the display substrate.

[0244] In an exemplary embodiment, as shown in Figures 13a and 13b, a barrier dam 04 can be provided in the peripheral region BB1. This barrier dam 04 can also be made of organic material. The orthographic projection of the organic layer 03 onto the substrate 01 and the orthographic projection of the barrier dam 04 onto the substrate 100 may not overlap. Since the barrier dam 04 is located within the peripheral region BB1, a gap D11 exists between the barrier dam 04 and the display region AA. This effectively prevents the organic material from flowing out of the encapsulation region AA when forming the organic encapsulation film layer in the encapsulation film using organic materials. Furthermore, it effectively prevents moisture in the air from entering the display region due to the hydrophilic properties of the organic material, thus affecting the display region's quality and further ensuring the quality of the display substrate.

[0245] In an exemplary embodiment, as shown in Figures 13a and 13b, the barrier dam 04 may include at least one closed annular structure 041, each annular structure 041 surrounding the display area AA of the substrate 100. By surrounding the display area AA with the annular structures 041, effective protection of the display area AA can be achieved.

[0246] In an exemplary embodiment, as shown in Figures 13a and 13b, the barrier dam 04 may include a plurality of spaced-apart annular structures 041. For example, Figures 10a and 10b both show a barrier dam 04 including two annular structures 041. Furthermore, the plurality of annular structures 041 may be equally spaced, meaning the spacing between any two adjacent annular structures 041 may be a fixed value. By spaced-aparting the plurality of annular structures 041, effective protection of the display area AA can be further improved. For example, the barrier dam 04 may be formed by deposition.

[0247] In this embodiment, the substrate 100 can be made of a flexible material. This flexible material can be polyimide (PI), which has good properties such as high temperature resistance, low temperature resistance, and oxidation resistance.

[0248] In an exemplary embodiment, as shown in Figures 11a to 11f, the edge region BB2 of the substrate 100 may also be provided with a cutting line L1 surrounding the first groove C1. After an inorganic film layer with multiple first grooves C1 is formed on one side of the substrate 100, it can be cut along the cutting line L1 to obtain a display substrate. Accordingly, the annular first groove C1 can be designed along the shape of the cutting line L1. Since cracks are prone to appear at the edge of the display substrate during the cutting operation, by designing the first groove C1 along the shape of the cutting line L1, the cracks generated during the cutting operation can be effectively blocked, that is, the extension of cracks that occur during the cutting operation can be effectively avoided.

[0249] In an exemplary embodiment, as shown in Figures 8a to 8f and Figures 11a to 11f, the border region BB may further include a second border region B2, a third border region B3, and a fourth border region B4. In the first direction X, the third border region B3 and the fourth border region B4 may be located on either side of the display region AA. In the second direction Y, the first border region B1 and the second border region B2 may be located on either side of the display region AA. The first direction X intersects the second direction Y. The display substrate may further include:

[0250] Multiple gate control signal lines SL are located in the display area AA. The multiple gate control signal lines SL may include multiple scan signal lines GL (as shown in Figures 6a to 6c, the scan signal lines GL can be connected to the control electrode of the fourth transistor T4); multiple sub-pixels Pxij can form multiple rows, and the scan signal lines GL can be electrically connected to at least one row of sub-pixels Pxij; the data line DL is configured to provide data signals to the corresponding sub-pixels Pxij under the control of the scan signal lines GL.

[0251] Multiple scan gate drive circuits GOA are located in the third border region B3 and the fourth border region B4, and each scan gate drive circuit GOA is electrically connected to at least one scan signal line GL.

[0252] Multiple bonding pads PA are located in the first border area B1. The multiple bonding pads PA may include multiple driving pads PA1 and multiple gate driving pads PA2. In the first direction X, the multiple gate driving pads PA2 may be located on both sides of the multiple driving pads PA1.

[0253] Multiple gate drive signal lines GOAL are located in the third frame region B3 and the fourth frame region B4, and extend to the first frame region B1, and are electrically connected to multiple gate drive pads PA2 and multiple scan gate drive circuits GOA.

[0254] Integrated circuit 20, located in the first border region B1, is bonded to multiple bonding pads PA. Integrated circuit 20 is electrically connected to multiple data lines DL through multiple drive pads PA1, and integrated circuit 20 is electrically connected to multiple gate drive signal lines GOAL through multiple gate drive pads PA2. Integrated circuit 20 is configured to provide data signals to multiple data lines DL and provide gate drive signals to multiple scan gate drive circuits GOA through multiple gate drive signal lines GOAL.

[0255] Multiple scan gate drive circuits (GOAs) are configured to provide scan timing signals to multiple scan signal lines (GLs) under the control of gate drive signals. Integrated circuit 20 is configured to output interval signals to multiple scan gate drive circuits (GOAs) at at least one position before and after the scan timing signals of a frame. Multiple scan signal lines (GLs) control the timing of receiving data signals from multiple rows of sub-pixels (Pxij) under the control of the scan timing signals and the interval signals.

[0256] In an exemplary embodiment, during the interval signal time, integrated circuit 20 is configured to stop outputting data signals to data line DL and stop providing gate drive signals to multiple gate drive signal lines GOAL, and multiple scan gate drive circuits GOA stop outputting scan timing signals to multiple scan signal lines GL;

[0257] The scanning timing signal of a frame corresponds to the interval signal at least one position before and after the scanning signal of that frame. The scanning timing signal of a frame and the corresponding interval signal constitute a signal of a scanning cycle. The time of the interval signal is the time of at least one blank line. The time of a blank line is equal to the time of receiving the data signal of a sub-pixel Pxij. In a scanning cycle, the time of the interval signal can be the product of the time of a blank line and the number of blank lines in the interval signal.

[0258] In an exemplary embodiment, the time for each row of sub-pixels Pxij to receive data signals in one scan cycle can be: the time of one scan cycle / (the number of blank rows + the number of rows of sub-pixels Pxij), where the time of one scan cycle is 1s / refresh rate. For example, with a refresh rate of 60Hz, 466 rows of subpixels, 12 blank rows before the scan timing signal (i.e., the front Blank), and 2 blank rows after the scan timing signal (i.e., the back Blank), the time for each row of subpixels (Pxij) to receive data signals in one scan cycle can be: 1s / 60 / (466 rows of subpixels + 12 rows of front Blank + 2 rows of back Blank) ≈ 34.7 microseconds. With a fixed refresh rate, number of subpixel rows, and scan cycle, the writing time of a row of subpixel data signals can be adjusted by changing the number of blank rows. This allows for adjustment of the data signal writing frequency in one cycle, minimizing the impact of the charging frequency (typically 120kHz for wireless charging). This reduces the ripple effect caused by the wireless electromagnetic signal before the data signal is written to the subpixels in the display area.

[0259] During wireless charging of the display device, if the display area AA, multiplexing circuit area 11, and signal access area B11 are placed within the charger's range, and the flexible circuit board FPC is placed outside the charger's range, ripples appear on the display area. If the display area AA, multiplexing circuit area 11, and signal access area B11 are placed outside the charger's range, and the flexible circuit board FPC is placed within the charger's range, no obvious ripples are generated. Research and analysis revealed that the bright and dark rolling ripples are mainly related to the data signal and the data signal writing frequency (period): the charging electromagnetic field couples the data signal writing process, causing the voltage of the data signal to fluctuate when the data signal is written to the first node N1 point in Figures 6a to 6c (the fluctuation is different for each line), resulting in the ripple phenomenon. Therefore, the generation of ripples is mainly related to the signal writing of the data output line DT of multiplexing circuit area 11 and signal access area B11. When there is a difference in the data signal output from the data output line DT to the display area AA, the voltage of the first node N1 also changes accordingly, thereby affecting the current output by the third transistor T3, forming bright and dark patterns. The technical solution provided in this disclosure, on the one hand, shields the data output line DT in the multiplexing circuit area 11 and the signal access area B11 through the shielding structure PL, thereby avoiding the influence of electromagnetic signals in the charging electromagnetic field on the data output line DT, and reducing or even avoiding the generation of water ripples during the charging process; on the other hand, when the refresh frequency and the number of sub-pixel rows are fixed, the writing period of the data signal (i.e., the writing frequency of the data signal) can be adjusted by adjusting the number of front Blank rows and back Blank rows, thereby minimizing the coupling between the frequency of the data signal writing and the frequency of the electromagnetic signal in the wireless charging electric field, reducing or even avoiding the generation of water ripples in the display area AA during the wireless charging process.

[0260] This disclosure also provides a method for operating a display substrate. As shown in Figures 8a to 8f and 11a to 11f, the display substrate may include an integrated circuit 20, multiple scanning gate driving circuits GOA, multiple sub-pixels Pxij, multiple data lines DL, and multiple scanning signal lines GL. Each scanning gate driving circuit GOA is electrically connected to the integrated circuit 20 and at least one scanning signal line GL. The multiple sub-pixels Pxij form multiple rows and columns. The scanning signal line GL is electrically connected to one of the scanning gate driving circuits GOA and at least one row of sub-pixels Pxij. The data lines DL are electrically connected to the integrated circuit 20 and at least one column of sub-pixels Pxij, and provide data signals from the integrated circuit 20 to the corresponding sub-pixels Pxij under the control of the scanning signal lines GL. The extension directions of the multiple data lines DL intersect the extension directions of the multiple scanning signal lines GL. The operating method may include:

[0261] Integrated circuit 20 controls multiple scanning gate drive circuits GOA to provide scanning timing signals to multiple scanning signal lines GL, and outputs interval signals to multiple scanning gate drive circuits GOA at at least one position before and after the scanning timing signals of a frame; under the control of the scanning timing signals and the interval signals, the multiple scanning signal lines GL control the time when multiple rows of sub-pixels Pxij receive data signals.

[0262] In an exemplary embodiment, during the interval signal time, integrated circuit 20 stops outputting data signals to data line DL;

[0263] Under the control of the interval signal, multiple scan gate drive circuits GOA stop outputting scan timing signals to multiple scan signal lines GL.

[0264] In an exemplary embodiment, the scanning timing signal of a frame can correspond to an interval signal at least one position before and after the scanning signal of that frame, and the scanning timing signal of a frame and the corresponding interval signal can be a signal of a scanning cycle.

[0265] The interval signal time is the time of at least one blank line. The time of one blank line is equal to the time of receiving the data signal of one sub-pixel Pxij. In one scan cycle, the interval signal time is: the time of one blank line * the number of blank lines.

[0266] In an exemplary embodiment, the time for each row of sub-pixels Pxij to receive data signals in one scan cycle is: the time of one scan cycle / (the number of blank rows + the number of rows of sub-pixels Pxij), and the time of one scan cycle is 1s / refresh rate. For example, with a refresh rate of 60Hz, 466 rows of subpixels, 12 blank rows before the scan timing signal (i.e., the front Blank), and 2 blank rows after the scan timing signal (i.e., the back Blank), the time for each row of subpixels (Pxij) to receive data signals in one scan cycle can be: 1s / 60 / (466 rows of subpixels + 12 rows of front Blank + 2 rows of back Blank) ≈ 34.7 microseconds. With a fixed refresh rate, number of subpixel rows, and scan cycle, the writing time of a row of subpixel data signals can be adjusted by changing the number of blank rows. This allows for adjustment of the data signal writing frequency in one cycle, minimizing the impact of the charging frequency (typically 120kHz for wireless charging). This reduces the ripple effect caused by the wireless electromagnetic signal before the data signal is written to the subpixels in the display area.

[0267] Research and practice have shown that, with a fixed refresh rate (60Hz), number of subpixel rows (466 rows), and wireless charger frequency (120kHz), setting the front Blank to 32 rows and the rear Blank to 6 rows results in a data signal reception time of approximately 33.08 microseconds per row of subpixels (Pxij): 1s / 60 / (466 subpixel rows + 32 front Blank rows + 6 rear Blank rows). This can easily lead to water ripples during wireless charging. However, if the front Blank is set to 12 rows and the rear Blank to 2 rows, the data signal reception time per row of subpixels (Pxij) becomes approximately 34.7 microseconds (Pxij): 1s / 60 / (466 subpixel rows + 12 front Blank rows + 2 rear Blank rows). This makes the water ripples less noticeable or even eliminates them during wireless charging. Therefore, it can be seen that adjusting the number of blank rows changes the data signal writing cycle (i.e., the writing frequency), thereby reducing or even eliminating water ripples.

[0268] This disclosure also provides a display device, as shown in FIG14, which may include a display substrate.

[0269] The display substrate is the same as the display substrate provided in any of the foregoing embodiments. The implementation principle and effect are similar, and will not be described again here.

[0270] In one exemplary embodiment, the display device can be a Liquid Crystal Display (LCD), an Organic Light Emitting Diode (OLED), or a Light Emitting Diode (LED) display device. The display device can be any product or component with display functionality, such as a liquid crystal panel, electronic paper, an OLED panel, an active-matrix organic light emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator.

[0271] The display substrate and its working method and display device provided in the embodiments of this disclosure have a first shielding structure provided in the first frame area. The orthographic projection of at least a portion of the structure of at least one data output line on the substrate is located within the range of the orthographic projection of the first shielding structure on the substrate. In the direction perpendicular to the plane of the substrate, the shielding structure is located between the data output line and the substrate. The first shielding structure can shield electromagnetic interference during wireless charging and can reduce the technical problem of water ripples in the display area caused by electromagnetic interference during wireless charging.

[0272] The accompanying drawings of the embodiments disclosed herein only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in a general design.

[0273] Where there is no conflict, the features of the embodiments disclosed herein can be combined with each other to obtain new embodiments.

[0274] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of these embodiments and is not intended to limit them. Any person skilled in the art to which these embodiments pertain may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the patent protection scope of these embodiments shall still be determined by the scope defined in the appended claims.

[0275] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit the invention. Any person skilled in the art may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope of this disclosure; however, the patent protection scope of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, comprising: A substrate, the substrate including a display area and a border area surrounding the display area, the border area including a first border area located on one side of the display area; Multiple sub-pixels are located on one side of the substrate and in the display area; Multiple data lines are located in the display area and electrically connected to the multiple sub-pixels; Multiple data output lines are located in the first border area and are electrically connected to the multiple data lines; Multiple driver pads are located in the first frame area and on the side of the multiple data output lines away from the display area; each of the multiple data output lines is connected to a corresponding data line at the end closer to the display area and to a corresponding driver pad at the end away from the display area. A shielding structure, comprising a first shielding structure located in the first border region, wherein at least a portion of the structure of at least one of the plurality of data output lines is projected onto the substrate and the orthographic projection of the first shielding structure onto the substrate is within the range of the orthographic projection of the first shielding structure onto the substrate. In a direction perpendicular to the plane of the substrate, the shielding structure is located between the at least one data output line and the substrate. 2.The display substrate of claim 1, wherein, The first border area has a bend; In the bending region, the first shielding structure includes a plurality of shielding strips, which extend along a second direction and are spaced apart along a first direction. The plurality of digital output lines extend along the second direction and are spaced apart along the first direction. In a plane parallel to the substrate, the first direction intersects the second direction. The portion of the plurality of digital output lines located in the bending region has its orthographic projection on the substrate within the orthographic projection of the plurality of shielding strips on the substrate.

3. The display substrate according to claim 2, wherein, In the bending area, the plurality of data output lines correspond one-to-one with the plurality of shielding strips, and the orthographic projection of each of the plurality of data output lines on the substrate is located within the range of the orthographic projection of the corresponding shielding strip on the substrate.

4. The display substrate according to claim 2 or 3, wherein, In the same shielding strip, on the same side of the first center line in the first direction, the distance between the edge of the shielding strip and the edge of the nearest data output line is greater than or equal to 0.3 micrometers, and the first center line is the center line of the shielding strip extending along the second direction.

5. The display substrate according to claim 1, wherein, At least one of the plurality of sub-pixels includes a plurality of transistors, and in a direction perpendicular to the plane of the substrate, at least one of the transistors includes: an active layer located on one side of the substrate, a gate located on the side of the active layer away from the substrate, and a source and a drain located on the side of the gate away from the substrate. The shielding structure is disposed on the same layer as the gate of at least one of the transistors; or, in a direction perpendicular to the plane of the substrate, the shielding structure is located between the active layer of at least one of the transistors and the substrate.

6. The display substrate according to claim 5 further includes a shielding layer, wherein in a direction perpendicular to the plane of the substrate, in a structure where the shielding structure is located between the active layer of at least one transistor and the substrate, the shielding structure and the shielding layer are disposed in the same layer.

7. The display substrate according to claim 5, wherein, The direction from the display area to the first border area, the first border area includes a multiplexed circuit area, a bending area and a signal access area arranged sequentially; In the bending region, the data output line is located on the side of the source and drain that is away from the substrate.

8. The display substrate according to claim 7, wherein, The at least one sub-pixel further includes at least one capacitor, the plurality of transistors include at least one first type transistor, the active layer includes the active layer of the at least one first type transistor, the gate includes the gate of the at least one first type transistor, the first plate of the capacitor is disposed in the same layer as the gate of the first type transistor, and in a direction perpendicular to the plane of the substrate, a second plate of the capacitor is further disposed between the gate of the first type transistor and the source and the drain. In the structure in which the shielding structure and the gate of at least one of the transistors are disposed on the same layer, the shielding structure and the gate of the first type of transistor are disposed on the same layer, and in the signal access area, at least one of the data output lines and the second plate of the capacitor are disposed on the same layer. In the structure where the shielding structure is located between the active layer and the substrate, the shielding structure is located between the active layer of the first type of transistor and the substrate. In the signal access area, at least one of the data output lines is disposed on the same layer as at least one of the gate of the first type of transistor and the second plate of the capacitor.

9. The display substrate according to claim 8, wherein, In the structure in which the shielding structure and the gate of the first type of transistor are disposed on the same layer, in the multiplexing circuit area, at least one of the data output lines is disposed on the same layer as the second plate of the capacitor; In the structure where the shielding structure is located between the active layer of the first type of transistor and the substrate, in the multiplexing circuit region, at least one of the data output lines is disposed on the same layer as at least one of the gate of the first type of transistor and the second plate of the capacitor.

10. The display substrate according to claim 8, wherein, The plurality of transistors further includes at least one second type transistor, the active layer further includes the active layer of the at least one second type transistor, the gate further includes the gate of the at least one second type transistor, and in a direction perpendicular to the plane of the substrate, the active layer of the at least one second type transistor is located on the side of the second plate of the capacitor away from the substrate, and the gate of the second type transistor is located between the active layer of the second type transistor and the source and the drain. In the structure in which the shielding structure and the gate of the first type of transistor are disposed on the same layer, in the signal access area, at least one of the data output lines is disposed on the same layer as at least one of the second plate of the capacitor and the gate of the second type of transistor. In the structure where the shielding structure is located between the active layer of the first type of transistor and the substrate, in the signal access area, at least one of the data output lines is disposed on the same layer as at least one of the gate of the first type of transistor, the second plate of the capacitor, and the gate of the second type of transistor.

11. The display substrate according to claim 10, wherein, In the structure in which the shielding structure and the gate of the first type of transistor are disposed on the same layer, in the multiplexing circuit area, at least one of the data output lines is disposed on the same layer as at least one of the second plate of the capacitor and the gate of the second type of transistor. In the structure where the shielding structure is located between the active layer of the first type of transistor and the substrate, in the multiplexing circuit region, at least one of the data output lines is disposed on the same layer as at least one of the gate of the first type of transistor, the second plate of the capacitor, and the gate of the second type of transistor.

12. The display substrate according to claim 8 or 10 further includes a plurality of multiplexing circuits, the plurality of multiplexing circuits being located in the multiplexing circuit area, the plurality of data output lines corresponding one-to-one with the plurality of multiplexing circuits, each of the data output lines being connected to a corresponding data line through a corresponding multiplexing circuit, and each of the multiplexing circuits being configured to provide a signal provided by one data output line to at least two of the plurality of data lines in a time-division manner; In the structure where the shielding structure is located between the active layer of the first type of transistor and the substrate, the orthogonal projection of the plurality of multiplexing circuits on the substrate is within the range of the orthogonal projection of the first shielding structure on the substrate, and in the direction perpendicular to the plane of the substrate, the plurality of multiplexing circuits are located on the side of the shielding structure away from the substrate. In the structure in which the shielding structure and the gate of the first type of transistor are disposed on the same layer, the orthographic projection of the plurality of multiplexer circuits on the substrate does not overlap with the orthographic projection of the first shielding structure on the substrate, and the area corresponding to the first shielding structure and the plurality of multiplexer circuits is set as a hollow structure.

13. The display substrate according to claim 12, further comprising: At least two data selection lines: located in the first border area, in a direction perpendicular to the plane of the substrate, the at least two data selection lines are located on the side of the shielding structure away from the substrate; At least one of the plurality of multiplexing circuits is electrically connected to the at least two data selection lines, and each of the multiplexing circuits is configured to provide the signal of one data output line to the at least two data lines in a time-division manner under the control of the at least two data selection lines.

14. The display substrate according to any one of claims 1 to 3 and 5 to 11, further comprising a plurality of constant voltage signal lines, the shielding structure further comprising a second shielding structure, the border region further comprising a second border region, a third border region and a fourth border region, wherein in a first direction, the third border region and the fourth border region are located on both sides of the display region, and in a second direction, the first border region and the second border region are located on both sides of the display region; in a direction parallel to the plane of the substrate, the first direction intersects the second direction; The second shielding structure is located in the second frame region, the third frame region, and the fourth frame region. The multiple constant voltage signal lines are located in the third frame region and the fourth frame region. In a direction perpendicular to the plane of the substrate, at least one of the multiple constant voltage signal lines is located on the side of the second shielding structure away from the substrate.

15. The display substrate according to claim 14, wherein, The first shielding structure and the second shielding structure are interconnected to form a ring structure surrounding the display area.

16. The display substrate according to claim 15, wherein, The first shielding structure and the second shielding structure are an integral structure.

17. The display substrate according to claim 14, wherein, The second shielding structure is electrically connected to one of the multiple constant voltage signal lines. The orthographic projection of the multiple constant voltage signal lines on the substrate is within the range of the orthographic projection of the second shielding structure on the substrate. In the direction perpendicular to the plane of the substrate, the multiple constant voltage signal lines are located on the side of the second shielding structure away from the substrate. Alternatively, the plurality of constant voltage signal lines may include a first type of constant voltage signal line and at least one second type of constant voltage signal line, wherein the second shielding structure is multiplexed as the first type of constant voltage signal line, and in a direction perpendicular to the plane of the substrate, the at least one second type of constant voltage signal line is located on the side of the second shielding structure away from the substrate.

18. The display substrate according to claim 14, wherein, The frame area includes a peripheral area surrounding the display area and an edge area surrounding the peripheral area, wherein the various constant voltage signal lines and the shielding structure are located in the peripheral area; The display substrate further includes: A blocking structure is located in the edge region and partially surrounds the display area, and is disposed in the same layer as the shielding structure; A plurality of first grooves are located in the edge region and are sequentially spaced apart in a direction away from the peripheral region, and partially surround the peripheral region, wherein at least one of the first grooves penetrates at least a portion of the blocking structure.

19. The display substrate according to any one of claims 1 to 3, 5 to 11, wherein, The border area further includes a second border area, a third border area, and a fourth border area. In a first direction, the third border area and the fourth border area are located on both sides of the display area. In a second direction, the first border area and the second border area are located on both sides of the display area. The first direction and the second direction intersect. The display substrate further includes: Multiple gate control signal lines are located in the display area, including multiple scan signal lines; the multiple sub-pixels form multiple rows, and the scan signal lines are electrically connected to at least one row of sub-pixels; the data lines are configured to provide data signals to the corresponding sub-pixels under the control of the scan signal lines. Multiple scan gate driving circuits are located in the third border region and the fourth border region, and each scan gate driving circuit is electrically connected to at least one scan signal line. Multiple bonding pads are located in the first frame area. The multiple bonding pads include multiple driving pads and multiple gate driving pads. In the first direction, the multiple gate driving pads are located on both sides of the multiple driving pads. Multiple gate drive signal lines are located in the third frame region and the fourth frame region, and extend to the first frame region, and are electrically connected to the multiple gate drive pads and the multiple scan gate drive circuits. An integrated circuit, located in the first frame area, is bonded to and connected to the plurality of bonding pads. The integrated circuit is electrically connected to the plurality of data lines through the plurality of driving pads, and is electrically connected to the plurality of gate driving signal lines through the plurality of gate driving pads. The integrated circuit is configured to provide data signals to the plurality of data lines and to provide gate driving signals to the plurality of scan gate driving circuits through the plurality of gate driving signal lines. The plurality of scanning gate driving circuits are configured to provide scanning timing signals to the plurality of scanning signal lines under the control of the gate driving signal. The integrated circuit is configured to output an interval signal to the plurality of scanning gate driving circuits at at least one position before and after the scanning timing signal of a frame. The plurality of scanning signal lines control the timing of the data signal received by the plurality of sub-pixels under the control of the scanning timing signal and the interval signal.

20. The display substrate according to claim 19, wherein, During the time interval signal, the integrated circuit is configured to stop outputting data signals to the data lines and stop providing gate drive signals to the multiple gate drive signal lines, and the multiple scan gate drive circuits stop outputting scan timing signals to the multiple scan signal lines; The scanning timing signal of a frame corresponds to the interval signal at least one position before and after the scanning signal of that frame. The scanning timing signal of a frame and the corresponding interval signal constitute a signal of a scanning cycle. The time of the interval signal is the time of at least one blank line. The time of a blank line is equal to the time of receiving data signal of a row of sub-pixels. In one scanning cycle, the time of the interval signal is the product of the time of a blank line and the number of blank lines in the interval signal. In one scan cycle, the time for each row of subpixels to receive data signals is: the time of one scan cycle / (the number of blank rows + the number of subpixel rows), and the time of one scan cycle is 1s / refresh rate.

21. A display device comprising a display substrate as described in any one of claims 1 to 20.

22. A method of operating a display substrate, the display substrate comprising an integrated circuit, a plurality of scanning gate driving circuits, a plurality of sub-pixels, a plurality of data lines, and a plurality of scanning signal lines, each of the scanning gate driving circuits being electrically connected to the integrated circuit and at least one scanning signal line, the plurality of sub-pixels forming multiple rows and columns, the scanning signal lines being electrically connected to one of the scanning gate driving circuits and at least one row of sub-pixels; the data lines being electrically connected to the integrated circuit and at least one column of sub-pixels, and providing data signals from the integrated circuit to the corresponding sub-pixels under the control of the scanning signal lines, the extending directions of the plurality of data lines intersecting the extending directions of the plurality of scanning signal lines; the method comprising: The integrated circuit controls the plurality of scanning gate driving circuits to provide scanning timing signals to the plurality of scanning signal lines, and outputs an interval signal to the plurality of scanning gate driving circuits at at least one position before and after the scanning timing signal of a frame; the plurality of scanning signal lines, under the control of the scanning timing signal and the interval signal, control the timing at which the plurality of sub-pixels receive the data signal.

23. The method of operating the display substrate according to claim 22, wherein, During the time interval of the signal, the integrated circuit stops outputting data signals to the data line; Under the control of the interval signal, the plurality of scan gate drive circuits stop outputting scan timing signals to the plurality of scan signal lines.

24. The method of operating the display substrate according to claim 22 or 23, wherein, The scanning timing signal of a frame corresponds to the interval signal at least one position before and after the scanning signal of that frame, and the scanning timing signal of a frame and the corresponding interval signal constitute a scanning cycle signal. The interval signal time is the time of at least one blank line. The time of one blank line is equal to the time of receiving data signals for one row of sub-pixels. In one scan cycle, the interval signal time is: the time of one blank line * the number of blank lines.

25. The method of operating a display substrate according to claim 24, wherein, In one scan cycle, the time for each row of subpixels to receive data signals is: the time of one scan cycle / (the number of blank rows + the number of subpixel rows), and the time of one scan cycle is 1s / refresh rate.

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