Memory and preparation method therefor, and electronic device

Abstract

The embodiments of the present application relate to the technical field of electronic devices. Provided are a memory and a preparation method therefor, and an electronic device. The memory comprises a substrate, a plurality of chips, a plurality of trace layers, and a plurality of connecting portions, wherein the plurality of chips and the plurality of trace layers are alternately stacked in a first direction, each of the trace layers comprises a plurality of traces, and the traces in the plurality of trace layers are respectively electrically connected to the plurality of chips, the first direction being parallel to the substrate; and the plurality of connecting portions is arranged between the plurality of chips and the substrate, and the plurality of connecting portions are respectively arranged corresponding to the plurality of chips; and the plurality of traces extend to the side of the chips that is close to the substrate and are electrically connected to the connecting portions. The number of stacked chips in the structure is not limited, thereby effectively improving the storage capacity of the memory.

Description

Memory and its fabrication method, electronic device

[0001] This application claims priority to Chinese Patent Application No. 202411750846.7, filed on November 30, 2024, entitled "Memory and Method of Fabrication Thereof, Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of electronic device technology, and in particular to a memory, a method for manufacturing the same, and an electronic device. Background Technology

[0003] Memory, such as dynamic random access memory (DRAM), enables the storage and retrieval of data. With the continuous development of technology, complex scenarios such as big data and cloud computing require the processing and storage of massive amounts of data, demanding that memory have higher read / write speeds and larger capacities.

[0004] Vertically stacking multiple chips in a memory can increase memory storage capacity. However, the number of chips that can be stacked in current memory structures is limited, making it impossible to further expand storage capacity. Summary of the Invention

[0005] This application provides a memory and its fabrication method, as well as an electronic device. The purpose is to decouple the number of chips stacked in the memory from the external interconnection method of the chips through structural design. That is, to avoid the external interconnection structure of the chips limiting the number of chips stacked, thereby optimizing the electrical performance of the memory, for example, increasing its storage capacity.

[0006] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0007] In a first aspect, a memory is provided, which includes a substrate, multiple chips, multiple wiring layers, and multiple interconnects.

[0008] In this configuration, multiple chips are stacked on a substrate along a first direction, which is parallel to the substrate. Multiple chips and multiple wiring layers are alternately stacked along the first direction. Each wiring layer includes multiple traces, and each trace in the multiple wiring layers is electrically connected to one of the chips. Multiple connection portions are disposed between the chips and the substrate and are electrically connected to the substrate; each connection portion corresponds to one of the chips; and multiple traces extend to the side of the chip closest to the substrate and are electrically connected to the connection portions.

[0009] In the memory provided in this application embodiment, by stacking multiple chips along a first direction and distributing the connection portion along a third direction on the side of the chips, the stacking direction of the chips (i.e., the first direction) is decoupled from the external direction of the multiple chips (e.g., externally connected to the substrate along the third direction), thus avoiding the limitation of the number of stacked chips on the external connection of the memory, thereby enabling the chips to be stacked an unlimited number of times, which is beneficial to improving the storage capacity of the memory.

[0010] Meanwhile, by setting up multiple chips and multiple wiring layers alternately, short-distance connections between chips and wiring layers can be achieved, reducing the difficulty of memory fabrication. The wiring only needs to extend within the wiring layer to connect the chip to the interconnect (i.e., achieve external connection of the chip). The wiring does not need to penetrate the entire chip, further reducing the difficulty of memory fabrication. At the same time, it will not occupy the design space of the memory cell in the chip, which is conducive to improving the storage density of the memory cell and reducing the fabrication cost of the memory.

[0011] In summary, in the memory provided by the embodiments of this application, there is no interference between the location and arrangement of the external interconnection structure (leads and connectors) of the chip and the number of chips stacked. The number of chips stacked or not will not affect the smooth external interconnection of the chip, and the chips can even be stacked an unlimited number of times, effectively expanding the storage capacity of the memory.

[0012] In one possible implementation of the first aspect, multiple chips and multiple wiring layers are arranged alternately in sequence. Each chip includes a substrate and a device layer stacked along a first direction, and each chip is electrically connected to an adjacent wiring layer located on the side of the device layer.

[0013] This ensures that each chip can achieve a short-distance electrical connection with the wiring layer, reducing the difficulty of external chip interconnection (i.e., reducing the difficulty of memory fabrication), and allows the placement of various structures in the memory to be more regular, thereby making the stress at different locations more uniform and improving the structural stability of the memory.

[0014] In one possible implementation of the first aspect, multiple chips are divided into multiple stack groups, each stack group including at least two chips arranged adjacently; multiple stack groups and multiple wiring layers are arranged alternately in sequence, and at least two chips in each stack group are electrically connected to the same wiring layer.

[0015] That is, a wiring layer can be set for every two or more adjacent chips, and the external connection of the two or more chips can be achieved through a single wiring layer, thereby reducing the number of wiring layers in the memory, which is beneficial to reducing the size of the memory and realizing the miniaturization design of the memory.

[0016] In one possible implementation of the first aspect, a connecting post is also included, which extends through at least two chips in the stack group and is electrically connected to the wiring layer via the connecting post.

[0017] In one possible implementation of the first aspect, at least two chips in the stack are arranged in a stepped configuration, with the stepped surface formed by the at least two chips parallel to the wiring layer. The memory also includes leads, one end of which is electrically connected to the chip via the stepped surface of the chip, and the other end of which is electrically connected to the wiring layer.

[0018] In other words, a small number of stacked chips can be electrically connected using through-silicon vias (used to fill connector pillars) with small aspect ratios, or using short-distance, few-numbered leads, and finally connected to the wiring layer. The wiring layer then enables the external interconnection of this part of the chips. In this structure, by setting the wiring layer, the stacking direction of some chips and the external interconnection direction can also be decoupled without affecting the further stacking of chips. In addition, the small number of chips electrically connected by a single wiring layer are electrically connected through through-silicon vias (i.e., connector pillars) or leads. The small aspect ratio of the through-silicon vias, the short length of the leads, and the small number of leads can also reduce the difficulty and cost of memory fabrication.

[0019] In one possible implementation of the first aspect, two adjacent chips are arranged symmetrically, at least one pair of chips is provided with a wiring layer, and each pair of chips is electrically connected to the wiring layer.

[0020] That is, the external interconnect structure of two adjacent chip layers is set in the same routing layer, which can reduce the number of routing layers, which is beneficial to reduce the size of the memory and realize the miniaturization design of the memory.

[0021] In one possible implementation of the first aspect, the memory also includes a heat dissipation layer, which is stacked between two adjacent chips.

[0022] In the memory provided in this application embodiment, by decoupling the chip stacking direction from the chip external connection direction, the size of the chip in the stacking direction is no longer limited by the chip external connection structure (traces and connections). Thus, heat dissipation layers can be stacked as needed in the chip stacking direction. The heat dissipation layers sandwiched between the chips can effectively dissipate the heat generated during chip operation, avoiding overheating inside the chip. In particular, it can prevent heat concentration in the middle stacked part of multiple stacked chips, effectively improving the heat dissipation capacity of the memory, thereby optimizing the memory's operating performance and extending its service life.

[0023] In one possible implementation of the first aspect, the heat dissipation layer includes cooling channels for the passage of a cooling medium; the cooling channels are arranged in a zigzag pattern on a plane parallel to the chip.

[0024] By setting up cooling channels, heat can be dissipated not only through the heat dissipation capacity of the heat dissipation layer material itself, but also by the heat dissipation capacity of the cooling medium, effectively improving the heat dissipation effect of the memory.

[0025] In one possible implementation of the first aspect, the inlet and outlet of the cooling channel are both located on the side of the chip away from the interconnection portion, thereby facilitating the injection and outflow of the cooling medium without affecting the external interconnection of the memory. The heat dissipation layer also includes a main flow channel, which is disposed on the side of multiple chips away from the substrate. The cooling channels of the multi-layer heat dissipation layer are interconnected through the main flow channel, thereby facilitating the synchronous injection and output of the cooling medium in the cooling channels of the multi-layer heat dissipation layer, that is, achieving synchronous heat dissipation at different locations of the memory and avoiding the generation of local hot spots.

[0026] In one possible implementation of the first aspect, the memory further includes a heat dissipation section disposed on the side of the plurality of chips away from the substrate; the heat dissipation section includes a heat dissipation base plate and a plurality of heat dissipation fins, the heat dissipation base plate covering the side of the plurality of chips away from the substrate, and the plurality of heat dissipation fins disposed on the heat dissipation base plate and arranged at intervals along a first direction.

[0027] This heat sink can dissipate heat from the top of the memory chip, which can also improve the heat dissipation effect of the memory and extend its service life.

[0028] In one possible implementation of the first aspect, the memory further includes a first encapsulation layer disposed on the side of the plurality of chips near the substrate, a connector embedded in the first encapsulation layer, and the surface of the connector away from the chips exposed relative to the first encapsulation layer; at least a portion of the first encapsulation layer is disposed between the chips and the connector.

[0029] This first packaging layer can improve the structural stability of the stacked structure formed by the chip and wiring layers, preventing the chip or wiring layers from collapsing. The connector is embedded in the first packaging layer, thereby achieving electrical isolation of the connector and preventing unexpected electrical connections from occurring.

[0030] In one possible implementation of the first aspect, the substrate includes at least one of a circuit board, a packaging substrate for internally packaged electronic devices, a redistribution layer adapter, a silicon adapter, and a composite structure of a redistribution layer adapter and a silicon adapter.

[0031] In one possible implementation of the first aspect, the chip includes a substrate and a device layer. The memory also includes an adhesion layer disposed on the surface of the substrate away from the device layer, the adhesion layer being disposed between adjacent chips to achieve a fixed connection between the adjacent chips.

[0032] In the memory provided in this application embodiment, by decoupling the chip stacking direction from the chip external connection direction, the size of the chip in the stacking direction is no longer limited by the chip external connection structure (traces and connections). Thus, an adhesion layer can be stacked as needed in the chip stacking direction, thereby improving the connection strength between chips and optimizing the structural stability of the memory.

[0033] In one possible implementation of the first aspect, the routing layer includes at least one of a redistribution layer adapter board, a silicon adapter board, and a composite structure of a redistribution layer adapter board and a silicon adapter board.

[0034] In one possible implementation of the first aspect, the memory further includes a second encapsulation layer disposed on a side surface of the substrate near the plurality of chips and surrounding the portion of the plurality of chips near the substrate; the surface of the second encapsulation layer away from the substrate is closer to the substrate than the surface of the plurality of chips away from the substrate.

[0035] That is, the top surface of the second encapsulation layer is lower than the top surface of the chip, thereby exposing the upper part of the stacked chips and improving the heat dissipation of the memory.

[0036] Secondly, a stacked structure is provided, which includes multiple chips, multiple wiring layers and multiple interconnects.

[0037] In this configuration, multiple chips and multiple wiring layers are alternately stacked along a first direction. Each wiring layer includes multiple traces, and the traces in the multiple wiring layers are electrically connected to the multiple chips respectively. The first direction is perpendicular to the chips. Multiple connection portions are disposed on one side of the chips along a third direction, and multiple traces extend to the side of the chips where the connection portions are located and are electrically connected to the connection portions. The third direction is parallel to the chips.

[0038] The technical effects of the stacked structure in the second aspect can be seen in the technical effects of the memory design in the first aspect, and will not be repeated here.

[0039] Thirdly, an electronic device is provided, comprising a circuit board and a memory provided in any of the embodiments of the second aspect. The memory is disposed on and electrically connected to the circuit board.

[0040] The technical effects of the electronic devices in the third aspect can be seen in the technical effects of the memory design in the first aspect, and will not be repeated here.

[0041] Fourthly, a method for fabricating a memory is provided, the method comprising: sequentially stacking multiple sets of chipsets along a first direction; and disposing the multiple sets of stacked units on a substrate; the first direction being parallel to the substrate.

[0042] Each stacked unit includes a chip, a wiring layer, and a connector. Multiple chips and multiple wiring layers in multiple stacked units are alternately stacked along a first direction. Each wiring layer includes multiple traces, and the traces in the multiple wiring layers are electrically connected to multiple chips respectively. Multiple connectors in multiple stacked units are disposed between multiple chips and a substrate and are electrically connected to the substrate. The multiple connectors are respectively disposed on one side of multiple chips. Multiple traces extend to the side of the chip closest to the substrate and are electrically connected to the connectors.

[0043] The fabrication method provided in this application embodiment can realize the fabrication of memory through a simple, repeated stacking process. It has low fabrication difficulty and high fabrication efficiency, and can produce memory that can stack a large number of chips.

[0044] In a possible implementation of the fourth aspect, forming each chipset includes: providing a chip; forming a wiring layer; the chip and the wiring layer are stacked along a first direction; forming a connection portion; the connection portion is disposed on one side of the chip along a third direction, the third direction being perpendicular to the first direction.

[0045] In a possible implementation of the fourth aspect, each stacked cell includes at least two chips. Providing the chips involves stacking at least two chips along a first direction. The at least two chips are then electrically connected. This results in a memory with a wiring layer spaced at least two chips apart.

[0046] In a possible implementation of the fourth aspect, forming each stacked unit further includes: forming a first encapsulation layer; the first encapsulation layer is disposed on one side where the interconnects of the multiple chips are located, the interconnects are embedded in the first encapsulation layer, and the surface of the interconnects away from the chips is exposed relative to the first encapsulation layer; at least a portion of the first encapsulation layer is disposed between the chips and the interconnects. This improves the structural stability of the stacked structure formed by the multiple chips and multiple wiring layers through the first encapsulation layer.

[0047] In a possible implementation of the fourth aspect, the fabrication method further includes: forming a second encapsulation layer; the second encapsulation layer is disposed on one side surface of the substrate near the plurality of chips, and surrounding the portion of the plurality of chips near the substrate; the surface of the second encapsulation layer away from the substrate is closer to the substrate than the surface of the plurality of chips away from the substrate. This achieves encapsulation between the chips and the substrate. Attached Figure Description

[0048] Figure 1 is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0049] Figure 2 is a cross-sectional view of an electronic device provided in an embodiment of this application;

[0050] Figure 3 is a schematic diagram of a memory structure provided in an embodiment of this application;

[0051] Figure 4 is a schematic diagram of another structure of the memory provided in an embodiment of this application;

[0052] Figure 5 is a schematic diagram of another structure of the memory provided in an embodiment of this application;

[0053] Figure 6 is a three-dimensional view of a stacked structure provided in an embodiment of this application;

[0054] Figure 7 is a cross-sectional view along section line A-A' in Figure 6;

[0055] Figure 8 is a cross-sectional view along section line B-B' in Figure 6;

[0056] Figure 9 is a cross-sectional view along section line C-C' in Figure 6;

[0057] Figure 10 is a top view of a memory provided in an embodiment of this application;

[0058] Figure 11 is a cross-sectional view of a memory provided in an embodiment of this application;

[0059] Figure 12 is another cross-sectional view of the memory provided in an embodiment of this application;

[0060] Figure 13 is another cross-sectional view of the stacked structure provided in an embodiment of this application;

[0061] Figure 14 is another cross-sectional view of the stacked structure provided in an embodiment of this application;

[0062] Figure 15 is another cross-sectional view of the stacked structure provided in an embodiment of this application;

[0063] Figure 16 is a schematic diagram of a heat sink provided in an embodiment of this application;

[0064] Figure 17 is a schematic diagram of another structure of the heat sink provided in an embodiment of this application;

[0065] Figure 18 is another cross-sectional view of the memory provided in an embodiment of this application;

[0066] Figure 19 is a flowchart of the fabrication process of the memory provided in an embodiment of this application;

[0067] Figures 20 to 30 are cross-sectional views corresponding to the fabrication steps of the memory. Detailed Implementation

[0068] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0069] In the description of this application, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0070] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, a particular feature, structure, material, or characteristic may be included in any suitable manner in any one or more embodiments or examples.

[0071] Hereinafter, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0072] Connection / linking: can refer to a mechanical or physical connection relationship, that is, A and B are connected or linked. It can mean that there are fastened components (such as screws, bolts, rivets, etc.) between A and B, or that A and B are in contact with each other and are difficult to separate. A and B can be fixed, detachable, or integrated; they can be directly connected or indirectly connected through an intermediate medium.

[0073] Coupling can be understood as direct coupling and / or indirect coupling. "Coupled connection" can be understood as a direct coupling connection and / or indirect coupling connection. Direct coupling, also known as "electrical connection," refers to components being in direct or indirect physical contact and electrically conductive. For example, in circuit construction, different components are connected through physical lines that can transmit electrical signals, such as copper foil or wires on a printed circuit board (PCB). "Indirect coupling" can be understood as two conductors conducting electricity through a gap or without contact. In one embodiment, indirect coupling can also be called capacitive coupling, for example, using the coupling between two conductive parts to form an equivalent capacitance to achieve signal transmission.

[0074] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0075] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0076] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0077] This document describes exemplary embodiments with reference to sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Therefore, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0078] Furthermore, the scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the emergence of new scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0079] This application provides an electronic device, which can be, for example, a mobile phone, tablet computer, personal digital assistant (PDA), television, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, rechargeable small household appliances (e.g., soymilk makers, robot vacuum cleaners), drones, radar, aerospace equipment, in-vehicle equipment, vehicles, and other different types of user equipment or terminal devices; the electronic device can also be a network device such as a base station. This application does not impose any special limitations on the specific form of the electronic device.

[0080] Figure 1 is a schematic diagram of the structure of an electronic device 1000 provided by an embodiment of this application. Figure 2 is a cross-sectional view of the electronic device 1000 provided by an embodiment of this application.

[0081] As shown in Figures 1 and 2, the electronic device 1000 may include a circuit board 200.

[0082] For example, circuit board 200 may be a printed circuit board (PCB), a flexible circuit board, or a rigid-flex circuit board.

[0083] For example, as shown in FIG1, the electronic device 1000 may further include an integrated circuit 100, which may be disposed on the circuit board 200.

[0084] For example, as shown in FIG1, the integrated circuit 100 may include logic circuit 101, analog circuit 102, storage circuit 103, and input / output circuit 104, etc.

[0085] It should be understood that the integrated circuit 100 includes, but is not limited to, logic circuit 101, analog circuit 102, storage circuit 103 and input / output circuit 104. For example, in addition to the four types of circuits mentioned above, the integrated circuit 100 may also include other types or functions of circuits, or discrete devices.

[0086] In addition, integrated circuit 100 may include one or more of logic circuit 101, analog circuit 102, storage circuit 103 and input / output circuit 104.

[0087] Based on this, the number of logic circuits 101, analog circuits 102, storage circuits 103, and input / output circuits 104 included in integrated circuit 100 can be set as needed. Integrated circuit 100 may include one or more logic circuits 101. Integrated circuit 100 may also include one or more analog circuits 102. Integrated circuit 100 may also include one or more storage circuits 103. Integrated circuit 100 may also include one or more input / output circuits 104.

[0088] As shown in Figures 1 and 2, the electronic device 1000 may also include a memory 300, which is electrically connected to the circuit board 200.

[0089] For example, referring to FIG1, the memory 300 can be integrated in the aforementioned integrated circuit 100. For example, the memory 300 can be integrated in both the logic circuit 101 and the storage circuit 103. For example, the memory 300 can be packaged with logic chips and / or storage chips. The embodiments of this application do not limit the location of the memory 300 or the type of packaged chip.

[0090] For example, referring to FIG2, the memory 300 may be disposed on the circuit board 200.

[0091] It is understood that the structure of the electronic device 1000 shown in Figures 1 and 2 does not constitute a specific limitation on the electronic device 1000. The electronic device 1000 may include more or fewer components than those shown in Figures 1 and 2, or may combine some of the components shown in Figures 1 and 2, or may have a different component arrangement than those shown in Figures 1 and 2. For example, referring to Figure 2, the electronic device 1000 may also include a power module 201 disposed on a circuit board 200.

[0092] This application embodiment also provides a memory 300. Figures 3, 4 and 5 are some structural diagrams of the memory 300 provided in this application embodiment, wherein each figure of Figures 3 to 5 includes a top view and a corresponding cross-sectional view of the memory 300.

[0093] As shown in Figures 2 to 5, the memory 300 may include a substrate 400 and a stacked structure 500. The stacked structure 500 is disposed on the substrate 400 and electrically connected to the substrate 400.

[0094] The substrate 400 can be used to provide support for the packaging of electrical devices such as the stacked structure 500, or to realize the electrical connection of various electrical devices disposed on the substrate 400 through multiple traces in the substrate 400, or to transfer some electrical devices disposed on the substrate 400 out, for example, to the circuit board 200 (see Figure 2).

[0095] For example, the substrate 400 may include a first adapter plate 401 and / or a second adapter plate 402 stacked together. Referring to Figures 2, 4 and 5, the stacking structure 500 may be disposed on the first adapter plate 401 and connected to the second adapter plate 402 stacked with the first adapter plate 401. Alternatively, referring to Figure 2, the stacking structure 500 may also be directly disposed on the second adapter plate 402.

[0096] For example, the first adapter board 401 and / or the second adapter board 402 can be an adapter board formed by 2.5D packaging technology based on silicon process (i.e., a Si interposer), or an adapter board with a redistribution layer (RDL) (i.e., a FOR RDL interposer), or a composite structure combining the two, which can play the role of adapter and bridging.

[0097] For example, chips, inductors or other electronic devices may also be embedded in the first adapter board 401 and / or the second adapter board 402.

[0098] For example, referring to FIG3, the substrate 400 may also include a second chip 403, and the stacked structure 500 may be disposed on the second chip 403.

[0099] For example, the second chip 403 can be a chip with a different function than the chips in the stacked structure 500. For instance, the second chip 403 can be a logic chip that can implement functions such as "AND", "OR", and "NOT".

[0100] For example, referring to Figure 4, the stacked structure 500 and the second chip 403 can both be disposed on the first adapter board 401, or referring to Figure 5, the stacked structure 500 and the second chip 403 can both be disposed on the second adapter board 402, and are connected to the first adapter board 401 through the second adapter board 402.

[0101] Alternatively, the substrate 400 may also be a circuit board 200, that is, the stacked structure 500 may be directly disposed on the circuit board 200, and the circuit board 200 serves as the substrate 400 in the memory 300.

[0102] That is, there can be many types of substrate 400 used for the stacking structure 500. It can be a transition board with a transition function, or a chip, or other substrates with a load-bearing function. This application does not limit its structure and type. Any substrate 400 that can be used for the stacking structure 500 and is electrically connected is within the protection scope of the embodiments of this application.

[0103] For example, referring to Figures 2 to 5, a plurality of stacked structures 500 may be loaded on the substrate 400, with different stacked structures 500 spaced apart.

[0104] For example, the substrate 400 can be soldered to the stacked structure 500. Referring to FIG2, the memory 300 can also include solder balls 202 (e.g., solder balls), and the stacked structure 500 can be soldered to the substrate 400 by solder balls 202.

[0105] For example, the memory 300 may also include electrical devices such as a DC-DC converter (DC / DC), a voltage regulator module (VRM), and an integrated voltage regulator (IVR), which may be disposed on the substrate 400 and electrically connected to the substrate 400.

[0106] It is understood that the memory 300 may include more or fewer structures than those shown in Figures 2 to 5, and the embodiments of this application do not limit this.

[0107] Figure 6 is a partial perspective view of the stacked structure 500 provided in the embodiment of this application. Figure 7 is a cross-sectional view along section line A-A' in Figure 6. Figure 8 is a cross-sectional view along section line B-B' in Figure 6. Figure 9 is a cross-sectional view along section line C-C' in Figure 6. Figures 10, 11 and 12 are structural diagrams of the stacked structure 500 packaged on the substrate 400. Among them, Figure 10 is a top view of the memory 300, Figure 11 is a cross-sectional view of the memory 300 (the cross-section of the plane containing XZ), and Figure 12 is another cross-sectional view of the memory 300 (the cross-section of the plane containing YZ).

[0108] Referring to Figure 6, the stacked structure 500 includes multiple chips 1, multiple wiring layers 2, and multiple connection portions 3. That is, the memory 300 includes a substrate 400, multiple chips 1, multiple wiring layers 2, and multiple connection portions 3.

[0109] For example, chip 1 can be a memory chip. For instance, each chip 1 may include multiple transistors, multiple capacitors, or other memory units capable of data storage.

[0110] Alternatively, the chip 1 can be other types of chips, such as logic chips, as exemplified by the present application, and this embodiment does not limit this.

[0111] The more chips 1 are set in the stacked structure 500, the larger the storage capacity of the memory 300 will be.

[0112] For example, the number of chips 1 stacked in the stacked structure 500 provided in this application embodiment can be greater than or equal to 20.

[0113] Referring to Figure 6, the multiple chips 1 are stacked sequentially along the first direction X.

[0114] Wherein, the first direction X is parallel to the substrate 400. For example, the first direction X is the thickness direction of the chip 1, or the first direction X is perpendicular to the chip 1. That is, the stacking direction of the plurality of chips 1 is parallel to the surface of the substrate 400.

[0115] For example, referring to Figures 6, 7, 8, 10 and 11, chip 1 may include a substrate 11 and a device layer 12, which are stacked in a first direction X.

[0116] In this embodiment, device layer 12 can be used to form devices such as memory cells (e.g., transistors, capacitors, etc.), and substrate 11 serves as a support for device layer 12. The material of substrate 11 may include at least one of single-crystal silicon (Si), single-crystal germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art. Alternatively, it may be made of non-conductive materials such as glass, plastic, or sapphire wafers. This application does not limit the material of substrate 11; any substrate with a support function capable of supporting the fabrication of components such as device layer 12 is within the protection scope of this application.

[0117] Exemplary, in other embodiments, after the device layer 12 is fabricated, the substrate 11 may also be thinned or even removed, and this application embodiment does not limit this.

[0118] For example, the aforementioned wiring layer 2 can be an adapter board, such as a redistribution layer (RDL) adapter board, or an adapter board formed by 2.5D packaging technology based on silicon process (i.e., Si interposer), or a composite structure combining the two. Any wiring layer 2 structure that can realize the electrical interconnection of devices in chip 1 is within the protection scope of the embodiments of this application.

[0119] Referring to Figures 6, 7, 8, 9, 10, 11 and 12, each routing layer 2 may include multiple routing lines L.

[0120] The trace L is used to realize the external connection of chip 1. For example, it can transmit data signals and power signals to chip 1. For example, it can be used to transmit control signals such as gate signals, source signals and / or drain signals to the memory cells in device layer 12, so as to realize the writing and reading of data stored in device layer 12.

[0121] It is understood that the number of traces L in each trace layer 2 can depend on the number of memory cells in chip 1. Furthermore, the traces L shown in Figures 6 to 12 are exemplary and do not limit their number, size, or placement. There can be various routing methods for traces L, and this application embodiment does not impose any limitations on them.

[0122] For example, the trace L is used to transmit electrical signals, and its material is a conductive material, such as a metal or alloy material, such as copper, tungsten, aluminum or silver.

[0123] Referring to Figures 6, 7, 8, 9, 10, 11 and 12, the multilayer wiring layer 2 is electrically connected to multiple chips 1 respectively. For example, referring to Figure 6, the multilayer wiring layer 2 can be electrically connected to multiple chips 1 in a one-to-one correspondence, that is, one chip 1 is electrically connected to multiple traces L in one layer of wiring layer 2, or for example, one layer of wiring layer 2 can be electrically connected to multiple chips 1, or for example, one chip 1 can be electrically connected to multiple wiring layers 2.

[0124] Referring to Figures 6 and 11, the multilayer wiring layer 2 and multiple chips 1 are alternately stacked in the first direction X, so that each chip 1 can be provided with a wiring layer 2 at a relatively close position, which facilitates the electrical connection between each chip 1 and the wiring layer 2 that is close to it, that is, to realize the short-distance connection between chip 1 and wiring layer 2, thereby reducing the difficulty of external connection of chip 1.

[0125] For example, referring to Figures 6 and 11, at least one pair of chips 1 and wiring layers 2 are arranged adjacent to each other. The wiring L in the wiring layer 2 does not need to penetrate too many film layers to be electrically connected to the chip 1. Therefore, it is not necessary to form a via with a large depth-to-width ratio in the stacked structure 500, which effectively reduces the difficulty of external interconnection of chip 1 and can ensure the electrical connection effect between chip 1 and wiring layer 2.

[0126] For example, referring to Figures 6 to 12, the routing layer 2 may include a dielectric layer 7.

[0127] Referring to Figures 6 to 12, the dielectric layer 7 is at least disposed between the chip 1 and the trace L. Through holes are provided only at the locations where the chip 1 needs to be externally connected to achieve electrical connection between the chip 1 and the trace L. For example, one end of the trace L passes through the dielectric layer 7 and is electrically connected to the chip 1, while the other end (which may pass through the dielectric layer 7 and / or the first packaging layer 61) is electrically connected to the connection part 3.

[0128] For example, referring to FIG8, the dielectric layer 7 also includes a portion disposed between two adjacent traces L in the same trace layer 2 to avoid interference between signals transmitted by different traces L. In addition, the dielectric layer 7 also includes a portion covering the trace L (e.g., the portion covering the right side of the trace L in FIG8) to protect the trace L from unexpected electrical connections and from external damage.

[0129] For example, the routing layer 2 may include multiple layers of routing L (the figure shows only one layer of routing L as an example). The multiple layers of routing L are stacked along the first direction X. Each layer of routing L has multiple routing Ls. The dielectric layer 7 also includes a portion disposed between two adjacent layers of routing L, which also avoids interference between signals transmitted by different routing Ls.

[0130] For example, the material of the dielectric layer 7 is an insulating material, such as a resin material, which may include polyimide (PI) or silicon oxide.

[0131] Referring to Figures 6, 8 and 11, a plurality of connecting portions 3 are disposed between a plurality of chips 1 and a substrate 400, that is, the connecting portions 3 are disposed on the side of the chip 1 near the substrate 400 along the third direction Z.

[0132] Among them, the third direction Z is parallel to chip 1, for example, the third direction Z is perpendicular to the first direction X, that is, the third direction Z is perpendicular to the substrate 400.

[0133] For example, taking the orientation in Figure 6 as an example, the connecting part 3 is located below the chip 1. That is, the connecting part 3 is not located on the side of the chip 1 with a larger area (such as the left and right sides in Figure 6), but on the side of the chip 1.

[0134] Referring to Figures 11 and 12, the connecting part 3 is used for electrical connection with the substrate 400.

[0135] For example, the connecting part 3 can be soldered to the substrate 400, or it can be connected by a pin, or it can be connected by a snap-fit.

[0136] For example, when the connecting part 3 is welded to the substrate 400, ball grid array (BGA) technology can be used, or welding technologies such as C4 welding technology or micro-bump technology can also be used.

[0137] For example, when the connecting part 3 is welded to the substrate 400, it can be a welding type such as eutectic welding, hybrid welding, or metal fusion welding.

[0138] For example, the connection portion 3 may include at least one pad, or may include at least one pin, or may include at least one plug-in (e.g., probe), or may include at least one snap-fit, or may be any other structure that facilitates electrical contact between the stacked structure 500 and the substrate 400 and enables external connection.

[0139] For example, the material of the connection part 3 is a conductive material, such as the same material as the trace L.

[0140] Referring to Figure 6, the plurality of connecting parts 3 are respectively provided with the plurality of chips 1.

[0141] For example, the plurality of connecting portions 3 and the plurality of chips 1 are respectively arranged facing each other. Here, "facing each other" means that the two have at least a partially facing area. For example, the orthographic projection of the chip 1 on the substrate 400 at least partially overlaps with the orthographic projection of the connecting portion 3 on the substrate 400.

[0142] For example, taking the orientation in Figure 6 as a reference, the multiple connecting parts 3 can be arranged one-to-one under the multiple chips 1, that is, one connecting part 3 is arranged under each chip 1, or for example, multiple connecting parts 3 can be arranged under one chip 1, or for example, one connecting part 3 can be arranged under multiple chips 1.

[0143] For example, a plurality of connection portions 3 can be provided along the second direction Y at intervals. Each of the plurality of connection portions 3 is used to electrically connect to a chip 1, thereby realizing the external connection of multiple signals of the same or different types in the chip 1.

[0144] The second direction Y is parallel to chip 1 and intersects the first direction X and the third direction Z. For example, the first direction X, the second direction Y and the third direction Z are perpendicular to each other.

[0145] For example, if the first direction X is the thickness direction of chip 1, then the second direction Y can be the length (or width) direction of chip 1, and the third direction Z can be the width (or length) direction of chip 1.

[0146] Referring to Figures 6, 8 and 11, the trace L extends to the side of the chip 1 near the substrate 400 (i.e. the side where the connection part 3 is located, for example, below the chip 1 in Figure 6) and is electrically connected to the connection part 3.

[0147] For example, the trace L in the trace layer 2 closest to the target chip 1 can be electrically connected to the connection part 3 closest to the target chip 1, thereby reducing the difficulty of connecting the trace L to the connection part 3.

[0148] That is, one end of the trace L is electrically connected to the chip 1, and the other end is electrically connected to the connection part 3. Since the connection part 3 is disposed on the side of the chip 1 along the third direction Z, the trace L does not need to extend a long distance in the thickness direction of the chip 1 (i.e., the first direction X) to connect to the connection part 3. This avoids the trace L occupying too much space in the stacking direction of the chip 1 (i.e., the first direction X), which helps to save space for the stacking of the chip 1 and increase the storage capacity. In addition, referring to Figure 6, the trace L only needs to be extended in the trace layer 2 to achieve the connection with the connection part 3. It does not need to penetrate the chip or a lot of film layers (i.e., it does not need to make a through hole with a large depth-to-width ratio). This can also reduce the fabrication difficulty of the memory 300 and ensure the electrical connection effect between the trace L and the connection part 3.

[0149] To increase memory capacity, it is necessary to stack as many chips as possible. However, all of these stacked chips need to be interconnected. In some other embodiments, the ends of the chips are arranged in a stepped shape to facilitate the interconnection of all chips using the exposed stepped surface of each chip. For example, electrical connections between adjacent chips are achieved by setting leads on the stepped surfaces of two adjacent chips, and the leads are then used to transfer the connections layer by layer to the substrate on which the chips are stacked, thus achieving the interconnection of multiple chips. Alternatively, for example, the stepped surface of each chip is directly electrically connected to the substrate via leads to achieve the interconnection of the chips. Or, in some other embodiments, through-silicon vias (TSVs) that penetrate the multiple chips are used to achieve the electrical connection between each chip and the substrate.

[0150] However, due to limitations imposed by leads or through-silicon vias (TSVs), such as excessively long leads leading to signal transmission errors or loss, or excessively large aspect ratios in TSVs causing difficulties in fabrication and poor connectivity, the number of chip stacking layers cannot be increased indefinitely. For example, the number of chip stacking layers is generally limited to no more than 20 layers, typically 16 layers, which restricts further expansion of memory storage capacity.

[0151] Furthermore, as the number of chip stacking layers increases, the number of leads becomes excessive, requiring more design space. In addition, through-silicon vias also occupy a large amount of chip design space, which leads to the memory sacrificing a significant amount of memory cell design area, resulting in increased costs.

[0152] In the memory 300 provided in this application embodiment, by stacking multiple chips 1 along the first direction X and distributing the connection portion 3 along the third direction Z on the side of the chips 1, the stacking direction of the chips 1 (i.e., the first direction X) is decoupled from the external direction of the memory 300 (electrically connected to the substrate 400 in the third direction Z). This avoids limiting the external connection of the memory 300 by the number of stacked chips 1, thereby enabling unlimited stacking of chips 1 and improving the storage capacity of the memory 300.

[0153] Meanwhile, by setting multiple chips 1 and multiple wiring layers 2 alternately stacked, short-distance connections between chips 1 and wiring layers 2 can be achieved, reducing the fabrication difficulty of memory 300. Furthermore, the wiring L only needs to extend in the wiring layer 2 to connect chips 1 and the connection part 3 (i.e., to achieve external connection of chips 1). The wiring L does not need to penetrate the entire chip 1, further reducing the fabrication difficulty of memory 300. At the same time, it will not occupy the design space of the memory cell in chip 1, which is conducive to improving the storage density of the memory cell and reducing the fabrication cost of memory 300.

[0154] In summary, in the memory 300 provided in this application embodiment, there is no interference between the setting position and setting method of the external connection structure (lead L and connection part 3) of chip 1 and the number of stacked chips 1. The number of stacked chips 1 will not affect the smooth external connection of chip 1, and even the chips 1 can be stacked an unlimited number of times, effectively realizing the further expansion of the storage capacity of memory 300.

[0155] In some embodiments, referring to Figures 6 and 11, multiple chips 1 and multiple wiring layers 2 are arranged alternately in sequence. That is, a wiring layer 2 is provided every other chip 1, so that multiple chips 1 and multiple wiring layers 2 are electrically connected in a one-to-one correspondence. That is, each chip 1 can be electrically connected to the wiring layer 2 arranged next to it, thereby ensuring that each chip 1 can achieve a short-distance electrical connection with the wiring layer 2, reducing the difficulty of external interconnection of chip 1 (that is, reducing the fabrication difficulty of memory 300), and making the arrangement positions of various structures in memory 300 more regular, so that the stress at different positions is more uniform, thereby improving the structural stability of memory 300.

[0156] For example, referring to Figures 6 and 11, each chip 1 can be electrically connected to the wiring layer 2 located adjacent to it and on the side of the device layer 12, so that the wiring L can be electrically connected to the memory cell in the device layer 12 without penetrating the substrate 11, reducing the fabrication difficulty of the memory 300.

[0157] Figures 13, 14 and 15 are all cross-sectional views of the memory 300 provided in the embodiments of this application.

[0158] In some other embodiments, the multiple chips 1 and the multilayer wiring layers 2 can be alternated according to other rules.

[0159] For example, referring to Figures 13 and 14, multiple chips 1 are divided into multiple stacking groups H. Each stacking group H includes at least two adjacent chips 1. Multiple stacking groups H and multiple wiring layers 2 are arranged alternately in sequence. At least two chips 1 in each stacking group H are electrically connected to the same wiring layer 2.

[0160] That is, a wiring layer 2 can be set every two or more chips 1, and the external connection of the two or more chips 1 can be realized through a wiring layer 2, thereby reducing the number of wiring layers 2 in the memory 300, which is beneficial to reduce the size of the memory 300 and realize the miniaturization design of the memory 300.

[0161] For example, referring to FIG13, the memory 300 further includes a connection post L1 that passes through the chip 1 in the stack group H, and the chip 1 in the stack group H is electrically connected to the wiring layer 2 through the connection post L1.

[0162] For example, referring to Figure 13, a wiring layer 2 is provided for every two adjacent chips 1, and the two adjacent chips 1 are electrically connected to the wiring layer 2. For example, the two adjacent chips 1 are electrically connected through a connecting post L1 (filled in a through-silicon via) with a small depth-to-width ratio, and finally connected to the wiring layer 2.

[0163] Alternatively, as exemplarily shown in FIG14, at least two chips 1 in the stack group H are arranged in a stepped configuration, and the stepped surface formed by the at least two chips 1 is parallel to the wiring layer 2. The memory 300 also includes a lead L2, one end of which is electrically connected to the chip 1 through the stepped surface of the chip 1, and the other end is electrically connected to the wiring layer 2.

[0164] For example, referring to Figure 14, a wiring layer 2 is provided for every two adjacent chips 1. The sides of the two adjacent chips 1 (for example, the upper side, lower side, front side and / or rear side in Figure 14, with the upper side as an example in Figure 14) are arranged in a stepped shape. The stepped surfaces of the two chips 1 are electrically connected to the wiring layer 2 through the lead L2.

[0165] For example, referring to FIG14, the stepped surfaces between adjacent chips 1 can be electrically connected by lead L2 and finally connected to the wiring layer 2. Alternatively, the stepped surfaces of chip 1 can be directly connected to the wiring layer 2 by lead L2.

[0166] That is, a small number of stacked chips 1 can be electrically connected by through-silicon vias (for filling the connecting pillars L1) with small aspect ratios, or by short and few leads L2, and finally connected to the wiring layer 2. The wiring layer 2 then enables the external connection of this part of the chips 1. In this structure, by setting the wiring layer 2, the stacking direction and external connection direction of some chips 1 can also be decoupled, without affecting the further stacking of chips 1. In addition, the small number of chips 1 electrically connected by a single wiring layer 2 are electrically connected by through-silicon vias (i.e., connecting pillars L1) or leads L2. The small aspect ratio of the through-silicon vias, the short length of the leads, and the small number of leads can also reduce the fabrication difficulty and cost of the memory 300.

[0167] Alternatively, as exemplarily provided in FIG15, a wiring layer 2 is provided between every two adjacent chips 1, and the two adjacent chips 1 are arranged axially symmetrically (for example, the two device layers 12 of the two chips 1 are arranged facing each other, or the two substrates 11 are arranged facing each other). At least one pair of symmetrically arranged chips 1 is provided with a wiring layer 2. For example, as exemplarily provided in FIG15, a wiring layer 2 is provided between two chips 1 whose device layers 12 are facing each other, and both of the symmetrically arranged chips 1 are electrically connected to the wiring layer 2.

[0168] The two symmetrically arranged chips 1 are electrically connected to different connection parts 3 through different traces L in the same trace layer 2. To avoid obstruction, only one of the two symmetrically arranged chips 1 is shown in Figure 15 connected to the connection part 3 through the trace L. It can be understood that the other chip 1 will also be connected to the connection part 3 through the trace L.

[0169] That is, the external interconnection structure of two adjacent chip layers 1 is set in the same routing layer 2, which can reduce the number of routing layers 2, which is beneficial to reduce the size of memory 300 and realize the miniaturization design of memory 300.

[0170] In some embodiments, referring to Figures 6, 8, 9, and 11, the memory 300 further includes a first encapsulation layer 61.

[0171] Referring to Figures 6, 8, 9, and 11, the first encapsulation layer 61 is disposed on the side where the connection portion 3 of the chip 1 is located (i.e., disposed between the chip 1 and the substrate 400, for example, below the chip 1 in Figure 2). The connection portion 3 is embedded in the first encapsulation layer 61, and the surface of the connection portion 3 away from the chip 1 is exposed relative to the first encapsulation layer 61. At least a portion of the first encapsulation layer 61 is disposed between the chip 1 and the connection portion 3.

[0172] The first encapsulation layer 61 is used to encapsulate the connection portion 3 with the chip 1 and the wiring layer 2. For example, referring to Figures 8 and 11, the end of each wiring layer 2 near the connection portion 3 is surrounded by the first encapsulation layer 61, which can improve the structural stability of the stacked structure 500 formed by stacking the chip 1 and the wiring layer 2 and prevent the chip 1 or the wiring layer 2 from collapsing.

[0173] The connection part 3 is embedded in the first encapsulation layer 61, thereby achieving electrical isolation of the connection part 3 and preventing unexpected electrical connections from occurring. For example, the portion of the first encapsulation layer 61 disposed between the connection part 3 and the chip 1 can achieve electrical insulation between the connection part 3 and the chip 1, so that the memory cells in the chip 1 can only be electrically connected to the connection part 3 at a preset position through the trace L, which facilitates independent data access to multiple memory cells in the chip 1.

[0174] For example, the material of the first encapsulation layer 61 can be the same as the material of the second encapsulation layer 62. For example, both materials can be molding materials, such as resin, silicon oxide, etc.

[0175] For example, in other embodiments, the first encapsulation layer 61 may not be provided, or the size of the first encapsulation layer 61 in the third direction Z may be the same as the size of the connecting part 3 in the third direction Z, and the upper and lower surfaces of the two may be flush. The above embodiments of this application are only examples of some possible implementations of the first encapsulation layer 61, and do not limit its setting position and size.

[0176] In some embodiments, referring to Figures 6 to 12, the memory 300 further includes a heat dissipation layer 4.

[0177] Referring to Figures 6 to 12, the heat dissipation layer 4 is stacked between two adjacent chips 1. For example, the heat dissipation layer 4 can be disposed between the wiring layer 2 and the substrate 11 of the chip 1.

[0178] For example, the material of the heat dissipation layer 4 can be a high thermal conductivity material, such as metal, metal-graphene composite, diamond, and other organic or inorganic materials with excellent heat dissipation capabilities.

[0179] For example, referring to Figures 6 and 11, a heat dissipation layer 4 can be provided between every two chips 1, or for example, a heat dissipation layer 4 can be provided every two or more chips 1, or for example, multiple heat dissipation layers 4 can be provided between two chips 1 at intervals.

[0180] In the memory 300 provided in this application embodiment, by decoupling the stacking direction of the chip 1 from the external connection direction of the chip 1, the size of the chip 1 in the stacking direction is no longer limited by the external connection structure (trace L and connection part 3) of the chip 1. Thus, the heat dissipation layer 4 can be stacked as needed in the stacking direction of the chip 1. The heat dissipation layer 4 sandwiched between the chips 1 can effectively dissipate the heat generated during the operation of the chip 1, avoid overheating inside the chip 1, and especially avoid the heat concentration of the chip 1 located in the middle stacking part among the multiple stacked chips 1, effectively improving the heat dissipation capacity of the memory 300, thereby optimizing the operation of the memory 300 and extending its service life.

[0181] Figure 16 is a structural diagram of the heat dissipation layer 4 provided in an embodiment of this application, Figure 17 is another structural diagram of the heat dissipation layer 4 provided in an embodiment of this application, and Figure 18 is another cross-sectional view of the memory 300 provided in an embodiment of this application.

[0182] For example, referring to FIG16, the heat dissipation layer 4 can be configured in a layered (or plate-like) manner.

[0183] Alternatively, as exemplarily shown in FIG17, the heat dissipation layer 4 includes a cooling channel 41 for the passage of a cooling medium.

[0184] For example, the cooling channel 41 can be a microchannel.

[0185] For example, the cooling medium that can be transported in the cooling channel 41 can be a gas, a liquid, or a gas-liquid mixture. For instance, the cooling medium can be a single-medium liquid, a two-phase flow medium, or a phase change medium.

[0186] By setting up cooling channels 41, heat can be dissipated not only through the heat dissipation capacity of the heat dissipation layer 4 material itself, but also by the heat dissipation capacity of the cooling medium, effectively improving the heat dissipation effect of the memory 300.

[0187] For example, referring to FIG17, the cooling channel 41 is arranged in a zigzag shape (e.g., wavy, meandering, etc.) on a plane parallel to the chip 1, so as to extend the path of the cooling channel 41 and improve the heat dissipation capacity of the heat dissipation layer 4.

[0188] For example, the cooling channels 41 are evenly distributed on a plane parallel to the chip 1 so as to achieve a uniform heat dissipation effect at different locations of the chip 1.

[0189] For example, the inlet 41A and outlet 41B of the cooling channel 41 (see FIG17) are both located on the side of the chip 1 away from the connection portion 3, so that the injection and outflow of the cooling medium can be facilitated without affecting the external connection of the memory 300.

[0190] For example, referring to FIG18, the heat dissipation layer 4 also includes a main flow channel 42, which is disposed on the side of the multiple chips 1 away from the multiple connection parts 3. The cooling channels 41 of the multi-layer heat dissipation layer 4 are interconnected through the main flow channel 42, thereby facilitating the synchronous injection and output of the cooling medium in the cooling channels 41 of the multi-layer heat dissipation layer 4, that is, realizing synchronous heat dissipation at different locations of the memory 300 and avoiding the generation of local hot spots.

[0191] For example, referring to FIG18, the memory 300 further includes a heat sink 43 disposed on the side of the plurality of chips 1 away from the plurality of connection portions 3.

[0192] The heat sink 43 can dissipate heat from the top of the memory 300 (taking the position in Figure 18 as an example), which can also improve the heat dissipation effect of the memory 300 and extend its service life.

[0193] For example, referring to FIG18, the heat dissipation part 43 includes a heat dissipation base plate 43A and a plurality of heat dissipation fins 43B. The heat dissipation base plate 43A covers the side surface of the plurality of chips 1 away from the plurality of connection parts 3. The plurality of heat dissipation fins 43B are disposed on the heat dissipation base plate 43A and are arranged at intervals along the first direction X.

[0194] This structural design can increase the total contact area between the heat dissipation part 43 and the air, thereby improving the heat exchange capacity between the heat dissipation part 43 and the air, that is, improving the heat dissipation effect of the heat dissipation part 43.

[0195] For example, referring to FIG18, the heat dissipation part 43 can contact the heat dissipation layer 4. The combination of the two can further improve the heat dissipation effect on the chip 1.

[0196] For example, referring to Figure 18, the aforementioned main flow channel 42 can be disposed in the heat dissipation base plate 43A, thereby achieving an effective superposition of the heat dissipation effects of the heat dissipation layer 4 and the heat dissipation part 43.

[0197] Furthermore, in some embodiments, referring to FIG18, in the memory 300 provided in the embodiments of this application, the chip 1 is stacked along the first direction X, but externally connected in the third direction Z (thickness direction of the substrate 400), so that the size of the stacked structure 500 in the thickness direction of the substrate 400 (i.e., approximately the width of the chip 1) is larger. For example, the size is larger than the thickness of the memory structure when the chips are stacked in the third direction Z in the conventional way, thereby increasing the utilization of the design space in the third direction Z (i.e., the vertical direction), which is beneficial to the development of the three-dimensional structure of the memory 300.

[0198] In some embodiments, referring to Figures 3, 4, 5, 11, 12 and 18, the memory 300 may further include a second encapsulation layer 62, and the stacked structure 500 may be encapsulated together with the substrate 400 through the second encapsulation layer 62.

[0199] Referring to Figures 3, 4, 5, 11, 12 and 18, the second encapsulation layer 62 is disposed on the side surface of the substrate 400 near the stacked structure 500 and is disposed around at least a portion of the stacked structure 500, thereby achieving encapsulation between the stacked structure 500 and the substrate 400 and improving the strength of the connection between the stacked structure 500 and the substrate 400.

[0200] It is understood that the second encapsulation layer 62 is encapsulated at least on the solder balls 202 between the substrate 400 and the stack structure 500, thereby preventing interconnection between adjacent solder balls 202.

[0201] For example, referring to Figures 3, 4 and 5, the size of the second encapsulation layer 62 in the third direction Z is less than or equal to the size of the stacked structure 500 in the third direction Z.

[0202] For example, the surface of the second encapsulation layer 62 that is away from the substrate 400 is closer to the substrate 400 than the surfaces of the plurality of chips 1 that are away from the substrate 400.

[0203] That is, the height of the second encapsulation layer 62 can be less than the height of the stacked structure 500, thereby reducing the area of ​​the stacked structure 500 covered by the second encapsulation layer 62 while realizing the encapsulation between the substrate 400 and the stacked structure 500, thereby improving the heat dissipation capability of the stacked structure 500.

[0204] In some embodiments, referring to Figures 6 to 12, the memory 300 further includes an adhesive layer 8.

[0205] The adhesive layer 8 has excellent adhesion. Referring to Figures 6 to 12, the adhesive layer 8 is disposed on the surface of the substrate 11 away from the device layer 12. For example, the adhesive layer 8 is disposed between the heat dissipation layer 4 and the substrate 11, thereby achieving a fixed connection between the stacked chips 1 without affecting the smooth external interconnection of the chip 1.

[0206] Similarly, in the memory 300 provided in this application embodiment, by decoupling the stacking direction of chip 1 from the external connection direction of chip 1, the size of chip 1 in the stacking direction is no longer limited by the external connection structure (trace L and connection part 3) of chip 1. Thus, the adhesion layer 8 can be stacked as needed in the stacking direction of chip 1, thereby improving the connection strength between chips 1 and optimizing the structural stability of memory 300.

[0207] For example, the adhesion layer 8 can also be disposed between any two adjacent film layers that need to be fixedly connected, thereby further improving the structural stability of the memory 300.

[0208] This application embodiment also provides a method for fabricating a memory 300. Figure 19 is a flowchart of the fabrication process of the memory 300 provided in this application embodiment, and Figures 20 to 27 are cross-sectional views corresponding to each step in the fabrication method.

[0209] As shown in Figure 19, the preparation method includes:

[0210] W1: Multiple stacking units M are stacked sequentially along the first direction X.

[0211] W2: Multiple stacked units M are disposed on the substrate 400.

[0212] Referring to Figure 27, each stacked unit M includes a chip 1, a wiring layer 2, and a connection part 3.

[0213] Referring to Figure 30, each stacking unit M includes a chip 1, a wiring layer 2, and a connection portion 3. Multiple chips 1 and multiple wiring layers 2 in multiple stacking units M are alternately stacked along a first direction X. The wiring layer 2 includes multiple traces L, and the traces L in the multiple wiring layers 2 are electrically connected to multiple chips 1 respectively. Multiple connection portions 3 in multiple stacking units N are disposed between multiple chips 1 and a substrate 400, and are electrically connected to the substrate 400. The multiple connection portions 3 are respectively disposed on one side of multiple chips 1. The multiple traces L extend to the side of the chip 1 closest to the substrate 400 and are electrically connected to the connection portions 3.

[0214] In some embodiments, step W1, the step of forming each stacked unit M includes subsequent steps S1 to S3. It is understood that the order of steps S1 to S3 can be arbitrarily combined. For example, referring to Figure 19, the order of steps S1 to S3 can be step S2 from step S1 to step S3, or it can be step S2 to step S3 to step S1. The embodiments of this application are only illustrative of the order of steps S1 to S3 and are not intended to limit it.

[0215] The fabrication method provided in this application embodiment can fabricate the memory 300 through a simple, repeated stacking process. It has low fabrication difficulty and high fabrication efficiency, and can fabricate a memory 300 that can stack a large number of chips 1.

[0216] The preparation method will be illustrated with an example below.

[0217] S1: Refer to Figure 20, chip 1 is provided.

[0218] For example, a wafer can be fabricated into a chip 1 through front-end processes such as photolithography, electroplating and chemical mechanical polishing. Referring to FIG20, the chip 1 may include a substrate 11 and a device layer 12. The fabrication step also includes thinning the substrate 11 of the chip 1, for example, thinning the wafer from more than 700 μm to less than 200 μm, to avoid the final memory 300 being too large.

[0219] For example, when each stacked unit M includes at least two chips 1, step S1 may include: stacking the at least two chips 1 along a first direction X, and then electrically connecting the at least two chips 1 to prepare a stacked structure 500 as shown in FIG13 or FIG14.

[0220] For example, the at least two chips 1 can be electrically connected by a connecting post L1 (see Figure 13) or by a lead L2 (see Figure 14).

[0221] For example, referring to Figure 21, the preparation method further includes:

[0222] M1: Form a first carrier plate P1 and form a release layer Q1 on the first carrier plate P1 so that the first carrier plate P1 can be removed through the release layer Q1 in the future.

[0223] The first carrier plate P1 is used to provide support for the fabrication of the memory 300.

[0224] S3: Referring to Figure 22, a connecting part 3 is formed.

[0225] Referring to Figure 22, the connecting part 3 is disposed on one side of the chip 1 along the third direction Z.

[0226] For example, before forming the connecting portion 3, it may also include:

[0227] S4: Referring to Figure 22, the first encapsulation layer 61 is formed.

[0228] Referring to Figure 22, the first encapsulation layer 61 is disposed on the side where the connection portion 3 of the plurality of chips 1 is located. The connection portion 3 is embedded in the first encapsulation layer 61, and the surface of the connection portion 3 away from the chip 1 is exposed relative to the first encapsulation layer 61. At least a portion of the first encapsulation layer 61 is disposed between the chip 1 and the connection portion 3.

[0229] Referring to Figure 22, chip 1 can be placed on the first substrate P1 first, and then the first encapsulation layer 61 can be used to wrap chip 1 to protect it. Then, the surface of chip 1 can be exposed by grinding, etching and other methods to facilitate the subsequent preparation of wiring layer 2.

[0230] For example, referring to FIG22, when forming the connecting part 3, a hole can be drilled in the first encapsulation layer 61 first, and then 3 can be filled in the hole, so that the connecting part 3 can be embedded in the first encapsulation layer 61.

[0231] For example, referring to FIG22, the top of the connection portion 3 is also exposed relative to the first encapsulation layer 61 to facilitate subsequent electrical connection with the wiring layer 2.

[0232] S2: Refer to Figure 23 to form wiring layer 2.

[0233] Referring to Figure 23, chip 1 and wiring layer 2 are stacked along the first direction X. The wiring layer 2 includes multiple wirings L, which are electrically connected to chip 1. The multiple wirings L extend to the side where the connection part 3 of chip 1 is located and are electrically connected to the connection part 3.

[0234] For example, referring to FIG23, this step also includes forming a dielectric layer 7 to protect the trace L.

[0235] For example, referring to FIG23, a portion of the dielectric layer 7 for being disposed between the chip 1 and the wiring layer 2 can be formed first, and then a portion covering the top surface of the wiring L can be formed. For example, the materials of the portion of the dielectric layer 7 disposed between adjacent wiring L, the portion disposed between the chip 1 and the wiring L, and the portion of the dielectric layer 7 located on the top surface of the wiring L can be the same or different. For example, the portion of the dielectric layer 7 located on the top surface of the wiring L can be a passivation layer, and the other portions can be insulating layers made of ordinary materials such as PI.

[0236] For example, referring to Figure 24, the preparation method further includes:

[0237] M2: Forms heat dissipation layer 4.

[0238] M3: Forms an adhesion layer 8.

[0239] A set of stacked units M can be formed through the aforementioned steps S1 → S3 → S2.

[0240] Alternatively, in other embodiments, referring to FIG25, a set of stacked units M can be formed through steps S2 → S3 → S1.

[0241] For example, referring to FIG25, a wiring layer 2 can be formed on the first substrate P1 first (i.e., step S2), then a connection portion 3 can be formed on the wiring layer 2 (i.e., step S3), then a chip 1 can be formed on the wiring layer 2 (i.e., step S1), and then the first packaging layer 61, the heat dissipation layer 4 and the adhesion layer 8 can be formed (i.e., steps S4, M2 and M3), and the stacking unit M can be obtained in the same way.

[0242] The stacked unit M can also be prepared through other preparation sequences. The embodiments in this application are merely exemplary and are not intended to limit the scope of the invention.

[0243] For example, referring to Figure 26, the formed stacking unit M can be flipped onto the second carrier plate P2, and then the first carrier plate P1 can be removed (or without flipping, subsequent stacking units M can be fabricated directly on the stacking unit M). Then, the steps S1→S3→S2 or S2→S3→S1 can be repeated to form multiple sets of stacking units M, resulting in a stacked structure 500.

[0244] For example, the first carrier plate P1 can be removed by means of laser debonding, thermal debonding, mechanical debonding, etc.

[0245] For example, referring to FIG27, the preparation method further includes applying a protective film to the stacked structure 500 (i.e., a buffer layer P3, which can act as a stress buffer when cutting the stacked structure 500), then removing the second carrier board P2, and removing excess parts of the stacked structure 500, such as cutting the first encapsulation layer 61, so as to expose the surface of the connection portion 3 away from the chip 1, thereby facilitating the electrical connection of the stacked structure 500 to external devices through the connection portion 3.

[0246] Figures 28 to 30 show some cross-sectional views corresponding to step W2.

[0247] For example, step W2 may include:

[0248] W21: Refer to Figure 28 to form substrate 400.

[0249] W22: Referring to Figure 29, multiple sets of stacked units M are arranged (e.g., soldered) on the substrate 400.

[0250] By way of example, referring then to FIG30, the preparation method may further include:

[0251] W3: Forms the second encapsulation layer 62.

[0252] Referring to Figure 30, a second encapsulation layer 62 is disposed on one surface of the substrate 400 near the plurality of chips 1, and surrounds the portion of the plurality of chips 1 near the substrate 400. The second encapsulation layer 62 can be used to achieve encapsulation between the substrate 400 and the stacked structure 500.

[0253] For example, referring to FIG30, the surface of the second encapsulation layer 62 away from the substrate 400 can be made closer to the substrate 400 relative to the surfaces of the plurality of chips 1 away from the substrate 400 through processes such as cutting and grinding.

[0254] For example, referring to Figure 28, techniques such as photolithography, electroplating, and chemical mechanical polishing can be used to form a logic chip (i.e., this embodiment uses substrate 400 as an example to illustrate the logic chip). Then, solder balls are fabricated on the surface of the logic chip (in wafer form). The logic chip wafer is then attached to a third temporary carrier. A buffer layer is placed between the carrier and the wafer to prevent the solder balls from directly contacting the carrier and causing damage. Then, the back solder balls are fabricated: the wafer surface is thinned to expose the TSV, and then a back conductive layer and a second solder ball layer are fabricated. The second solder ball forms an electrical connection with the first solder ball layer through the back conductive layer, TSV, and front conductive layer, thereby achieving conductivity between the upper and lower surfaces of substrate 400. Afterward, the wafer is attached to a fourth temporary carrier. A buffer layer is placed between the carrier and the wafer to prevent the solder balls from directly contacting the carrier and causing damage. Then, the third temporary carrier is removed to expose the solder balls on substrate 400 for electrical connection with the stacked structure 500.

[0255] For example, referring to FIG29, the aforementioned stacked structure 500 is mounted on a logic chip. The logic chip can be in the form of a wafer or a single chip structure. The solder balls of the logic chip are bonded to the connection portion 3 of the stacked structure 500 to form an electrical connection.

[0256] For example, referring to Figure 30, a second encapsulation layer 62 is formed: the bottom and gaps of the memory chip are filled with materials such as resin, PI, and silicon oxide, which not only prevents the solder balls on the bottom from being oxidized or corroded, but also enhances the mechanical strength of the structure. The fourth temporary carrier board is then removed to obtain the memory 300.

[0257] It is understood that Figures 28 to 30 are merely illustrative and do not constitute a limitation on the packaging process of the stacked structure 500. Other packaging steps or packaging sequences for implementing the stacked structure 500 are also within the protection scope of the embodiments of this application.

[0258] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed herein should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A memory, characterized in that, include: substrate; Multiple chips are stacked on the substrate along a first direction; The first direction is parallel to the substrate; A multi-layer wiring layer is provided, wherein the plurality of chips and the multi-layer wiring layer are alternately stacked along the first direction, and the wiring layer includes a plurality of traces, wherein the traces in the multi-layer wiring layer are electrically connected to the plurality of chips respectively; A plurality of connection portions corresponding to the plurality of chips are disposed between the plurality of chips and the substrate and are electrically connected to the substrate; the plurality of traces extend to the side of the chip near the substrate and are electrically connected to the connection portions.

2. The memory according to claim 1, characterized in that, The plurality of chips and the multi-layer wiring layers are arranged alternately in sequence; The chip includes a substrate and a device layer stacked along the first direction, and each chip is electrically connected to an adjacent wiring layer located on the side of the device layer.

3. The memory according to claim 1, characterized in that, The multiple chips are divided into multiple stacking groups, and each stacking group includes at least two chips arranged adjacent to each other; the multiple stacking groups and the multiple wiring layers are arranged alternately in sequence, and the at least two chips in each stacking group are electrically connected to the same wiring layer.

4. The memory according to claim 3, characterized in that, Also includes: A connecting post extends through at least two chips in the stack, and the at least two chips are electrically connected to the wiring layer via the connecting post.

5. The memory according to claim 3, characterized in that, The at least two chips in the stack are arranged in a stepped manner, and the stepped surface formed by the at least two chips is parallel to the wiring layer; The memory also includes: The lead wire has one end electrically connected to the chip through the stepped surface of the chip, and the other end electrically connected to the wiring layer.

6. The memory according to claim 1, characterized in that, Two adjacent chips are arranged symmetrically, and at least one pair of chips is provided with a wiring layer, and both pairs of chips are electrically connected to the wiring layer.

7. The memory according to any one of claims 1 to 6, characterized in that, Also includes: A heat dissipation layer is stacked between two adjacent chips.

8. The memory according to claim 7, characterized in that, The heat dissipation layer includes cooling channels for the passage of cooling medium; the cooling channels are arranged in a zigzag shape on a plane parallel to the chip.

9. The memory according to claim 8, characterized in that, The inlet and outlet of the cooling channel are both located on the side of the chip away from the connection portion; The heat dissipation layer also includes a main flow channel, which is disposed on the side of the plurality of chips away from the substrate, and the cooling channels of the multi-layer heat dissipation layer are interconnected through the main flow channel.

10. The memory according to any one of claims 1 to 9, characterized in that, Also includes: A heat dissipation section is disposed on the side of the plurality of chips away from the substrate; the heat dissipation section includes a heat dissipation base plate and a plurality of heat dissipation fins, the heat dissipation base plate covers the side of the plurality of chips away from the substrate, and the plurality of heat dissipation fins are disposed on the heat dissipation base plate and are spaced apart along the first direction.

11. The memory according to any one of claims 1 to 10, characterized in that, Also includes: A first encapsulation layer is disposed on the side of the plurality of chips near the substrate, the connector is embedded in the first encapsulation layer, and the surface of the connector away from the chip is exposed relative to the first encapsulation layer; at least a portion of the first encapsulation layer is disposed between the chip and the connector.

12. The memory according to any one of claims 1 to 11, characterized in that, Also includes: The second encapsulation layer is disposed on the side surface of the substrate near the plurality of chips, and is disposed around the portion of the plurality of chips near the substrate; The surface of the second encapsulation layer that is away from the substrate is closer to the substrate than the surfaces of the plurality of chips that are away from the substrate.

13. The memory according to any one of claims 1 to 12, characterized in that, The chip includes a substrate and a device layer; The memory also includes: An adhesion layer is disposed on the surface of the substrate away from the device layer.

14. The memory according to any one of claims 1 to 13, characterized in that, The routing layer includes at least one of a redistribution layer adapter board, a silicon adapter board, and a composite structure of a redistribution layer adapter board and a silicon adapter board.

15. The memory according to any one of claims 1 to 14, characterized in that, The substrate includes at least one of the following: a circuit board, a packaging substrate for internally packaged electronic devices, a redistribution layer adapter board, a silicon adapter board, and a composite structure of a redistribution layer adapter board and a silicon adapter board.

16. An electronic device, characterized in that, include: The memory as described in any one of claims 1 to 15; A circuit board, wherein the memory is disposed on the circuit board and electrically connected to the circuit board.

17. A method for fabricating a memory, characterized in that, include: Multiple stacking units are sequentially stacked along the first direction; The multiple sets of stacked units are disposed on the substrate; The first direction is parallel to the substrate; Each stacked unit includes a chip, a wiring layer, and a connector. Multiple chips and multiple wiring layers in the stacked units are alternately stacked along the first direction. Each wiring layer includes multiple traces, and the traces in the multiple wiring layers are electrically connected to the multiple chips. Multiple connectors in the stacked units are disposed between the multiple chips and the substrate, and are electrically connected to the substrate. Each connector is correspondingly disposed on one side of the multiple chips. The multiple traces extend to the side of the chip closest to the substrate and are electrically connected to the connectors.

18. The preparation method according to claim 17, characterized in that, Each stack of cells consists of: Provide the chip; The wiring layer is formed; the wiring layer and the chip are stacked together along the first direction; The connection portion is formed; the connection portion is disposed on one side of the chip along a third direction; the third direction is perpendicular to the first direction.

19. The preparation method according to claim 18, characterized in that, Each stacked unit includes at least two chips; The chip being provided includes: The at least two chips are stacked along the first direction; The at least two chips are electrically connected.

20. The preparation method according to claim 18 or 19, characterized in that, The formation of each stacked unit also includes: A first encapsulation layer is formed; the first encapsulation layer is disposed on one side of the plurality of chips where the connection portion is located, the connection portion is embedded in the first encapsulation layer, and the surface of the connection portion away from the chip is exposed relative to the first encapsulation layer; at least a portion of the first encapsulation layer is disposed between the chip and the connection portion.

21. The preparation method according to any one of claims 17 to 20, characterized in that, Also includes: Form a second encapsulation layer; The second encapsulation layer is disposed on the side surface of the substrate near the plurality of chips and is disposed around the portion of the plurality of chips near the substrate; the surface of the second encapsulation layer away from the substrate is closer to the substrate than the surface of the plurality of chips away from the substrate.

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