Driving circuit and driving method therefor, display panel and display apparatus

Abstract

A driving circuit and a driving method therefor, a display panel and a display apparatus. The driving circuit is used for driving a pixel circuit. The pixel circuit comprises a driving transistor, and a gate reset transistor, a data writing transistor and a threshold capturing transistor that are electrically connected to the driving transistor. The driving circuit comprises a plurality of cascaded shift register units, wherein each shift register unit comprises a first-type signal output module and a second-type signal output module; an output end of the first-type signal output module is electrically connected to a gate electrode of the gate reset transistor and / or a gate electrode of the threshold capturing transistor; and an output end of the second-type signal output module is electrically connected to a gate electrode of the data writing transistor. The structure of the driving circuit can reduce the number of peripheral driving circuits required by a pixel circuit, thus being conducive to realizing a narrow bezel of a display panel and to reducing power consumption.

Description

A driving circuit and its driving method, a display panel, and a display device.

[0001] This invention claims priority to Chinese Patent Application No. 202411748803.5, filed on November 29, 2024, entitled "A driving circuit and driving method thereof, display panel, display device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, and in particular to a driving circuit and driving method thereof, a display panel, and a display device. Background Technology

[0003] In the field of display technology, display panels typically incorporate multiple driving circuits to power the pixel circuits within the display area. However, existing display panels often have a large number of driving circuits, which hinders both the achievement of narrow bezels and the reduction of power consumption. Therefore, a solution is urgently needed. Summary of the Invention

[0004] In view of this, embodiments of this application provide a driving circuit and driving method thereof, a display panel, and a display device to solve the above problems.

[0005] In a first aspect, embodiments of this application provide a driving circuit for driving a pixel circuit. The pixel circuit includes a driving transistor and a gate reset transistor, a data write transistor, and a threshold grabbing transistor electrically connected to the driving transistor. The driving circuit includes multiple cascaded shift register units. Each shift register unit includes a first type of signal output module and a second type of signal output module. The output terminal of the first type of signal output module is electrically connected to the gate of the gate reset transistor and / or the threshold grabbing transistor, and the output terminal of the second type of signal output module is electrically connected to the gate of the data write transistor.

[0006] Secondly, based on the same inventive concept, embodiments of this application provide a driving method for a driving circuit, used to drive the driving circuit as provided in the first aspect. The working process of the driving circuit includes a first type of enable signal output stage and a second type of enable signal output stage. The driving method includes:

[0007] During the first type of enable signal output stage, the first type of signal output module outputs an enable signal;

[0008] During the second type of enable signal output stage, the second type of signal output module outputs an enable signal;

[0009] Wherein, the first type of enable signal output stage and the second type of enable signal output stage do not overlap, or the second type of enable signal output stage is located within the first type of enable signal output stage.

[0010] Thirdly, based on the same inventive concept, embodiments of this application provide a display panel including the driving circuit as provided in the first aspect.

[0011] Fourthly, based on the same inventive concept, embodiments of this application provide a display device, including a display panel as provided in the third aspect.

[0012] In this embodiment, by configuring at least one of the gate reset transistor and threshold grabbing transistor in the pixel circuit to be electrically connected to the same driving circuit as the data write transistor, the number of peripheral driving circuits required for the pixel circuit can be reduced. When the driving circuit and pixel circuit are applied in a display panel, it is beneficial to reduce the area occupied by the peripheral driving circuits, thereby facilitating the achievement of a narrow bezel in the display panel.

[0013] Furthermore, reducing the number of peripheral driving circuits required for pixel circuits can also reduce the number of clock signals required for peripheral driving circuits, which helps to reduce the power consumption of the display panel. Attached Figure Description

[0014] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 is a plan view of a display panel provided in an embodiment of this application;

[0016] Figure 2 is a partial schematic diagram of a shift register unit provided in an embodiment of this application;

[0017] Figure 3 is a schematic diagram of a pixel circuit provided in an embodiment of this application;

[0018] Figure 4 is a plan view of another display panel provided in an embodiment of this application;

[0019] Figure 5 is a partial schematic diagram of another shift register unit provided in an embodiment of this application;

[0020] Figure 6 is a schematic diagram of a shift register unit provided in an embodiment of this application;

[0021] Figure 7 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0022] Figure 8 is a schematic diagram of one type of shift register unit shown in Figure 7;

[0023] Figure 9 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0024] Figure 10 is a schematic diagram of one type of shift register unit shown in Figure 9;

[0025] Figure 11 is a schematic diagram of a cascaded shift register unit provided in an embodiment of this application;

[0026] Figure 12 is another schematic diagram of the shift register unit shown in Figure 9;

[0027] Figure 13 is another schematic diagram of the shift register unit shown in Figure 9;

[0028] Figure 14 is another schematic diagram of the shift register unit shown in Figure 9;

[0029] Figure 15 is another schematic diagram of the shift register unit shown in Figure 9;

[0030] Figure 16 is another schematic diagram of the shift register unit shown in Figure 9;

[0031] Figure 17 is a timing diagram of a shift register unit provided in an embodiment of this application;

[0032] Figure 18 is a connection diagram of a shift register unit provided in an embodiment of this application;

[0033] Figure 19 is a timing diagram of a clock signal line provided in an embodiment of this application;

[0034] Figure 20 is a connection diagram of another shift register unit provided in an embodiment of this application;

[0035] Figure 21 is a connection diagram of another shift register unit provided in an embodiment of this application;

[0036] Figure 22 is a timing diagram of another clock signal line provided in an embodiment of this application;

[0037] Figure 23 is a connection diagram of another shift register unit provided in an embodiment of this application;

[0038] Figure 24 is a timing diagram of the output signals of each type I signal output module in the multiple shift register units shown in Figure 23;

[0039] Figure 25 is another timing diagram of the output signals of each type I signal output module in the multiple shift register units shown in Figure 23;

[0040] Figure 26 is a schematic diagram of another shift register circuit provided in an embodiment of this application;

[0041] Figure 27 is a schematic diagram of another shift register circuit provided in an embodiment of this application;

[0042] Figure 28 is a flowchart of a driving method provided in an embodiment of this application;

[0043] Figure 29 is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0044] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0045] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0046] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0047] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0048] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this application can be combined with each other without contradiction.

[0049] Figure 1 is a plan view of a display panel provided in an embodiment of this application, and Figure 2 is a partial view of a shift register unit provided in an embodiment of this application.

[0050] This application provides a driving circuit 01 for driving a pixel circuit 02. As shown in FIG1, in one possible application scenario, both the driving circuit 01 and the pixel circuit 02 are disposed in a display panel 100. The display panel 100 includes a display area AA and a border area NA located around the display area AA. The border area NA may surround the display area AA.

[0051] The driving circuit 01 is located in the bezel area NA, and the pixel circuit 02 is located in the display area AA. The pixel circuit 02 is electrically connected to the light-emitting device 03 and is used to drive the light-emitting device 03 to emit light. The driving circuit 01 is also electrically connected to the pixel circuit 02 and is used to provide a gate scan signal to the pixel circuit 02, thereby driving the pixel circuit 02 to work.

[0052] The driving circuit 01 includes multiple cascaded shift register units 10. As shown in Figure 2, the shift register unit 10 includes a first type of signal output module 11 and a second type of signal output module 12. The first type of signal output module 11 and the second type of signal output module 12 are used to transmit gate scan signals to different transistors in the pixel circuit 02.

[0053] As shown in Figure 3, Figure 3 is a schematic diagram of a pixel circuit provided in an embodiment of this application. The pixel circuit 02 includes a driving transistor Md and a gate reset transistor M1, a data writing transistor M2, and a threshold grabbing transistor M3 that are electrically connected to the driving transistor Md.

[0054] The driving transistor Md is used to generate the light-emitting driving current, the gate reset transistor M1 is used to transmit the reset voltage to the gate of the driving transistor Md, the data write transistor M2 is used to transmit the data voltage to the driving transistor Md, and the threshold grab transistor M3 is used to compensate the threshold voltage of the driving transistor Md to the gate of the driving transistor Md.

[0055] For example, as shown in Figure 3, the first terminal of the gate reset transistor M1 is electrically connected to the first reset signal line SL1, the second terminal is electrically connected to the gate of the driving transistor Md, and the gate is electrically connected to the first scan line S1N. The first reset signal line SL1 transmits the first reset voltage Vref1. The first terminal of the data write transistor M2 is electrically connected to the data signal line DL1, the second terminal is electrically connected to the first terminal of the driving transistor Md, and the gate is electrically connected to the second scan line SP. The data signal line DL1 transmits the data voltage Data. The first terminal of the threshold grabbing transistor M3 is electrically connected to the second terminal of the driving transistor Md, the second terminal is electrically connected to the gate of the driving transistor Md, and the gate is electrically connected to the third scan line S2N.

[0056] In addition, pixel circuit 02 also includes a power supply voltage writing transistor M4, a light-emitting control transistor M5, a light-emitting reset transistor M6, and a storage capacitor Cst. The first terminal of the power supply voltage writing transistor M4 is electrically connected to the first power supply signal line DL2, the second terminal is electrically connected to the first terminal of the driving transistor Md, and the gate is electrically connected to the light-emitting control signal line EM. The first power supply signal line DL2 transmits the first power supply voltage PVDD. The first terminal of the light-emitting control transistor M5 is electrically connected to the second terminal of the driving transistor Md, the second terminal is electrically connected to the first terminal of the light-emitting device 03, and the gate is electrically connected to the light-emitting control signal line EM. The first terminal of the light-emitting reset transistor M6 is electrically connected to the second reset signal line SL2, the second terminal is electrically connected to the first terminal of the light-emitting device 03, and the gate is electrically connected to the second scan line SP. The second reset signal line SL2 transmits the second reset voltage Vref2. One plate of the storage capacitor Cst is electrically connected to the gate of the driving transistor Md, and the other plate is electrically connected to the first power supply signal line DL1.

[0057] For example, both the gate reset transistor M1 and the threshold grabbing transistor M3 are metal oxides. The gate reset transistor M1 and the threshold grabbing transistor M3 are N-type transistors, while the driving transistor Md, the data writing transistor M2, the power supply voltage writing transistor M4, the light-emitting control transistor M5, and the light-emitting reset transistor M6 are P-type transistors.

[0058] The operation of pixel circuit 02 can be the same as that of existing technology, and will not be described in detail here.

[0059] Among them, the output terminal SN_OUT of the first type of signal output module 11 is electrically connected to the gate of the gate reset transistor M1 and / or the gate of the threshold grabbing transistor M3, and the output terminal SP_OUT of the second type of signal output module 12 is electrically connected to the gate of the data writing transistor M2.

[0060] In other words, the first type of signal output module 11 can provide a scan signal to the gate of the gate reset transistor M1 via the first scan line S1N, and / or provide a scan signal to the gate of the threshold grabbing transistor M3 via the third scan line S2N. The second type of signal output module 12 can provide a scan signal to the gate of the data write transistor M2 via the second scan line SP. In the same pixel circuit 02, at least one of the gate reset transistor M1 and the threshold grabbing transistor M3 and the data write transistor M2 can be connected to the same shift register unit 10.

[0061] It should be noted that Figure 3 only illustrates the case where the gates of the first type of signal output module 11 are electrically connected to the gate reset transistor M1 and the threshold grabbing transistor M3.

[0062] The enable signal output by the output terminal SN_OUT of the first type of signal output module 11 can be a high-level signal, and the enable signal output by the output terminal SP_OUT of the second type of signal output module 12 can be a low-level signal.

[0063] In this embodiment, by configuring at least one of the gate reset transistor M1 and the threshold grabbing transistor M3 in the pixel circuit 02 to be electrically connected to the same driving circuit 01 as the data writing transistor M2, the number of peripheral driving circuits required for the pixel circuit 02 can be reduced. When the driving circuit 01 and the pixel circuit 02 are applied in the display panel 100, it is beneficial to reduce the area occupied by the peripheral driving circuits, thereby facilitating the achievement of a narrow bezel in the display panel 100.

[0064] Furthermore, reducing the number of peripheral driving circuits required for the pixel circuit 02 can also reduce the number of clock signals required for the peripheral driving circuits, which is beneficial for reducing the power consumption of the display panel 100.

[0065] Figure 4 is a plan view of another display panel provided in an embodiment of this application, and Figure 5 is a partial view of another shift register unit provided in an embodiment of this application.

[0066] In one embodiment of this application, as shown in Figures 4 and 5, the second type of signal output module 12 includes a first scan signal output module 121 and a second scan signal output module 122. The first scan signal output module 121 and the second scan signal output module 122 are respectively electrically connected to the gates of the data writing transistors M2 in different row pixel circuits 02.

[0067] Optionally, as shown in Figure 4, the output terminal SP1_OUT of the first scan signal output module 121 is electrically connected to the i-th row pixel circuit 02, and the output terminal SP2_OUT of the second scan signal output module 122 is electrically connected to the (i+1)-th row pixel circuit 02; i≥1. That is, in the display panel 100, the same shift register unit 10 can drive the data writing transistor M2 in two adjacent rows of pixel circuits 02.

[0068] It should be noted that the output terminal SP1_OUT of the first scan signal output module 121 and the output terminal SP2_OUT of the second scan signal output module 122 can both be the output terminal SP_OUT of the second type of signal output module 12.

[0069] In this embodiment of the application, the same shift register unit 10 is set to drive two rows of pixel circuits 02, which can reduce the number of shift register units 10 in the driving circuit 01. While implementing the driving pixel circuit 02, it is beneficial to further reduce the area occupied by the driving circuit 01, thereby further reducing the bezel of the display panel 100.

[0070] Referring to Figures 4 and 5, in one embodiment of this application, the output terminal SN_OUT of the first type of signal output module 11 is electrically connected to at least two rows of pixel circuits 02.

[0071] For example, the output terminal SN_OUT of the first type of signal output module 11 is electrically connected to the two-row pixel circuit 02. That is, the same shift register unit 10 can drive the gate reset transistor M1 and / or threshold grabbing transistor M3 in the two-row pixel circuit 02.

[0072] In this embodiment, the output terminal SN_OUT of the first type of signal output module 11 is electrically connected to at least two rows of pixel circuits 02. This is beneficial because in the same shift register unit 10, the first type of signal output module 11 and the second type of signal output module 12 can drive the same number of rows of pixel circuits 02, thereby reducing the control difficulty of the shift register unit 101 and simplifying the control method of the drive circuit 01.

[0073] Figure 6 is a schematic diagram of a shift register unit provided in an embodiment of this application.

[0074] In one embodiment of this application, as shown in FIG6, the first type of signal output module 11 includes a first output unit 11 and a second output unit 112. The input terminal of the first output unit 11 receives a first fixed potential signal, and its output terminal is electrically connected to the output terminal SN_OUT of the first type of signal output module 11. The input terminal of the second output unit 112 receives a second fixed potential signal, and its output terminal is electrically connected to the output terminal SN_OUT of the first type of signal output module 11.

[0075] For example, the first fixed potential signal is a high-level signal VGH, and the second fixed potential signal is a low-level signal VGL.

[0076] The shift register unit 10 further includes a first input module 13, a transmission module 14, and a gating module 15. The first input module 13 receives a first trigger signal SN_IN at its input terminal, is electrically connected to the first node N1 at its output terminal, and receives a first clock signal CK1 at its control terminal. The first type of signal output module 11 can output the signal required by the pixel circuit 02 in response to the first trigger signal SN_IN.

[0077] The cascading module 14 is electrically connected to the first node N1. The first output terminal of the cascading module 14 is electrically connected to the second node N2, and the second output terminal SN_NEXT is electrically connected to the gating module 15 and the second output unit 112. The first output terminal of the cascading module 14 transmits a control signal to the second node N2 in response to the potential of the first node N1, and the second output terminal SN_NEXT of the cascading module 14 transmits a control signal to the gating module 15 and the second output unit 112 in response to the potential of the second node N2.

[0078] The gating module 15 is electrically connected to the second node N2, and the output terminal of the gating module 15 is electrically connected to the first output unit 11. The gating module 15 transmits a control signal to the first output unit 11 in response to the potential of the second node N2 and the second output terminal SN_NEXT of the cascading module 14.

[0079] Optionally, as shown in Figure 7, which is a schematic diagram of another shift register unit provided in an embodiment of this application, the cascading module 14 includes a first module 141 and a second module 142. The first input terminal of the first module 141 receives a first fixed potential signal VGH, the second input terminal receives a second fixed potential signal VGL, the output terminal is electrically connected to the second node N2, and the control terminal is electrically connected to the first node N1. The output terminal of the first module 141 can be the first output terminal of the cascading module 14.

[0080] The first input terminal of the second module 142 receives the first fixed potential signal VGH, the second input terminal receives the second fixed potential signal VGL, the output terminal is electrically connected to the second output terminal SN_NEXT of the cascade module 14, and the control terminal is electrically connected to the second node N2. The output terminal of the second module 142 can be equivalent to the second output terminal SN_NEXT of the cascade module 14, and the output terminal of the second module 142 is electrically connected to the gating module 15 and the second output unit 112.

[0081] For example, as shown in Figure 8, which is a schematic diagram of the shift register unit shown in Figure 7, the first input module 13 includes a first transistor T1. The first terminal of the first transistor T1 receives a first trigger signal SN_IN, the second terminal is electrically connected to the first node N1, and the gate receives a first clock signal CK1. The first transistor T1 is used to transmit the first trigger signal SN_IN to the first node N1.

[0082] The first module 141 includes a second transistor T2 and a third transistor T3. The first terminal of the second transistor T2 receives a first fixed potential signal VGH, its second terminal is electrically connected to the second node N2, and its gate is electrically connected to the first node N1. The first terminal of the third transistor T3 receives a second fixed potential signal VGL, its second terminal is electrically connected to the second node N2, and its gate is electrically connected to the first node N1. The second transistor T2 and the third transistor T3 have different channel types. The first module 141 transmits either the first fixed potential signal VGH or the second fixed potential signal VGL to the second node N2 in response to the potential of the first node N1.

[0083] For example, the second transistor T2 is a P-type transistor, and the third transistor T3 is an N-type transistor. The potential level of the second node N2 is opposite to the potential level of the first node N1.

[0084] The second module 142 includes a fourth transistor T4 and a fifth transistor T5. The first terminal of the fourth transistor T4 receives a first fixed potential signal VGH, its second terminal is electrically connected to the output terminal of the second module 142, and its gate is electrically connected to the second node N2. The channel type of the fourth transistor T4 is the same as that of the second transistor T2. The first terminal of the fifth transistor T5 receives a second fixed potential signal VGL, its second terminal is electrically connected to the output terminal of the second module 142, and its gate is electrically connected to the second node N2. The channel type of the fifth transistor T5 is the same as that of the third transistor T3. The second module 142 transmits either the first fixed potential signal VGH or the second fixed potential signal VGL to the gating module 15 and the second output unit 112 in response to the potential of the second node N2. The output potential level of the second module 142 is opposite to the potential level of the second node N2.

[0085] In one embodiment of this application, please continue to refer to Figures 6 and 7. The second type of signal output module 12 includes a first scan signal output module 121 and a second scan signal output module 122. The first scan signal output module 121 and the second scan signal output module 122 can be electrically connected to pixel circuits 02 in different rows.

[0086] The first scan signal output module 121 includes a third output unit 1211 and a fourth output unit 1212. The input terminal of the third output unit 1211 receives a first fixed potential signal VGH, the output terminal is electrically connected to the output terminal SP1_OUT of the first scan signal output module 121, and the control terminal is electrically connected to the second node N2. The input terminal of the fourth output unit 1212 receives a second clock signal CK2, and the output terminal is electrically connected to the output terminal SP1_OUT of the first scan signal output module 121.

[0087] The second scan signal output module 122 includes a fifth output unit 1221 and a sixth output unit 1222. The input terminal of the fifth output unit 1221 receives a first fixed potential signal VGH, its output terminal is electrically connected to the output terminal SP2_OUT of the second scan signal output module 122, and its control terminal is electrically connected to the second node N2. The input terminal of the sixth output unit 1222 receives a third clock signal CK3, and its output terminal is electrically connected to the output terminal SP2_OUT of the second scan signal output module 122.

[0088] The shift register unit 10 also includes a second input module 16. The input terminal of the second input module 16 receives the second trigger signal SP_IN, the output terminal is coupled to the control terminal of the fourth output unit 1212 and the control terminal of the sixth output unit 1222, and the control terminal receives the first clock signal CK1.

[0089] Based on this configuration, the first scan signal output module 121 responds to the potential of the second node N2 and the second trigger signal SP_IN by outputting either a first fixed potential signal VGH or a second clock signal CK2. The second scan signal output module 122 responds to the potential of the second node N2 and the second trigger signal SP_IN by outputting either a first fixed potential signal VGH or a third clock signal CK3. The first scan signal output module 121 and the second scan signal output module 122 can share the same control signal. While driving the multi-row pixel circuit 02, this helps to further reduce the number of transistors in the shift register unit 10, thereby facilitating the further realization of a narrow bezel on the display panel 100.

[0090] As one possible implementation, as shown in Figure 8, the first output unit 111 includes a sixth transistor T6. The first terminal of the sixth transistor T6 receives a first fixed potential signal VGH, the second terminal is electrically connected to the output terminal of the first output unit 111, and the gate is electrically connected to the output terminal of the gating module 15. The sixth transistor T6 transmits the first fixed potential signal VGH to the output terminal SN_OUT of the first type of signal output module 11 in response to the output signal of the gating module 15. The second output unit 112 includes a seventh transistor T7. The first terminal of the seventh transistor T7 receives a second fixed potential signal VGL, the second terminal is electrically connected to the output terminal of the second output unit 112, and the gate is electrically connected to the second output terminal SN_NEXT of the cascade module 13. The seventh transistor T7 transmits the second fixed potential signal VGL to the output terminal SN_OUT of the first type of signal output module 11 in response to the potential of the second output terminal SN_NEXT of the cascade module 13. The sixth transistor T6 and the seventh transistor T7 have different channel types.

[0091] For example, the sixth transistor T6 is a P-type transistor and the seventh transistor T7 is an N-type transistor.

[0092] The third output unit 1211 includes an eighth transistor T8. The first terminal of the eighth transistor T8 receives a first fixed potential signal VGH, its second terminal is electrically connected to the output terminal of the third output unit 1211, and its gate is electrically connected to the second node N2. In response to the potential of the second node N2, the eighth transistor T8 transmits the first fixed potential signal VGH to the output terminal SP1_OUT of the first scan signal output module 121. The fourth output unit 1212 includes a ninth transistor T9. The first terminal of the ninth transistor T9 receives a second clock signal CK2, its second terminal is electrically connected to the output terminal of the fourth output unit 1212, and its gate is electrically connected to the output terminal of the second input module 16. In response to the potential of the output terminal of the second input module 16, the ninth transistor T9 transmits the second clock signal CK2 to the output terminal SP1_OUT of the first scan signal output module 121. The channel type of the eighth transistor T8 is the same as that of the ninth transistor T9.

[0093] For example, both the eighth transistor T8 and the ninth transistor T9 are P-type transistors.

[0094] The fifth output unit 1221 includes a tenth transistor T10. The first terminal of the tenth transistor T10 receives a first fixed potential signal VGH, its second terminal is electrically connected to the output terminal of the fifth output unit 1221, and its gate is electrically connected to the second node N2. In response to the potential of the second node N2, the tenth transistor T10 transmits the first fixed potential signal VGH to the output terminal SP2_OUT of the second scan signal output module 122. The sixth output unit 1222 includes an eleventh transistor T11. The first terminal of the eleventh transistor T11 receives a third clock signal CK3, its second terminal is electrically connected to the output terminal of the sixth output unit 1222, and its gate is electrically connected to the output terminal of the second input module 16. In response to the potential of the output terminal of the second input module 16, the eleventh transistor T11 transmits the third clock signal CK3 to the output terminal SP2_OUT of the second scan signal output module 122. The channel type of the tenth transistor T10 is the same as that of the eleventh transistor T11.

[0095] For example, both the tenth transistor T10 and the eleventh transistor T11 are P-type transistors.

[0096] As one possible implementation, as shown in Figure 8, the second input module 16 includes a twelfth transistor T12. The first terminal of the twelfth transistor T12 receives the second trigger signal SP_IN, the second terminal is electrically connected to the output terminal of the second input module 16, and the gate receives the first clock signal CK1. In response to the first clock signal CK1, the twelfth transistor T12 transmits the second trigger signal SP_IN to the control terminal of the fourth output unit 1212 and the control terminal of the sixth output unit 1222.

[0097] Figure 9 is a schematic diagram of another shift register unit provided in an embodiment of this application.

[0098] In one embodiment of this application, as shown in FIG9, a first voltage regulator module 17 is included between the output terminal of the second input module 16 and the fourth output unit 1212, and a second voltage regulator module 18 is included between the output terminal of the second input module 16 and the sixth output unit 1222. The control terminals of both the first voltage regulator module 17 and the second voltage regulator module 18 receive a fixed potential signal. During the operation of the shift register unit 10, the first voltage regulator module 17 and the second voltage regulator module 18 can be in an on state.

[0099] Optionally, as shown in Figure 9, the control terminals of both the first voltage regulator module 17 and the second voltage regulator module 18 receive the second fixed potential signal VGL.

[0100] For example, as shown in Figure 10, which is a schematic diagram of the shift register unit shown in Figure 9, the first voltage regulator module 17 includes a thirteenth transistor T13. The first terminal of the thirteenth transistor T13 is electrically connected to the output terminal of the second input module 16, the second terminal is electrically connected to the control terminal of the fourth output unit 1212, and the gate is electrically connected to the second fixed potential signal VGL. The second voltage regulator module 18 includes a fourteenth transistor T14. The first terminal of the fourteenth transistor T14 is electrically connected to the output terminal of the second input module 16, the second terminal is electrically connected to the control terminal of the sixth output unit 1222, and the gate is electrically connected to the second fixed potential signal VGL. Both the thirteenth transistor T13 and the fourteenth transistor T14 are P-type transistors.

[0101] In this embodiment, the first voltage regulator module 17 and the second voltage regulator module 18 are configured to stabilize the potential at the output terminal of the second input module 16. When the potential at the control terminal of the fourth output unit 1212 changes, the first voltage regulator module 17 can reduce the impact of this potential change on the potential at the output terminal of the second input module 16, thereby stabilizing the potential at the output terminal of the second input module 16. When the potential at the control terminal of the sixth output unit 1222 changes, the second voltage regulator module 18 can reduce the impact of this potential change on the potential at the output terminal of the second input module 16, thereby stabilizing the potential at the output terminal of the second input module 16. This, in turn, helps ensure the accuracy of the second trigger signal SP_IN potential output by the second input module 16.

[0102] Please continue referring to Figures 6, 7, and 9. In one embodiment of this application, the shift register unit 10 further includes a reset module 19. The input terminal of the reset module 19 receives a first fixed potential signal VGH, the output terminal is electrically connected to the first node N1, and the control terminal is electrically connected to the reset signal line RST. The reset module 19 transmits the first fixed potential signal VGL to the first node N1 in response to the signal on the reset signal line RET, thereby resetting the first node N1. Furthermore, the cascading module 14 can then be used to reset the output terminal SN_OUT of the first type of signal output module 11 and the output terminal SP_OUT of the second type of signal output module 12.

[0103] For example, as shown in Figures 8 and 10, the reset module 19 includes a fifteenth transistor T15. The first terminal of the fifteenth transistor T15 receives a first fixed potential signal line VGH, the second terminal is electrically connected to the first node N1, and the gate is electrically connected to the reset signal line RST.

[0104] Optionally, at the start of operation of the shift register unit 10, the reset signal line RST transmits the enable signal to control the reset module 19 to turn on.

[0105] In this embodiment, when the shift register unit 10 is reset, the reset signal line RST transmits the enable signal to control the reset module 19 to turn on. The first node N1 receives the first fixed potential signal VGH and maintains a high level potential. The second transistor T2 in the transmission module 14 is turned off, and the third transistor T3 is turned on. The third transistor T3 transmits the second fixed potential signal VGL to the second node N2, and the second node N2 maintains a low level potential.

[0106] The fourth transistor T4 is turned on, and the fifth transistor T5 is turned off. The fourth transistor T4 transmits the first fixed potential signal VGH to the second output terminal SN_NEXT of the transmission module 14, controlling the seventh transistor T7 to turn on. The seventh transistor T7 transmits the second fixed potential signal VGL to the output terminal SN_OUT of the first type of signal output module 11, thereby resetting the output terminal SN_OUT of the first type of signal output module 11. The eighth transistor T8 and the tenth transistor T10 are turned on. The eighth transistor T8 transmits the first fixed potential signal VGH to the output terminal SP1_OUT of the first scan signal output module 121, and the tenth transistor T10 transmits the first fixed potential signal VGH to the output terminal SP2_OUT of the second scan signal output module 122, thereby resetting the output terminals SP1_OUT of the first scan signal output module 121 and SP2_OUT of the second scan signal output module 122.

[0107] Figure 11 is a schematic diagram of a cascaded shift register unit provided in an embodiment of this application.

[0108] In one embodiment of this application, as shown in FIG11, the cascaded multiple shift register units 10 include a j-th stage shift register unit 10 and a j+1-th stage shift register unit 10. The second output terminal SN_NEXT of the cascade module 14 in the j-th stage shift register unit 10 is electrically connected to the input terminal of the first input module 13 in the j+1-th stage shift register unit 10. The output terminal SP2_OUT of the second scan signal output module 122 in the j-th stage shift register unit 10 is electrically connected to the input terminal of the second input module 16 in the j+1-th stage shift register unit 10, where j≥1.

[0109] Based on this configuration, the signal output from the second output terminal SN_NEXT of the intermediate transmission module 14 in the j-th stage shift register unit 10 can be used as the first trigger signal SN_IN of the (j+1)-th stage shift register unit 10. Similarly, the signal output from the output terminal SP2_OUT of the second scan signal output module 122 in the j-th stage shift register unit 10 can be used as the second trigger signal SP_IN of the (j+1)-th stage shift register unit 10.

[0110] Referring to Figures 8 and 10, in one embodiment of this application, the gating module 15 includes a sixteenth transistor T16 and a seventeenth transistor T17. The first terminal of the sixteenth transistor T16 receives a first fixed potential signal VGH, its second terminal is electrically connected to the control terminal of the first output unit 111, and its gate is electrically connected to the second node N2. The first terminal of the seventeenth transistor T17 is electrically connected to the gating signal line CTRL, its second terminal is electrically connected to the control terminal of the first output unit 111, and its gate is electrically connected to the second output terminal SN_NEXT of the cascade module 14. The second terminals of the sixteenth transistor T16 and the seventeenth transistor T17 can serve as output terminals of the gating module 15.

[0111] In this embodiment, the sixteenth transistor T16 transmits a first fixed potential signal VGH to the control terminal of the first output unit 111 in response to the potential of the second node N2, and the seventeenth transistor T17 transmits a signal on the strobe signal line CTRL to the control terminal of the first output unit 111 in response to the potential of the second output terminal SN_NEXT of the cascade module 14.

[0112] For example, both the sixteenth transistor T16 and the seventeenth transistor T17 are P-type transistors.

[0113] When the selected signal line CTRL transmits a high-level signal, both the sixteenth transistor T16 and the seventeenth transistor T16 can only transmit high-level signals to the sixth transistor T6. The sixth transistor T6 remains off, and the output terminal SN_OUT of the first type of signal output module 11 maintains a low-level second fixed potential signal VGL. At this time, the second output terminal SN_NEXT of the cascade module 14 can output a normal cascade signal.

[0114] When the selected signal line CTRL transmits a low-level signal, the sixteenth transistor T16 and the seventeenth transistor T17 can transmit high and low levels to the sixth transistor T6, respectively. The sixth transistor T6 can remain in the on or off state, and the output terminal SN_OUT of the first type of signal output module 11 can output the scan signal normally. At this time, the second output terminal SN_NEXT of the transmission module 14 transmits a signal with the opposite level to the output terminal SN_OUT of the first type of signal output module 11.

[0115] Based on this configuration, the frequency of the enable signal output at the output terminal SN_OUT of the first type of signal output module 11 can be controlled by controlling the signal on the strobe signal line CTRL.

[0116] Figure 12 is another schematic diagram of the shift register unit shown in Figure 9.

[0117] In one embodiment of this application, as shown in FIG12, the gating module 15 includes a sixteenth transistor T16, a seventeenth transistor T17, and an eighteenth transistor T18. The first terminal of the sixteenth transistor T16 receives a first fixed potential signal VGH, the second terminal is electrically connected to the control terminal of the first output unit 111, and the gate is electrically connected to the second node N2. The first terminal of the seventeenth transistor T17 is electrically connected to the third node N3, the second terminal is electrically connected to the control terminal of the first output unit 111, and the gate is electrically connected to the second output terminal SN_NEXT of the cascade module 14. The first terminal of the eighteenth transistor T18 is electrically connected to the gating signal line CTRL, the second terminal is electrically connected to the third node N3, and the gate is electrically connected to the second node N2. The second terminals of the sixteenth transistor T16 and the seventeenth transistor T17 can be the output terminals of the gating module 15.

[0118] In this embodiment, the sixteenth transistor T16 transmits a first fixed potential signal VGH to the control terminal of the first output unit 111 in response to the potential of the second node N2; the eighteenth transistor T18 transmits the potential of the signal on the signal line CTRL to the third node N3 in response to the potential of the second node N2; and the seventeenth transistor T17 transmits the potential of the third node N3 to the control terminal of the first output unit 111 in response to the potential of the second output terminal SN_NEXT of the transmission module 14.

[0119] For example, the sixteenth transistor T16, the seventeenth transistor T17, and the eighteenth transistor T18 are all P-type transistors.

[0120] When the selected signal line CTRL transmits a high-level signal, both the sixteenth transistor T16 and the seventeenth transistor T16 can only transmit high-level signals to the sixth transistor T6. The sixth transistor T6 remains off, and the output terminal SN_OUT of the first type of signal output module 11 maintains a low-level second fixed potential signal VGL. At this time, the second output terminal SN_NEXT of the cascade module 14 can output a normal cascade signal.

[0121] When the strobe signal line CTRL transmits a low-level signal, the low-level signal on the strobe signal line CTRL can be transmitted to the third node N3 through the eighteenth transistor T18. The sixteenth transistor T16 and the seventeenth transistor T16 can transmit high and low levels to the sixth transistor T6, respectively. The sixth transistor T6 can remain in the on or off state, and the output terminal SN_OUT of the first type of signal output module 11 can output the scan signal normally. At this time, the second output terminal SN_NEXT of the cascade module 14 transmits a signal with the opposite level to the output terminal SN_OUT of the first type of signal output module 11.

[0122] Based on this configuration, the frequency of the enable signal output at the output terminal SN_OUT of the first type of signal output module 11 can be controlled by controlling the signal on the strobe signal line CTRL.

[0123] Figure 13 is another schematic diagram of the shift register unit shown in Figure 9.

[0124] In one embodiment of this application, as shown in FIG13, the gating module 15 includes a sixteenth transistor T16, a seventeenth transistor T17, and an eighteenth transistor T18. The first terminal of the sixteenth transistor T16 is electrically connected to the second output terminal SN_NEXT of the cascade module 14, the second terminal is electrically connected to the control terminal of the first output unit 111, and the gate is electrically connected to the third node N3. The first terminal of the seventeenth transistor T17 receives a first fixed potential signal VGH, the second terminal is electrically connected to the control terminal of the first output unit 111, and the gate is electrically connected to the third node N3. The first terminal of the eighteenth transistor T18 is electrically connected to the gating signal line CTRL, the second terminal is electrically connected to the third node N3, and the gate is electrically connected to the second node N2. The second terminals of the sixteenth transistor T16 and the seventeenth transistor T17 can be the output terminals of the gating module 15.

[0125] Among them, the sixteenth transistor T16 and the seventeenth transistor T17 have different channel types, while the sixteenth transistor T16 and the eighteenth transistor T18 have the same channel type.

[0126] For example, the sixteenth transistor T16 and the eighteenth transistor T18 are P-type transistors, and the seventeenth transistor T17 is an N-type transistor.

[0127] In this embodiment, the eighteenth transistor T18 responds to the potential of the second node N2 and transmits the potential of the signal on the signal line CTRL to the third node N3; the seventeenth transistor T17 responds to the potential of the third node N3 and transmits the first fixed potential signal VGH to the control terminal of the first output unit 111; and the sixteenth transistor T16 responds to the potential of the third node N3 and transmits the potential of the second output terminal SN_NEXT of the transmission module 14 to the control terminal of the first output unit 111.

[0128] When the selected signal line CTRL transmits a high-level signal, the eighteenth transistor T18 can transmit the high-level signal to the third node N3, the sixteenth transistor T16 remains off, and the seventeenth transistor T17 can only transmit a high-level signal to the control terminal of the sixth transistor T6. The sixth transistor T6 remains off, and the output terminal SN_OUT of the first type of signal output module 11 maintains a low-level second fixed potential signal VGL. At this time, the second output terminal SN_NEXT of the cascade module 14 can output a normal cascade signal.

[0129] When the selected signal line CTRL transmits a low-level signal, the eighteenth transistor T18 can transmit the low-level signal to the third node N3, the seventeenth transistor T17 remains off, and the sixteenth transistor T16 can transmit the potential of the second output terminal SN_NEXT of the transmission module 14 to the control terminal of the sixth transistor T6. The potential of the second output terminal SN_NEXT of the transmission module 14 includes both high and low level potentials. The sixth transistor T6 can remain on or off, and the output terminal SN_OUT of the first type of signal output module 11 can output the scan signal normally. At this time, the second output terminal SN_NEXT of the transmission module 14 and the output terminal SN_OUT of the first type of signal output module 11 transmit signals with opposite levels.

[0130] Based on this configuration, the frequency of the enable signal output at the output terminal SN_OUT of the first type of signal output module 11 can be controlled by controlling the signal on the strobe signal line CTRL.

[0131] Figure 14 is another schematic diagram of the shift register unit shown in Figure 9.

[0132] In one embodiment of this application, as shown in FIG14, the gating module 15 includes a sixteenth transistor T16, a seventeenth transistor T17, and an eighteenth transistor T18. The first terminal of the sixteenth transistor T16 receives a first fixed potential signal VGH, the second terminal is electrically connected to the control terminal of the first output unit 111, and the gate is electrically connected to the second output terminal SN_NEXT of the cascade module 14. The first terminal of the seventeenth transistor T17 is electrically connected to the third node N3, the second terminal is electrically connected to the control terminal of the first output unit 111, and the gate is electrically connected to the second output terminal SN_NEXT of the cascade module 14. The first terminal of the eighteenth transistor T18 is electrically connected to the gating signal line CTRL, the second terminal is electrically connected to the third node N3, and the gate is electrically connected to the second node N2. The second terminals of the sixteenth transistor T16 and the seventeenth transistor T17 can be the output terminals of the gating module 15.

[0133] Among them, the channel types of the sixteenth transistor T16 and the seventeenth transistor T17 are different, and the channel types of the sixteenth transistor T16 and the eighteenth transistor T18 are different.

[0134] For example, the sixteenth transistor T16 is an N-type transistor, and the seventeenth transistor T17 and the eighteenth transistor T18 are P-type transistors.

[0135] In this embodiment, the eighteenth transistor T18 transmits the potential of the signal on the signal line CTRL to the third node N3 in response to the potential of the second node N2; the seventeenth transistor T17 transmits the potential of the third node N3 to the control terminal of the first output unit 111 in response to the potential of the second output terminal SN_NEXT of the cascade module 14; and the sixteenth transistor T16 transmits the first fixed potential signal VGH to the control terminal of the first output unit 111 in response to the potential of the second output terminal SN_NEXT of the cascade module 14.

[0136] When the selected signal line CTRL transmits a high-level signal, the eighteenth transistor T18 can transmit the high-level signal to the third node N3. If the potential of the second output terminal SN_NEXT of the cascade module 14 is low, the sixteenth transistor T16 is turned off, and the seventeenth transistor T17 transmits the high-level potential of the third node N3 to the control terminal of the sixth transistor T6, which remains off. If the potential of the second output terminal SN_NEXT of the cascade module 14 is high, the seventeenth transistor T17 is turned off, and the sixteenth transistor T16 transmits the high-level first fixed potential signal VGH to the control terminal of the sixth transistor T6, which remains off. The output terminal SN_OUT of the first type of signal output module 11 maintains a low-level second fixed potential signal VGL. At this time, the second output terminal SN_NEXT of the cascade module 14 can output a normal cascade signal.

[0137] When the selected signal line CTRL transmits a low-level signal, the eighteenth transistor T18 can transmit the low-level signal to the third node N3. If the potential of the second output terminal SN_NEXT of the cascade module 14 is low, the seventeenth transistor T17 can transmit the low-level potential of the third node N3 to the control terminal of the sixth transistor T6. If the potential of the second output terminal SN_NEXT of the cascade module 14 is high, the sixteenth transistor T16 can transmit the high-level first fixed potential signal VGH to the control terminal of the sixth transistor T6. The sixth transistor T6 can remain in the on or off state, and the output terminal SN_OUT of the first type of signal output module 11 can output the scan signal normally. At this time, the second output terminal SN_NEXT of the cascade module 14 and the output terminal SN_OUT of the first type of signal output module 11 transmit signals with opposite levels.

[0138] Based on this configuration, the frequency of the enable signal output at the output terminal SN_OUT of the first type of signal output module 11 can be controlled by controlling the signal on the strobe signal line CTRL.

[0139] Figure 15 is another schematic diagram of the shift register unit shown in Figure 9.

[0140] In one embodiment of this application, as shown in FIG15, the gating module 15 includes a sixteenth transistor T16, a seventeenth transistor T17, and an eighteenth transistor T18. The first terminal of the sixteenth transistor T16 receives a first fixed potential signal VGH, the second terminal is electrically connected to the control terminal of the first output unit 111, and the gate is electrically connected to the third node N3. The first terminal of the seventeenth transistor T17 is electrically connected to the second output terminal SN_NEXT of the cascade module 14, the second terminal is electrically connected to the control terminal of the first output unit 111, and the gate is electrically connected to the third node N3. The first terminal of the eighteenth transistor T18 is electrically connected to the gating signal line CTRL, the second terminal is electrically connected to the third node N3, and the gate is electrically connected to the second node N2. The second terminals of the sixteenth transistor T16 and the seventeenth transistor T17 can be the output terminals of the gating module 15.

[0141] Among them, the sixteenth transistor T16 and the seventeenth transistor T17 have different channel types, while the sixteenth transistor T16 and the eighteenth transistor T18 have the same channel type.

[0142] For example, the sixteenth transistor T16 and the eighteenth transistor T18 are P-type transistors, and the seventeenth transistor T17 is an N-type transistor.

[0143] In this embodiment, the eighteenth transistor T18 responds to the potential of the second node N2 and transmits the potential of the signal on the signal line CTRL to the third node N3; the sixteenth transistor T16 responds to the potential of the third node N3 and transmits the first fixed potential signal VGH to the control terminal of the first output unit 111; and the seventeenth transistor T17 responds to the potential of the third node N3 and transmits the potential of the second output terminal SN_NEXT of the transmission module 14 to the control terminal of the first output unit 111.

[0144] When the selected signal line CTRL transmits a low-level signal, the eighteenth transistor T18 can transmit the low-level signal to the third node N3, the seventeenth transistor T17 remains off, and the sixteenth transistor T16 can only transmit the high-level first fixed potential signal VGH to the control terminal of the sixth transistor T6. The sixth transistor T6 remains off, and the output terminal SN_OUT of the first type of signal output module 11 maintains a low-level second fixed potential signal VGL. At this time, the second output terminal SN_NEXT of the cascade module 14 can output a normal cascade signal.

[0145] When the selected signal line CTRL transmits a high-level signal, the eighteenth transistor T18 can transmit the high-level signal to the third node N3, the sixteenth transistor T16 remains off, and the seventeenth transistor T17 can transmit the potential of the second output terminal SN_NEXT of the transmission module 14 to the control terminal of the sixth transistor T6. The potential of the second output terminal SN_NEXT of the transmission module 14 includes both high and low level potentials. The sixth transistor T6 can remain on or off, and the output terminal SN_OUT of the first type of signal output module 11 can output the scan signal normally. At this time, the second output terminal SN_NEXT of the transmission module 14 transmits signals with opposite levels to the output terminal SN_OUT of the first type of signal output module 11.

[0146] Based on this configuration, the frequency of the enable signal output at the output terminal SN_OUT of the first type of signal output module 11 can be controlled by controlling the signal on the strobe signal line CTRL.

[0147] Please continue to refer to Figures 12-15. In one embodiment of this application, the gating module 15 further includes a first capacitor C1. One plate of the first capacitor C1 is electrically connected to the third node N3, and the other plate receives a fixed potential signal.

[0148] For example, as shown in Figures 12-15, the fixed potential signal received by the first capacitor C1 is the second fixed potential signal VGL.

[0149] In this embodiment, the setting of the first capacitor C1 can improve the stability of the potential of the third node N3, which is beneficial to improving the accuracy of the signal transmission from the third node N3 to other devices in the gating module 15.

[0150] In one embodiment of this application, referring further to Figures 8, 10-15, the shift register unit 10 also includes a second capacitor C2, a third capacitor C3, and a fourth capacitor C4. One plate of the second capacitor C2 is electrically connected to the output terminal of the fourth output unit 1212, and the other plate is electrically connected to the control terminal of the fourth output unit 1212. Based on this arrangement, the signal output by the fourth output unit 1212 can be used to stabilize the control terminal signal of the fourth output unit 1212, thereby improving the stability of the operating state of the fourth output unit 1212.

[0151] One plate of the third capacitor C3 is electrically connected to the output terminal of the sixth output unit 1222, and the other plate is electrically connected to the control terminal of the sixth output unit 1222. Based on this configuration, the signal output by the sixth output unit 1222 can be used to stabilize the control terminal signal of the sixth output unit 1222, thereby improving the stability of the operating state of the sixth output unit 1222.

[0152] One plate of the fourth capacitor C4 is electrically connected to the first node N1, while the other plate receives a fixed potential signal. For example, the fixed potential signal received by the fourth capacitor C4 is the second fixed potential signal VGL. This configuration improves the potential stability of the first node N1, thereby enhancing the accuracy of signal transmission from the first node N1 to the transmission module 14.

[0153] Figure 16 is another schematic diagram of the shift register unit shown in Figure 9.

[0154] As shown in Figure 16, in one embodiment of this application, the selection module 15 further includes a first inverter 151 and a second inverter 152. The input terminal of the first inverter 151 is electrically connected to the output terminal of the second inverter and a third node, and the output terminal is electrically connected to the input terminal of the second inverter 152. That is, the first inverter 151 and the second inverter 152 are connected end-to-end, and both the input terminal of the first inverter 151 and the output terminal of the second inverter 152 are electrically connected to the third node N3.

[0155] For example, as shown in Figure 16, the first inverter 151 includes a nineteenth transistor T19 and a twelfth transistor T20. The nineteenth transistor T19 is a P-type transistor, and the twelfth transistor T20 is an N-type transistor. The first terminal of the nineteenth transistor T19 receives a first fixed potential signal VGH, the second terminal is electrically connected to the input terminal of the second inverter 152, and the gate is electrically connected to the third node N3. The first terminal of the twelfth transistor T20 receives a second fixed potential signal VGL, the second terminal is electrically connected to the input terminal of the second inverter 152, and the gate is electrically connected to the third node N3. The gates of the nineteenth transistor T19 and the twelfth transistor T20 are the input terminals of the first inverter 151, and the second terminals of the nineteenth transistor T19 and the twelfth transistor T20 are the output terminals of the first inverter 151.

[0156] The second inverter 152 includes a twenty-first transistor T21 and a twenty-second transistor T22. T21 is a P-type transistor, and T22 is an N-type transistor. The first terminal of transistor T21 receives a first fixed potential signal VGH, its second terminal is electrically connected to a third node N3, and its gate is electrically connected to the output terminal of the first inverter 151. The first terminal of transistor T22 receives a second fixed potential signal VGL, its second terminal is electrically connected to the third node N3, and its gate is electrically connected to the output terminal of the first inverter 151. The gates of transistors T21 and T22 serve as the input terminals of the second inverter 152, and the second terminals of transistors T21 and T22 serve as the output terminals of the second inverter 152.

[0157] In this embodiment, the potential of the third node N3 is inverted sequentially by the first inverter 151 and the second inverter 152, thus maintaining the current potential of the third node N3 and achieving its stability. Furthermore, when a slight disturbance occurs in the potential of the third node N3, the first fixed potential signal VGH / second fixed potential signal VGL connected to the second inverter 152 refreshes the potential of the third node N3, stabilizing it and making the output potential of the third node N3 more stable.

[0158] It should be noted that the difference between the shift register unit shown in Figure 16 and the shift register unit shown in Figure 12 is that the structure of the first inverter 151 and the second inverter 152 in Figure 16 replaces the first capacitor C1 in Figure 12. The first capacitor C1 in Figures 13-15 can also be replaced by the structure of the first inverter 151 and the second inverter 152 in Figure 16.

[0159] Figure 17 is a timing diagram of a shift register unit provided in an embodiment of this application.

[0160] To facilitate understanding of the technical solution of this application, the enable signal output process of the shift register unit shown in Figure 10 will be explained below with reference to Figures 10 and 17. Taking the transmission of a low-level signal by the strobe signal line CTRL, the enable signal output by the first type of signal output module 11 being high-level, and the enable signal output by the second type of signal output module 12 being low-level as an example, the signal output stage Z of the shift register unit 10 includes the first stage Z1, the second stage Z2, the third stage Z3, and the fourth stage Z4 performed sequentially.

[0161] In the first stage Z1, the first trigger signal SN_IN is low, the second trigger signal SP_IN is low, the first clock signal CK1 is low, and the second and third clock signals CK2 and CK3 are high. The first transistor T1 is turned on, transmitting the low-level first trigger signal SN_IN to the first node N1. The second transistor T2 is turned on, and the third transistor T3 is turned off. The second transistor T2 transmits the high-level first fixed-point signal VGH to the second node N2. The fourth transistor T4, the sixteenth transistor T16, the eighth transistor T8, and the tenth transistor T10 are turned off, and the fifth transistor T5 is turned on. The fifth transistor T5 transmits the low-level second fixed potential signal VGL to the gates of the seventh transistor T7 and the seventeenth transistor T17. The seventh transistor T7 is turned off, and the seventeenth transistor T17 is turned on. The seventeenth transistor T17 transmits the low-level signal transmitted by the strobe signal line CTRL to the gate of the sixth transistor T6. The sixth transistor T6 is turned on, and the sixth transistor T6 outputs the high-level first fixed potential signal VGH to the output terminal SN_OUT of the first type of signal output module 11.

[0162] The fourteenth transistor T14 is turned on, and transmits the low-level second trigger signal SP_IN to the gate of the ninth transistor T9 and the gate of the eleventh transistor T11. The ninth transistor T9 and the eleventh transistor T11 are turned on, and the ninth transistor T9 transmits the high-level second clock signal CK2 to the output terminal SP1_OUT of the first scan signal output module 121. The eleventh transistor T11 transmits the high-level third clock signal CK3 to the output terminal SP2_OUT of the second scan signal output module 122.

[0163] In the second stage Z2, the first trigger signal SN_IN is low, the second trigger signal SP_IN is high, the first clock signal CK1 is high, the second clock signal CK2 is low, and the third clock signal CK3 is high. The first transistor T1 and the fourteenth transistor T14 are off. The first node N1 maintains the low-level potential of the previous stage, and the output of the fourteenth transistor T14 maintains the low-level potential of the previous stage. The ninth transistor T9 and the eleventh transistor T11 remain on. The ninth transistor T9 transmits the low-level second clock signal CK2 to the output SP1_OUT of the first scan signal output module 121, and the eleventh transistor T11 transmits the high-level third clock signal CK3 to the output SP2_OUT of the second scan signal output module 122.

[0164] The second node N2 maintains the high level potential of the previous stage. The fourth transistor T4, the sixteenth transistor T16, the eighth transistor T8, and the tenth transistor T10 are turned off, and the fifth transistor T5 is turned on. The fifth transistor T5 transmits the low-level second fixed potential signal VGL to the gates of the seventh transistor T7 and the seventeenth transistor T17. The seventh transistor T7 is turned off, and the seventeenth transistor T17 is turned on. The seventeenth transistor T17 transmits the low-level signal transmitted by the strobe signal line CTRL to the gate of the sixth transistor T6. The sixth transistor T6 is turned on, and the sixth transistor T6 outputs the high-level first fixed potential signal VGH to the output terminal SN_OUT of the first type of signal output module 11.

[0165] In the third stage Z3, the first trigger signal SN_IN is high, the second trigger signal SP_IN is high, the first clock signal CK1 is high, the second clock signal CK2 is high, and the third clock signal CK3 is low. The first transistor T1 and the fourteenth transistor T14 are off. The first node N1 maintains the low potential of the previous stage, and the output of the fourteenth transistor T14 maintains the low potential of the previous stage. The ninth transistor T9 and the eleventh transistor T11 remain on. The ninth transistor T9 transmits the high-level second clock signal CK2 to the output SP1_OUT of the first scan signal output module 121, and the eleventh transistor T11 transmits the low-level third clock signal CK3 to the output SP2_OUT of the second scan signal output module 122.

[0166] The second node N2 maintains the high level potential of the previous stage. The fourth transistor T4, the sixteenth transistor T16, the eighth transistor T8, and the tenth transistor T10 are turned off, and the fifth transistor T5 is turned on. The fifth transistor T5 transmits the low-level second fixed potential signal VGL to the gates of the seventh transistor T7 and the seventeenth transistor T17. The seventh transistor T7 is turned off, and the seventeenth transistor T17 is turned on. The seventeenth transistor T17 transmits the low-level signal transmitted by the strobe signal line CTRL to the gate of the sixth transistor T6. The sixth transistor T6 is turned on, and the sixth transistor T6 outputs the high-level first fixed potential signal VGH to the output terminal SN_OUT of the first type of signal output module 11.

[0167] In the fourth stage Z4, the first trigger signal SN_IN is high, the second trigger signal SP_IN is high, the first clock signal CK1 is high, the second clock signal CK2 is high, and the third clock signal CK3 is high. The first transistor T1 and the fourteenth transistor T14 remain off. The first node N1 maintains the low potential of the previous stage, and the output of the fourteenth transistor T14 maintains the low potential of the previous stage. The ninth transistor T9 and the eleventh transistor T11 remain on. The ninth transistor T9 transmits the high-level second clock signal CK2 to the output SP1_OUT of the first scan signal output module 121, and the eleventh transistor T11 transmits the high-level third clock signal CK3 to the output SP2_OUT of the second scan signal output module 122.

[0168] The second node N2 maintains the high level potential of the previous stage. The fourth transistor T4, the sixteenth transistor T16, the eighth transistor T8, and the tenth transistor T10 are turned off, and the fifth transistor T5 is turned on. The fifth transistor T5 transmits the low-level second fixed potential signal VGL to the gates of the seventh transistor T7 and the seventeenth transistor T17. The seventh transistor T7 is turned off, and the seventeenth transistor T17 is turned on. The seventeenth transistor T17 transmits the low-level signal transmitted by the strobe signal line CTRL to the gate of the sixth transistor T6. The sixth transistor T6 is turned on, and the sixth transistor T6 outputs the high-level first fixed potential signal VGH to the output terminal SN_OUT of the first type of signal output module 11.

[0169] It should be noted that, in some other embodiments, the timing of the first trigger signal SN_IN and the second trigger signal SP_IN can be controlled to ensure that the time period during which the output terminal SN_OUT of the first type of signal output module 11 outputs the enable signal does not overlap with the time period during which the output terminal SP_OUT of the second type of signal output module 12 outputs the enable signal. This allows the gate reset transistor M1 in the pixel circuit 02 to be driven independently, thereby resetting the gate of the driving transistor Md in the pixel circuit 02.

[0170] Figure 18 is a connection diagram of a shift register unit provided in an embodiment of this application.

[0171] In one embodiment of this application, as shown in FIG18, the shift register unit 10 is electrically connected to a first fixed potential signal line XL1, a second fixed potential signal line XL2, and a gating signal line CTRL. The first fixed potential signal line XL1 transmits a first fixed potential signal VGH, and the second fixed potential signal line XL2 transmits a second fixed potential signal VGL. The gating signal line CTRL can transmit a low-level signal or a high-level signal according to control requirements.

[0172] In addition, the shift register unit 10 is connected to multiple clock signal lines, which are used to provide clock signals to the shift register unit 10. Referring to Figures 10 and 18, in the odd-level shift register unit 10, the control terminals of the first input module 13 and the second input module 16 are electrically connected to the first clock signal line CLK1, the input terminal of the fourth output unit 1212 is electrically connected to the second clock signal line CLK2, and the input terminal of the sixth output unit 1222 is electrically connected to the third clock signal line CLK3.

[0173] Specifically, the clock signal transmitted via the first clock signal line CLK1 serves as the first clock signal CK1 received by the odd-level shift register unit 10. The clock signal transmitted via the second clock signal line CLK2 serves as the second clock signal CK2 received by the odd-level shift register unit 10. The clock signal transmitted via the third clock signal line CLK3 serves as the third clock signal CK3 received by the odd-level shift register unit 10.

[0174] In the even-level shift register unit 10, the control terminals of the first input module 13 and the second input module 16 are electrically connected to the third clock signal line CLK3, the input terminal of the fourth output unit 1212 is electrically connected to the fourth clock signal line CLK4, and the input terminal of the sixth output unit 1222 is electrically connected to the first clock signal line CLK1.

[0175] The clock signal transmitted via the third clock signal line CLK3 serves as the first clock signal CK1 received by the even-stage shift register unit 10. The clock signal transmitted via the fourth clock signal line CLK4 serves as the second clock signal CK2 received by the even-stage shift register unit 10. The clock signal transmitted via the first clock signal line CLK1 serves as the third clock signal CK3 received by the even-stage shift register unit 10.

[0176] For example, as shown in FIG19, FIG19 is a timing diagram of a clock signal line provided in an embodiment of the present application, wherein the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3 and the fourth clock signal line CLK4 sequentially transmit low-level signals.

[0177] In this embodiment, a first clock signal line CLK1, a second clock signal line CLK2, a third clock signal line CLK3, and a fourth clock signal line CLK4 are configured to transmit clock signals to the shift register unit 10 in the driving circuit 01. The shift register unit 10 in the driving circuit 01 can include only two ways of connecting the clock signal lines, which helps to reduce the complexity of connecting the shift register unit 10 to the clock signal lines in the driving circuit 01 and simplifies the connection structure of the driving circuit 01.

[0178] Figure 20 is a connection diagram of another shift register unit provided in an embodiment of this application.

[0179] In one embodiment of this application, as shown in Figures 10 and 20, the shift register unit 10 is connected to multiple clock signal lines. In the j-th stage shift register unit 10, the control terminals of the first input module 13 and the second input module 16 are electrically connected to the first clock signal line CLK1, the input terminal of the fourth output unit 1212 is electrically connected to the second clock signal line CLK2, and the input terminal of the sixth output unit 1222 is electrically connected to the third clock signal line CLK3.

[0180] Specifically, the clock signal transmitted via the first clock signal line CLK1 serves as the first clock signal CK1 received by the j-th stage shift register unit 10. The clock signal transmitted via the second clock signal line CLK2 serves as the second clock signal CK2 received by the j-th stage shift register unit 10. The clock signal transmitted via the third clock signal line CLK3 serves as the third clock signal CK3 received by the j-th stage shift register unit 10.

[0181] In the (j+1)th level shift register unit 10, the control terminals of the first input module 13 and the second input module 16 are electrically connected to the third clock signal line CLK3, the input terminal of the fourth output unit 1212 is electrically connected to the first clock signal line CLK1, and the input terminal of the sixth output unit 1222 is electrically connected to the second clock signal line CLK2.

[0182] The clock signal transmitted via the third clock signal line CLK3 serves as the first clock signal CK1 received by the (j+1)th stage shift register unit 10. The clock signal transmitted via the first clock signal line CLK1 serves as the second clock signal CK2 received by the (j+1)th stage shift register unit 10. The clock signal transmitted via the second clock signal line CLK2 serves as the third clock signal CK3 received by the (j+1)th stage shift register unit 10.

[0183] In the (j+2)th level shift register unit 10, the control terminals of the first input module 13 and the second input module 16 are electrically connected to the second clock signal line CLK2, the input terminal of the fourth output unit 1212 is electrically connected to the third clock signal line CLK3, and the input terminal of the sixth output unit 1222 is electrically connected to the first clock signal line CLK1. j≥1.

[0184] Specifically, the clock signal transmitted via the second clock signal line CLK2 serves as the first clock signal CK1 received by the (j+2)th stage shift register unit 10. The clock signal transmitted via the third clock signal line CLK3 serves as the second clock signal CK2 received by the (j+2)th stage shift register unit 10. The clock signal transmitted via the first clock signal line CLK1 serves as the third clock signal CK3 received by the (j+2)th stage shift register unit 10.

[0185] For example, as shown in Figure 19, the first clock signal line CLK1, the second clock signal line CLK2, and the third clock signal line CLK3 sequentially transmit low-level signals.

[0186] In this embodiment, the driving circuit 01 can be connected to only three clock signal lines to meet the clock signal requirements of each shift register unit 10. On the one hand, this reduces the number of clock signal lines connected to the driving circuit 01, saving energy. On the other hand, it makes the load of clock signal transmission on the first clock signal line CLK1, the second clock signal line CLK2, and the third clock signal line CLK3 more balanced, which helps to reduce the signal output difference of the shift register units caused by the uneven load of the clock signal lines.

[0187] Figure 21 is a connection diagram of another shift register unit provided in an embodiment of this application.

[0188] In another embodiment of this application, as shown in FIG10 and FIG21, the shift register unit 10 is connected to multiple clock signal lines. In the j-th stage shift register unit 10, the control terminals of the first input module 13 and the second input module 16 are electrically connected to the first clock signal line CLK1, the input terminal of the fourth output unit 1212 is electrically connected to the second clock signal line CLK2, and the input terminal of the sixth output unit 1222 is electrically connected to the third clock signal line CLK3.

[0189] Specifically, the clock signal transmitted via the first clock signal line CLK1 serves as the first clock signal CK1 received by the j-th stage shift register unit 10. The clock signal transmitted via the second clock signal line CLK2 serves as the second clock signal CK2 received by the j-th stage shift register unit 10. The clock signal transmitted via the third clock signal line CLK3 serves as the third clock signal CK3 received by the j-th stage shift register unit 10.

[0190] In the (j+1)th level shift register unit 10, the control terminals of the first input module 13 and the second input module 16 are electrically connected to the third clock signal line CLK3, the input terminal of the fourth output unit 1212 is electrically connected to the fourth clock signal line CLK4, and the input terminal of the sixth output unit 1222 is electrically connected to the fifth clock signal line CLK5.

[0191] Specifically, the clock signal transmitted via the third clock signal line CLK3 serves as the first clock signal CK1 received by the (j+1)th stage shift register unit 10. The clock signal transmitted via the fourth clock signal line CLK4 serves as the second clock signal CK2 received by the (j+1)th stage shift register unit 10. The clock signal transmitted via the fifth clock signal line CLK5 serves as the third clock signal CK3 received by the (j+1)th stage shift register unit 10.

[0192] In the (j+2)th level shift register unit 10, the control terminals of the first input module 13 and the second input module 16 are electrically connected to the fifth clock signal line CLK5, the input terminal of the fourth output unit 1212 is electrically connected to the first clock signal line CLK1, and the input terminal of the sixth output unit 1222 is electrically connected to the second clock signal line CLK2.

[0193] Specifically, the clock signal transmitted via the fifth clock signal line CLK5 serves as the first clock signal CK1 received by the (j+2)th stage shift register unit 10. The clock signal transmitted via the first clock signal line CLK1 serves as the second clock signal CK2 received by the (j+2)th stage shift register unit 10. The clock signal transmitted via the second clock signal line CLK2 serves as the third clock signal CK3 received by the (j+2)th stage shift register unit 10.

[0194] In the (j+3)th level shift register unit 10, the control terminals of the first input module 13 and the second input module 16 are electrically connected to the second clock signal line CLK2, the input terminal of the fourth output unit 1212 is electrically connected to the third clock signal line CLK3, and the input terminal of the sixth output unit 1222 is electrically connected to the fourth clock signal line CLK4.

[0195] Specifically, the clock signal transmitted via the second clock signal line CLK2 serves as the first clock signal CK1 received by the (j+3)th stage shift register unit 10. The clock signal transmitted via the third clock signal line CLK3 serves as the second clock signal CK2 received by the (j+3)th stage shift register unit 10. The clock signal transmitted via the fourth clock signal line CLK4 serves as the third clock signal CK3 received by the (j+3)th stage shift register unit 10.

[0196] In the (j+4)th level shift register unit 10, the control terminals of the first input module 13 and the second input module 16 are electrically connected to the fourth clock signal line CLK4, the input terminal of the fourth output unit 1212 is electrically connected to the fifth clock signal line CLK5, and the input terminal of the sixth output unit 1222 is electrically connected to the first clock signal line CLK1. j≥1.

[0197] Specifically, the clock signal transmitted via the fourth clock signal line CLK4 serves as the first clock signal CK1 received by the (j+4)th stage shift register unit 10. The clock signal transmitted via the fifth clock signal line CLK5 serves as the second clock signal CK2 received by the (j+4)th stage shift register unit 10. The clock signal transmitted via the first clock signal line CLK1 serves as the third clock signal CK3 received by the (j+4)th stage shift register unit 10.

[0198] For example, as shown in FIG22, FIG22 is a timing diagram of another clock signal line provided in an embodiment of the present application, wherein the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, the fourth clock signal line CLK4 and the fifth clock signal line CLK5 transmit low-level signals in sequence.

[0199] In this embodiment, the driving circuit 01 can be connected to only five clock signal lines. While ensuring that the number of clock signal lines connected to the driving circuit 01 is small, the load of the clock signal transmitted by the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, the fourth clock signal line CLK4, and the fifth clock signal line CLK5 is more balanced, which helps to reduce the signal output difference of the shift register unit caused by the unbalanced load of the clock signal lines.

[0200] Figure 23 is a connection diagram of another shift register unit provided in the embodiment of this application, and Figure 24 is a timing diagram of the output signals of each first type of signal output module in the multiple shift register units shown in Figure 23.

[0201] In one embodiment of this application, as shown in Figures 8 and 10-16, the gating module 15 is electrically connected to the gating signal line CTRL, and the gating module 15 also transmits a control signal to the first output unit 111 in response to the signal on the gating signal line CTRL.

[0202] For example, as shown in Figures 8 and 10, the first terminal of the seventeenth transistor T17 in the gating module 15 is electrically connected to the gating signal line CTRL, and the seventeenth transistor T17 can transmit the signal on the gating signal line CTRL to the control terminal of the first output unit 111.

[0203] Referring to Figures 23 and 24, the driving circuit 01 is electrically connected to at least two gating signal lines CTRL, which include a first gating signal line CTRL1 and a second gating signal line CTRL2. The cascaded multiple shift register units 10 include a first-region shift register unit 101, a second-region shift register unit 102, and a third-region shift register unit 103, with the second-region shift register unit 102 located between the first-region shift register unit 101 and the third-region shift register unit 103. The first-region shift register unit 101, the second-region shift register unit 102, and the third-region shift register unit 103 can sequentially output scan signals.

[0204] The first shift register unit 101 and the third shift register unit 103 are both electrically connected to the first strobe signal line CTRL1, and the second shift register unit 102 is electrically connected to the second strobe signal line CTRL2.

[0205] The first-level shift register unit 101 includes a final-level shift register unit 101B, which is a first-level shift register unit in the first-level shift register unit 101 that is closest to the second-level shift register unit 102. The third-level shift register unit 103 includes a first-level shift register unit 103A, which is a first-level shift register unit in the third-level shift register unit 103 that is closest to the second-level shift register unit 102.

[0206] During one operating cycle of the driving circuit 01, in the final stage shift register unit 101B of the first zone shift register unit 101, the enable signal output by the output terminal SN_OUT of the first type of signal output module 11 is the first enable signal XH1. In the first stage shift register unit 103A of the third zone shift register unit 103, the enable signal output by the output terminal SN_OUT of the first type of signal output module 11 is the second enable signal XH2.

[0207] It should be noted that within one operating cycle of the driving circuit 01, when the output terminal SN_OUT of the first type of signal output module 11 outputs multiple enable signals consecutively, in the final stage shift register unit 101B of the first zone shift register unit 101, the last enable signal output by the output terminal SN_OUT of the first type of signal output module 11 is the first enable signal XH1. In the first stage shift register unit 103A of the third zone shift register unit 103, the first enable signal output by the output terminal SN_OUT of the first type of signal output module 11 is the second enable signal XH2.

[0208] Specifically, the second enable signal XH2 is output after the first enable signal XH1 has finished outputting. There is a gap N between the start time of the second enable signal XH2 and the end time of the first enable signal XH1.

[0209] In other words, in the first-zone shift register unit 101 and the third-zone shift register unit 103 that are electrically connected to the same first strobe signal line CTRL1, there is a gap N between the last enable signal output by the first-zone shift register unit 101 and the first enable signal output by the third-zone shift register unit 103.

[0210] In this embodiment, the signal on the first strobe signal line CTRL1 can be set to change during the time interval N. While realizing the partition control of the first zone shift register unit 101 and the third zone shift register unit 101, and thus realizing the partition refresh of the display panel 100, it can avoid the situation where the output signal of the first type of signal output module 11 in the first zone shift register unit 101 and the third zone shift register unit 101 is incomplete, which is beneficial to improving the picture quality of the partition display of the display panel 100.

[0211] For example, as shown in Figure 25, which is another timing diagram of the output signals of each first-type signal output module in the multiple shift register units shown in Figure 23, within one working cycle of the driving circuit 01, the second strobe signal line CTRL2 transmits a low-level signal, and the first strobe signal line CTRL1 first transmits a low-level signal and then a high-level signal. During the time interval N, the signal on the first strobe signal line CTRL1 changes from low to high. In this way, while each first-type signal output module 11 in the first-zone shift register unit 101 fully outputs the enable signal, the first-type signal output module 11 in the third-zone shift register unit 101 is controlled to no longer output the enable signal, thereby realizing the partition refresh of the display panel 100.

[0212] It should be noted that, in the aforementioned embodiments, the gating module 15 includes the structure of the sixteenth transistor T16, the seventeenth transistor T17 and the eighteenth transistor T18, as shown in Figures 12-16 as a shift register unit. The driving circuit 01 can also connect only one gating signal line CTRL to achieve partition refresh of the display panel 100.

[0213] Taking the shift register unit 10 shown in Figure 12 as an example, when the signal on the strobe signal line CTRL changes from low to high, if the first type of signal output module 11 in a certain shift register unit is outputting a high-level signal, as can be seen from the aforementioned signal output process of the shift register, at this time the second node N2 is high, the eighteenth transistor T18 is off, and the high-level signal on the strobe signal line CTRL will not be written to the third node N3. Only after the first type of signal output module 11 in that shift register unit completes its high-level output and changes back to low will the high-level signal on the strobe signal line CTRL be written to the third node N3. This prevents the output signal SN_OUT of the first type of signal output module 11 in each shift register unit 10 from being incomplete.

[0214] Figure 26 is a schematic diagram of another shift register unit provided in an embodiment of this application.

[0215] In one embodiment of this application, as shown in FIG26, the second type of signal output module 12 includes a first scan signal output module 121 and a second scan signal output module 122, which can be electrically connected to pixel circuits 02 in different rows.

[0216] The first scan signal output module 121 includes a third output unit 1211 and a fourth output unit 1212. The input terminal of the third output unit 1211 receives a first fixed potential signal VGH, the output terminal is electrically connected to the output terminal SP1_OUT of the first scan signal output module 121, and the control terminal is electrically connected to the second node N2. The input terminal of the fourth output unit 1212 receives a second clock signal CK2, and the output terminal is electrically connected to the output terminal SP1_OUT of the first scan signal output module 121.

[0217] The second scan signal output module 122 includes a fifth output unit 1221 and a sixth output unit 1222. The input terminal of the fifth output unit 1221 receives a first fixed potential signal VGH, its output terminal is electrically connected to the output terminal SP2_OUT of the second scan signal output module 122, and its control terminal is electrically connected to the second node N2. The input terminal of the sixth output unit 1222 receives a third clock signal CK3, and its output terminal is electrically connected to the output terminal SP2_OUT of the second scan signal output module 122.

[0218] The shift register unit 10 also includes a second input module 16. The input terminal of the second input module 16 is electrically connected to the second output terminal SN_NEXT of the cascade module 15, and the output terminal is coupled to the control terminal of the fourth output unit 1212 and the control terminal of the sixth output unit 1222. The control terminal receives the first clock signal CK1.

[0219] The difference between the shift register circuit shown in Figure 26 and the shift register circuit shown in Figure 10 is that the input terminal of the second input module 16 is electrically connected to the second output terminal SN_NEXT of the cascade module 15. The second trigger signal SP_IN received by the second input module 16 can be the signal output by the second output terminal SN_NEXT of the cascade module 15.

[0220] As can be seen from the signal output process of the shift register unit 10, in the signal output stage Z of the shift register unit 10, the fourth transistor T4 is turned off, and the signal potential output by the fifth transistor T5 is opposite to the level of the output terminal SN_OUT of the first type of signal output module 11. That is, in the signal output stage Z of the shift register unit 10, the second output terminal SN_NEXT of the cascade module 15 outputs a low-level signal. This is equivalent to the second output terminal SN_NEXT of the cascade module 15 providing a low-level signal to the second input module 16 in the first stage Z1. According to the working process of the second stage Z2, the third stage Z3, and the fourth stage Z4, the potential received by the input terminal of the second input module 16 will not affect the signal output of the output terminal SP1_OUT of the first scan signal output module 121 and the output terminal SP2_OUT of the second scan signal output module 122.

[0221] The embodiments of this application can increase the structural diversity of the shift register unit 10 and help reduce the number of cascade lines between the shift register units 10, thus saving costs.

[0222] Figure 27 is a schematic diagram of another shift register unit provided in an embodiment of this application.

[0223] In one embodiment of this application, as shown in FIG27, the shift register unit 10 further includes a third voltage regulator module 20. The input terminal of the third voltage regulator module receives a first fixed potential signal VGH, the output terminal is electrically connected to the output terminal of the second input module 16, and the control terminal is electrically connected to the second node N2. The third voltage regulator module 20 can transmit a high-level first fixed potential signal VGH to the output terminal of the second input module 16 in response to the potential of the second node N2.

[0224] For example, as shown in Figure 27, the third voltage regulator module 20 includes a transistor Tx. The first terminal of the transistor Tx receives a first fixed potential signal VGH, the second terminal is electrically connected to the output terminal of the second input module 16, and the gate is electrically connected to the second node N3. The transistor Tx is a P-type transistor.

[0225] In this embodiment, during the period when the output terminal of the second input module 16 outputs a high level, the third voltage regulator module 20 can be controlled to turn on, so that the third voltage regulator module 20 transmits the high-level first fixed potential signal VGH to the output terminal of the second input module 16, thereby improving the potential stability of the output terminal of the second input module 16. This can stabilize the control terminals of the fourth output unit 1212 and the sixth output unit 1222 to a high potential, which is beneficial to improve the coupling effect of the second clock signal CK2 on the control terminal of the fourth output unit 1212 and the coupling effect of the third clock signal CK3 on the control terminal of the sixth output unit 1222.

[0226] Figure 28 is a flowchart of a driving method provided in an embodiment of this application.

[0227] This application embodiment also provides a driving method for driving the driving circuit 01 provided in the above embodiments. The circuit structure of the driving circuit 01 can be shown in Figures 8, 10, 12-16, and 26-27. The working process of the driving circuit 01 includes a first type of enable signal output stage and a second type of enable signal output stage, as shown in Figure 28. The driving method includes:

[0228] Step B1: In the first type of enable signal output stage, the first type of signal output module outputs an enable signal.

[0229] Step B2: In the second type of enable signal output stage, the second type of signal output module outputs an enable signal.

[0230] Wherein, the first type of enable signal output stage and the second type of enable signal output stage do not overlap, or the second type of enable signal output stage is located within the first type of enable signal output stage.

[0231] For example, in the driving circuit 01, if the output terminal SN_OUT of the first type of signal output module 11 is only electrically connected to the gate reset transistor M1 in the pixel circuit 02, then in one working cycle of the driving circuit 01, the first type of enable signal output stage and the second type of enable signal output stage can be non-overlapping. The driving circuit 01 can first drive the pixel circuit 02 to complete the gate reset operation of the driving transistor Md, and then drive the pixel circuit 02 to perform the data signal writing operation.

[0232] If the output terminal SN_OUT of the first type signal output module 11 is only electrically connected to the threshold grabbing transistor M3 in the pixel circuit 02, then in one working cycle of the driving circuit 01, the second type enable signal output stage can be located within the first type enable signal output stage. When the driving circuit 01 drives the data writing transistor M2 in the pixel circuit 02 to turn on, it simultaneously drives the threshold grabbing transistor M3 to turn on, so as to ensure that the data signal can be written to the gate of the driving transistor Md.

[0233] Furthermore, if the output terminal SN_OUT of the first type of signal output module 11 is electrically connected to both the gate reset transistor M1 and the threshold grabbing transistor M3 in the pixel circuit 02, then the driving circuit 01 may include multiple first type of enable signal output stages. In one operating cycle of the driving circuit 01, some first type of enable signal output stages do not overlap with second type of enable signal output stages to ensure that the driving pixel circuit 02 completes the gate reset operation of the driving transistor Md. Some first type of enable signal output stages include second type of enable signal output stages to ensure that the driving pixel circuit 02 completes the data signal writing operation.

[0234] In this embodiment, at least one of the gate reset transistor M1 and the threshold grabbing transistor M3 in the pixel circuit 02 is electrically connected to the same driving circuit 01 as the data writing transistor M2. That is, the driving circuit 01 can simultaneously drive at least one of the gate reset transistor M1 and the threshold grabbing transistor M3 in the pixel circuit 02, as well as the data writing transistor M2. This reduces the number of peripheral driving circuits required for the pixel circuit 02. When the driving circuit 01 and the pixel circuit 02 are applied in the display panel 100, it is beneficial to reduce the area occupied by the peripheral driving circuits, thereby facilitating the achievement of a narrow bezel in the display panel 100.

[0235] Furthermore, reducing the number of peripheral driving circuits required for the pixel circuit 02 can also reduce the number of clock signals required for the peripheral driving circuits, which is beneficial for reducing the power consumption of the display panel 100.

[0236] In one embodiment of this application, as shown in Figures 8, 10, 12-16, and 26-27, the second type of signal output module 12 includes a first scan signal output module 121 and a second scan signal output module 122. The first scan signal output module 121 and the second scan signal output module 122 are electrically connected to the gates of data writing transistors M2 in different row pixel circuits 02, respectively. The second type of enable signal output stage includes a first sub-stage and a second sub-stage. The second type of signal output module outputs an enable signal, including:

[0237] Step B21: In the first sub-stage, the first scan signal output module 121 outputs an enable signal.

[0238] Step B22: In the second sub-stage, the second scan signal output module 122 outputs an enable signal.

[0239] The first sub-phase and the second sub-phase are carried out sequentially.

[0240] For example, the first sub-stage and the second sub-stage do not overlap. In this embodiment, the first sub-stage can be the second stage Z2 in Figure 17, and the second sub-stage can be the third stage Z3 in Figure 17.

[0241] In this embodiment of the application, the same shift register unit 10 is set to drive two rows of pixel circuits 02, which can reduce the number of shift register units 10 in the driving circuit 01. While implementing the driving pixel circuit 02, it is beneficial to further reduce the area occupied by the driving circuit 01, thereby further reducing the bezel of the display panel 100.

[0242] As shown in Figures 1 and 4, this application embodiment also provides a display panel 100, which includes the driving circuit 01 provided in the above embodiments. Exemplarily, the display panel 100 can be any one of an organic light-emitting diode (OLED) display panel, a micro-light-emitting diode (Micro-LED) display panel, or a mini-LED display panel; this application does not specifically limit it.

[0243] In the display panel 100, the driving circuit 01 can simultaneously drive at least one of the gate reset transistor M1 and the threshold grabbing transistor M3 in the pixel circuit 02, as well as the data writing transistor M2. This reduces the number of peripheral driving circuits required for the pixel circuit 02. It helps to reduce the area occupied by the peripheral driving circuits, thereby facilitating the achievement of a narrow bezel in the display panel 100.

[0244] Furthermore, reducing the number of peripheral driving circuits required for the pixel circuit 02 can also reduce the number of clock signals required for the peripheral driving circuits, which is beneficial for reducing the power consumption of the display panel 100.

[0245] Figure 29 is a schematic diagram of a display device provided in an embodiment of this application.

[0246] This application also provides a display device 200, as shown in FIG29. The display device 200 includes the display panel 100 as provided in the above embodiments. Exemplarily, the display device 200 can be an electronic device such as a mobile phone, computer, television, vehicle display, or wearable display, and this application does not specifically limit it.

[0247] In the display device 200, by configuring at least one of the gate reset transistor M1 and the threshold grabbing transistor M3 in the pixel circuit 02 to be electrically connected to the same driving circuit 01 as the data writing transistor M2, the number of sets of peripheral driving circuits required for the pixel circuit 02 can be reduced. This helps to reduce the area occupied by the peripheral driving circuits, thereby facilitating the achievement of a narrow bezel in the display panel 100.

[0248] Furthermore, reducing the number of peripheral driving circuits required for the pixel circuit 02 can also reduce the number of clock signals required for the peripheral driving circuits, which is beneficial for reducing the power consumption of the display device 200.

[0249] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A driving circuit, characterized in that, For driving pixel circuits, the pixel circuits include driving transistors and gate reset transistors, data write transistors, and threshold grabbing transistors electrically connected to the driving transistors; The driving circuit includes multiple cascaded shift register units, each of which includes a first type of signal output module and a second type of signal output module. The output terminal of the first type of signal output module is electrically connected to the gate of the gate reset transistor and / or the threshold grab transistor, and the output terminal of the second type of signal output module is electrically connected to the gate of the data write transistor.

2. The driving circuit according to claim 1, characterized in that, The second type of signal output module includes a first scan signal output module and a second scan signal output module, wherein the first scan signal output module and the second scan signal output module are electrically connected to the gates of the data writing transistors in different row pixel circuits, respectively.

3. The driving circuit according to claim 2, characterized in that, The output terminal of the first scan signal output module is electrically connected to the pixel circuit in the i-th row, and the output terminal of the second scan signal output module is electrically connected to the pixel circuit in the (i+1)-th row; i≥1.

4. The driving circuit according to claim 2, characterized in that, The output terminal of the first type of signal output module is electrically connected to at least two rows of pixel circuits.

5. The driving circuit according to claim 1, characterized in that, The first type of signal output module includes a first output unit and a second output unit. The input terminal of the first output unit receives a first fixed potential signal, and its output terminal is electrically connected to the output terminal of the first type of signal output module. The input terminal of the second output unit receives a second fixed potential signal, and its output terminal is electrically connected to the output terminal of the first type of signal output module. The shift register unit further includes a first input module, a transmission module, and a gating module. The input terminal of the first input module receives a first trigger signal, the output terminal is electrically connected to the first node, and the control terminal receives a first clock signal. The cascading module is electrically connected to the first node. The first output terminal of the cascading module is electrically connected to the second node, and the second output terminal is electrically connected to the gating module and the second output unit. The first output terminal of the cascading module transmits a control signal to the second node in response to the potential of the first node, and the second output terminal of the cascading module transmits a control signal to the gating module and the second output unit in response to the potential of the second node. The gating module is electrically connected to the second node, and the output terminal of the gating module is electrically connected to the first output unit. The gating module transmits a control signal to the first output unit in response to the potential of the second node and the second output terminal of the cascade module.

6. The driving circuit according to claim 5, characterized in that, The transmission module includes a first module and a second module. The first module receives the first fixed potential signal at its first input terminal, receives the second fixed potential signal at its second input terminal, is electrically connected to the second node at its output terminal, and is electrically connected to the first node at its control terminal. The second module has a first input terminal receiving the first fixed potential signal, a second input terminal receiving the second fixed potential signal, an output terminal electrically connected to the second output terminal of the cascade module, and a control terminal electrically connected to the second node.

7. The driving circuit according to claim 5, characterized in that, The second type of signal output module includes a first scan signal output module and a second scan signal output module. The first scan signal output module includes a third output unit and a fourth output unit. The input terminal of the third output unit receives the first fixed potential signal, the output terminal is electrically connected to the output terminal of the first scan signal output module, and the control terminal is electrically connected to the second node. The input terminal of the fourth output unit receives the second clock signal, and the output terminal is electrically connected to the output terminal of the first scan signal output module. The second scan signal output module includes a fifth output unit and a sixth output unit. The input terminal of the fifth output unit receives the first fixed potential signal, the output terminal is electrically connected to the output terminal of the second scan signal output module, and the control terminal is electrically connected to the second node. The input terminal of the sixth output unit receives a third clock signal, and the output terminal is electrically connected to the output terminal of the second scan signal output module. The shift register unit further includes a second input module, the input terminal of which receives a second trigger signal, the output terminal of which is coupled to the control terminal of the fourth output unit and the control terminal of the sixth output unit, and the control terminal receives the first clock signal.

8. The driving circuit according to claim 7, characterized in that, The output terminal of the second input module includes a first voltage regulator module between it and the fourth output unit, and a second voltage regulator module between it and the sixth output unit. The control terminals of the first voltage regulator module and the second voltage regulator module both receive a fixed potential signal.

9. The driving circuit according to claim 5, characterized in that, The shift register unit further includes a reset module, wherein the input terminal of the reset module receives the first fixed potential signal, the output terminal is electrically connected to the first node, and the control terminal is electrically connected to the reset signal line.

10. The driving circuit according to claim 7, characterized in that, The cascaded shift register units include a j-th stage shift register unit and a (j+1)-th stage shift register unit. The second output terminal of the cascade module in the j-th stage shift register unit is electrically connected to the input terminal of the first input module in the (j+1)-th stage shift register unit. The output terminal of the second scan signal output module in the j-th stage shift register unit is electrically connected to the input terminal of the second input module in the (j+1)-th stage shift register unit, where j≥1.

11. The driving circuit according to claim 5, characterized in that, The first input module includes a first transistor, wherein the first terminal of the first transistor receives the first trigger signal, the second terminal is electrically connected to the first node, and the gate receives the first clock signal.

12. The driving circuit according to claim 6, characterized in that, The first module includes a second transistor and a third transistor. The first terminal of the second transistor receives the first fixed potential signal, the second terminal is electrically connected to the second node, and the gate is electrically connected to the first node. The first terminal of the third transistor receives the second fixed potential signal, the second terminal is electrically connected to the second node, and the gate is electrically connected to the first node. The third transistor has a different channel type than the second transistor. The second module includes a fourth transistor and a fifth transistor. The first terminal of the fourth transistor receives the first fixed potential signal, the second terminal is electrically connected to the output terminal of the second module, and the gate is electrically connected to the second node. The fourth transistor and the second transistor have the same channel type. The first terminal of the fifth transistor receives the second fixed potential signal, the second terminal is electrically connected to the output terminal of the second module, and the gate is electrically connected to the second node. The fifth transistor has the same channel type as the third transistor.

13. The driving circuit according to claim 7, characterized in that, The first output unit includes a sixth transistor, wherein the first terminal of the sixth transistor receives the first fixed potential signal, the second terminal is electrically connected to the output terminal of the first output unit, and the gate is electrically connected to the output terminal of the gating module; the second output unit includes a seventh transistor, wherein the first terminal of the seventh transistor receives the second fixed potential signal, the second terminal is electrically connected to the output terminal of the second output unit, and the gate is electrically connected to the second output terminal of the cascade module; the sixth transistor and the seventh transistor have different channel types; The third output unit includes an eighth transistor, the first terminal of which receives the first fixed potential signal, the second terminal of which is electrically connected to the output terminal of the third output unit, and the gate of which is electrically connected to the second node; the fourth output unit includes a ninth transistor, the first terminal of which receives the second clock signal, the second terminal of which is electrically connected to the output terminal of the fourth output unit, and the gate of which is electrically connected to the output terminal of the second input module, and the channel type of the eighth transistor is the same as that of the ninth transistor; The fifth output unit includes a tenth transistor, the first terminal of which receives the first fixed potential signal, the second terminal of which is electrically connected to the output terminal of the fifth output unit, and the gate of which is electrically connected to the second node; the sixth output unit includes an eleventh transistor, the first terminal of which receives the third clock signal, the second terminal of which is electrically connected to the output terminal of the sixth output unit, and the gate of which is electrically connected to the output terminal of the second input module, and the channel type of the tenth transistor is the same as that of the eleventh transistor.

14. The driving circuit according to claim 7, characterized in that, The second input module includes a twelfth transistor, wherein the first terminal of the twelfth transistor receives the second trigger signal, the second terminal is electrically connected to the output terminal of the second input module, and the gate receives the first clock signal.

15. The driving circuit according to claim 8, characterized in that, The first voltage regulator module includes a thirteenth transistor, the first terminal of which is electrically connected to the output terminal of the second input module, the second terminal of which is electrically connected to the control terminal of the fourth output unit, and the gate of which receives the second fixed potential signal; the second voltage regulator module includes a fourteenth transistor, the first terminal of which is electrically connected to the output terminal of the second input module, the second terminal of which is electrically connected to the control terminal of the sixth output unit, and the gate of which receives the second fixed potential signal.

16. The driving circuit according to claim 9, characterized in that, The reset module includes a fifteenth transistor, wherein the first electrode of the fifteenth transistor receives the first fixed potential signal, the second electrode is electrically connected to the first node, and the gate is electrically connected to the reset signal line.

17. The driving circuit according to claim 5, characterized in that, The gating module includes a sixteenth transistor and a seventeenth transistor. The first terminal of the sixteenth transistor receives the first fixed potential, the second terminal is electrically connected to the control terminal of the first output unit, and the gate is electrically connected to the second node. The first terminal of the seventeenth transistor is electrically connected to the gating signal line, the second terminal is electrically connected to the control terminal of the first output unit, and the gate is electrically connected to the second output terminal of the cascade module.

18. The driving circuit according to claim 5, characterized in that, The gating module includes a sixteenth transistor, a seventeenth transistor, and an eighteenth transistor. The first terminal of the sixteenth transistor receives the first fixed potential signal, the second terminal is electrically connected to the control terminal of the first output unit, and the gate is electrically connected to the second node. The first terminal of the seventeenth transistor is electrically connected to the third node, the second terminal is electrically connected to the control terminal of the first output unit, and the gate is electrically connected to the second output terminal of the cascade module. The first terminal of the eighteenth transistor is electrically connected to the gating signal line, the second terminal is electrically connected to the third node, and the gate is electrically connected to the second node.

19. The driving circuit according to claim 5, characterized in that, The gating module includes a sixteenth transistor, a seventeenth transistor, and an eighteenth transistor. The first terminal of the sixteenth transistor receives the first fixed potential, the second terminal is electrically connected to the control terminal of the first output unit, and the gate is electrically connected to the third node. The first terminal of the seventeenth transistor is electrically connected to the second output terminal of the cascade module, the second terminal is electrically connected to the control terminal of the first output unit, and the gate is electrically connected to the third node. The first terminal of the eighteenth transistor is electrically connected to the gating signal line, the second terminal is electrically connected to the third node, and the gate is electrically connected to the second node. The sixteenth transistor has a different channel type than the seventeenth transistor, and the sixteenth transistor has the same channel type as the eighteenth transistor.

20. The driving circuit according to claim 5, characterized in that, The gating module includes a sixteenth transistor, a seventeenth transistor, and an eighteenth transistor. The first terminal of the sixteenth transistor is electrically connected to the second output terminal of the cascade module, the second terminal is electrically connected to the control terminal of the first output unit, and the gate is electrically connected to the third node. The first terminal of the seventeenth transistor receives the first fixed potential signal, the second terminal is electrically connected to the control terminal of the first output unit, and the gate is electrically connected to the third node. The first terminal of the eighteenth transistor is electrically connected to the gating signal line, the second terminal is electrically connected to the third node, and the gate is electrically connected to the second node. The sixteenth transistor has a different channel type than the seventeenth transistor, and the sixteenth transistor has the same channel type as the eighteenth transistor.

21. The driving circuit according to claim 5, characterized in that, The gating module includes a sixteenth transistor, a seventeenth transistor, and an eighteenth transistor. The first terminal of the sixteenth transistor receives the first fixed potential, the second terminal is electrically connected to the control terminal of the first output unit, and the gate is electrically connected to the second output terminal of the cascade module. The first terminal of the seventeenth transistor is electrically connected to the third node, the second terminal is electrically connected to the control terminal of the first output unit, and the gate is electrically connected to the second output terminal of the cascade module. The first terminal of the eighteenth transistor is electrically connected to the gating signal line, the second terminal is electrically connected to the third node, and the gate is electrically connected to the second node. The sixteenth transistor has a different channel type than the seventeenth transistor, and the sixteenth transistor has a different channel type than the eighteenth transistor.

22. The driving circuit according to any one of claims 18-21, characterized in that, The gating module also includes a first capacitor, one plate of which is electrically connected to the third node, and the other plate receives a fixed potential signal.

23. The driving circuit according to any one of claims 18-21, characterized in that, The gating module includes a first inverter and a second inverter. The input terminal of the first inverter is electrically connected to the output terminal of the second inverter and the third node, and the output terminal is electrically connected to the input terminal of the second inverter.

24. The driving circuit according to claim 7, characterized in that, The shift register unit further includes a second capacitor, a third capacitor, and a fourth capacitor. One plate of the second capacitor is electrically connected to the output terminal of the fourth output unit, and the other plate is electrically connected to the control terminal of the fourth output unit. One plate of the third capacitor is electrically connected to the output terminal of the sixth output unit, and the other plate is electrically connected to the control terminal of the sixth output unit; one plate of the fourth capacitor is electrically connected to the first node, and the other plate receives a fixed potential signal.

25. The driving circuit according to claim 7, characterized in that, In the odd-level shift register unit, the control terminals of the first input module and the second input module are both electrically connected to the first clock signal line, the input terminal of the fourth output unit is electrically connected to the second clock signal line, and the input terminal of the sixth output unit is electrically connected to the third clock signal line. In the even-level shift register unit, the control terminals of the first input module and the second input module are both electrically connected to the third clock signal line, the input terminal of the fourth output unit is electrically connected to the fourth clock signal line, and the input terminal of the sixth output unit is electrically connected to the first clock signal line.

26. The driving circuit according to claim 7, characterized in that, In the j-th level shift register unit, the control terminals of the first input module and the second input module are both electrically connected to the first clock signal line, the input terminal of the fourth output unit is electrically connected to the second clock signal line, and the input terminal of the sixth output unit is electrically connected to the third clock signal line. In the (j+1)th level shift register unit, the control terminals of the first input module and the second input module are both electrically connected to the third clock signal line, the input terminal of the fourth output unit is electrically connected to the first clock signal line, and the input terminal of the sixth output unit is electrically connected to the second clock signal line. In the (j+2)th level shift register unit, the control terminals of the first input module and the second input module are both electrically connected to the second clock signal line, the input terminal of the fourth output unit is electrically connected to the third clock signal line, and the input terminal of the sixth output unit is electrically connected to the first clock signal line; j≥1.

27. The driving circuit according to claim 7, characterized in that, In the j-th level shift register unit, the control terminals of the first input module and the second input module are both electrically connected to the first clock signal line, the input terminal of the fourth output unit is electrically connected to the second clock signal line, and the input terminal of the sixth output unit is electrically connected to the third clock signal line. In the (j+1)th level shift register unit, the control terminals of the first input module and the second input module are both electrically connected to the third clock signal line, the input terminal of the fourth output unit is electrically connected to the fourth clock signal line, and the input terminal of the sixth output unit is electrically connected to the fifth clock signal line. In the (j+2)th level shift register unit, the control terminals of the first input module and the second input module are both electrically connected to the fifth clock signal line, the input terminal of the fourth output unit is electrically connected to the first clock signal line, and the input terminal of the sixth output unit is electrically connected to the second clock signal line. In the (j+3)th level shift register unit, the control terminals of the first input module and the second input module are both electrically connected to the second clock signal line, the input terminal of the fourth output unit is electrically connected to the third clock signal line, and the input terminal of the sixth output unit is electrically connected to the fourth clock signal line. In the (j+4)th level shift register unit, the control terminals of the first input module and the second input module are both electrically connected to the fourth clock signal line, the input terminal of the fourth output unit is electrically connected to the fifth clock signal line, and the input terminal of the sixth output unit is electrically connected to the first clock signal line; j≥1.

28. The driving circuit according to claim 5, characterized in that, The gating module is electrically connected to the gating signal line, and the gating module also transmits a control signal to the first output unit in response to the signal on the gating signal line. The driving circuit is electrically connected to at least two gating signal lines, including a first gating signal line and a second gating signal line. The cascaded multiple shift register units include a first-area shift register unit, a second-area shift register unit, and a third-area shift register unit. The second-area shift register unit is located between the first-area shift register unit and the third-area shift register unit. Both the first-area shift register unit and the third-area shift register unit are electrically connected to the first gating signal line, and the second-area shift register unit is electrically connected to the second gating signal line. During one working cycle of the driving circuit, in the last stage shift register of the first region shift register unit, the enable signal output by the output terminal of the first type of signal output module is the first enable signal, and in the first stage shift register of the third region shift register unit, the enable signal output by the output terminal of the first type of signal output module is the second enable signal. The second enable signal is output after the first enable signal output ends.

29. The driving circuit according to claim 5, characterized in that, The second type of signal output module includes a first scan signal output module and a second scan signal output module. The first scan signal output module includes a third output unit and a fourth output unit. The input terminal of the third output unit receives the first fixed potential signal, the output terminal is electrically connected to the output terminal of the first scan signal output module, and the control terminal is electrically connected to the second node. The input terminal of the fourth output unit receives the second clock signal, and the output terminal is electrically connected to the output terminal of the first scan signal output module. The second scan signal output module includes a fifth output unit and a sixth output unit. The input terminal of the fifth output unit receives the first fixed potential signal, the output terminal is electrically connected to the output terminal of the second scan signal output module, and the control terminal is electrically connected to the second node. The input terminal of the sixth output unit receives a third clock signal, and the output terminal is electrically connected to the output terminal of the second scan signal output module. The shift register unit further includes a second input module, the input terminal of which is electrically connected to the second output terminal of the cascade module, the output terminal of which is coupled to the control terminal of the fourth output unit and the control terminal of the sixth output unit, and the control terminal receives the first clock signal.

30. The driving circuit according to claim 7 or 29, characterized in that, The shift register unit further includes a third voltage regulator module, the input terminal of which receives the first fixed potential signal, the output terminal of which is electrically connected to the output terminal of the second input module, and the control terminal of which is electrically connected to the second node.

31. A driving method for a driving circuit, characterized in that, The method is used to drive the driving circuit as described in any one of claims 1-30, wherein the operation of the driving circuit includes a first type of enable signal output stage and a second type of enable signal output stage, and the driving method includes: During the first type of enable signal output phase, the first type of signal output module outputs an enable signal; During the second type of enable signal output phase, the second type of signal output module outputs an enable signal; Wherein, the first type of enable signal output stage and the second type of enable signal output stage do not overlap, or the second type of enable signal output stage is located within the first type of enable signal output stage.

32. The driving method according to claim 31, characterized in that, The second type of signal output module includes a first scan signal output module and a second scan signal output module, wherein the first scan signal output module and the second scan signal output module are respectively electrically connected to the gate of the data writing transistor in different row pixel circuits; The second type of enable signal output stage includes a first sub-stage and a second sub-stage. The second type of signal output module outputs an enable signal, including: In the first sub-stage, the first scan signal output module outputs an enable signal; In the second sub-stage, the second scan signal output module outputs an enable signal; The first sub-stage and the second sub-stage are performed sequentially.

33. A display panel, characterized in that, Includes the driving circuit as described in any one of claims 1-30.

34. A display device, characterized in that, Includes the display panel as described in claim 33.

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