Phototransistor of CMOS image sensor, and phototransistor unit

Abstract

The embodiments of the present invention relate to a phototransistor of a CMOS image sensor, and a phototransistor unit. An epitaxial structure of the phototransistor comprises: a substrate, a collector layer, a first base layer, a second base layer, an emitter layer and a heavily doped layer, wherein the collector layer is arranged on the substrate, the thickness of the collector layer ranging from 100 nm to 1000 nm, and the doping concentration of the collector layer ranging from 5×1013 / cm3 to 1×1016 / cm3; the first base layer is arranged on the collector layer, the doping type of the first base layer being opposite to that of the collector layer; the second base layer is arranged on the first base layer; the emitter layer is arranged on the second base layer, the doping type of the emitter layer being the same as that of the collector layer; the heavily doped layer is arranged on the emitter layer, the doping type of the heavily doped layer being the same as that of the emitter layer; and under an externally applied voltage of less than 6V, the average electric field strength inside the collector layer of the phototransistor ranges from 5×104V / cm to 3×105V / cm.

Description

A phototransistor and phototransistor unit for a CMOS image sensor

[0001] This application claims priority to Chinese Patent Application No. 2024117059010, filed on November 26, 2024, entitled "A phototransistor and phototransistor unit for a CMOS image sensor". Technical Field

[0002] This invention relates to the field of semiconductor phototransistors, and more particularly to a phototransistor and phototransistor unit for a CMOS image sensor. Background Technology

[0003] CMOS image sensors utilize photoelectric conversion units to convert incident light signals into processable electrical signals. These electrical signals are then converted into image data for recording and further processing. An ideal CMOS image sensor photoelectric conversion unit requires good output linearity, fast readout speed, and high responsivity.

[0004] Currently, phototransistors are rarely used in image sensors, mainly because it is difficult to achieve both high responsivity and fast readout. When the absorption layer (the width of the depletion region of the collector-base first pn junction) of a phototransistor is thicker than 3 micrometers, achieving a quantum efficiency of over 50% in the visible light range, the phototransistor can generally obtain a responsivity of 1 A / W to 10 A / W. However, the thicker absorption layer leads to a longer readout time, making it difficult to meet the requirements of practical applications.

[0005] The depletion region width of the collector-base first pn junction in a phototransistor is inversely correlated with the cutoff frequency, while the cutoff frequency is positively correlated with the readout speed. Therefore, it is necessary to reduce the depletion region width of the collector-base first pn junction to increase the cutoff frequency, thereby enabling fast readout and high-speed image capture in image sensors. However, based on the balanced absorption theory, reducing the depletion region width of the collector-base first pn junction will decrease the phototransistor's responsivity.

[0006] How to make phototransistors balance high responsiveness and fast readout speed is the key research area that needs to be addressed in phototransistor development. Summary of the Invention

[0007] The purpose of this invention is to address the deficiencies of existing technologies by providing a phototransistor and phototransistor unit for a CMOS image sensor.

[0008] To achieve the above objectives, in a first aspect, the present invention provides a phototransistor for a CMOS image sensor, wherein the epitaxial structure of the phototransistor includes: a substrate, a collector layer, a first base layer, a second base layer, an emitter layer, and a highly doped layer;

[0009] The current collector layer is disposed on the substrate, and the thickness of the current collector layer is 100nm-1000nm, with a doping concentration of 5×10⁻⁶. 13 / cm 3 -1×10 16 / cm 3 ;

[0010] The first base layer is disposed on the collector layer, and the doping type of the first base layer is opposite to that of the collector layer.

[0011] The second base layer is disposed on the first base layer, and the doping type of the second base layer is the same as that of the first base layer;

[0012] The emitter layer is disposed on the second base layer, and the doping type of the emitter layer is the same as the doping type of the collector layer;

[0013] The highly doped layer is disposed on the emitter layer, and the doping type of the highly doped layer is the same as that of the emitter layer; wherein the doping concentration of the highly doped layer is greater than that of the emitter layer.

[0014] Under an applied voltage of less than 6V, the average electric field strength inside the collector layer of the phototransistor is 5×10⁻⁶. 4 V / cm-3×10 5 V / cm.

[0015] Preferably, the epitaxial structure of the phototransistor further includes a transition layer; the transition layer is disposed between the substrate and the collector layer; the thickness of the transition layer is 0 nm-500 nm, and the doping method is unintentional doping or low-concentration doping, wherein the low-concentration doping concentration is 1 × 10⁻⁶. 13 / cm 3 -1×10 15 / cm 3 .

[0016] Preferably, the substrate includes an n-type single-crystal silicon substrate, a p-type single-crystal silicon substrate, or an SOI-type single-crystal silicon substrate.

[0017] Preferably, the material of the first base layer is monocrystalline silicon or monocrystalline silicon-germanium alloy, and the doping concentration is 4×10⁻⁶. 13 / cm 3 -4×10 15 / cm3 The second base layer is made of single-crystal silicon or a single-crystal silicon-germanium alloy, with a doping concentration of 1×10⁻⁶. 16 / cm 3 -5×10 18 / cm 3 The chemical formula of the single-crystal silicon-germanium alloy is Si. x Ge 1-x ,0 <x<1。

[0018] Preferably, the thickness of the first base layer is 10nm-100nm; the thickness of the second base layer is 50nm-500nm.

[0019] Preferably, the doping concentration of the emitter layer is 1×10⁻⁶. 17 / cm 3 -1×10 19 / cm 3 The thickness is 50nm-300nm.

[0020] Preferably, the doping concentration of the highly doped layer is 5 × 10⁻⁶. 18 / cm 3 -3×10 20 / cm 3 The thickness is 30nm-200nm.

[0021] Preferably, the phototransistor further includes: an upper electrode, a back electrode, and an isolation region;

[0022] The upper electrode is located on the highly doped layer of the epitaxial structure;

[0023] The back electrode is located beneath the substrate of the epitaxial structure;

[0024] The isolation zone is positioned perpendicular to the extension structure.

[0025] In a second aspect, the present invention provides a phototransistor unit, the phototransistor unit comprising the phototransistor of the CMOS image sensor described in any of the first aspects above.

[0026] Thirdly, the present invention provides a method for fabricating the phototransistor unit described in the second aspect above, the method comprising:

[0027] A transition layer, a collector layer, a first base layer, a second base layer, an emitter layer, and a highly doped layer are sequentially grown on a substrate to obtain the epitaxial structure of a phototransistor.

[0028] An isolation region is set along the vertical direction of the epitaxial structure of the phototransistor to obtain a phototransistor array separated by the isolation region;

[0029] An upper electrode is fabricated on the highly doped layer;

[0030] A back electrode is fabricated under the substrate to obtain the phototransistor unit.

[0031] This invention provides a phototransistor for a CMOS image sensor. It utilizes a thinner collector layer to improve the phototransistor's readout speed and leverages a strong electric field to enhance the absorption characteristics of the thin collector layer, thereby improving its photoelectric conversion efficiency. By dividing the base and emitter into multilayer structures with different doping concentrations, it optimizes the extraction efficiency of photogenerated carriers and the phototransistor gain, thus improving the phototransistor's responsivity, while also reducing the phototransistor's dark current. This unique design not only exhibits excellent photosensitivity, ensuring accurate image capture and rich detail, but also significantly improves the image data readout rate, providing strong technical support for real-time imaging and high-speed dynamic scene capture. Attached Figure Description

[0032] Figure 1 is a schematic diagram of the epitaxial structure of the phototransistor in the CMOS image sensor provided in an embodiment of the present invention;

[0033] Figure 2 is a schematic diagram of the structure of the phototransistor provided in an embodiment of the present invention;

[0034] Figure 3 is a top view of the phototransistor unit provided in an embodiment of the present invention;

[0035] Figure 4 is a flowchart of the fabrication method of the phototransistor unit provided in the embodiment of the present invention;

[0036] Figure 5 shows the response test results of the phototransistor provided in the embodiment of the present invention. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0038] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0039] As shown in Figure 1, the phototransistor of a CMOS image sensor provided in this embodiment of the invention mainly includes the following epitaxial structure 101: substrate 1, collector layer 2, first base layer 3, second base layer 4, emitter layer 5, and highly doped layer 6.

[0040] Substrate 1 is the supporting structure of the phototransistor, located at the bottom layer of epitaxial structure 101. The substrate may specifically include an n-type single crystal silicon substrate, a p-type single crystal silicon substrate, or an SOI-type single crystal silicon substrate.

[0041] The collector layer 2 can be made of single-crystal silicon, with the same doping type as the substrate 1. When the substrate 1 is an n-type single-crystal silicon substrate, the collector layer 2 is doped with n-type doping, and the doping elements can be P or As. When the substrate 1 is a p-type single-crystal silicon substrate, the collector layer 2 is doped with p-type doping, and the doping element can be B. The doping concentration of the collector layer 2 can be 5 × 10⁻⁶. 13 / cm 3 -1×10 16 / cm 3 1×10 is preferred 15 / cm 3 The thickness of collector layer 2 is specifically 100nm-1000nm, preferably 300nm. The main function of collector layer 2 is to collect charge carriers, and it also serves to isolate external circuits, maintaining the stability and reliability of the phototransistor. Collector layer 2 is specifically disposed on substrate 1.

[0042] The thickness of collector layer 2 is reduced to several times that of existing technologies. Firstly, this improves the readout speed of the phototransistor. Secondly, it allows for a thinner epitaxial structure, reducing the number of contaminant particles generated during epitaxy and lowering process costs. Furthermore, with the reduced thickness of collector layer 2, an applied voltage of less than 6V is sufficient to achieve an average electric field strength of 5 × 10⁻⁶ within the collector layer 2. 4 V / cm-3×10 5 Within the V / cm range, the absorption enhancement effect of the non-equilibrium absorption enhancement theory is realized, enabling more light to be absorbed per unit length in the depletion region of the collector-base first pn junction, generating more photogenerated carriers and improving the photoelectric conversion efficiency. In other words, the absorption characteristics of the relatively thin collector layer 2 are enhanced by strong internal and external electric fields. Furthermore, the thickness of collector layer 2 is reduced to several times that of existing structures, significantly reducing the overall thickness of the phototransistor and alleviating the high aspect ratio etching challenge of the deep trench isolation trenches between phototransistors.

[0043] Furthermore, considering the three key objectives of achieving efficient extraction of photogenerated carriers, reducing the dark current of the phototransistor, and improving the gain of the phototransistor under weak illumination (below 1 lux), it is necessary to balance the doping concentration and thickness of the collector layer 2, base, and emitter of the phototransistor. The collector-base first pn junction designed for efficient extraction of photogenerated carriers needs to completely deplete the collector layer (which acts as an absorption layer) while ensuring the pn junction can separate photogenerated carriers without any excess unextracted photogenerated carriers recombinating. This requires the doping concentrations of the collector layer and base to be similar. Then, the dark current of the pn junction is inversely correlated with the doping concentrations of the p and n layers. The dark current of the phototransistor mainly originates from the collector-base first pn junction. This means that during phototransistor operation, the doping concentrations of the collector layer 2 and base need to be minimized to reduce the dark current of the phototransistor. The gain of a phototransistor under low light conditions is also affected by the doping concentration in the depletion region of the base-emitter second pn junction. Reducing the doping concentration in the depletion region of the base-emitter second pn junction, i.e., reducing the doping concentration of both the base and emitter, helps reduce recombination current in the depletion region, improves gain under low light conditions, and enhances the signal output linearity of the phototransistor under low light. Furthermore, the gain of a phototransistor is primarily inversely correlated with the ratio of base doping concentration to emitter doping concentration and the ratio of the width of the base neutral region to the width of the emitter neutral region. The width of the depletion region in the p-layer or n-layer of the pn junction is inversely correlated with the doping concentration of that layer; that is, the higher the doping concentration, the smaller the width of the depletion region within that layer. A lower base doping concentration results in a smaller ratio of base to emitter doping concentration; a smaller ratio of base to emitter doping concentration leads to a higher gain. However, the depletion region of the emitter-base pn junction expands more significantly on the base side. To avoid excessive modulation of the neutral region width of the base layer due to voltage fluctuations, the base layer needs to have relatively high doping levels.

[0044] Furthermore, an ohmic contact needs to be formed between the emitter and the deposited metal layer for the external circuit to read the phototransistor's output current. The emitter requires high doping to achieve this good ohmic contact (low resistance). However, a high emitter doping concentration means a high defect concentration, which enhances the recombination current at the depleted base-emitter second pn junction, affecting the linearity of the phototransistor's signal output under illumination below 1 lux. Therefore, the emitter doping concentration cannot be too high.

[0045] This creates a contradiction: the base of the phototransistor needs a lower doping concentration to reduce dark current, improve photogenerated carrier extraction efficiency, and increase gain; conversely, the base needs a higher doping concentration to reduce gain fluctuations with applied voltage during operation. A higher emitter doping concentration increases gain and creates a low-resistance ohmic contact; a lower emitter doping concentration reduces the impact of recombination current in the depletion region of the second pn junction on signal output linearity under low light conditions. Therefore, the base is divided into multilayer structures with different doping concentrations to meet these requirements.

[0046] The first base layer 3 and the second base layer 4 are the bases of the epitaxial structure 101, disposed on top of the collector layer 2. The doping type is opposite to that of the collector layer 2. When the collector layer 2 is doped with n-type doping, the base is doped with p-type doping, and the doping element can be B. When the collector layer 2 is doped with p-type doping, the base is doped with n-type doping, and the doping element can be P or As.

[0047] Emitter layer 5 and highly doped layer 6 form the emitter of the epitaxial structure, specifically disposed above the second base layer 4. The doping type is the same as that of collector layer 2. When collector layer 2 is n-type doped, the base is p-type doped, and the emitter is n-type doped; the doping element can be P or As. When collector layer 2 is p-type doped, the base is n-type doped, and the emitter is p-type doped; the doping element can be B.

[0048] Thus, the first base layer 3 and the collector layer 2 can form a first pn junction. The first pn junction affects the photoelectric conversion efficiency, photogenerated carrier extraction efficiency, and dark current of the phototransistor. To achieve a low dark current in the phototransistor, the doping concentrations of the first base layer 3 and the collector layer 2 cannot be too high. Furthermore, a higher photogenerated carrier extraction efficiency also means that, under the constraint of a lower doping concentration in the collector layer 2, the doping concentration of the collector layer 2 must only be slightly higher than that of the first base layer 3. Moreover, the doping concentration must satisfy the condition that no unextracted photogenerated carriers accumulate and recombine within the first pn junction during photoelectric conversion, thus avoiding the photogenerated carrier blocking effect and achieving efficient carrier extraction.

[0049] Specifically, the material of the first base layer 3 is monocrystalline silicon or monocrystalline silicon-germanium alloy, and the doping concentration is 4 × 10⁻⁶. 13 / cm 3 -4×10 15 / cm 3 2×10 is preferred 14 / cm 3. Among them, the chemical formula of the single-crystalline silicon-germanium alloy is Si x Ge 1-x , where 0 < x < 1. The thickness of the first base layer 3 can be 10 nm - 100 nm, preferably 40 nm. The first base layer 3 is disposed on the collector layer 2.

[0050] The material of the second base layer 4 is specifically single-crystalline silicon or a single-crystalline silicon-germanium alloy, and the doping concentration can be 1×10 16 / cm 3 - 5×10 18 / cm 3 , preferably 9×10 16 / cm 3 . The thickness of the second base layer 4 can be 50 nm - 500 nm, preferably 190 nm. The second base layer 4 is disposed on the first base layer 3. Among them, the chemical formula of the single-crystalline silicon-germanium alloy is Si x Ge 1-x , where 0 < x < 1. And, the base neutral region, that is, the non-depletion region, is within the second base layer 4. In order to avoid the modulation of the depletion region width of the first pn junction by the applied bias voltage, resulting in the extension of the depletion region to the second base layer 4, thereby changing the base neutral region width and affecting the gain, therefore, the doping concentration of the second base layer 4 is greater than that of the first base layer 3.

[0051] The material of the emitter layer 5 is specifically single-crystalline silicon, and the doping concentration is specifically 1×10 17 / cm 3 - 1×10 19 / cm 3 , preferably 4×10 18 / cm 3 , and the thickness is 50 nm - 300 nm, preferably 120 nm. The emitter layer 5 is disposed on the second base layer 4. The doping concentration of the emitter layer 5 is greater than that of the second base layer 4.

[0052] In this way, the emitter layer 5 and the second base layer 4 can form a second pn junction.

[0053] The material of the highly doped layer 6 is specifically single-crystalline silicon, and it usually forms a good electrical contact with the external electrode to facilitate the application of the bias voltage and the collection of the current formed by the photo-generated carriers. It is disposed on the emitter layer 5, and the doping type of the highly doped layer 6 is the same as that of the emitter layer 5. The doping concentration of the highly doped layer 6 is specifically 5×10 18 / cm 3 - 3×10 20 / cm 3 , preferably 5×10 19 / cm 3 , and the thickness is 30 nm - 200 nm, preferably 50 nm.

[0054] The second pn junction affects the gain of the phototransistor and whether the gain remains constant within a certain range. When the phototransistor outputs a photocurrent signal, the gain needs to remain constant within a certain range so that the magnitude of the photocurrent is only positively correlated with the magnitude of the optical signal, achieving a linear output of the photocurrent. The gain is inversely correlated with the ratio of the base doping concentration to the emitter doping concentration. Therefore, the doping concentration of the emitter layer 5 is greater than the doping concentration of the second base layer 4.

[0055] However, under low illumination (less than 1 lux) conditions, if the small photogenerated current is lower than the recombination current in the depletion region of the second pn junction, it will lead to a decrease in the current gain value, resulting in nonlinearity in the output of the photogenerated electrical signal.

[0056] Therefore, the emitter is designed in layers, with the highly doped layer 6 as a separate layer and the doping concentration of the highly doped layer 6 being greater than that of the emitter layer 5. This not only achieves the function of an ohmic contact and facilitates the adjustment of the doping concentration of the emitter layer 5, but also reduces the defect concentration in the depletion region of the second pn junction, reduces the recombination current in the depletion region of the second pn junction, and improves the linearity of the output current under low light conditions.

[0057] In a preferred embodiment, the epitaxial structure 101 of the phototransistor further includes a transition layer 7, primarily used to improve the surface roughness of the substrate 1 and provide an atomically smooth interface. The transition layer 7 is specifically made of single-crystal silicon. The thickness of the transition layer 7 can be 0 nm to 500 nm, preferably 100 nm. The doping method is unintentional doping or low-concentration doping, wherein the low-concentration doping concentration is 1 × 10⁻⁶. 13 / cm 3 -1×10 15 / cm 3 The transition layer 7 is specifically disposed between the substrate 1 and the collector layer 2.

[0058] As shown in Figure 2, in addition to the epitaxial structure 101, the phototransistor also includes: an upper electrode 102, a back electrode 103, and an isolation region 104.

[0059] The upper electrode 102 is located on the highly doped layer 6 of the epitaxial structure 101. The back electrode 103 is located under the substrate 1 of the epitaxial structure 101.

[0060] The isolation region 104 is specifically set perpendicular to the epitaxial structure 101, mainly to achieve electrical and optical isolation between phototransistors.

[0061] The above improvements give the phototransistor of this application the following advantages:

[0062] First, based on the non-equilibrium absorption theory, the collector-base first pn junction enhances the absorption performance of the absorption region, and can reduce the collector layer thickness without being lower than the responsivity of existing phototransistors, thereby improving the readout speed of phototransistors.

[0063] Secondly, the reduction in the overall thickness of the phototransistor brings additional benefits such as reduced epitaxial costs and reduced etching difficulty.

[0064] Third, a multi-layer structure was designed for the base. The first base layer provides a degree of freedom for optimizing the doping concentration of the base layer in the space charge region of the collector-base first pn junction, which can better optimize the photogenerated carrier efficiency. Reducing the doping concentration of the first base layer and the collector layer reduces the charge concentration of the space charge in the depletion region of the collector-base first pn junction, which helps to reduce dark current. Reducing the doping concentration of the second base layer and the emitter layer reduces the charge concentration of the space charge in the depletion region of the base-emitter second pn junction, which helps to reduce the recombination current in the depletion region, improves the gain under illumination conditions of less than 1 lux, and improves the signal output linearity of the phototransistor.

[0065] In summary, the phototransistor for a CMOS image sensor provided by this invention utilizes a thinner collector layer to improve the phototransistor's readout speed, and leverages a strong electric field to enhance the absorption characteristics of the thin collector layer, thereby improving its photoelectric conversion efficiency. By dividing the base and emitter into multilayer structures with different doping concentrations, it optimizes the extraction efficiency of photogenerated carriers and the phototransistor gain, thus improving the phototransistor's responsivity, while also reducing the phototransistor's dark current. This unique design not only exhibits excellent photosensitivity, ensuring accurate image capture and rich detail, but also significantly improves the image data readout rate, providing strong technical support for real-time imaging and high-speed dynamic scene capture.

[0066] This invention also provides a phototransistor unit, which includes the phototransistor of any of the CMOS image sensors described above.

[0067] The present invention also provides a method for fabricating the above-mentioned phototransistor unit, specifically including the steps shown in Figure 4:

[0068] Step 110: A transition layer, a collector layer, a first base layer, a second base layer, an emitter layer, and a highly doped layer are sequentially grown on the substrate to obtain the epitaxial structure of the phototransistor.

[0069] Specifically, the epitaxial structure can be understood as the functional region of a phototransistor. It can be achieved using reduced-pressure chemical vapor deposition (RPCVD), low-pressure chemical vapor deposition (LPCVD), or ultra-high-vacuum chemical vapor deposition (UHVCVD) processes.

[0070] In a preferred approach, RPCVD deposition is used.

[0071] The selection of materials, doping concentration, and doping type for each layer correspond to those described in the above structure, and will not be repeated here.

[0072] Step 120: An isolation region is set along the vertical direction of the epitaxial structure of the phototransistor to obtain a phototransistor array separated by the isolation region;

[0073] Specifically, the isolation region is set vertically along the epitaxial structure, specifically from the upper surface of the highly doped layer to the lower surface of the transition layer. The isolation region can divide the epitaxial structure into an array.

[0074] More specifically, firstly, dry etching of the isolation trenches using deep trench isolation is employed. Specifically, the isolation trenches can be etched using inductively coupled plasma (ICP), and the etching gas can be SF6 or C4F8.

[0075] Secondly, the epitaxial structure of the phototransistor with isolation trench is placed in a high-temperature oxidation furnace and subjected to high-temperature thermal oxidation in an oxygen atmosphere to form a silicon dioxide passivation layer on the surface of the epitaxial structure and the surface of the isolation trench. The high-temperature thermal oxidation temperature is 750℃-1200℃.

[0076] Finally, dielectric material is filled into the isolation tank using PECVD (Plasma Enhanced Chemical Vapor Deposition) or HDPCVD (High Density Plasma Chemical Vapor Deposition) equipment to form an isolation region. The dielectric material can be any one of photoresist, silicon dioxide, silicon nitride, or polysilicon, with silicon dioxide being preferred.

[0077] The main function of the isolation region is to form an electrically isolated region between adjacent phototransistors in the phototransistor unit, and to isolate the photoelectric conversion region, i.e. the collector layer, of adjacent phototransistors, so as not to generate crosstalk of photocurrent signals.

[0078] Step 130: Fabricate the top electrode in the highly doped layer;

[0079] Specifically, metal electrodes are deposited using electron beam metal deposition equipment or magnetron sputtering equipment. The material for the top electrode can be a titanium-aluminum alloy.

[0080] Step 140: Prepare a back electrode on the substrate to obtain a phototransistor unit.

[0081] Specifically, the back electrode is deposited using electron beam metal deposition equipment or magnetron sputtering equipment. The material for the back electrode can be titanium-aluminum alloy. As shown in Figure 3, the function of the light-transmitting window area is to allow external light signals to enter the phototransistor for photoelectric conversion.

[0082] The phototransistor unit fabrication method provided by this invention utilizes epitaxial technology to precisely control the doping concentration and thickness of functional layers such as the collector layer, base layer, and emitter layer, thereby better suppressing the dark current and increasing the gain of the phototransistor. This overcomes the shortcomings of phototransistors fabricated using bipolar junction transistor (BJT) or BiCMOS processes, which incorporate deeply buried, highly doped silicon layers formed by ion implantation. The tailing effect of ion implantation increases the doping concentration of the pre-designated low-doped layer in the ion implantation path, affecting the doping concentration and distribution of the doped layer, and consequently impacting the dark current and gain of the phototransistor. In summary, this fabrication method has a simple process flow and is highly operable.

[0083] To better understand the technical solution provided by the present invention, the following uses several specific examples to illustrate the specific process of preparing a phototransistor unit using the method provided in the above embodiments of the present invention, as well as the performance of the prepared phototransistor.

[0084] Example 1

[0085] The first step involves sequentially growing a transition layer, a collector layer, a first base layer, a second base layer, an emitter layer, and a highly doped layer on a p-type single-crystal silicon substrate using RPCVD technology to obtain the epitaxial structure of a phototransistor.

[0086] The transition layer, collector layer, first base layer, second base layer, emitter layer, and highly doped layer are all made of single-crystal silicon. The transition layer is unintentionally doped and has a thickness of 100 nm. The epitaxial parameters of RPCVD are: temperature 900℃, pressure 7980 Pa, and epitaxial gases are dichlorosilane and hydrogen.

[0087] The collector layer is doped with boron (B) at a concentration of 8 × 10⁻⁶.14 / cm 3 The thickness is 100nm, and the epitaxial parameters of RPCVD are: temperature 900℃, pressure 7980Pa, and epitaxial gases are dichlorosilane, hydrogen and borane.

[0088] The first base electrode layer is doped with P at a concentration of 1 × 10⁻⁶. 14 / cm 3 The thickness is 50nm, and the epitaxial parameters of RPCVD are: temperature 900℃, pressure 7980Pa, and epitaxial gases are dichlorosilane, hydrogen and phosphine.

[0089] The second base electrode layer is doped with P at a concentration of 6 × 10⁻⁶. 16 / cm 3 The thickness is 200nm, and the epitaxial parameters of RPCVD are: temperature 900℃, pressure 7980Pa, and epitaxial gases are dichlorosilane, hydrogen and phosphine.

[0090] The emitter layer is doped with boron (B) at a concentration of 2 × 10⁻⁶. 18 / cm 3 The thickness is 150nm, and the epitaxial parameters of RPCVD are: temperature 900℃, pressure 7980Pa, and epitaxial gases are dichlorosilane, hydrogen and borane.

[0091] The highly doped layer is doped with boron (B) at a concentration of 5 × 10⁻⁶. 19 / cm 3 The thickness is 50nm, and the epitaxial parameters of RPCVD are: temperature 900℃, pressure 7980Pa, and epitaxial gases are dichlorosilane, hydrogen and borane.

[0092] The second step is to set an isolation region along the vertical direction of the epitaxial structure of the phototransistor to obtain an array of phototransistors separated by the isolation region.

[0093] First, ICP etching is used to etch the isolation trench with a depth-to-width ratio of 4:1, and SF6 is used as the etching gas.

[0094] Secondly, the epitaxial structure of the phototransistor with isolation trench is placed in a high-temperature oxidation furnace and subjected to a hot dry oxidation process in an oxygen atmosphere to form a silicon dioxide passivation layer on the surface of the epitaxial structure and the surface of the isolation trench. The hot dry oxidation temperature is 950℃.

[0095] Finally, using the HDPCVD method, a 900 nm thick silicon dioxide-filled isolation trench was deposited at 399 Pa and 300 °C to form an isolation region.

[0096] The third step involves fabricating a TiAl alloy electrode on a highly doped layer using electron beam metal deposition, with a Ti metal thickness of 20 nm and an Al metal thickness of 300 nm.

[0097] The fourth step involves fabricating a TiAl alloy back electrode on the substrate using electron beam metal deposition. The Ti metal thickness is 20 nm and the Al metal thickness is 300 nm, resulting in a 60 μm × 60 μm phototransistor unit.

[0098] Next, the responsivity of the phototransistor unit was tested using a phototransistor responsivity test system. The test conditions were: input light wavelength: 600nm-800nm; and the phototransistor unit was illuminated with pulsed 850nm light. The waveform of the output pulse signal of the phototransistor unit was observed with an oscilloscope. The bias voltage between the upper electrode and the back electrode was 3V.

[0099] Example 2

[0100] The first step involves sequentially growing a transition layer, a collector layer, a first base layer, a second base layer, an emitter layer, and a highly doped layer on a p-type single-crystal silicon substrate using RPCVD technology to obtain the epitaxial structure of a phototransistor.

[0101] The transition layer, collector layer, first base layer, second base layer, emitter layer, and highly doped layer are all made of single-crystal silicon. The transition layer is unintentionally doped and has a thickness of 100 nm. The epitaxial parameters of RPCVD are: temperature 900℃, pressure 7980 Pa, and epitaxial gases are dichlorosilane and hydrogen.

[0102] The collector layer is doped with boron (B) at a concentration of 1 × 10⁻⁶. 15 / cm 3 The thickness is 300 nm, and the epitaxial parameters of RPCVD are: temperature 900℃, pressure 7980 Pa, and epitaxial gases are dichlorosilane, hydrogen and borane.

[0103] The first base electrode layer is doped with P at a concentration of 2 × 10⁻⁶. 14 / cm 3 The thickness is 40nm, and the epitaxial parameters of RPCVD are: temperature 900℃, pressure 7980Pa, and epitaxial gases are dichlorosilane, hydrogen and phosphine.

[0104] The second base electrode layer is doped with P at a concentration of 9 × 10⁻⁶. 16 / cm 3 The thickness is 190nm, and the epitaxial parameters of RPCVD are: temperature 900℃, pressure 7980Pa, and epitaxial gases are dichlorosilane, hydrogen and phosphine.

[0105] The emitter layer is doped with boron (B) at a concentration of 4 × 10⁻⁶.18 / cm 3 The thickness is 120nm, and the epitaxial parameters of RPCVD are: temperature 900℃, pressure 7980Pa, and epitaxial gases are dichlorosilane, hydrogen and borane.

[0106] The highly doped layer is doped with boron (B) at a concentration of 5 × 10⁻⁶. 19 / cm 3 The thickness is 50nm, and the epitaxial parameters of RPCVD are: temperature 900℃, pressure 7980Pa, and epitaxial gases are dichlorosilane, hydrogen and borane.

[0107] The second step is to set an isolation region along the vertical direction of the epitaxial structure of the phototransistor to obtain an array of phototransistors separated by the isolation region.

[0108] First, ICP etching is used to etch the isolation trench, with a depth-to-width ratio of 5:1, and the etching gas can be SF6.

[0109] Secondly, the epitaxial structure of the phototransistor with isolation trench is placed in a high-temperature oxidation furnace and subjected to a hot dry oxidation process in an oxygen atmosphere to form a silicon dioxide passivation layer on the surface of the epitaxial structure and the surface of the isolation trench. The hot dry oxidation temperature is 950℃.

[0110] Finally, using the HDPCVD method, a 1100 nm thick silicon dioxide-filled isolation trench was deposited at 399 Pa and 300 °C to form an isolation region.

[0111] The third step involves fabricating a TiAl alloy electrode on a highly doped layer using electron beam metal deposition, with a Ti metal thickness of 20 nm and an Al metal thickness of 300 nm.

[0112] The fourth step involves using electron beam metal deposition to fabricate a TiAl alloy back electrode on the substrate. The Ti metal thickness is 20 nm and the Al metal thickness is 300 nm, resulting in a 60 μm × 60 μm phototransistor unit.

[0113] Next, the responsivity of the phototransistor unit was tested using a phototransistor responsivity test system. The test conditions were: input light wavelength: 600nm-800nm; and the phototransistor unit was illuminated with pulsed 850nm light. The waveform of the output pulse signal of the phototransistor unit was observed with an oscilloscope. The bias voltage between the upper electrode and the back electrode was 3V.

[0114] Comparative Example 1

[0115] The first step involves sequentially growing a transition layer, a collector layer, a base layer, and an emitter layer on a p-type single-crystal silicon substrate using RPCVD technology to obtain the epitaxial structure of a phototransistor.

[0116] The transition layer, collector layer, base layer, and emitter layer are all made of single-crystal silicon. The transition layer is unintentionally doped and has a thickness of 100 nm. The epitaxial parameters of RPCVD are: temperature 900℃, pressure 7980 Pa, and epitaxial gases are dichlorosilane and hydrogen.

[0117] The collector layer is doped with boron (B) at a concentration of 8 × 10⁻⁶. 13 / cm 3 The thickness is 3000 nm, and the epitaxial parameters of RPCVD are: temperature 900℃, pressure 7980 Pa, and epitaxial gases are dichlorosilane, hydrogen and borane.

[0118] The base layer is doped with P at a concentration of 5 × 10⁻⁶. 17 / cm 3 The thickness is 300nm, and the epitaxial parameters of RPCVD are: temperature 900℃, pressure 7980Pa, and epitaxial gases are dichlorosilane, hydrogen and phosphine.

[0119] The emitter layer is doped with boron (B) at a concentration of 2 × 10⁻⁶. 19 / cm 3 The thickness is 200nm, and the epitaxial parameters of RPCVD are: temperature 900℃, pressure 7980Pa, and epitaxial gases are dichlorosilane, hydrogen and phosphine.

[0120] The second step involves etching the isolation trench using ICP. The aspect ratio of the isolation trench is 18:1, and the etching gas can be SF6.

[0121] Secondly, the epitaxial structure of the phototransistor with isolation trench is placed in a high-temperature oxidation furnace and subjected to a hot dry oxidation process in an oxygen atmosphere to form a silicon dioxide passivation layer on the surface of the epitaxial structure and the surface of the isolation trench. The hot dry oxidation temperature is 950℃.

[0122] The third step involves using the HDPCVD method to deposit a 3600nm thick silicon dioxide-filled isolation trench at 399Pa and 300℃ to form an isolation region.

[0123] The fourth step involves fabricating a TiAl alloy electrode on a highly doped layer using electron beam metal deposition. The Ti metal thickness is 20 nm, and the Al metal thickness is 300 nm.

[0124] In the fifth step, a TiAl alloy back electrode is prepared on the substrate by electron beam metal deposition. The thickness of Ti metal is 20 nm and the thickness of Al metal is 300 nm, thus obtaining a 60 μm × 60 μm phototransistor unit.

[0125] Next, the responsivity of the phototransistor unit was tested using a phototransistor responsivity test system. The test conditions were: input light wavelength: 600nm-800nm; and the phototransistor unit was illuminated with pulsed 850nm light. The waveform of the output pulse signal of the phototransistor unit was observed with an oscilloscope. The bias voltage between the upper electrode and the back electrode was 3V.

[0126] Table 1 shows the test results of the signal rise time and fall time of the phototransistor provided in the embodiments of the present invention.

[0127] Table 1

[0128] It should be noted that rise time is defined as the time required for the signal waveform to rise from 10% to 90%, and fall time is defined as the time required for the signal waveform to fall from 90% to 10%.

[0129] As shown in Table 1, the signal rise time and signal fall time of the phototransistor of the present invention are both shorter than those of Comparative Example 1, indicating that the signal readout time of the phototransistor of the present invention is greatly reduced. This is because the phototransistor of the present invention utilizes an ultra-thin collector layer, which shortens the transit distance of photogenerated carriers. Furthermore, under a strong electric field, the velocity of photogenerated carriers approaches the saturation drift velocity, thereby reducing the transit time of photogenerated carriers and resulting in a significant reduction in the signal readout time of the phototransistor.

[0130] As shown in Figure 5, compared to Comparative Example 1, the phototransistor of the present invention exhibits a higher responsivity. This is because the present invention utilizes the principle of enhanced photoelectric conversion under strong electric field and pn junction non-equilibrium conditions using an extremely thin collector layer. By adjusting the thickness and doping concentration of the collector layer, base, and emitter, as well as the structure of the base and emitter, the photogenerated carrier extraction efficiency and gain of the phototransistor are optimized, thereby increasing the responsivity of the phototransistor.

[0131] Example 3

[0132] The first step involves growing a transition layer, a collector layer, a first base layer, a second base layer, an emitter layer, and a highly doped layer sequentially on an n-type single-crystal silicon substrate using LPCVD technology to obtain the epitaxial structure of a phototransistor.

[0133] The transition layer, collector layer, emitter layer, and highly doped layer are all made of single-crystal silicon. The first base layer and the second base layer are made of single-crystal silicon-germanium alloy. The transition layer is low-concentration doped and has a thickness of 300 nm. The epitaxial parameters of LPCVD are: temperature 850°C, pressure 133.2 Pa, and epitaxial gases are dichlorosilane and hydrogen.

[0134] The collector layer is doped with P at a concentration of 5 × 10⁻⁶. 13 / cm3 The thickness is 1000nm, and the epitaxial parameters of LPCVD are: temperature 850, pressure 133.2Pa, and epitaxial gases are dichlorosilane, hydrogen and phosphine.

[0135] The first base electrode layer is doped with boron at a concentration of 4 × 10⁻⁶. 13 / cm 3 The thickness was 10 nm, and the epitaxial parameters of LPCVD were: temperature 850, pressure 133.2 Pa, and epitaxial gases were dichlorosilane, hydrogen, germane and borane.

[0136] The second base electrode layer is doped with boron at a concentration of 5 × 10⁻⁶. 18 / cm 3 The thickness was 50 nm, and the epitaxial parameters of LPCVD were: temperature 850 °C, pressure 133.2 Pa, and epitaxial gases were dichlorosilane, hydrogen, germane and borane.

[0137] The emitter layer is doped with P at a concentration of 1 × 10⁻⁶. 19 The thickness is 50nm, and the epitaxial parameters of LPCVD are: temperature 850, pressure 133.2Pa, and epitaxial gases are dichlorosilane, hydrogen and phosphine.

[0138] The highly doped layer is doped with P, and the doping concentration is 3 × 10⁻⁶. 20 / cm 3 The thickness is 30nm, and the epitaxial parameters of LPCVD are: temperature 850, pressure 133.2Pa, and epitaxial gases are dichlorosilane, hydrogen and phosphine.

[0139] The second step is to set an isolation region along the vertical direction of the epitaxial structure of the phototransistor to obtain an array of phototransistors separated by the isolation region.

[0140] First, ICP etching is used to etch the isolation trench with a depth-to-width ratio of 4:1, and the etching gas is C4F8.

[0141] Secondly, the epitaxial structure of the phototransistor with isolation trench is placed in a high-temperature oxidation furnace and subjected to a hot dry oxidation process in an oxygen atmosphere to form a silicon dioxide passivation layer on the surface of the epitaxial structure and the surface of the isolation trench. The hot dry oxidation temperature is 950℃.

[0142] Finally, using the PECVD method, a 900 nm thick silicon nitride-filled isolation trench was deposited at 250 Pa and 300 °C to form an isolation region.

[0143] The third step involves fabricating a TiAl alloy electrode on a highly doped layer using electron beam metal deposition, with a Ti metal thickness of 20 nm and an Al metal thickness of 300 nm.

[0144] The fourth step involves fabricating a TiAl alloy back electrode on the substrate using electron beam metal deposition. The Ti metal thickness is 20 nm and the Al metal thickness is 300 nm, resulting in a 60 μm × 60 μm phototransistor unit.

[0145] Example 4

[0146] The first step involves growing a transition layer, a collector layer, a first base layer, a second base layer, an emitter layer, and a highly doped layer sequentially on a p-type single-crystal silicon substrate using UHVCVD technology to obtain the epitaxial structure of a phototransistor.

[0147] The transition layer, collector layer, emitter layer, and highly doped layer are all made of single-crystal silicon. The first base layer and the second base layer are made of single-crystal silicon-germanium alloy. The transition layer is low-concentration doped and has a thickness of 500 nm. The epitaxial parameters of UHVCVD are: temperature 560℃, pressure 6.67 Pa, and epitaxial gases are silane and hydrogen.

[0148] The collector layer is doped with boron (B) at a concentration of 1 × 10⁻⁶. 16 / cm 3 The thickness is 800 nm. The epitaxial parameters of UHVCVD are: temperature 560℃, pressure 6.67 Pa, and epitaxial gases are silane, hydrogen and borane.

[0149] The first base electrode layer is doped with P at a concentration of 4 × 10⁻⁶. 15 / cm 3 The thickness is 100 nm. The epitaxial parameters of UHVCVD are: temperature 560℃, pressure 6.67 Pa, and epitaxial gases are silane, hydrogen, germane and phosphine.

[0150] The second base electrode layer is doped with P at a concentration of 1 × 10⁻⁶. 16 / cm 3 The thickness is 500 nm. The epitaxial parameters of UHVCVD are: temperature 560℃, pressure 6.67 Pa, and epitaxial gases are silane, hydrogen, germane and phosphine.

[0151] The emitter layer is doped with boron (B) at a concentration of 1 × 10⁻⁶. 17 / cm 3 The thickness is 50nm, and the epitaxial parameters of UHVCVD are: temperature 560℃, pressure 6.67Pa, and epitaxial gases are silane, hydrogen and borane.

[0152] The highly doped layer is doped with boron (B) at a concentration of 5 × 10⁻⁶. 18 / cm 3 The thickness is 200 nm. The epitaxial parameters of UHVCVD are: temperature 560℃, pressure 6.67 Pa, and epitaxial gases are silane, hydrogen and borane.

[0153] The second step is to set an isolation region along the vertical direction of the epitaxial structure of the phototransistor to obtain an array of phototransistors separated by the isolation region.

[0154] First, ICP etching is used to etch the isolation trench with a depth-to-width ratio of 5:1 and C4F8 as the etching gas.

[0155] Secondly, the epitaxial structure of the phototransistor with isolation trench is placed in a high-temperature oxidation furnace and subjected to a hot dry oxidation process in an oxygen atmosphere to form a silicon dioxide passivation layer on the surface of the epitaxial structure and the surface of the isolation trench. The hot dry oxidation temperature is 950℃.

[0156] Finally, using the PECVD method, a 900 nm thick silicon nitride-filled isolation trench was deposited at 250 Pa and 300 °C to form an isolation region.

[0157] The third step involves fabricating a TiAl alloy electrode on a highly doped layer using electron beam metal deposition, with a Ti metal thickness of 20 nm and an Al metal thickness of 300 nm.

[0158] The fourth step involves fabricating a TiAl alloy back electrode on the substrate using electron beam metal deposition. The Ti metal thickness is 20 nm and the Al metal thickness is 300 nm, resulting in a 60 μm × 60 μm phototransistor unit.

[0159] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A phototransistor for a CMOS image sensor, characterized in that, The epitaxial structure of the phototransistor includes: a substrate, a collector layer, a first base layer, a second base layer, an emitter layer, and a highly doped layer; The current collector layer is disposed on the substrate, and the thickness of the current collector layer is 100nm-1000nm, with a doping concentration of 5×10⁻⁶. 13 / cm 3 -1×10 16 / cm 3 ; The first base layer is disposed on the collector layer, and the doping type of the first base layer is opposite to that of the collector layer. The second base layer is disposed on the first base layer, and the doping type of the second base layer is the same as that of the first base layer; The emitter layer is disposed on the second base layer, and the doping type of the emitter layer is the same as the doping type of the collector layer; The highly doped layer is disposed on the emitter layer, and the doping type of the highly doped layer is the same as that of the emitter layer; wherein the doping concentration of the highly doped layer is greater than that of the emitter layer. Under an applied voltage of less than 6V, the average electric field strength inside the collector layer of the phototransistor is 5×10⁻⁶. 4 V / cm-3×10 5 V / cm.

2. The phototransistor according to claim 1, characterized in that, The epitaxial structure of the phototransistor further includes a transition layer; the transition layer is disposed between the substrate and the collector layer; the thickness of the transition layer is 0 nm-500 nm, and the doping method is unintentional doping or low-concentration doping, wherein the low-concentration doping concentration is 1 × 10⁻⁶. 13 / cm 3 -1×10 15 / cm 3 .

3. The phototransistor according to claim 1, characterized in that, The substrate includes an n-type monocrystalline silicon substrate, a p-type monocrystalline silicon substrate, or an SOI-type monocrystalline silicon substrate.

4. The phototransistor according to claim 1, characterized in that, The first base layer is made of single-crystal silicon or a single-crystal silicon-germanium alloy, with a doping concentration of 4 × 10⁻⁶. 13 / cm 3 -4×10 15 / cm 3 The second base layer is made of single-crystal silicon or a single-crystal silicon-germanium alloy, with a doping concentration of 1×10⁻⁶. 16 / cm 3 -5×10 18 / cm 3 The chemical formula of the single-crystal silicon-germanium alloy is Si. x Ge 1-x ,0 <x<1。 5. The phototransistor according to claim 1, characterized in that, The thickness of the first base layer is 10nm-100nm; the thickness of the second base layer is 50nm-500nm.

6. The phototransistor according to claim 1, characterized in that, The doping concentration of the emitter layer is 1×10⁻⁶. 17 / cm 3 -1×10 19 / cm 3 The thickness is 50nm-300nm.

7. The phototransistor according to claim 1, characterized in that, The doping concentration of the highly doped layer is 5 × 10⁻⁶. 18 / cm 3 -3×10 20 / cm 3 The thickness is 30nm-200nm.

8. The phototransistor according to claim 1, characterized in that, The phototransistor also includes: an upper electrode, a back electrode, and an isolation region; The upper electrode is located on the highly doped layer of the epitaxial structure; The back electrode is located beneath the substrate of the epitaxial structure; The isolation zone is positioned perpendicular to the extension structure.

9. A phototransistor unit, characterized in that, The phototransistor unit includes the phototransistor of the CMOS image sensor according to any one of claims 1-8.

10. A method for fabricating the phototransistor unit according to claim 9, characterized in that, The preparation method includes: A transition layer, a collector layer, a first base layer, a second base layer, an emitter layer, and a highly doped layer are sequentially grown on a substrate to obtain the epitaxial structure of a phototransistor. An isolation region is set along the vertical direction of the epitaxial structure of the phototransistor to obtain a phototransistor array separated by the isolation region; An upper electrode is fabricated on the highly doped layer; A back electrode is fabricated under the substrate to obtain the phototransistor unit.

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