Drive control circuit, gate drive circuit, display substrate, and display device

Abstract

Provided is a display substrate, comprising: a base substrate (100); and a plurality of first sub-pixels (PX) and a plurality of data lines (DL) arranged on the base substrate (100). A first sub-pixel (PX) comprises a first switching transistor (T1), a first pixel electrode (EP1), a second pixel electrode (EP2), a first common electrode (EC1), and a second common electrode (EC2). The first switching transistor (T1) comprises a first active layer (T10). The first active layer (T10) comprises a first channel region (T100), and a first region (T101) and a second region (T102) located on two sides of the first channel region (T100). The first region (T101) is connected to a data line (DL), the second region (T102) is connected to the first pixel electrode (EP1), and the second pixel electrode (EP2) is connected to the first pixel electrode (EP1). The plurality of data lines (DL) are located on the side of the first active layer (T10) close to the base substrate (100). The plurality of data lines (DL) and the first common electrode (EC1) are disposed on a same layer.

Description

Drive control circuit, gate drive circuit, display substrate and display device

[0001] This application claims priority to Chinese Patent Application No. 202411746754.1, filed on November 29, 2024, entitled "Display Substrate and Display Device", and Chinese Patent Application No. 202510104491.2, filed on January 22, 2025, entitled "Display Substrate and Display Device", the contents of which should be understood to be incorporated herein by reference. Technical Field

[0002] This article relates to, but is not limited to, the field of display technology, and in particular to a driving control circuit, a gate driving circuit, a display substrate, and a display device. Background Technology

[0003] Electronic paper primarily employs electrophoresis display (EPD) technology. Electronic paper displays not only offer advantages similar to paper, such as comfortable reading, ultra-thin and lightweight design, and flexibility, but also allow for content refresh and consume less power than LCD displays. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a drive control circuit, a gate drive circuit, a display substrate, and a display device.

[0006] On one hand, this embodiment provides a display substrate, including: a substrate, a plurality of first sub-pixels disposed on the substrate, and a plurality of data lines; at least one of the plurality of first sub-pixels includes: a first switching transistor, a first pixel electrode, a second pixel electrode, a first common electrode, and a second common electrode; the first switching transistor includes a first active layer, the first active layer including a first channel region, and a first region and a second region located on both sides of the first channel region, the first region being connected to the data lines, the second region being connected to the first pixel electrode, the second pixel electrode being connected to the first pixel electrode, the orthographic projection of the first pixel electrode on the substrate at least partially overlapping the orthographic projection of the first common electrode on the substrate, and the orthographic projection of the second pixel electrode on the substrate at least partially overlapping the orthographic projection of the second common electrode on the substrate. The plurality of data lines are located on the side of the first active layer closer to the substrate, and the plurality of data lines are disposed in the same layer as the first common electrode.

[0007] In some exemplary embodiments, the display substrate further includes: a plurality of light-shielding electrodes disposed on the substrate, wherein the orthographic projection of the first channel region on the substrate is located within the orthographic projection range of the light-shielding electrodes on the substrate, and the plurality of light-shielding electrodes are disposed in the same layer as the plurality of data lines.

[0008] In some exemplary embodiments, the first pixel electrode is located on the side of the first common electrode away from the substrate, the second common electrode is located on the side of the first pixel electrode away from the substrate, and the second pixel electrode is located on the side of the second common electrode away from the substrate.

[0009] In some exemplary embodiments, the gate of the first switching transistor and the first pixel electrode are disposed on the same layer.

[0010] In some exemplary embodiments, the first region of the first switching transistor is connected to the data line through a first conductive block, the first common electrode is connected to the second common electrode through a second conductive block, and the first pixel electrode is connected to the second pixel electrode through a third conductive block; the first conductive block, the second conductive block, and the first pixel electrode are disposed on the same layer, and the third conductive block and the second common electrode are disposed on the same layer.

[0011] In some exemplary embodiments, in a direction perpendicular to the display substrate, the display substrate includes: a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer, and a fourth conductive layer stacked on the substrate; the first conductive layer includes: the plurality of data lines, the plurality of light-shielding electrodes, and a first common electrode; the semiconductor layer includes: a first active layer of the first switching transistor; the second conductive layer includes: the gate of the first switching transistor and the first pixel electrode; the third conductive layer includes: the second common electrode; and the fourth conductive layer includes: the second pixel electrode.

[0012] In some exemplary embodiments, a plurality of first sub-pixels arranged along a first direction constitute a row of sub-pixels; the display substrate includes: a plurality of gate lines extending along the first direction and a plurality of groups of sub-pixels arranged along a second direction, each group of sub-pixels including two adjacent rows of sub-pixels along the second direction, the first direction intersecting the second direction; the gate of the first switching transistor of each group of sub-pixels is connected to the same gate line; the gate line is located in the middle of the two rows of sub-pixels within the group of sub-pixels.

[0013] In some exemplary embodiments, the substrate includes a display center region and a display boundary region; the plurality of first sub-pixels are located in the display center region. The display substrate further includes a plurality of second sub-pixels located in the display boundary region, at least one of the second sub-pixels including: a second switching transistor, a third pixel electrode, a fourth pixel electrode, a third common electrode that at least partially overlaps with the orthographic projection of the third pixel electrode on the substrate, and a fourth common electrode that at least partially overlaps with the orthographic projection of the fourth pixel electrode on the substrate; the first electrode of the second switching transistor is connected to the data line, the second electrode of the second switching transistor is not electrically connected to the third pixel electrode, and the fourth pixel electrode is not electrically connected to either the third pixel electrode or the second electrode of the second switching transistor. The first and second electrodes of the second switching transistor, the third pixel electrode, and the first pixel electrode are disposed in the same layer; the third common electrode is disposed in the same layer as the first common electrode; the fourth pixel electrode is disposed in the same layer as the second pixel electrode, and the fourth common electrode is disposed in the same layer as the second common electrode.

[0014] In some exemplary embodiments, the substrate includes a display center region and a display boundary region. The plurality of first sub-pixels are located in the display center region. The display substrate further includes a plurality of second sub-pixels located in the display boundary region, at least one of the second sub-pixels including a second switching transistor, a fourth pixel electrode, and a fourth common electrode that at least partially overlaps with the orthographic projection of the fourth pixel electrode on the substrate; the first electrode of the second switching transistor is connected to the data line, and the second electrode of the second switching transistor is not electrically connected to the fourth pixel electrode. The fourth pixel electrode and the second pixel electrode are disposed in the same layer, and the fourth common electrode and the second common electrode are disposed in the same layer.

[0015] On the other hand, this embodiment provides a display device, including a counter substrate, an electrophoretic solution, and a display substrate as described above, wherein the electrophoretic solution is located between the counter substrate and the display substrate.

[0016] On the other hand, this embodiment provides a drive control circuit, including: an input circuit, a first control circuit, a first output circuit, a second output circuit, and a first noise reduction circuit. The input circuit is electrically connected to an input terminal and a first node, configured to write an input signal provided by the input terminal to the first node under the control of the input terminal. The first control circuit is electrically connected to a first clock terminal, a first power supply terminal, and a second node, configured to write a first power supply signal provided by the first power supply terminal to the second node under the control of the effective level of the first clock signal provided by the first clock terminal. The first output circuit is electrically connected to the first node, the second clock terminal, and the first output terminal, configured to control the first output terminal to output a second clock signal provided by the second clock terminal under the control of the first node. The second output circuit is electrically connected to the first node, a third clock terminal, and a second output terminal, configured to control the second output terminal to output a third clock signal provided by the third clock terminal under the control of the first node. The first noise reduction circuit is electrically connected to the second node, the first output terminal, the second output terminal, the third power supply terminal, and a fourth power supply terminal, configured to control the first output terminal to output a third power supply signal provided by the third power supply terminal and control the second output terminal to output a fourth power supply signal provided by the fourth power supply terminal under the control of the second node. Specifically, during the periods when the input circuit writes the input signal to the first node, during the periods when the first output terminal outputs the second clock signal, and during the periods when the second output terminal outputs the third clock signal, the first clock signal provides an inactive level; after the periods when the first output terminal outputs the second clock signal and the second output terminal outputs the third clock signal, the first clock signal provides an active level.

[0017] In some exemplary embodiments, the effective level of the first clock signal accounts for 25% of a pulse cycle.

[0018] In some exemplary embodiments, the drive control circuit further includes: a first node capacitor, the first electrode of the first node capacitor being electrically connected to the first node, and the second electrode of the first node capacitor being electrically connected to the fourth power supply terminal.

[0019] In some exemplary embodiments, the drive control circuit further includes a second control circuit and a second noise reduction circuit. The second control circuit is electrically connected to the first clock terminal, the third node, and the second power supply terminal, and is configured to write a second power signal provided by the second power supply terminal to the third node under the control of the effective level of the first clock signal provided by the first clock terminal; the first power signal is different from the second power signal. The second noise reduction circuit is electrically connected to the third node, the first output terminal, the second output terminal, the third power supply terminal, and the fourth power supply terminal, and is configured to, under the control of the third node, control the first output terminal to output the third power signal provided by the third power supply terminal, and control the second output terminal to output the fourth power signal provided by the fourth power supply terminal.

[0020] In some exemplary embodiments, the first control circuit includes: a fifth transistor, the gate of which is electrically connected to the first clock terminal, the first terminal of which is electrically connected to the first power supply terminal, and the second terminal of which is electrically connected to the second node. The second control circuit includes: a thirteenth transistor, the gate of which is electrically connected to the first clock terminal, the first terminal of which is electrically connected to the second power supply terminal, and the second terminal of which is electrically connected to the third node. The first noise reduction circuit includes: a ninth transistor and a tenth transistor, the gate of which is electrically connected to the second node, the first terminal of which is electrically connected to the third power supply terminal, and the second terminal of which is electrically connected to the first output terminal; the gate of which is electrically connected to the second node, the first terminal of which is electrically connected to the fourth power supply terminal, and the second terminal of which is electrically connected to the second output terminal. The second noise reduction circuit includes an eleventh transistor and a twelfth transistor. The gate of the eleventh transistor is electrically connected to the third node, the first terminal of the eleventh transistor is electrically connected to the third power supply terminal, and the second terminal of the eleventh transistor is electrically connected to the first output terminal. The gate of the twelfth transistor is electrically connected to the third node, the first terminal of the twelfth transistor is electrically connected to the fourth power supply terminal, and the second terminal of the twelfth transistor is electrically connected to the second output terminal.

[0021] In some exemplary embodiments, the drive control circuit further includes a first pull-down circuit and a second pull-down circuit. The first pull-down circuit is electrically connected to the first node, the second node, and the first clock terminal, and is configured to write a first clock signal provided by the first clock terminal to the second node under the control of the first node; or, it is electrically connected to the first node, the second node, and the fourth power supply terminal, and is configured to write a fourth power signal provided by the fourth power supply terminal to the second node under the control of the first node. The second pull-down circuit is electrically connected to the first node, the third node, and the first clock terminal, and is configured to write the first clock signal provided by the first clock terminal to the third node under the control of the first node; or, it is electrically connected to the first node, the third node, and the fourth power supply terminal, and is configured to write the fourth power signal provided by the fourth power supply terminal to the third node under the control of the first node.

[0022] In some exemplary embodiments, the first pull-down circuit includes: a sixth transistor, the gate of which is electrically connected to the first node, a first terminal of which is electrically connected to the first clock terminal or the fourth power supply terminal, and a second terminal of which is electrically connected to the second node. The second pull-down circuit includes: a fourteenth transistor, the gate of which is electrically connected to the first node, a first terminal of which is electrically connected to the first clock terminal or the fourth power supply terminal, and a second terminal of which is electrically connected to the third node.

[0023] In some exemplary embodiments, the drive control circuit further includes: a second node capacitor and a third node capacitor; the first electrode of the second node capacitor is electrically connected to the second node, and the second electrode of the second node capacitor is electrically connected to the fourth power supply terminal; the first electrode of the third node capacitor is electrically connected to the third node, and the second electrode of the third node capacitor is electrically connected to the fourth power supply terminal.

[0024] In some exemplary embodiments, the drive control circuit further includes a third pull-down circuit, a fourth pull-down circuit, and a fifth pull-down circuit. The third pull-down circuit is electrically connected to the first node, the second node, and the fourth power supply terminal, and is configured to write a fourth power signal provided by the fourth power supply terminal to the first node under the control of the second node. The fourth pull-down circuit is electrically connected to the first node, the third node, and the fourth power supply terminal, and is configured to write the fourth power signal provided by the fourth power supply terminal to the first node under the control of the third node. The fifth pull-down circuit is electrically connected to the first node, a first control terminal, and the fourth power supply terminal, and is configured to write the fourth power signal provided by the fourth power supply terminal to the first node under the control of the first control terminal.

[0025] In some exemplary embodiments, the third pull-down circuit includes: two seventh transistors, the gates of which are electrically connected to the second node; the first terminal of the first seventh transistor is electrically connected to the second terminal of the second seventh transistor; the second terminal of the first seventh transistor is electrically connected to the first node; and the first terminal of the second seventh transistor is electrically connected to the fourth power supply terminal. The fourth pull-down circuit includes: two eighth transistors, the gates of which are electrically connected to the third node; the first terminal of the first eighth transistor is electrically connected to the second terminal of the second eighth transistor; the second terminal of the first eighth transistor is electrically connected to the first node; and the first terminal of the second eighth transistor is electrically connected to the fourth power supply terminal. The fifth pull-down circuit includes: two second transistors, the gates of which are electrically connected to the first control terminal; the first terminal of the first second transistor is electrically connected to the second terminal of the second second transistor; the second terminal of the first second transistor is electrically connected to the first node; and the first terminal of the second second transistor is electrically connected to the fourth power supply terminal.

[0026] In some exemplary embodiments, the drive control circuit further includes a first pull-up circuit. The first pull-up circuit is electrically connected to the fourth node, the second control terminal, and the fifth power supply terminal, and is configured to write a fifth power signal provided by the fifth power supply terminal to the fourth node under the control of the second control terminal. The first terminal of the first seventh transistor and the second terminal of the second seventh transistor, the first terminal of the first eighth transistor and the second terminal of the second eighth transistor, and the first terminal of the first second transistor and the second terminal of the second second transistor are all electrically connected to the fourth node.

[0027] In some exemplary embodiments, the input circuit includes: two first transistors, the gates of the two first transistors being electrically connected to the input terminal, the first terminal of the first first transistor being electrically connected to the input terminal, the second terminal of the first first transistor being electrically connected to the first terminal of the second first transistor, and the second terminal of the second first transistor being electrically connected to the first node.

[0028] In some exemplary embodiments, the drive control circuit further includes a second pull-up circuit. The second pull-up circuit is electrically connected to the fifth node, the second control terminal, and the fifth power supply terminal, and is configured to write a fifth power signal provided by the fifth power supply terminal to the fifth node under the control of the second control terminal; the second terminal of the first transistor and the first terminal of the second first transistor are both electrically connected to the fifth node.

[0029] In some exemplary embodiments, the second control terminal is electrically connected to the first node.

[0030] In some exemplary embodiments, the second control terminal is electrically connected to the second output terminal.

[0031] In some exemplary embodiments, the first output circuit includes: a third transistor, or a third transistor and a first capacitor; the gate of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second clock terminal, and the second electrode of the third transistor is electrically connected to the first output terminal; the first electrode of the first capacitor is electrically connected to the first node, and the second electrode of the first capacitor is electrically connected to the first output terminal. The second output circuit includes: a fourth transistor, or a fourth transistor and a second capacitor; the gate of the fourth transistor is electrically connected to the first node, the first electrode of the fourth transistor is electrically connected to the third clock terminal, and the second electrode of the fourth transistor is electrically connected to the second output terminal; the first electrode of the second capacitor is electrically connected to the first node, and the second electrode of the second capacitor is electrically connected to the second output terminal.

[0032] In some exemplary embodiments, the drive control circuit further includes a first reset circuit. The first reset circuit is electrically connected to the first node, the first reset terminal, and the fourth power supply terminal, and is configured to write a fourth power signal provided by the fourth power supply terminal to the first node under the control of the first reset terminal.

[0033] In some exemplary embodiments, the first reset circuit includes: two seventeenth transistors, the gates of the two seventeenth transistors being electrically connected to the first reset terminal, the first terminal of the first seventeenth transistor being electrically connected to the second terminal of the second seventeenth transistor, the second terminal of the first seventeenth transistor being electrically connected to the first node, and the first terminal of the second seventeenth transistor being electrically connected to the fourth power supply terminal.

[0034] In some exemplary embodiments, the drive control circuit further includes a second reset circuit. The second reset circuit is electrically connected to the first control terminal, the first output terminal, and the third power supply terminal, and is configured to control the first output terminal to output the third power supply signal provided by the third power supply terminal under the control of the first control terminal.

[0035] In some exemplary embodiments, the second clock terminal and the third clock terminal provide the same signal; or, the effective level of the second clock signal provided by the second clock terminal is higher than the effective level of the third clock signal provided by the third clock terminal.

[0036] On the other hand, this embodiment provides a gate driving circuit, including multiple cascaded driving control circuits as described above. The input terminal of the first-stage driving control circuit is electrically connected to the start signal line, and the input terminal of the (i+1)th-stage driving control circuit is electrically connected to the second output terminal of the ith-stage driving control circuit, where i is an integer greater than 0.

[0037] In some exemplary embodiments, the first control terminal of the i-th stage drive control circuit is electrically connected to the second output terminal of the (i+1)-th stage drive control circuit, and the second control terminal of the i-th stage drive control circuit is electrically connected to the second output terminal or the first node of the i-th stage drive control circuit.

[0038] In some exemplary embodiments, the first control terminal of the last-stage drive control circuit is electrically connected to the first reset terminal.

[0039] In some exemplary embodiments, the second and third clock terminals of the 4k+1 level drive control circuit are electrically connected to the first clock line, and the first clock terminal of the 4k+1 level drive control circuit is electrically connected to the second clock line; the second and third clock terminals of the 4k+2 level drive control circuit are electrically connected to the second clock line, and the first clock terminal of the 4k+2 level drive control circuit is electrically connected to the third clock line; the second and third clock terminals of the 4k+3 level drive control circuit are electrically connected to the third clock line, and the first clock terminal of the 4k+3 level drive control circuit is electrically connected to the fourth clock line; the second and fourth clock terminals of the 4k+4 level drive control circuit are electrically connected to the fourth clock line, and the first clock terminal of the 4k+4 level drive control circuit is electrically connected to the first clock line, where k is an integer greater than or equal to 0; the effective levels of the clock signals provided by the first clock line, the second clock line, the third clock line, and the fourth clock line are output sequentially without timing overlap.

[0040] On the other hand, this embodiment provides a display substrate, including: a display area and a non-display area located around the display area. The non-display area is provided with a gate driving circuit. The gate driving circuit includes multiple cascaded driving control circuits. The driving control circuit includes: an input circuit, a first control circuit, a first output circuit, a second output circuit, and a first noise reduction circuit. An input circuit is electrically connected to an input terminal and a first node, configured to write an input signal provided by the input terminal to the first node under the control of the input terminal; a first control circuit is electrically connected to a first clock terminal, a first power supply terminal, and a second node, configured to write a first power supply signal provided by the first power supply terminal to the second node under the control of the effective level of the first clock signal provided by the first clock terminal; a first output circuit is electrically connected to the first node, a second clock terminal, and a first output terminal, configured to control the first output terminal to output a second clock signal provided by the second clock terminal under the control of the first node; a second output circuit is electrically connected to the first node, a third clock terminal, and a second output terminal, configured to control the second output terminal to output a third clock signal provided by the third clock terminal under the control of the first node; a first noise reduction circuit is electrically connected to a second node, a first output terminal, a second output terminal, a third power supply terminal, and a fourth power supply terminal, configured to control the first output terminal to output a third power supply signal provided by the third power supply terminal under the control of the second node, and control the second output terminal to output a fourth power supply signal provided by the fourth power supply terminal. The first control circuit, the input circuit, the first noise reduction circuit, and the first output circuit are arranged along a first direction, the second output circuit is located on one side of the first control circuit along a second direction, and the second output circuit and the first output circuit are located on both sides of the input circuit along the first direction; the first direction and the second direction intersect.

[0041] In some exemplary embodiments, the drive control circuit further includes: a first node capacitor, a first electrode of the first node capacitor being electrically connected to the first node, and a second electrode of the first node capacitor being electrically connected to the fourth power supply terminal; the first node capacitor is located between the first noise reduction circuit and the first output circuit along the first direction, and is adjacent to the first output circuit in the first direction.

[0042] In some exemplary embodiments, the first output circuit includes: a third transistor and a first capacitor; the gate of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second clock terminal, and the second electrode of the third transistor is electrically connected to the first output terminal; the first electrode of the first capacitor is electrically connected to the first node, and the second electrode of the first capacitor is electrically connected to the first output terminal. The first capacitor is located between the first node capacitor and the third transistor in the first direction; the first capacitor and the first node capacitor are adjacent along the first direction, and the first electrode of the first capacitor and the first electrode of the first node capacitor are integrally formed; the second electrode of the first capacitor and the second electrode of the third transistor are integrally formed.

[0043] In some exemplary embodiments, the second output circuit includes: a fourth transistor and a second capacitor; the gate of the fourth transistor is electrically connected to the first node, the first electrode of the fourth transistor is electrically connected to the third clock terminal, and the second electrode of the fourth transistor is electrically connected to the second output terminal; the first electrode of the second capacitor is electrically connected to the first node; the fourth transistor and the second capacitor are adjacent in the first direction, the gate of the fourth transistor and the first electrode of the second capacitor are integrally formed, and the second electrode of the second capacitor and the second output terminal are integrally formed.

[0044] In some exemplary embodiments, the drive control circuit further includes: a second control circuit, a second noise reduction circuit, a first pull-down circuit, and a second pull-down circuit. The second control circuit is electrically connected to the first clock terminal, the third node, and the second power supply terminal, and is configured to write a second power signal provided by the second power supply terminal to the third node under the control of the effective level of the first clock signal provided by the first clock terminal; the first power signal is different from the second power signal. The second noise reduction circuit is electrically connected to the third node, the first output terminal, the second output terminal, the third power supply terminal, and the fourth power supply terminal, and is configured to, under the control of the third node, control the first output terminal to output the third power signal provided by the third power supply terminal, and control the second output terminal to output the fourth power signal provided by the fourth power supply terminal. The first pull-down circuit is electrically connected to the first node, the second node, and the first clock terminal, and is configured to, under the control of the first node, write the first clock signal provided by the first clock terminal to the second node; or, is electrically connected to the first node, the second node, and the fourth power supply terminal, and is configured to, under the control of the first node, write the fourth power signal provided by the fourth power supply terminal to the second node. The second pull-down circuit is electrically connected to the first node, the third node, and the first clock terminal, and is configured to write a first clock signal provided by the first clock terminal to the third node under the control of the first node; or, it is electrically connected to the first node, the third node, and the fourth power supply terminal, and is configured to write a fourth power signal provided by the fourth power supply terminal to the third node under the control of the first node. The second control circuit is located between the first control circuit and the second output circuit in the second direction; the first pull-down circuit and the second pull-down circuit are arranged adjacent to each other in the first direction, and are located on the side of the first control circuit closer to the input circuit in the first direction; the transistors included in the second noise reduction circuit and the transistors included in the first noise reduction circuit are spaced apart in the first direction.

[0045] In some exemplary embodiments, the first noise reduction circuit includes: a ninth transistor and a tenth transistor, wherein the gate of the ninth transistor is electrically connected to the second node, the first terminal of the ninth transistor is electrically connected to the third power supply terminal, and the second terminal of the ninth transistor is electrically connected to the first output terminal; the gate of the tenth transistor is electrically connected to the second node, the first terminal of the tenth transistor is electrically connected to the fourth power supply terminal, and the second terminal of the tenth transistor is electrically connected to the second output terminal. The second noise reduction circuit includes: an eleventh transistor and a twelfth transistor, wherein the gate of the eleventh transistor is electrically connected to the third node, the first terminal of the eleventh transistor is electrically connected to the third power supply terminal, and the second terminal of the eleventh transistor is electrically connected to the first output terminal; the gate of the twelfth transistor is electrically connected to the third node, the first terminal of the twelfth transistor is electrically connected to the fourth power supply terminal, and the second terminal of the twelfth transistor is electrically connected to the second output terminal. The tenth transistor, the twelfth transistor, the eleventh transistor, and the ninth transistor are arranged sequentially along the first direction.

[0046] In some exemplary embodiments, the drive control circuit further includes a third pull-down circuit, a fourth pull-down circuit, and a fifth pull-down circuit. The third pull-down circuit is electrically connected to the first node, the second node, and the fourth power supply terminal, and is configured to write a fourth power signal provided by the fourth power supply terminal to the first node under the control of the second node. The fourth pull-down circuit is electrically connected to the first node, the third node, and the fourth power supply terminal, and is configured to write the fourth power signal provided by the fourth power supply terminal to the first node under the control of the third node. The fifth pull-down circuit is electrically connected to the first node, a first control terminal, and the fourth power supply terminal, and is configured to write the fourth power signal provided by the fourth power supply terminal to the first node under the control of the first control terminal. The third and fourth pull-down circuits are arranged adjacent to each other along the first direction, located between the input circuit and the first output circuit in the first direction, and on the same side of the first noise reduction circuit and the second noise reduction circuit along the second direction; the fifth pull-down circuit is located between the second pull-down circuit and the input circuit along the first direction.

[0047] In some exemplary embodiments, the drive control circuit further includes: a second node capacitor and a third node capacitor; the first electrode of the second node capacitor is electrically connected to the second node, and the second electrode of the second node capacitor is electrically connected to the fourth power supply terminal; the first electrode of the third node capacitor is electrically connected to the third node, and the second electrode of the third node capacitor is electrically connected to the fourth power supply terminal. The second node capacitor is located between the third pull-down circuit and the fourth pull-down circuit in the first direction. The third node capacitor is located between the two transistors included in the fourth pull-down circuit in the first direction; the second electrode of the second node capacitor and the second electrode of the third node capacitor are of a single integrated structure.

[0048] In some exemplary embodiments, the drive control circuit further includes a first pull-up circuit and a second pull-up circuit. The first pull-up circuit is electrically connected to the fourth node, the second control terminal, and the fifth power supply terminal, and is configured to write a fifth power signal provided by the fifth power supply terminal to the fourth node under the control of the second control terminal. The second pull-up circuit is electrically connected to the fifth node, the second control terminal, and the fifth power supply terminal, and is configured to write a fifth power signal provided by the fifth power supply terminal to the fifth node under the control of the second control terminal. Both transistors included in the input circuit are electrically connected to the fifth node, and the third, fourth, and fifth pull-down circuits are all electrically connected to the fourth node; the first pull-up circuit and the second pull-up circuit are arranged adjacent to each other along the first direction, located between the input circuit and the second output circuit in the first direction, and located on the same side of the fifth pull-down circuit along the second direction.

[0049] In some exemplary embodiments, the driving control circuit includes a plurality of transistors, the gates of which include interconnected bottom gates and top gates. In a direction perpendicular to the display substrate, the display substrate includes a substrate and a first conductive layer, a semiconductor layer, and a second conductive layer disposed on the substrate; the first conductive layer includes the bottom gates of the plurality of transistors; the semiconductor layer includes the active layer of the plurality of transistors; and the second conductive layer includes the top gates of the plurality of transistors.

[0050] In some exemplary embodiments, the drive control circuit is electrically connected to multiple clock lines and multiple power lines, wherein the multiple clock lines are located in the first conductive layer, and at least one of the multiple power lines is located in the first conductive layer or the second conductive layer.

[0051] In some exemplary embodiments, the drive control circuit includes: a first structure transistor and a second structure transistor, wherein the gate of the first structure transistor is located on the side of the active layer of the first structure transistor away from the substrate; the second structure transistor includes a top gate located on the side of the active layer of the second structure transistor away from the substrate, and a bottom gate located on the side of the active layer of the second structure transistor close to the substrate, the bottom gate being electrically connected to the top gate.

[0052] In some exemplary embodiments, the transistors included in the first control circuit, the second control circuit, the first noise reduction circuit, and the second noise reduction circuit are first structure transistors.

[0053] In some exemplary embodiments, the display substrate further includes: a detection circuit electrically connected to a detection control line, a detection signal line, and a first output terminal of the drive control circuit, configured to write a detection signal provided by the detection signal line to the first output terminal of the drive control circuit under the control of the detection control line; the detection circuit is located in the non-display area and is located in the first direction on the side of the first output circuit of the drive control circuit closer to the display area.

[0054] In some exemplary embodiments, the display substrate further includes: a plurality of gate lines, a first electrostatic discharge circuit, and a second electrostatic discharge circuit. The plurality of gate lines are located in the display area; the first electrostatic discharge circuit is electrically connected to a common electrode and a short-circuit ring; the second electrostatic discharge circuit is electrically connected to the short-circuit ring and the gate lines; the first electrostatic discharge circuit and the second electrostatic discharge circuit are located in the non-display area, and are positioned on the side of the detection circuit closer to the display area in the first direction.

[0055] On the other hand, this embodiment provides a display device including the display substrate as described above.

[0056] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0057] Overview of the attached figures

[0058] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0059] Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0060] Figure 2 is a planar schematic diagram of the region where the first sub-pixel is located according to at least one embodiment of the present disclosure;

[0061] Figure 3 is a partial cross-sectional view along the PP' direction in Figure 2;

[0062] Figure 4 is a planar schematic diagram of the area where the first sub-pixel is located after the first conductive layer is formed in Figure 2;

[0063] Figure 5 is a planar schematic diagram of the region where the first sub-pixel is located after the semiconductor layer is formed in Figure 2;

[0064] Figure 6 is a planar schematic diagram of the area where the first sub-pixel is located after the formation of the first type of via in Figure 2;

[0065] Figure 7A is a planar schematic diagram of the region where the first sub-pixel is located after the second conductive layer is formed in Figure 2;

[0066] Figure 7B is a schematic diagram of the second conductive layer in Figure 7A;

[0067] Figure 7C is a schematic diagram of the second insulating layer in Figure 2;

[0068] Figure 8 is a planar schematic diagram of the area where the first sub-pixel is located after the second type of via is formed in Figure 2;

[0069] Figure 9A is a planar schematic diagram of the region where the first sub-pixel is located after the third conductive layer is formed in Figure 2;

[0070] Figure 9B is a schematic diagram of the third conductive layer in Figure 9A;

[0071] Figure 10 is a planar schematic diagram of the first sub-pixel region after the formation of the third type of via in Figure 2;

[0072] Figure 11 is a planar schematic diagram of the third conductive layer, the third type of via, and the fourth conductive layer in Figure 2;

[0073] Figure 12 is an equivalent circuit diagram of the first sub-pixel of at least one embodiment of the present disclosure;

[0074] Figure 13A is a planar schematic diagram of two first sub-pixels sharing a common gate line according to at least one embodiment of the present disclosure;

[0075] Figure 13B is a schematic diagram of the first conductive layer, semiconductor layer and second conductive layer in Figure 13;

[0076] Figure 13C is a schematic diagram of the first conductive layer, semiconductor layer, second conductive layer and third conductive layer in Figure 13A;

[0077] Figure 14 is an equivalent circuit diagram of two first sub-pixels sharing a common gate line according to at least one embodiment of the present disclosure;

[0078] Figure 15 is another partial planar schematic diagram of the region where the first sub-pixel is located according to at least one embodiment of the present disclosure;

[0079] Figure 16 is another partial planar schematic diagram of the region where the first sub-pixel is located according to at least one embodiment of the present disclosure;

[0080] Figure 17 is an equivalent circuit diagram of the second sub-pixel of at least one embodiment of the present disclosure;

[0081] Figure 18 is a partial cross-sectional schematic diagram of the display boundary area according to at least one embodiment of the present disclosure;

[0082] Figure 19 is another equivalent circuit diagram of the second sub-pixel of at least one embodiment of the present disclosure;

[0083] Figure 20 is a schematic diagram of the structure of a drive control circuit according to at least one embodiment of the present disclosure;

[0084] Figure 21 is another structural schematic diagram of the drive control circuit of at least one embodiment of the present disclosure;

[0085] Figure 22 is another structural schematic diagram of the drive control circuit of at least one embodiment of the present disclosure;

[0086] Figure 23 is another structural schematic diagram of the drive control circuit of at least one embodiment of the present disclosure;

[0087] Figure 24 is another structural schematic diagram of the drive control circuit of at least one embodiment of the present disclosure;

[0088] Figure 25 is an equivalent circuit diagram of the drive control circuit of at least one embodiment of the present disclosure;

[0089] Figure 26 is a timing diagram of the operation of the drive control circuit of at least one embodiment of the present disclosure;

[0090] Figure 27A is a schematic diagram of the state of the drive control circuit in the first stage according to at least one embodiment of the present disclosure;

[0091] Figure 27B is a schematic diagram of the state of the drive control circuit in the second stage according to at least one embodiment of the present disclosure;

[0092] Figure 27C is a schematic diagram of the state of the drive control circuit in the third stage according to at least one embodiment of the present disclosure;

[0093] Figure 28 is a schematic diagram of the voltage change of the first node in at least one embodiment of the present disclosure;

[0094] Figure 29 is another equivalent circuit diagram of the drive control circuit of at least one embodiment of the present disclosure;

[0095] Figure 30 is a timing diagram of the fifth node of the drive control circuit shown in Figure 29;

[0096] Figure 31 is another equivalent circuit diagram of the drive control circuit of at least one embodiment of the present disclosure;

[0097] Figure 32 is another equivalent circuit diagram of the drive control circuit of at least one embodiment of the present disclosure;

[0098] Figure 33 is another equivalent circuit diagram of the drive control circuit of at least one embodiment of the present disclosure;

[0099] Figure 34 is another equivalent circuit diagram of the drive control circuit of at least one embodiment of the present disclosure;

[0100] Figure 35 is another equivalent circuit diagram of the drive control circuit of at least one embodiment of the present disclosure;

[0101] Figure 36 is another equivalent circuit diagram of the drive control circuit of at least one embodiment of the present disclosure;

[0102] Figure 37 is another equivalent circuit diagram of the drive control circuit of at least one embodiment of the present disclosure;

[0103] Figure 38 is a schematic diagram of a gate driving circuit according to at least one embodiment of the present disclosure;

[0104] Figure 39 is an equivalent circuit diagram of the drive control circuit and the detection circuit of at least one embodiment of the present disclosure;

[0105] Figure 40 is an equivalent circuit diagram of an electrostatic discharge circuit according to at least one embodiment of the present disclosure;

[0106] Figures 41A to 41C are partial planar schematic diagrams of the non-display area of ​​a display substrate according to at least one embodiment of the present disclosure;

[0107] Figure 42A is a schematic diagram of the first conductive layer in Figure 41A;

[0108] Figure 42B is a schematic diagram of the first conductive layer in Figure 41B;

[0109] Figure 42C is a schematic diagram of the first conductive layer in Figure 41C;

[0110] Figure 43A is a schematic diagram of the semiconductor layer in Figure 41A;

[0111] Figure 43B is a schematic diagram of the semiconductor layer in Figure 41B;

[0112] Figure 43C is a schematic diagram of the semiconductor layer in Figure 41C;

[0113] Figure 44A is a schematic diagram of the semiconductor layer and the second conductive layer in Figure 41A;

[0114] Figure 44B is a schematic diagram of the semiconductor layer and the second conductive layer in Figure 41B.

[0115] Figure 44C is a schematic diagram of the semiconductor layer and the second conductive layer in Figure 41C;

[0116] Figure 45 is a schematic diagram of the tenth transistor in Figure 41B;

[0117] Figure 46 is a partial cross-sectional view along the AA' direction in Figure 45;

[0118] Figure 47 is a partial cross-sectional view along the BB' direction in Figure 45;

[0119] Figure 48A is a schematic diagram of a first-structure transistor according to at least one embodiment of the present disclosure;

[0120] Figure 48B is a schematic diagram of a second structure transistor according to at least one embodiment of the present disclosure;

[0121] Figure 49 is a cross-sectional structural schematic diagram of a display device according to at least one embodiment of the present disclosure;

[0122] Figure 50 is a schematic diagram of the connection structure of a display device according to at least one embodiment of the present disclosure.

[0123] Detailed Explanation

[0124] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0125] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0126] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0127] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0128] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "coupled" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or link; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0129] In this specification, "connection" can include "electrical connection." An "electrical connection" includes the situation where constituent elements are connected together by a component that has some electrical function. There are no particular limitations on the "component that has some electrical function," as long as it enables the transmission of electrical signals between the connected constituent elements. Examples of "components that have some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with multiple functions.

[0130] In this specification, a transistor is a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between its drain (drain terminal, drain region, or drain electrode) and its source (source terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region through which current primarily flows.

[0131] In this specification, the first terminal can be the drain and the second terminal can be the source, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged. Additionally, the gate can also be called the control terminal.

[0132] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0133] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined. They can be approximate circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, such as chamfers, curved edges, and other variations.

[0134] In this disclosure, "about" and "approximately" refer to situations where there are no strict limits and the process and measurement errors are allowed. In this disclosure, "same" can include numerical values ​​differing by no more than 10%.

[0135] In this disclosure, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped solid. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In this disclosure, "A extends along direction B" refers to "the main part of A extends along direction B".

[0136] The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, or that the surfaces of A and B closest to the substrate are at substantially the same distance from the substrate, or that the surfaces of A and B closest to the substrate are in direct contact with the same film layer. The phrase "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. The phrase "the shape of A" in this disclosure refers to the shape of the orthographic projection of A onto the substrate.

[0137] In this disclosure, the effective level includes the level at which a transistor is turned on. For example, the effective level for turning on a P-type transistor is a low level, and the effective level for turning on an N-type transistor is a high level.

[0138] Electrophoretic displays, with their energy-saving and eye-friendly characteristics, are widely used in the field of e-reading. To achieve optimal display effects, electrophoretic display devices require high pixel density (PPI). However, a higher PPI typically leads to a reduction in the storage capacitance within sub-pixels, which is detrimental to the voltage stability of the pixel electrodes before the display refreshes. On the other hand, to increase the display colors in e-readers, three-color (e.g., black, white, red), four-color (e.g., black, white, red, yellow), or multi-color e-readers have gradually emerged. To improve the response speed of multi-color charged particles, higher driving voltages are usually required. Correspondingly, gate drive circuits capable of withstanding higher voltages need to be designed.

[0139] This embodiment provides a display substrate, including: a substrate, a plurality of first sub-pixels disposed on the substrate, and a plurality of data lines. At least one first sub-pixel includes: a first switching transistor, a first pixel electrode, a second pixel electrode, a first common electrode, and a second common electrode. The first switching transistor includes a first active layer, which includes a first channel region and a first region and a second region located on both sides of the first channel region. The first region is connected to the data lines, the second region is connected to the first pixel electrode, and the second pixel electrode is connected to the first pixel electrode. The orthographic projection of the first pixel electrode onto the substrate at least partially overlaps with the orthographic projection of the first common electrode onto the substrate, and the orthographic projection of the second pixel electrode onto the substrate at least partially overlaps with the orthographic projection of the second common electrode onto the substrate. The plurality of data lines are located on the side of the first active layer closest to the substrate, and the plurality of data lines are disposed in the same layer as the first common electrode.

[0140] The display substrate provided in this embodiment uses a first common electrode and a first pixel electrode to form a first storage capacitor, and uses a second common electrode and a second pixel electrode to form a second storage capacitor. The first storage capacitor and the second storage capacitor are designed in parallel, which can help increase the size of the storage capacitor of the first sub-pixel and help the voltage stability of the pixel electrode before the display screen refreshes.

[0141] In some exemplary embodiments, the display substrate may further include: a plurality of light-shielding electrodes disposed on the substrate, wherein the orthographic projection of the first channel region of the first switching transistor onto the substrate may be located within the orthographic projection range of the light-shielding electrodes onto the substrate, and the plurality of light-shielding electrodes are disposed on the same layer as the plurality of data lines. This example utilizes light-shielding electrodes to shield the first channel region of the first switching transistor, which can prevent external light sources from affecting the performance of the transistor.

[0142] The following examples illustrate the solution of this embodiment.

[0143] Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 1, the display substrate may include a display area AA and a non-display area NA. For example, the non-display area NA may be located around the display area AA. The non-display area NA may include: an upper border area and a lower border area located on both sides of the display area AA along a second direction D2, and a left border area and a right border area located on both sides of the display area AA along a first direction D1. The first direction D1 and the second direction D2 may intersect; for example, the first direction D1 may be perpendicular to the second direction D2.

[0144] In some examples, the display area AA may include a display center area A1 and a display boundary area A2 surrounding the display center area A1. The display center area A1 may have multiple first sub-pixels PX, and the display boundary area A2 may have multiple second sub-pixels. The structure of the first sub-pixels may differ from the structure of the second sub-pixels.

[0145] Figure 2 is a plan view of the region where the first sub-pixel is located according to at least one embodiment of the present disclosure. Figure 3 is a partial cross-sectional view along the PP' direction in Figure 2. In some examples, as shown in Figure 2, the first sub-pixel may include: a first switching transistor T1; the first switching transistor T1 may be electrically connected to a data line DL1 extending along the second direction D2 and a gate line GL extending along the first direction D1, and is located within the sub-pixel region enclosed by adjacent data lines (such as adjacent data lines DL1 and DL2) and the gate line GL.

[0146] In some examples, as shown in FIG3, in the direction perpendicular to the display substrate, the display substrate may include: a substrate 100, and a first conductive layer, a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a second conductive layer, a third insulating layer 103, a fourth insulating layer 104, a third conductive layer, a fifth insulating layer 105, and a fourth conductive layer sequentially stacked on the substrate 100.

[0147] The following description uses the fabrication process of a display substrate as an example to illustrate the structure of the display area of ​​the substrate. The "patterning process" mentioned in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. "Thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes.

[0148] The fabrication process of the display substrate in this exemplary embodiment may include the following steps.

[0149] (1) A substrate 100 is provided. In some examples, the substrate 100 may be a rigid substrate or a flexible substrate. For example, the material of the rigid substrate may include, but is not limited to, one or more of glass and quartz; the material of the flexible substrate may include, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. However, this embodiment is not limited in this respect.

[0150] (2) Forming a first conductive layer on the substrate 100. In some examples, a first conductive thin film is deposited on the substrate 100, and the first conductive thin film is patterned by a patterning process to form a first conductive layer.

[0151] Figure 4 is a planar schematic diagram of the region where the first sub-pixel is located after the formation of the first conductive layer in Figure 2. In some examples, as shown in Figure 4, the first conductive layer may include at least: data lines DL1 and DL2 extending along the second direction D2, a light-shielding electrode SLD, and a first common electrode EC1. The light-shielding electrode SLD and the first common electrode EC1 may be located between the data lines DL1 and DL2 in the first direction D1. The light-shielding electrode SLD may be located on one side of the first common electrode EC1 in the second direction D2. The orthographic projection of the light-shielding electrode SLD onto the substrate may be rectangular, and the orthographic projection of the first common electrode EC1 onto the substrate may also be rectangular. Two data lines may be correspondingly arranged in the region where a single first sub-pixel is located. For example, two adjacent first sub-pixels arranged along the second direction D2 may share a gate line, which helps to increase the gate turn-on time of the first switching transistor, thereby improving the charging rate of the first sub-pixel.

[0152] In some examples, the first conductive layer can be made of a metallic material, such as any one or more of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), or an alloy of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti.

[0153] (3) Forming a semiconductor layer. In some examples, a first insulating film and a semiconductor film are sequentially deposited on the substrate 100 on which the aforementioned structure is formed. The semiconductor film is patterned using a patterning process to form a first insulating layer and a semiconductor layer disposed on the substrate 100. In some examples, the material of the semiconductor layer may include an oxide semiconductor material. For example, the semiconductor layer may be one or more materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), and indium zinc tin oxide (IZTO). That is, the embodiments of this disclosure are applicable to transistors manufactured based on oxide technology.

[0154] Figure 5 is a planar schematic diagram of the region where the first sub-pixel is located after the semiconductor layer is formed in Figure 2. In some examples, as shown in Figure 5, the semiconductor layer may include: a first active layer T10 of the first switching transistor. The first active layer T10 may include: a first channel region T100, a first region T101 and a second region T102 located on both sides of the first channel region T100. The orthographic projection of the first active layer T10 onto the substrate can be a dumbbell shape set along the first direction D1. The orthographic projection of the first channel region T100 of the first active layer T10 onto the substrate can be located within the orthographic projection range of the light-shielding electrode SLD onto the substrate. By using the light-shielding electrode SLD to shield the first channel region T100, external light can be prevented from affecting the performance of the first switching transistor.

[0155] In some examples, as shown in Figure 5, the orthographic projection of the first region T101 of the first active layer T10 onto the substrate overlaps with the orthographic projection of the data line DL1 onto the substrate. The length of the overlapping portion along the first direction D1 can be 'a', and 'a' is greater than or equal to 2 micrometers. This arrangement in this example ensures that the subsequently formed first conductive block can be simultaneously connected to both the first region T101 of the first active switching layer T10 and the data line DL1 through a first-type via.

[0156] In some examples, the channel region of the active layer of the transistor may be undoped and possess semiconductor characteristics. The first and second regions can be doped regions on either side of the channel region, and are doped with impurities, thus possessing conductivity. The impurities can vary depending on the type of transistor. In some examples, the doped regions of the active layer can be interpreted as the source or drain electrodes of the transistor. For example, the first region of the active layer can be interpreted as the first electrode of the transistor, and the second region of the active layer can be interpreted as the second electrode of the transistor. The portions of the active layer between transistors can be interpreted as doped wiring, which can be used to electrically connect the transistors. This embodiment is not limited in this respect.

[0157] (4) A second insulating film is deposited on the substrate 100 that forms the aforementioned structure, and the second insulating film is patterned to form a plurality of first-type vias, such as first-type vias VIA1-1, VIA1-2 and VIA1-3.

[0158] Figure 6 is a planar schematic diagram of the region where the first sub-pixel is located after the formation of the first type of via in Figure 2. In some examples, as shown in Figure 6, the orthographic projections of the first type of vias VIA1-1, VIA1-2, and VIA1-3 onto the substrate can all be rectangular. The second insulating film and the first insulating film within the first type of via VIA1-1 can be removed, exposing a portion of the surface of the first region of the first active layer T10 and a portion of the surface of the data line DL1. The second insulating film within the first type of via VIA1-2 can be removed, exposing a portion of the surface of the second region of the first active layer T10. The first and second insulating films within the first type of via VIA1-3 can be removed, exposing a portion of the surface of the first common electrode EC1.

[0159] In some examples, as shown in Figure 6, a portion of the first type of via VIA1-1 overlaps with the orthographic projection of the data line DL1 onto the substrate, but this portion of the first type of via VIA1-1 does not overlap with the orthographic projection of the first active layer T10 onto the substrate. The length of this portion of the first type of via VIA1-1 along the first direction D1 can be b, and b is greater than 0, for example, b is greater than or equal to 3 micrometers. This arrangement in this example ensures the electrical connection between the subsequently formed first conductive block and the data line DL1.

[0160] (5) Forming a second conductive layer. A second conductive film is deposited on the substrate 100 on which the aforementioned structure is formed, and the second conductive film is patterned by a patterning process to form a second conductive layer; subsequently, using the second conductive layer as a mask, a large-area etching is performed on the second insulating film to form a second insulating layer.

[0161] Figure 7A is a planar schematic diagram of the region where the first sub-pixel is located after the second conductive layer is formed in Figure 2; Figure 7B is a schematic diagram of the second conductive layer in Figure 7A; Figure 7C is a schematic diagram of the second insulating layer in Figure 2.

[0162] In some examples, as shown in Figures 7A and 7B, the second conductive layer may include: a gate T11 of a first switching transistor T1, a gate line GL, a first pixel electrode EP1, a first conductive block CP1, and a second conductive block CP2. The gate line GL may extend along a first direction D1, and the gate T11 of the first switching transistor T1 may extend along a second direction D2, with the gate T11 and gate line GL forming an integral structure. The orthographic projection of the gate T11 onto the substrate may cover the orthographic projection of the first channel region T100 onto the substrate and overlap with the orthographic projection of the light-shielding electrode SLD onto the substrate. The orthographic projection of the first pixel electrode EP1 onto the substrate may be located between the orthographic projections of data lines DL1 and DL2 onto the substrate. The first pixel electrode EP1 may be connected to the second region of the first active layer T10 via a first type of via VIA1-2, thereby achieving an electrical connection between the first pixel electrode EP1 and the second electrode of the first switching transistor T1. The orthographic projections of the first conductive block CP1 and the second conductive block CP2 onto the substrate may be rectangular. The first conductive block CP1 can be connected to the first region of the first active layer T10 through a first type of via VIA1-1, and can also be connected to the data line DL1, thereby realizing the electrical connection between the first electrode of the first switching transistor T1 and the data line DL1. The second conductive block CP2 can be connected to the first common electrode EC1 through a first type of via VIA1-3.

[0163] In some examples, after the formation of the second conductive layer, the second insulating film is etched over a large area, so that only the second insulating film covered by the second conductive layer is retained, that is, the orthogonal projection of the second conductive layer onto the substrate can cover the orthogonal projection of the second insulating film onto the substrate. As shown in Figure 7C, the second insulating layer 102 in the region where the first sub-pixel is located may include: a first insulating block 1021, a second insulating block 1022, a third insulating block 1023, and a fourth insulating block 1024. The first insulating block 1021 is located on the side of the integrated structure of the gate T11 and the gate line GL of the first switching transistor near the substrate, the second insulating block 1022 is located on the side of the first pixel electrode EP1 near the substrate, the third insulating block 1023 is located on the side of the first conductive block CP1 near the substrate, and the fourth insulating block 1024 is located on the side of the second conductive block CP2 near the substrate.

[0164] In some examples, the second conductive layer can be made of a metallic material, such as any one or more of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), or an alloy of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti.

[0165] (6) On the substrate forming the aforementioned structure, a third insulating film is deposited and a fourth insulating film is coated. The fourth insulating film and the third insulating film are patterned by a patterning process to form a third insulating layer, a fourth insulating layer, and multiple second-type vias, such as second-type vias VIA2-1 and VIA2-2.

[0166] Figure 8 is a planar schematic diagram of the region where the first sub-pixel is located after the formation of the second type of via in Figure 2. In some examples, as shown in Figure 8, the orthographic projections of the second type of vias VIA2-1 and VIA2-2 onto the substrate can be rectangular. The second type of via VIA2-1 may include: a first sub-via VIA2-11 and a second sub-via VIA2-12; the second type of via VIA2-2 may include: a first sub-via VIA2-21 and a second sub-via VIA2-22. The third insulating film within the first sub-vias VIA2-11 and VIA2-21 can be removed, and the third and fourth insulating films within the second sub-vias VIA2-12 and VIA2-22 can be removed. The orthographic projection of the second sub-via VIA2-12 onto the substrate can cover the orthographic projection of the first sub-via VIA2-11 onto the substrate, and the overlapping area of ​​the first sub-vias VIA2-11 and the second sub-via VIA2-12 can expose a portion of the surface of the first pixel electrode EP1. The orthographic projection of the second sub-via VIA2-22 onto the substrate can cover the orthographic projection of the first sub-via VIA2-21 onto the substrate. The overlapping area of ​​the first sub-via VIA2-21 and the second sub-via VIA2-22 can expose part of the surface of the second conductive block CP2. In this embodiment, the position of the second type of via VIA2-1 is not limited, as long as it can achieve the electrical connection between the first pixel electrode EP1 and the subsequently formed third conductive block.

[0167] In some examples, the orthographic projection of the second type of via VIA2-2 onto the substrate may not overlap with the orthographic projection of the first type of via VIA1-3 onto the substrate, thereby ensuring the yield of the display substrate. In other examples, the orthographic projection of the second type of via VIA2-2 onto the substrate may partially overlap with the orthographic projection of the first type of via VIA1-3 onto the substrate, in order to reduce the area of ​​the second conductive block, thereby correspondingly increasing the area of ​​the first pixel electrode EP1, and thus increasing the size of the first storage capacitor.

[0168] (7) Forming a third conductive layer. In some examples, a third conductive film is deposited on the substrate on which the aforementioned structure is formed, and the third conductive film is patterned by a patterning process to form a third conductive layer.

[0169] Figure 9A is a planar schematic diagram of the region where the first sub-pixel is located after the formation of the third conductive layer in Figure 2; Figure 9B is a schematic diagram of the third conductive layer in Figure 9A. In some examples, as shown in Figures 9A and 9B, the third conductive layer may include: a second common electrode EC2 and a third conductive block CP3. The orthographic projection of the third conductive block CP3 onto the substrate is rectangular. The second common electrode EC2 has a recessed region facing the third conductive block CP3, and the third conductive block CP3 is located within this recessed region. The third conductive block CP3 can be connected to the first pixel electrode EP1 through a second type of via VIA2-1. The second common electrode EC2 can be connected to the second conductive block CP2 through a second type of via VIA2-2.

[0170] In some examples, as shown in Figure 9A, the orthographic projection of the first active layer T10 of the first switching transistor T1 onto the substrate can be located within the orthographic projection range of the second common electrode EC2 onto the substrate. This reduces the influence of ambient light on the first switching transistor T1.

[0171] In some examples, the third conductive layer can be made of a metallic material, such as any one or more of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), or an alloy of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti.

[0172] (8) On the substrate forming the aforementioned structure, a fifth insulating film is deposited, and the fifth insulating film is patterned by a patterning process to form a fifth insulating layer. The fifth insulating layer has a third type of via, such as a third type of via VIA3.

[0173] Figure 10 is a planar schematic diagram of the first sub-pixel region after the formation of the third type of via in Figure 2. In some examples, as shown in Figure 10, the fifth insulating film within the third type of via VIA3 can be removed, exposing a portion of the surface of the third conductive block CP3. The orthographic projection of the third type of via VIA3 onto the substrate can be rectangular. The orthographic projection of the third type of via VIA3 onto the substrate can at least partially overlap with the orthographic projection of the second type of via VIA2-1 onto the substrate, thereby helping to reduce the area of ​​the third conductive block CP3 and correspondingly increase the area of ​​the second common electrode EC2, thus increasing the size of the second storage capacitor.

[0174] (9) Forming a fourth conductive layer. In some examples, a fourth conductive film is deposited on the substrate on which the aforementioned structure is formed, and the fourth conductive film is patterned by a patterning process to form a fourth conductive layer.

[0175] Figure 11 is a planar schematic diagram of the third conductive layer, the third type of via, and the fourth conductive layer in Figure 2. In some examples, as shown in Figures 2 and 11, the fourth conductive layer may include a second pixel electrode EP2. The second pixel electrode EP2 can be connected to the third conductive block CP3 through a third type of via VIA3. The orthographic projection of the second pixel electrode EP2 onto the substrate at least partially overlaps with the orthographic projection of the second common electrode EC2 onto the substrate.

[0176] In some examples, the fourth conductive layer can be made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0177] In some examples, the first, second, third, and fifth insulating films can be any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. The fourth insulating film can be an organic insulating material. However, this embodiment is not limited in this respect.

[0178] In some examples, as shown in Figures 2 to 11, this example uses a nine-mask process (including the following fabrication stages: first conductive layer, semiconductor layer, first type of via, second conductive layer, second insulating layer, third insulating layer, third conductive layer, fourth insulating layer, and fourth conductive layer) to fabricate the first sub-pixel. The first switching transistor of the first sub-pixel is a metal-oxide-slim transistor with a top gate bottom contact (TGBC) structure. In this example, when the gate of the first switching transistor is off, there is no overlap between the gate and drain, the capacitance of the gate and drain is small, and the capacitance of the data line is also small.

[0179] In some examples, as shown in Figures 2 to 11, the first pixel electrode EP1 and the second pixel electrode EP2 are connected via a third conductive block CP3, and the first common electrode EC1 and the second common electrode EC2 are connected via a second conductive block CP2. The first pixel electrode EP1 and the first common electrode EC1 can form a first storage capacitor, and a first insulating layer 101 and a second insulating layer 102 exist between them. To obtain a first switching transistor T1 that meets the requirements, the first insulating layer 101 and the second insulating layer 102 have a certain thickness, resulting in a relatively small first storage capacitor. The second pixel electrode EP2 and the second common electrode EC2 can form a second storage capacitor, and a fifth insulating layer 105 exists between them. The fifth insulating layer 105 has a relatively small thickness, resulting in a relatively large second storage capacitor. The first and second storage capacitors are connected in parallel, such that the total storage capacitor of the first sub-pixel is the sum of the capacitances of the first and second storage capacitors. The first sub-pixel provided in this example can have a high storage capacitor.

[0180] Figure 12 is an equivalent circuit diagram of a first sub-pixel according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 12, the first sub-pixel can be equivalent to a circuit structure including one transistor and two capacitors. The first sub-pixel may include: a first switching transistor T1, a first storage capacitor Cst1, and a second storage capacitor Cst2. The gate of the first switching transistor T1 is electrically connected to the gate line GL, the first electrode of the first switching transistor T1 is electrically connected to the data line DL, and the second electrode of the first switching transistor T1 is electrically connected to the first electrode of the first storage capacitor Cst1 and the first electrode of the second storage capacitor Cst2; the second electrode of the first storage capacitor Cst1 and the second electrode of the second storage capacitor Cst2 are electrically connected and electrically connected to the common voltage line COM. The first storage capacitor Cst1 and the second storage capacitor Cst2 are connected in parallel. The first electrode of the first storage capacitor Cst1 is equivalent to the aforementioned first pixel electrode, and the second electrode of the first storage capacitor Cst1 is equivalent to the aforementioned first common electrode; the first electrode of the second storage capacitor Cst2 is equivalent to the aforementioned second pixel electrode, and the second electrode of the second storage capacitor Cst2 is equivalent to the aforementioned second common electrode.

[0181] Figure 13A is a planar schematic diagram of two first sub-pixels sharing a common gate line according to at least one embodiment of the present disclosure; Figure 13B is a schematic diagram of the first conductive layer, semiconductor layer, and second conductive layer in Figure 13A; Figure 13C is a schematic diagram of the first conductive layer, semiconductor layer, second conductive layer, and third conductive layer in Figure 13A. Figure 14 is an equivalent circuit diagram of two first sub-pixels sharing a common gate line according to at least one embodiment of the present disclosure.

[0182] In some examples, multiple first sub-pixels arranged along the first direction D1 form a row of sub-pixels, and two adjacent rows of sub-pixels arranged along the second direction D2 form a group of sub-pixels. The gate of the first switching transistor in each group of sub-pixels is connected to the same gate line GL, and the gate line GL may be located in the middle of the two rows of sub-pixels within the group of sub-pixels along the second direction D2. Figures 13A to 13C illustrate two first sub-pixels located in adjacent rows as an example. Two first sub-pixels located in adjacent rows and arranged along the second direction D2 can be a repeating unit. Multiple repeating units can be arranged in an array along the first direction D1 and the second direction D2.

[0183] In some examples, as shown in Figures 13A to 13C, the first sub-pixel connected to data line DL1 and the first sub-pixel connected to data line DL2 can be located in the middle of data lines DL1 and DL2, and on both sides of gate line GL along the second direction D2. A repeating unit may include a first sub-pixel connected to data line DL1 and a first sub-pixel connected to data line DL2. The gates of the first switching transistor T1a and the second switching transistor T1b within the repeating unit can be integral with the gate line GL and located in the second conductive layer. The first switching transistor T1a can overlap with the first switching transistor T1b when rotated 180 degrees counterclockwise.

[0184] In some examples, the first common electrodes EC1a and EC1b may be located in the first conductive layer; the first pixel electrodes EP1a and EP1b may be located in the second conductive layer; the second common electrodes EC2a and EC2b may be located in the third conductive layer, and the second common electrodes EC2a and EC2b are an integral structure; the second pixel electrodes EP2a and EP2b may be located in the fourth conductive layer.

[0185] In some examples, the end of the first common electrode EC1a furthest from the gate line GL can be flush with the end of the second common electrode EC2a furthest from the gate line GL, and the end of the first common electrode EC1b furthest from the gate line GL can be flush with the end of the second common electrode EC2b furthest from the gate line GL. This maximizes the area of ​​the first common electrode, which helps improve the uniformity of the common voltage transmitted by the first common electrode, thereby improving image quality. The orthographic projections of the first and second common electrodes onto the substrate do not overlap with the orthographic projections of the data lines DL1 and DL2 onto the substrate, reducing the capacitance between the data lines and the common electrodes.

[0186] In some examples, as shown in Figure 14, a repeating unit including two first sub-pixels can be equivalent to a circuit structure including two transistors and four capacitors. The repeating unit may include: first switching transistors T1a and T1b, first storage capacitors Cst1_1 and Cst1_2, and second storage capacitors Cst2_1 and Cst2_2. The gates of the first switching transistors T1a and T1b are both electrically connected to the gate line GL; the first electrode of the first switching transistor T1a is electrically connected to the data line DL1, and the second electrode of the first switching transistor T1a is electrically connected to the first electrode of the first storage capacitor Cst1_1 (i.e., the first pixel electrode EP1a) and the first electrode of the second storage capacitor Cst2_1 (i.e., the first pixel electrode EP2a); the second electrode of the first storage capacitor Cst1_1 (i.e., the first common electrode EC1a) and the second electrode of the second storage capacitor Cst2_1 (i.e., the first common electrode EC2a) are also electrically connected. The first electrode of the first switching transistor T1b is electrically connected to the data line DL2, and the second electrode of the first switching transistor T1b is electrically connected to the first electrode (i.e., the first pixel electrode EP1b) of the first storage capacitor Cst1_2 and the first electrode (i.e., the first pixel electrode EP2b) of the second storage capacitor Cst2_2. The second electrode (i.e., the first common electrode EC1b) of the first storage capacitor Cst1_2 and the second electrode (i.e., the first common electrode EC2b) of the second storage capacitor Cst2_2 are electrically connected and electrically connected to the common voltage line COM.

[0187] The display substrate in this example uses a design where adjacent rows of sub-pixels share a common gate line, which can increase the charging time of the first sub-pixel and facilitate a higher charging rate. The remaining structure of the first sub-pixel in this example can be referred to the description in the foregoing embodiments, and therefore will not be repeated here.

[0188] Figure 15 is another partial planar schematic diagram of the region where the first sub-pixel is located, according to at least one embodiment of the present disclosure. Figure 15 illustrates the structure of the first conductive layer, the semiconductor layer, and the second conductive layer. In some examples, as shown in Figure 15, the display substrate of this example does not have a light-shielding electrode provided in the first conductive layer. Further descriptions of the display substrate of this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0189] Figure 16 is another partial planar schematic diagram of the region where the first sub-pixel is located, according to at least one embodiment of the present disclosure. Figure 16 illustrates the structure of the first conductive layer, the semiconductor layer, the second conductive layer, the third conductive layer, and the fourth conductive layer. In some examples, as shown in Figure 16, the region where the first sub-pixel is located may be provided with only one data line, such as data line DL1. Further descriptions of the display substrate of this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0190] Figure 17 is an equivalent circuit diagram of the second sub-pixel according to at least one embodiment of the present disclosure. Figure 18 is a partial cross-sectional schematic diagram of the display boundary region according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 1, the display boundary region A2 may surround the display center region A1, for example, the width of the display boundary region A2 may be 0.5 mm to 1 mm.

[0191] In some examples, as shown in Figures 17 and 18, the second sub-pixel located in the display boundary area can be equivalent to a circuit structure including one transistor and two capacitors. The second sub-pixel may include: a second switching transistor T2, a third storage capacitor Cst3, and a fourth storage capacitor Cst4. The gate T21 of the second switching transistor T2 may be electrically connected to the gate line GL. The second switching transistor T2 may include a second active layer T20, which may include a second channel region T200, and a first region T201 and a second region T202 located on both sides of the second channel region T200. The first region T201 may be electrically connected to the data line DL through a fourth conductive block CP4, and the second region T202 may be electrically connected to a sixth conductive block CP6. The fourth conductive block CP4 corresponds to the first electrode of the second switching transistor T2, and the sixth conductive block CP6 corresponds to the second electrode of the second switching transistor T2. The third pixel electrode EP3 located in the first conductive layer is not electrically connected to the second electrode of the second switching transistor T2. The third pixel electrode EP3 is not electrically connected to the fourth pixel electrode EP4 located in the fourth conductive layer. The third common electrode EC3 is located in the first conductive layer and is electrically connected to the fourth common electrode EC4 in the third conductive layer via the fifth conductive block CP5 located in the second conductive layer. The third pixel electrode EP3 and the third common electrode EC3 can form the third storage capacitor Cst3; the fourth pixel electrode EP4 and the fourth common electrode EC4 can form the fourth storage capacitor Cst4. The third conductive layer may also have a separately configured seventh conductive block CP7, which can be floating. The isolated seventh conductive block CP7 can ensure that the display center area and the display boundary area have the same structure in the third conductive layer, so that the surrounding environment of the first sub-pixel and the second sub-pixel is consistent, which is beneficial to achieving consistency of characteristics in different areas.

[0192] In some examples, the multiple fourth pixel electrodes EP4 located in the display boundary region and the fourth conductive layer can be a single structure, resulting in an equivalent capacitance of multiple fourth storage capacitors Cst4 connected in parallel in the display boundary region. During electrophoretic solution display driving, a fixed signal with a fixed voltage V_border can be applied to the single structure of the fourth pixel electrodes EP4 in the fourth conductive layer of the display boundary region. The design in this example allows the display boundary region to display a fixed color, and the display color of the display boundary region can be varied by adjusting the fixed voltage V_border.

[0193] Figure 19 is another equivalent circuit diagram of the second sub-pixel according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 19, the second sub-pixel located in the display boundary area can be equivalent to a circuit structure including a transistor and a capacitor. The second sub-pixel may include: a second switching transistor T2 and a fourth storage capacitor Cst4. The second terminal of the second switching transistor T2 is not electrically connected to the fourth storage capacitor Cst4. This example, by reducing the capacitor structure of the second sub-pixel, can facilitate the realization of a smaller second sub-pixel, which is beneficial for reducing the size of the display boundary area. Further descriptions of this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0194] In other examples, the display boundary area can be combined with the second sub-pixel as shown in Figures 17 and 19.

[0195] In some examples, a gate driving circuit can be disposed in the non-display area. This gate driving circuit may include multiple cascaded drive control circuits, which can be configured to provide gate driving signals to multiple gate lines in the display area. As mentioned earlier, a relatively high driving voltage is typically required to drive multicolor electrophoretic display particles. However, a high driving voltage may result in a large current and burn out the associated thin-film transistors. Prolonged use of a high driving voltage may also cause a significant shift in the threshold voltage of the corresponding thin-film transistors, leading to the failure of the corresponding gate driving circuit. This embodiment provides a drive control circuit, a gate driving circuit, a display substrate, and a display device that can implement a drive control circuit capable of withstanding high driving voltages.

[0196] Figure 20 is a schematic diagram of the drive control circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 20, the drive control circuit provided in this example may include: an input circuit 210, a first control circuit 221, a first output circuit 231, a second output circuit 232, and a first noise reduction circuit 241. The input circuit 210 is electrically connected to the input terminal INPUT and the first node PU, and is configured to write the input signal provided by the input terminal INPUT to the first node PU under the control of the input terminal INPUT. The first control circuit 221 is electrically connected to the first clock terminal CLKR1, the first power supply terminal VDD1, and the second node PD1, and is configured to write the first power supply signal provided by the first power supply terminal VDD1 to the second node PD1 under the control of the effective level of the first clock signal provided by the first clock terminal CLKR1. The first output circuit 231 is electrically connected to the first node PU, the second clock terminal CLKR2, and the first output terminal OUT1, and is configured to control the first output terminal OUT1 to output the second clock signal provided by the second clock terminal CLKR2 under the control of the first node PU. The second output circuit 232 is electrically connected to the first node PU, the third clock terminal CLKR3, and the second output terminal OUT2. It is configured to, under the control of the first node PU, control the second output terminal OUT2 to output the third clock signal provided by the third clock terminal CLKR3. The first noise reduction circuit 241 is electrically connected to the second node PD1, the first output terminal OUT1, the second output terminal OUT2, the third power supply terminal VGL1, and the fourth power supply terminal VGL2. It is configured to, under the control of the second node PD1, control the first output terminal OUT1 to output the third power supply signal provided by the third power supply terminal VGL1, and control the second output terminal OUT2 to output the fourth power supply signal provided by the fourth power supply terminal VGL2. Specifically, during the periods when the input circuit 210 writes the input signal to the first node PU, the first output terminal 231 outputs the second clock signal, and the second output terminal 232 outputs the third clock signal, the first clock signal provides an inactive level; after the period when the first output terminal OUT1 outputs the second clock signal and the second output terminal OUT2 outputs the third clock signal, the first clock signal provides an active level.

[0197] In some examples, the first clock terminal CLKR1 and the second clock terminal CLKR2 are configured to provide different signals. The second clock terminal CLKR2 and the third clock terminal CLKR3 can be configured to provide the same signal. In other examples, the effective level of the second clock signal provided by the second clock terminal CLKR2 can be higher than the effective level of the third clock signal provided by the third clock terminal CLKR3, thereby increasing the drive voltage of the gate drive signal output by the first output terminal OUT1.

[0198] In some examples, the first clock signal provided by the first clock terminal CLKR1, the second clock signal provided by the second clock terminal CLKR2, and the third clock signal provided by the third clock terminal CLKR3 are all pulse signals.

[0199] In some examples, the first power supply terminal VDD1, the third power supply terminal VGL1, and the fourth power supply terminal VGL2 can be configured to provide a DC signal. Specifically, the third power supply terminal VGL1 and the fourth power supply terminal VGL2 can be configured to provide the same signal, such as a third power signal. This example simplifies wiring by configuring the third power supply terminal VGL1 and the fourth power supply terminal VGL2, and also helps reduce the capacitance of the traces transmitting the third power signal.

[0200] The drive control circuit provided in this example provides a pulse signal at the first clock terminal. During the time period when the input signal is written to the first node PU, the time period when the second clock signal is output at the first output terminal OUT1, and the time period when the third clock signal is output at the second output terminal OUT2, the first clock signal provides an inactive level, which can effectively reduce or eliminate the static current generated by the first control circuit and effectively reduce the risk of the first control circuit being burned out.

[0201] In some exemplary embodiments, the duty cycle of the first clock signal can be 25%. Duty cycle refers to the proportion of the effective level duration within a pulse cycle (including the effective level duration and the ineffective level duration). In other words, the effective level of the first clock signal accounts for 25% of a pulse cycle. For example, the effective level can be a high level. This example can reduce the on-time of the first control circuit, thereby effectively reducing the transistor threshold voltage offset of the first control circuit.

[0202] Figure 21 is another structural schematic diagram of the drive control circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 21, compared with the drive control circuit shown in Figure 20, the drive control circuit of this example may further include: a first node capacitor Cpu, the first electrode of the first node capacitor Cpu being electrically connected to the first node PU, and the second electrode of the first node capacitor Cpu being electrically connected to the fourth power supply terminal VGL2.

[0203] This example demonstrates how setting the first node capacitor (Cpu) can significantly reduce the secondary pull-up of the first node (PU) during circuit operation, making the relevant circuit characteristics more readily meet design requirements. Further details regarding the drive control circuit of this example can be found in the description of the foregoing embodiments and will not be repeated here.

[0204] Figure 22 is another structural schematic diagram of the drive control circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 22, compared with the drive control circuit shown in Figure 20, the drive control circuit of this example may further include: a second control circuit 222, a second noise reduction circuit 242, a first pull-down circuit 251, and a second pull-down circuit 252.

[0205] In some examples, as shown in Figure 22, the second control circuit 222 can be electrically connected to the first clock terminal CLKR1, the third node PD2, and the second power supply terminal VDD2. It is configured to write a second power signal provided by the second power supply terminal VDD2 to the third node PD2 under the control of the effective level of the first clock signal provided by the first clock terminal CLKR1; the first power signal is different from the second power signal. The second noise reduction circuit 242 can be electrically connected to the third node PD2, the first output terminal OUT1, the second output terminal OUT2, the third power supply terminal VGL1, and the fourth power supply terminal VGL2. It is configured to, under the control of the third node PD2, control the first output terminal OUT1 to output the third power signal provided by the third power supply terminal VGL1, and control the second output terminal OUT2 to output the fourth power signal provided by the fourth power supply terminal VGL2.

[0206] In some examples, the first pull-down circuit 251 can be electrically connected to the first node PU, the second node PD1, and the first clock terminal CLKR1, and configured to write the first clock signal provided by the first clock terminal CLKR1 to the second node PD1 under the control of the first node PU; or, it can be electrically connected to the first node PU, the second node PD1, and the fourth power terminal VGL2, and configured to write the fourth power signal provided by the fourth power terminal VGL2 to the second node PD1 under the control of the first node PU.

[0207] In some examples, the second pull-down circuit 252 can be electrically connected to the first node PU, the third node PD2, and the first clock terminal CLKR1, and configured to write the first clock signal provided by the first clock terminal CLKR1 to the third node PD2 under the control of the first node PU; or, it can be electrically connected to the first node PU, the third node PD2, and the fourth power terminal VGL2, and configured to write the fourth power signal provided by the fourth power terminal VGL2 to the third node PD2 under the control of the first node PU.

[0208] In this example, the first noise reduction circuit 241, under the control of the second node PD1, eliminates the output noise of the first output terminal OUT1 and the second output terminal OUT2. The second noise reduction circuit 242, under the control of the third node PD2, eliminates the output noise of the first output terminal OUT1 and the second output terminal OUT2. Under the control of the first clock terminal CLKR1, the first control circuit 221 and the second control circuit 222 can effectively reduce or eliminate the static current generated by the first control circuit 221 and the second control circuit 222 during the period when the input signal is written to the first node PU and the first output terminal OUT1 and the second output terminal OUT2 output valid levels, effectively reducing the risk of the first control circuit 221 and the second control circuit 222 being burned out. Moreover, by reducing or eliminating the static current, the static current can be prevented from flowing through the first pull-down circuit 251 and the second pull-down circuit 252, which can help avoid threshold shift of the transistors of the first pull-down circuit 251 and the second pull-down circuit 252. The remaining description of the drive control circuit of this example can be referred to the description of the foregoing embodiments, and will not be repeated here.

[0209] Figure 23 is another structural schematic diagram of the drive control circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 23, compared with the drive control circuit shown in Figure 22, the drive control circuit of this example may further include: a second node capacitor Cpd1 and a third node capacitor Cpd2. The first electrode of the second node capacitor Cpd1 is electrically connected to the second node PD1, and the second electrode of the second node capacitor Cpd1 is electrically connected to the fourth power supply terminal VGL2. The first electrode of the third node capacitor Cpd2 is electrically connected to the third node PD2, and the second electrode of the third node capacitor Cpd2 is electrically connected to the fourth power supply terminal VGL2.

[0210] This example maintains the voltage of the second node PD1 during the noise reduction phase by setting the second node capacitor Cpd1, and maintains the voltage of the third node PD2 during the noise reduction phase by setting the third node capacitor Cpd2, thereby ensuring the noise reduction effect of the first output terminal OUT1 and the second output terminal OUT2. Further descriptions of the drive control circuit in this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0211] Figure 24 is another structural schematic diagram of the drive control circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 24, compared with the drive control circuit shown in Figure 22, the drive control circuit of this example may further include: a third pull-down circuit 261, a fourth pull-down circuit 262, and a fifth pull-down circuit 263. The third pull-down circuit 261 can be electrically connected to the first node PU, the second node PD1, and the fourth power supply terminal VGL2, and is configured to write the fourth power signal provided by the fourth power supply terminal VGL2 to the first node PU under the control of the second node PD1. The fourth pull-down circuit 262 can be electrically connected to the first node PU, the third node PD2, and the fourth power supply terminal VGL2, and is configured to write the fourth power signal provided by the fourth power supply terminal VGL2 to the first node PU under the control of the third node PD2. The fifth pull-down circuit 263 can be electrically connected to the first node PU, the first control terminal IN1, and the fourth power supply terminal VGL2, and is configured to write the fourth power signal provided by the fourth power supply terminal VGL2 to the first node PU under the control of the first control terminal IN1.

[0212] In this example, the third pull-down circuit 261, the fourth pull-down circuit 262, and the fifth pull-down circuit 263 are all used to pull down the potential of the first node PU, which can prevent abnormal output of the first output terminal OUT1 and the second output terminal OUT2. Further descriptions of the drive control circuit in this example can be found in the descriptions of the foregoing embodiments, and therefore will not be repeated here.

[0213] Figure 25 is an equivalent circuit diagram of a drive control circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 25, the drive control circuit provided in this example may include: an input circuit 210, a first control circuit 221, a second control circuit 222, a first output circuit 231, a second output circuit 232, a first noise reduction circuit 241, a second noise reduction circuit 242, a first pull-down circuit 251, a second pull-down circuit 252, a third pull-down circuit 261, a fourth pull-down circuit 262, a fifth pull-down circuit 263, a first pull-up circuit 271, a second pull-up circuit 272, a first reset circuit 281, a first node capacitor Cpu, a second node capacitor Cpd1, and a third node capacitor Cpd2.

[0214] In some examples, the input circuit 210 may include two first transistors, M1A and M1B. The gate and first terminal of the first transistor M1A are electrically connected to the input terminal INPUT. The second terminal of the first transistor M1A is electrically connected to the first terminal of the first transistor M1B. The gate of the first transistor M1B is electrically connected to the input terminal INPUT. The second terminal of the first transistor M1B is electrically connected to the first node PU. The second terminal of the first transistor M1A and the first terminal of the first transistor M1B are both electrically connected to the fifth node CB2.

[0215] In some examples, the first control circuit 221 may include a fifth transistor M5. The gate of the fifth transistor M5 is electrically connected to the first clock terminal CLKR1, the first terminal of the fifth transistor M5 is electrically connected to the first power supply terminal VDD1, and the second terminal of the fifth transistor M5 is electrically connected to the second node PD1. The second control circuit 222 may include a thirteenth transistor M13. The gate of the thirteenth transistor M13 is electrically connected to the first clock terminal CLKR1, the first terminal of the thirteenth transistor M13 is electrically connected to the second power supply terminal VDD2, and the second terminal of the thirteenth transistor M13 is electrically connected to the third node PD2. The first power signal provided by the first power supply terminal VDD1 may be different from the second power signal provided by the second power supply terminal VDD2.

[0216] In some examples, the first output circuit 231 may include a third transistor M3 and a first capacitor C1. The gate of the third transistor M3 is electrically connected to the first node PU, the first electrode of the third transistor M3 is electrically connected to the second clock terminal CLKR2, and the second electrode of the third transistor M3 is electrically connected to the first output terminal OUT1. The first electrode of the first capacitor C1 is electrically connected to the first node PU, and the second electrode of the first capacitor C1 is electrically connected to the first output terminal OUT1. The second output circuit 232 may include a fourth transistor M4 and a second capacitor C2. The gate of the fourth transistor M4 is electrically connected to the first node PU, the first electrode of the fourth transistor M4 is electrically connected to the third clock terminal CLKR3, and the second electrode of the fourth transistor M4 is electrically connected to the second output terminal OUT2. The first electrode of the second capacitor C2 is electrically connected to the first node PU, and the second electrode of the second capacitor C2 is electrically connected to the second output terminal OUT2. The second clock terminal CLKR2 and the third clock terminal CLKR3 may be configured to provide the same signal.

[0217] In some examples, the first noise reduction circuit 241 may include a ninth transistor M9 and a tenth transistor M10. The gate of the ninth transistor M9 is electrically connected to the second node PD1, the first terminal of the ninth transistor M9 is electrically connected to the third power supply terminal VGL1, and the second terminal of the ninth transistor M9 is electrically connected to the first output terminal OUT1. The gate of the tenth transistor M10 is electrically connected to the second node PD1, the first terminal of the tenth transistor M10 is electrically connected to the fourth power supply terminal VGL2, and the second terminal of the tenth transistor M10 is electrically connected to the second output terminal OUT2.

[0218] In some examples, the second noise reduction circuit 242 may include an eleventh transistor M11 and a twelfth transistor M12. The gate of the eleventh transistor M11 is electrically connected to the third node PD2, the first terminal of the eleventh transistor M11 is electrically connected to the third power supply terminal VGL1, and the second terminal of the eleventh transistor M11 is electrically connected to the first output terminal OUT1. The gate of the twelfth transistor M12 is electrically connected to the third node PD2, the first terminal of the twelfth transistor M12 is electrically connected to the fourth power supply terminal VGL2, and the second terminal of the twelfth transistor M12 is electrically connected to the second output terminal OUT2.

[0219] In some examples, the first pull-down circuit 251 may include a sixth transistor M6. The gate of the sixth transistor M6 is electrically connected to the first node PU, the first terminal of the sixth transistor M6 is electrically connected to the first clock terminal CLKR1, and the second terminal of the sixth transistor M6 is electrically connected to the second node PD1.

[0220] In some examples, the second pull-down circuit 252 may include a fourteenth transistor M14. The gate of the fourteenth transistor M14 is electrically connected to the first node PU, the first terminal of the fourteenth transistor M14 is electrically connected to the first clock terminal CLKR1, and the second terminal of the fourteenth transistor M14 is electrically connected to the third node PD2.

[0221] In some examples, the third pull-down circuit 261 may include two seventh transistors, M7A and M7B. The gate of the seventh transistor M7A is electrically connected to the second node PD1, the first terminal of the seventh transistor M7A is electrically connected to the second terminal of the seventh transistor M7B, and the second terminal of the seventh transistor M7A is electrically connected to the first node PU; the gate of the seventh transistor M7B is electrically connected to the second node PD1, and the first terminal of the seventh transistor M7B is electrically connected to the fourth power supply terminal VGL2. The first terminal of the seventh transistor M7A and the second terminal of the seventh transistor M7B are both electrically connected to the fourth node CB1.

[0222] In some examples, the fourth pull-down circuit 262 may include two eighth transistors, M8A and M8B. The gate of the eighth transistor M8A is electrically connected to the third node PD2, the first terminal of the eighth transistor M8A is electrically connected to the second terminal of the eighth transistor M8B, and the second terminal of the eighth transistor M8A is electrically connected to the first node PU; the gate of the eighth transistor M8B is electrically connected to the third node PD2, and the first terminal of the eighth transistor M8B is electrically connected to the fourth power supply terminal VGL2. The first terminal of the eighth transistor M8A and the second terminal of the eighth transistor M8B are both electrically connected to the fourth node CB1.

[0223] In some examples, the fifth pull-down circuit 263 may include two second transistors, M2A and M2B. The gate of the second transistor M2A is electrically connected to the first control terminal IN1, the first terminal of the second transistor M2A is electrically connected to the second terminal of the second transistor M2B, and the second terminal of the second transistor M2A is electrically connected to the first node PU; the gate of the second transistor M2B is electrically connected to the first control terminal IN1, and the first terminal of the second transistor M2B is electrically connected to the fourth power supply terminal VGL2. The first terminal of the second transistor M2A and the second terminal of the second transistor M2B are both electrically connected to the fourth node CB1.

[0224] In some examples, the first pull-up circuit 271 can be electrically connected to the fourth node CB1, the second control terminal IN2, and the fifth power supply terminal VGH, and is configured to write the fifth power signal provided by the fifth power supply terminal VGH to the fourth node CB1 under the control of the second control terminal IN2. The second pull-up circuit 272 can be electrically connected to the fifth node CB2, the second control terminal IN2, and the fifth power supply terminal VGH, and is configured to write the fifth power signal provided by the fifth power supply terminal VGH to the fifth node CB2 under the control of the second control terminal IN2. The voltage of the fifth power signal can be greater than the voltage of the third power signal and greater than the voltage of the fourth power signal. The first pull-up circuit 271 reduces the leakage current between the first node PU and the fourth power supply terminal VGL2 by writing the fifth power supply signal provided by the fifth power supply terminal VGH to the fourth node CB1, thereby helping to maintain the first node PU at a higher level and facilitating the output of the first output terminal OUT1 and the second output terminal OUT2. The second pull-up circuit 272 reduces the leakage current between the first node PU and the fifth node CB2 by writing the fifth power supply signal provided by the fifth power supply terminal VGH to the fifth node CB2, thereby helping to maintain the first node PU at a higher level and facilitating the output of the first output terminal OUT1 and the second output terminal OUT2.

[0225] In some examples, the first pull-up circuit 271 may include a sixteenth transistor M16. The gate of the sixteenth transistor M16 is electrically connected to the second control terminal IN2, the first terminal of the sixteenth transistor M16 is electrically connected to the fifth power supply terminal VGH, and the second terminal of the sixteenth transistor M16 is electrically connected to the fourth node CB1.

[0226] In some examples, the second pull-up circuit 272 may include a fifteenth transistor M15. The gate of the fifteenth transistor M15 is electrically connected to the second control terminal IN2, the first terminal of the fifteenth transistor M15 is electrically connected to the fifth power supply terminal VGH, and the second terminal of the fifteenth transistor M15 is electrically connected to the fifth node CB2.

[0227] In some examples, the first reset circuit 281 can be electrically connected to the first node PU, the first reset terminal TRST, and the fourth power supply terminal VGL2, and configured to write a fourth power supply signal provided by the fourth power supply terminal VGL2 to the first node PU under the control of the first reset terminal TRST. The first reset terminal TRST can be configured to provide a valid level signal after a frame ends, thereby resetting the entire frame so that the next frame can be displayed.

[0228] In some examples, the first reset circuit 281 may include two seventeenth transistors, M17A and M17B. The gate of the seventeenth transistor M17A is electrically connected to the first reset terminal TRST, the first terminal of the seventeenth transistor M17A is electrically connected to the second terminal of the seventeenth transistor M17B, and the second terminal of the seventeenth transistor M17A is electrically connected to the first node PU; the gate of the seventeenth transistor M17B is electrically connected to the first reset terminal TRST, and the first terminal of the seventeenth transistor M17B is electrically connected to the fourth power supply terminal VGL2. The first terminal of the seventeenth transistor M17A and the second terminal of the seventeenth transistor M17B are both electrically connected to the fourth node CB1.

[0229] In some examples, the first electrode of the first node capacitor Cpu is electrically connected to the first node PU, and the second electrode of the first node capacitor Cpu is electrically connected to the fourth power supply terminal VGL2. The first electrode of the second node capacitor Cpd1 is electrically connected to the second node PD1, and the second electrode of the second node capacitor Cpd1 is electrically connected to the fourth power supply terminal VGL2. The first electrode of the third node capacitor Cpd2 is electrically connected to the third node PD2, and the second electrode of the third node capacitor Cpd2 is electrically connected to the fourth power supply terminal VGL2.

[0230] In this example, the first node PU is the connection point of the first transistor M1B, the second transistor M2A, the third transistor M3, the fourth transistor M4, the sixth transistor M6, the seventh transistor M7A, the eighth transistor M8A, the fourteenth transistor M14, the seventeenth transistor M17A, the first node capacitor Cpu, the first capacitor C1, and the second capacitor C2. The second node PD1 is the connection point of the fifth transistor M5, the sixth transistor M6, the seventh transistors M7A and M7B, the ninth transistor M9, the tenth transistor M10, and the second node capacitor Cpd1. The third node PD2 is the connection point of the thirteenth transistor M13, the fourteenth transistor M14, the eleventh transistor M11, the twelfth transistor M12, the eighth transistors M8A and M8B, and the third node capacitor Cpd2. The fourth node CB1 is the connection point of the second transistors M2A and M2B, the seventh transistors M7A and M7B, the eighth transistors M8A and M8B, the seventeenth transistors M17A and M17B, and the sixteenth transistor M16. The fifth node CB2 is the connection point of the first transistors M1A and M1B and the fifteenth transistor M15.

[0231] The following explanation uses the working process of the nth-level drive control circuit as an example to illustrate the working process of the drive control circuit.

[0232] Figure 26 is a timing diagram of the operation of the drive control circuit of at least one embodiment of the present disclosure. Figure 27A is a schematic diagram of the state of the drive control circuit of at least one embodiment of the present disclosure in the first stage; Figure 27B is a schematic diagram of the state of the drive control circuit of at least one embodiment of the present disclosure in the second stage; Figure 27C is a schematic diagram of the state of the drive control circuit of at least one embodiment of the present disclosure in the third stage.

[0233] In this circuit, the input terminal INPUT of the nth-stage drive control circuit is electrically connected to the second output terminal OUT2(n-1) of the (n-1)th-stage drive control circuit. The first control terminal IN1 is electrically connected to the second output terminal OUT2(n+1) of the (n+1)th-stage drive control circuit, and the second control terminal IN2 is electrically connected to the second output terminal OUT2(n) of this stage. n can be an integer greater than 0. The first clock terminal CLKR1 of the nth-stage drive control circuit can be electrically connected to the second clock line CLK2. The second clock terminal CLKR2 and the third clock terminal CLKR3 can provide the same signal, for example, both can be electrically connected to the first clock line CLK1. The first clock line CLK1, the second clock line CLK2, the third clock line CLK3, and the fourth clock line CLK4 are configured to provide pulse signals. The duty cycles of the clock signals provided by the first clock line CLK1, the second clock line CLK2, the third clock line CLK3, and the fourth clock line CLK4 can be the same, and the high-level periods of the four clock signals are different. The effective levels of the clock signals provided by the first clock line CLK1, the second clock line CLK2, the third clock line CLK3, and the fourth clock line CLK4 are output sequentially without timing overlap. For example, the effective level of the clock signals provided by the first clock line CLK1, the second clock line CLK2, the third clock line CLK3, and the fourth clock line CLK4 can each account for 25% of a pulse cycle. The voltage of the first power supply signal transmitted at the first power supply terminal VDD1 can be higher than the voltage of the second power supply signal provided at the second power supply terminal VDD2.

[0234] In this example, the transistor types of transistors M1A through M17B can be the same, such as all being N-type transistors. In this example, the active level can be high, and the inactive level can be low.

[0235] In some examples, as shown in Figures 26 to 27C, the operation of the nth stage drive control circuit may include the following stages.

[0236] In some examples, as shown in Figures 26 and 27A, in the first stage t1 (also known as the input stage), the input terminal of the nth-stage drive control circuit receives a high-level signal from the second output terminal OUT2(n-1). The first transistors M1A and M1B are turned on, writing the high-level signal from the second output terminal OUT2(n-1) to the first node PU, allowing the first node PU to charge to Vgh-Vth_M1. Here, Vgh represents the voltage of the fifth power supply signal provided by the fifth power supply terminal VGH, and Vth_M1 represents the sum of the threshold voltages of the first transistors M1A and M1B.

[0237] In the first phase t1, the second clock line CLK2 provides a low-level signal, turning off the fifth transistor M5 and the thirteenth transistor M13, preventing charging of the second node PD1 and the third node PD2. During this phase, the fifth transistor M5 is off, its gate-source voltage difference Vgs = 0, and its leakage current Ids is approximately 2nA, reducing the risk of burnout.

[0238] In the first phase t1, the first node PU is at a high level, the sixth transistor M6 and the fourteenth transistor M14 are turned on, and the second node PD1 and the third node PD2 are pulled low to the low level provided by the second clock line CLK2. When the second node PD1 is at a low level, the seventh transistors M7A and M7B, the ninth transistor M9 and the tenth transistor M10 are all turned off; when the third node PD2 is at a low level, the eighth transistors M8A and M8B, the eleventh transistor M11 and the twelfth transistor M12 are all turned off.

[0239] In the first stage t1, the first node PU is at a high level, and the third transistor M3 and the fourth transistor M4 are turned on. When the third transistor M3 is turned on, the first output terminal OUT1(n) outputs a low-level signal provided by the first clock line CLK1; when the fourth transistor M4 is turned on, the second output terminal OUT2(n) outputs a low-level signal provided by the first clock line CLK1.

[0240] In the first stage t1, the second output terminal OUT2(n) provides a low-level signal, and both the fifteenth transistor M15 and the sixteenth transistor M16 are turned off. The second output terminal OUT2(n+1) provides a low-level signal, and the second transistors M2A and M2B are turned off. The first reset terminal TRST provides a low-level signal, and the seventeenth transistors M17A and M17B are turned off.

[0241] In some examples, as shown in Figures 26 and 27B, during the second stage t2 (also known as the output stage), due to the bootstrap effect of the first capacitor C1, the voltage of the first node PU is pulled up twice, and the third transistor M3, the fourth transistor M4, the sixth transistor M6, and the fourteenth transistor M14 remain on. During this stage, the first clock line CLK1 provides a high-level signal, the third transistor M3 is turned on, and the first output terminal OUT1(n) outputs a high-level signal; the fourth transistor M4 is turned on, and the second output terminal OUT2(n) outputs a high-level signal.

[0242] In the second phase t2, the second clock line CLK2 remains low, and both the fifth transistor M5 and the thirteenth transistor M13 are turned off. Nodes PD1 and PD2 cannot charge. During this phase, the fifth transistor M5 is off, its gate-source voltage difference Vgs_M5 = 0, and its leakage current Ids is approximately 2nA, reducing the risk of burnout. The sixth transistor M6 is turned on, and node PD1 maintains the low-level signal provided by the second clock line CLK2; the fourteenth transistor M14 is turned on, and node PD2 maintains the low-level signal provided by the second clock line CLK2.

[0243] In the second stage t2, the second output terminal OUT2(n) outputs a high-level signal, the fifteenth transistor M15 and the sixteenth transistor M16 are turned on, and high-level signals are written to the fourth node CB1 and the fifth node CB2, which can reduce the leakage current present in the fourth node CB1 and the fifth node CB2.

[0244] In the second stage t2, due to the secondary pull-up of the first node PU, the gate-source voltage difference Vgs_M6 of the sixth transistor M6 increases significantly. For example, when the clock signal provided by the first clock line CLK1 fluctuates between -38V and 38V, the maximum value of Vgs_M6 can reach 120V. Although the operating time of the sixth transistor M6 under high voltage is short within one frame, as the usage time of the display substrate increases, the operating time of the sixth transistor M6 under high voltage gradually accumulates, and the threshold voltage offset of the sixth transistor M6 gradually increases, posing a risk of failure for the sixth transistor M6. The fourteenth transistor M14 has the same problem. This example significantly reduces the secondary pull-up voltage of the first node PU by adjusting the first node capacitor Cpu, thereby significantly reducing the gate-source voltage difference between the sixth transistor M6 and the fourteenth transistor M14.

[0245] Table 1 shows the relationship between the size of the first node capacitor Cpu and the voltage change of the first node PU.

[0246] As shown in Table 1, when the capacitance value of the first node capacitor Cpu increases from 0 to 5pF, the voltage of the first node PU decreases from 110V to 79.2V, and the maximum voltage of the first node PU can be reduced by 30V. By setting the first node capacitor Cpu, the threshold voltage offset of the sixth transistor M6 and the fourteenth transistor M14 is significantly reduced under long-term positive bias temperature stress (PBTS), and the relevant characteristics are more likely to meet the design requirements.

[0247] Figure 28 is a schematic diagram of the voltage change of the first node in at least one embodiment of the present disclosure. In some examples, as shown in Figure 28, in the second stage t2, the first output terminal OUT1(n) outputs a high-level signal, and the voltage of the first output terminal OUT1(n) jumps to ΔGout=Vgh-Vgl; Vgh is the voltage of the high-level signal provided by the first clock line CLK1, and Vgl is the voltage of the low-level signal provided by the first clock line CLK1.

[0248] After setting the first node capacitor Cpu, the secondary stretching voltage ΔV_PU of the first node PU caused by the first capacitor C1 can be determined by the following formula:

[0249] ΔV_PU=C1 / (C1+CPU)×ΔGout;

[0250] Where C1 represents the capacitance value of the first capacitor C1, and CPU represents the capacitance value of the first node capacitor Cpu.

[0251] Thus, in the second stage t2, the voltage of the first node PU = Vgh - Vth_M1 + ΔV_PU = Vgh - Vth_M1 + C1 / (C1 + CPU) × (Vgh - Vgl).

[0252] It can be seen that ΔV_PU and the voltage of the first node PU can be adjusted by increasing the capacitance value of the first node capacitor Cpu and adjusting the ratio between the capacitance value of the first node capacitor Cpu and the capacitance value of the first capacitor C1.

[0253] In some examples, as shown in Figures 26 and 27C, during the third stage t3, the second clock line CLK2 provides a high-level signal, and the fifth transistor M5 and the thirteenth transistor M13 are turned on. When the first power supply terminal VDD1 provides a high-level signal and the second power supply terminal VDD2 provides a low-level signal, the second node PD1 can gradually charge, while the third node PD2 remains low.

[0254] Assume the high-level signal provided by the second clock line CLK2 has a voltage value of H1, the high-level signal provided by the first power supply terminal VDD1 has a voltage value of H2, and the threshold voltage of the fifth transistor M5 is Vth_M5, where Vth_M5 > 0. The second node PD1 can gradually charge to H2 (when H2 ≤ H1 - Vth_M5) or H1 - Vth_M5 (when H2 > H1 - Vth_M5). To ensure that the transistors operate at the smallest possible drive voltage to increase their lifetime, in this example, the high-level signal H2 of the first power supply terminal VDD1 can be a smaller value, i.e., H2 ≤ H1 - Vth_M5; at this time, the second node PD1 can gradually charge to H2. For the seventh transistors M7A and M7B and the tenth transistor M10, the gate-source voltage difference of these transistors is H2 - LVGL, where LVGL is the voltage provided by the fourth power supply terminal VGL2; for the ninth transistor M9, its gate-source voltage difference is H2 - VGL, where VGL is the voltage provided by the third power supply terminal VGL1. In this example, H2 can be 5V, while LVGL or VGL can be -38V, and the gate-source voltage difference between the transistor connected to the gate of the second node PD1 can be 43V. The seventh transistors M7A and M7B are turned on, the first node PU is gradually pulled low, and the ninth transistor M9 and the tenth transistor M10 are turned on. The first output terminal OUT1(n) and the second output terminal OUT2(n) remain low.

[0255] In the third stage t3, the second output terminal OUT2(n+1) outputs a high-level signal, the second transistors M2A and M2B are turned on, and the first node PU discharges.

[0256] In the third stage t3, the seventh transistors M7A and M7B, and the second transistors M2A and M2B simultaneously discharge to the first node PU. Since the seventh transistors M7A and M7B operate for extended periods, their lifespan is relatively short; while the operating time of the second transistors M2A and M2B is significantly reduced, ensuring the overall circuit's lifespan.

[0257] After stage t3, the second clock line CLK2 provides a low-level signal, and the fifth transistor M5 and the thirteenth transistor M13 are turned off. Due to the setting of the second node capacitor Cpd1, the second node PD1 can maintain voltage H2. When the signal provided by the second clock line CLK2 transitions from high to low, the voltage of the second node PD1 transitions to ΔV_PD1, where ΔV_PD1 = (Vgh_CLK2 - Vgl_CLK2) × Cgs_M5 / (Cgs_M5 + CPD1); where Vgh_CLK2 is the high-level voltage value provided by the second clock line CLK2, Vgl_CLK2 is the low-level voltage value provided by the second clock line CLK2, Cgs_M5 is the gate-source capacitance value of the fifth transistor M5, and CPD1 is the capacitance value of the second node capacitor Cpd1.

[0258] Afterwards, the second clock line CLK2 provides a high-level signal, the fifth transistor M5 and the thirteenth transistor M13 are turned on, and the second node PD1 is charged to voltage H2 again; subsequently, the drive control circuit can repeat the operation of the first and second stages as before until the next frame arrives.

[0259] In the drive control circuit provided in this example, the first clock terminal CLKR1 (e.g., electrically connected to the second clock line CLK2) is connected to the gates of the fifth transistor M5 and the thirteenth transistor M13. During the first stage t1 and the second stage t2, the first clock terminal CLKR1 provides a low-level signal, the gate-source voltage difference between the fifth transistor M5 and the thirteenth transistor M13 is zero, and both transistors are turned off. This reduces the leakage current of the fifth transistor M5 and the thirteenth transistor M13, significantly reducing the risk of burnout. Furthermore, the clock signal received by the first clock terminal CLKR1 uses a 25% duty cycle design, with the effective level (high level) occupying 25% of one pulse cycle. This reduces the on-time of the fifth transistor M5 and the thirteenth transistor M13, effectively reducing the transistor threshold voltage offset.

[0260] In the drive control circuit of this example, by setting the first node capacitor Cpu, the secondary pull-up of the first node PU due to the capacitor bootstrap effect can be significantly reduced. This significantly reduces the gate-source voltage difference between the sixth transistor M6 and the fourteenth transistor M14, and significantly reduces the threshold voltage offset of the transistors under long-term PBTS, making the relevant characteristics of the transistors more likely to meet design requirements. Moreover, the stability of the transistors connected to the first node can be improved by adjusting the voltage of the first node.

[0261] In the drive control circuit of this example, by setting the second node capacitor Cpd1 and the third node capacitor Cpd2, the voltages of the second node PD1 and the third node PD2 can be maintained after the third stage t3, thereby ensuring the noise reduction effect of the first output terminal OUT1(n) and the second output terminal OUT2(n). Furthermore, the voltage of the first power supply signal provided by the first power supply terminal VDD1 is H2, and the high-level voltage provided by the first clock terminal CLKR1 is H1, where H2 ≤ H1 - Vth_M5; where Vth_M5 is the threshold voltage of the fifth transistor M5. In this way, the fifth transistor M5 can be ensured to operate at the smallest possible drive voltage to increase its lifespan.

[0262] In the drive control circuit of this example, the voltage H2 provided by the first power supply terminal VDD1 is adjustable between 38V and -5V. After H2 is adjusted, it can still be ensured that the leakage current of the fifth transistor M5 and the sixth transistor M6 remains at the nanoampere (nA) level in the first stage t1 and the second stage t2, which can reduce the possibility of the fifth transistor M5 and the sixth transistor M6 burning out due to static current.

[0263] In the drive control circuit of this example, the start signal line STV or the output signal of the second output terminal of the previous stage drive control circuit can be used as the input signal of this stage drive control circuit, which can significantly reduce the duty cycle of the first transistors M1A and M1B.

[0264] Figure 29 is another equivalent circuit diagram of the drive control circuit of at least one embodiment of the present disclosure. In some examples, as shown in Figure 29, the input terminal of the nth stage drive control circuit is electrically connected to the second output terminal OUT2(n-1) of the (n-1)th stage drive control circuit, and the first control terminal IN1 and the second control terminal IN2 are both electrically connected to the first node PU. The second clock terminal CLKR2 and the third clock terminal CLKR3 are configured to transmit the same signal. The remaining structure of the drive control circuit in this example is the same as that in the aforementioned embodiments, and therefore will not be described again here.

[0265] In this example, from the first stage t1 to the third stage t3, when the first node PU remains high, both the fifteenth transistor M15 and the sixteenth transistor M16 are turned on, and the fourth node CB1 and the fifth node CB2 can remain high. In the second stage t2, the first node PU is pulled up again, and the fourth node CB1 and the fifth node CB2 can be charged to the high level (e.g., 38V) provided by the fifth power supply terminal VGH. In contrast, in the examples shown in Figures 27A to 27C, since the second control terminal IN2 is electrically connected to the second output terminal OUT2(n), the fifth node CB2 can only be charged to Vgh-Vtr_M15, which is approximately 36.2V, where Vgh is the voltage provided by the fifth power supply terminal VGH, and Vtr_M15 is the reverse conduction voltage of the fifteenth transistor M15.

[0266] Figure 30 is a timing diagram of the fifth node of the drive control circuit shown in Figure 29. As shown in Figure 30, the first curve L1 is the timing curve of the fifth node CB2 of the drive control circuit shown in Figures 27A to 27C, and the second curve L2 is the timing curve of the fifth node CB2 of the drive control circuit shown in Figure 29. It can be seen that in the second stage t2, the voltage of the fifth node CB2 in the example shown in Figure 29 is higher than that in the examples shown in Figures 27A to 27C, and the leakage current of the fifth node CB2 in the example shown in Figure 29 is smaller. Similarly, the example shown in Figure 29 can reduce the leakage current of the fourth node CB1.

[0267] In addition, in the example shown in Figure 29, the node voltage of the first node PU is relatively higher, which can help the sixth transistor M6 and the fourteenth transistor M14 to quickly pull down the first output terminal OUT1(n) and the second output terminal OUT2(n), thereby achieving a smaller falling edge Tf of the output signal, which is beneficial for the sub-pixel to achieve a higher charging rate.

[0268] The remaining descriptions of this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0269] Figure 31 is another equivalent circuit diagram of the drive control circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 31, compared to the example shown in Figure 29, in this example, the first terminal of the sixth transistor M6 and the first terminal of the fourteenth transistor M14 are both electrically connected to the fourth power supply terminal VGL2. The operating timing of this example is similar to that of the aforementioned embodiments, and therefore will not be described again here.

[0270] In this example, during the first stage t1 and the second stage t2, the first clock terminal CLKR1 provides a low-level signal, and both the fifth transistor M5 and the thirteenth transistor M13 are turned off. In the third stage t3, the first clock terminal CLKR1 provides a high-level signal, and both the fifth transistor M5 and the thirteenth transistor M13 are turned on. The gate-source voltage difference Vgs_M6 of the sixth transistor M6 is VPU - LVGL = 0, and the drain-source voltage Vds_M6 of the sixth transistor M6 is VPD1 - LVGL = 5 - (-38) = 43V, where VPU is the voltage of the first node PU, VPD1 is the potential of the second node PD1, and LVGL is the voltage provided by the fourth power supply terminal VGL2; during this stage, the sixth transistor M6 is turned off. The drive control circuit in this example works normally.

[0271] The remaining descriptions of this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0272] Figure 32 is another equivalent circuit diagram of the drive control circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 32, compared with the example shown in Figure 31, in this example, the second control terminal is electrically connected to the second output terminal OUT2(n), wherein the gate of the fifteenth transistor M15 and the gate of the sixteenth transistor M16 are electrically connected to the second output terminal OUT2(n). Further description of this example can be found in the description of the foregoing embodiments, and therefore will not be repeated here.

[0273] Figure 33 is another equivalent circuit diagram of the drive control circuit of at least one embodiment of the present disclosure. In some examples, as shown in Figure 33, the second control terminal is electrically connected to the second output terminal OUT2(n), wherein the gates of the fifteenth transistor M15 and the sixteenth transistor M16 are electrically connected to the second output terminal OUT2(n). The first terminal of the sixth transistor M6 and the first terminal of the fourteenth transistor M14 are electrically connected to the first clock terminal CLKR1. The first output circuit includes the third transistor M3, and the second output circuit includes the fourth transistor M4. Since the transistors themselves have capacitance, the first capacitor C1 and the second capacitor C2 can be omitted in this example. The remaining descriptions of this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0274] Figure 34 is another equivalent circuit diagram of the drive control circuit of at least one embodiment of the present disclosure. In some examples, as shown in Figure 34, the second control terminal is electrically connected to the first node PU, wherein the gate of the fifteenth transistor M15 and the gate of the sixteenth transistor M16 are electrically connected to the first node PU. The first terminal of the sixth transistor M6 and the first terminal of the fourteenth transistor M14 are electrically connected to the first clock terminal CLKR1. The first output circuit includes the third transistor M3, and the second output circuit includes the fourth transistor M4. Since the transistors themselves have capacitance, the first capacitor C1 and the second capacitor C2 can be omitted in this example. The remaining description of this example can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0275] Figure 35 is another equivalent circuit diagram of the drive control circuit of at least one embodiment of the present disclosure. In some examples, as shown in Figure 35, the second control terminal is electrically connected to the first node PU, wherein the gate of the fifteenth transistor M15 and the gate of the sixteenth transistor M16 are electrically connected to the first node PU. The first terminal of the sixth transistor M6 and the first terminal of the fourteenth transistor M14 are electrically connected to the fourth power supply terminal VLG2. The first output circuit includes the third transistor M3, and the second output circuit includes the fourth transistor M4. Since the transistors themselves have capacitance, the first capacitor C1 and the second capacitor C2 can be omitted in this example. The remaining description of this example can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0276] Figure 36 is another equivalent circuit diagram of the drive control circuit of at least one embodiment of the present disclosure. In some examples, as shown in Figure 36, the second control terminal is electrically connected to the second output terminal OUT2(n), wherein the gate of the fifteenth transistor M15 and the gate of the sixteenth transistor M16 are electrically connected to the second output terminal OUT2(n). The first terminal of the sixth transistor M6 and the first terminal of the fourteenth transistor M14 are electrically connected to the fourth power supply terminal VLG2. The first output circuit includes the third transistor M3, and the second output circuit includes the fourth transistor M4. Since the transistors themselves have capacitance, the first capacitor C1 and the second capacitor C2 can be omitted in this example. The remaining description of this example can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0277] Figure 37 is another equivalent circuit diagram of the drive control circuit of at least one embodiment of the present disclosure. In some examples, as shown in Figure 37, the drive control circuit of this example may include: an input circuit 210, a first control circuit 221, a second control circuit 222, a first output circuit 231, a second output circuit 232, a first noise reduction circuit 241, a second noise reduction circuit 242, a first pull-down circuit 251, a second pull-down circuit 252, a third pull-down circuit 261, a fourth pull-down circuit 262, a fifth pull-down circuit 263, a second pull-up circuit 272, a first reset circuit 281, a second reset circuit 282, a first node capacitor Cpu, a second node capacitor Cpd1, and a third node capacitor Cpd2.

[0278] In some examples, the input circuit 210 may include two first transistors M1A and M1B. The gate and first terminal of the first transistor M1A are electrically connected to the input terminal INPUT, the second terminal of the first transistor M1A is electrically connected to the first terminal of the first transistor M1B, the gate of the first transistor M1B is electrically connected to the input terminal INPUT, and the second terminal of the first transistor M1B is electrically connected to the first node PU. The second terminal of the first transistor M1A and the first terminal of the first transistor M1B are both electrically connected to the fourth node CB1. The input terminal INPUT of the nth stage drive control circuit may be electrically connected to the second output terminal OUT2(n-1) of the (n-1)th stage drive control circuit.

[0279] In some examples, the first control circuit 221 may include two fifth transistors, M5A and M5B. The gate and first terminal of the fifth transistor M5A are both electrically connected to the first power supply terminal VDD1, and the second terminal of the fifth transistor M5A is electrically connected to the first terminal of the fifth transistor M5B; the gate of the fifth transistor M5B is electrically connected to the first power supply terminal VDD1, and the second terminal of the fifth transistor M5B is electrically connected to the second node PD1.

[0280] In some examples, the second control circuit 222 may include two thirteenth transistors, M13A and M13B. The gate and first terminal of the thirteenth transistor M13A are both electrically connected to the first power supply terminal VDD1, and the second terminal of the thirteenth transistor M13A is electrically connected to the first terminal of the thirteenth transistor M13B; the gate of the thirteenth transistor M13B is electrically connected to the first power supply terminal VDD1, and the second terminal of the thirteenth transistor M13B is electrically connected to the second node PD1.

[0281] In some examples, the first output circuit 231 may include a third transistor M3 and a first capacitor C1. The gate of the third transistor M3 is electrically connected to the first node PU, the first electrode of the third transistor M3 is electrically connected to the second clock terminal CLKR2, and the second electrode of the third transistor M3 is electrically connected to the first output terminal OUT1(n). The first electrode of the first capacitor C1 is electrically connected to the first node PU, and the second electrode of the first capacitor C1 is electrically connected to the first output terminal OUT1(n).

[0282] In some examples, the second output circuit 232 may include a fourth transistor M4. The gate of the fourth transistor M4 is electrically connected to the first node PU, the first terminal of the fourth transistor M4 is electrically connected to the third clock terminal CLKR3, and the second terminal of the fourth transistor M4 is electrically connected to the second output terminal OUT2(n). The second clock terminal CLKR2 and the third clock terminal CLKR3 may be configured to provide different signals.

[0283] In some examples, the first noise reduction circuit 241 may include a ninth transistor M9 and a tenth transistor M10. The gate of the ninth transistor M9 is electrically connected to the second node PD1, the first terminal of the ninth transistor M9 is electrically connected to the third power supply terminal VGL1, and the second terminal of the ninth transistor M9 is electrically connected to the first output terminal OUT1(n). The gate of the tenth transistor M10 is electrically connected to the second node PD1, the first terminal of the tenth transistor M10 is electrically connected to the fourth power supply terminal VGL2, and the second terminal of the tenth transistor M10 is electrically connected to the second output terminal OUT2(n).

[0284] In some examples, the second noise reduction circuit 242 may include an eleventh transistor M11 and a twelfth transistor M12. The gate of the eleventh transistor M11 is electrically connected to the third node PD2, the first terminal of the eleventh transistor M11 is electrically connected to the third power supply terminal VGL1, and the second terminal of the eleventh transistor M11 is electrically connected to the first output terminal OUT1(n). The gate of the twelfth transistor M12 is electrically connected to the third node PD2, the first terminal of the twelfth transistor M12 is electrically connected to the fourth power supply terminal VGL2, and the second terminal of the twelfth transistor M12 is electrically connected to the second output terminal OUT2(n).

[0285] In some examples, the first pull-down circuit 251 may include a sixth transistor M6 and an eighteenth transistor M18. The gate of the sixth transistor M6 is electrically connected to the first node PU, the first terminal of the sixth transistor M6 is electrically connected to the fourth power supply terminal VGL2, and the second terminal of the sixth transistor M6 is electrically connected to the second node PD1. The gate of the eighteenth transistor M18 is electrically connected to the second output terminal OUT2(n-1), the first terminal of the eighteenth transistor M18 is electrically connected to the fourth power supply terminal VGL2, and the second terminal of the eighteenth transistor M18 is electrically connected to the second node PD1.

[0286] In some examples, the second pull-down circuit 252 may include a fourteenth transistor M14 and a nineteenth transistor M19. The gate of the fourteenth transistor M14 is electrically connected to the first node PU, the first terminal of the fourteenth transistor M14 is electrically connected to the fourth power supply terminal VLG2, and the second terminal of the fourteenth transistor M14 is electrically connected to the third node PD2. The gate of the nineteenth transistor M19 is electrically connected to the second output terminal OUT2(n-1), the first terminal of the nineteenth transistor M19 is electrically connected to the fourth power supply terminal VLG2, and the second terminal of the nineteenth transistor M19 is electrically connected to the third node PD2.

[0287] In some examples, the third pull-down circuit 261 may include two seventh transistors, M7A and M7B. The gate of the seventh transistor M7A is electrically connected to the second node PD1, the first terminal of the seventh transistor M7A is electrically connected to the second terminal of the seventh transistor M7B, and the second terminal of the seventh transistor M7A is electrically connected to the first node PU; the gate of the seventh transistor M7B is electrically connected to the second node PD1, and the first terminal of the seventh transistor M7B is electrically connected to the fourth power supply terminal VGL2. The first terminal of the seventh transistor M7A and the second terminal of the seventh transistor M7B are both electrically connected to the fourth node CB1.

[0288] In some examples, the fourth pull-down circuit 262 may include two eighth transistors, M8A and M8B. The gate of the eighth transistor M8A is electrically connected to the third node PD2, the first terminal of the eighth transistor M8A is electrically connected to the second terminal of the eighth transistor M8B, and the second terminal of the eighth transistor M8A is electrically connected to the first node PU; the gate of the eighth transistor M8B is electrically connected to the third node PD2, and the first terminal of the eighth transistor M8B is electrically connected to the fourth power supply terminal VGL2. The first terminal of the eighth transistor M8A and the second terminal of the eighth transistor M8B are both electrically connected to the fourth node CB1.

[0289] In some examples, the fifth pull-down circuit 263 may include two second transistors M2A and M2B. The gate of the second transistor M2A is electrically connected to the first control terminal, the first terminal of the second transistor M2A is electrically connected to the second terminal of the second transistor M2B, and the second terminal of the second transistor M2A is electrically connected to the first node PU; the gate of the second transistor M2B is electrically connected to the first control terminal, and the first terminal of the second transistor M2B is electrically connected to the fourth power supply terminal VGL2. The first terminal of the second transistor M2A and the second terminal of the second transistor M2B are both electrically connected to the fourth node CB1. The first control terminal is electrically connected to the second output terminal OUT2(n+1) of the nth stage drive control circuit.

[0290] In some examples, the second pull-up circuit 272 may include a fifteenth transistor M15. The gate of the fifteenth transistor M15 is electrically connected to the first node PU, the first terminal of the fifteenth transistor M15 is electrically connected to the fifth power supply terminal VGH, and the second terminal of the fifteenth transistor M15 is electrically connected to the fourth node CB1.

[0291] In some examples, the first reset circuit 281 may include two seventeenth transistors, M17A and M17B. The gate of the seventeenth transistor M17A is electrically connected to the first reset terminal TRST, the first terminal of the seventeenth transistor M17A is electrically connected to the second terminal of the seventeenth transistor M17B, and the second terminal of the seventeenth transistor M17A is electrically connected to the first node PU; the gate of the seventeenth transistor M17B is electrically connected to the first reset terminal TRST, and the first terminal of the seventeenth transistor M17B is electrically connected to the fourth power supply terminal VGL2. The first terminal of the seventeenth transistor M17A and the second terminal of the seventeenth transistor M17B are both electrically connected to the fourth node CB1.

[0292] In some examples, the second reset circuit 282 may include a twentieth transistor M20. The gate of the twentieth transistor M20 is electrically connected to the second output terminal OUT2(n+1) of the nth stage drive control circuit, the first terminal of the twentieth transistor M20 is electrically connected to the third power supply terminal VGL1, and the second terminal of the twentieth transistor M20 is electrically connected to the first output terminal OUT1(n).

[0293] In some examples, the first electrode of the first node capacitor Cpu is electrically connected to the first node PU, and the second electrode of the first node capacitor Cpu is electrically connected to the fourth power supply terminal VGL2. The first electrode of the second node capacitor Cpd1 is electrically connected to the second node PD1, and the second electrode of the second node capacitor Cpd1 is electrically connected to the fourth power supply terminal VGL2. The first electrode of the third node capacitor Cpd2 is electrically connected to the third node PD2, and the second electrode of the third node capacitor Cpd2 is electrically connected to the fourth power supply terminal VGL2.

[0294] In this example, by setting the first node capacitor Cpu, the voltage of the first node PU can be regulated, thereby improving the stability of the transistors connected to the first node PU. Adjusting the high level provided by the first power supply terminal VDD1 within the range of 38V to -5V can reduce the leakage current of the fifth transistors M5A and M5B, and the sixth transistor M6 in the input and output stages, and can reduce the high level of the second node PD1, thus improving the stability of the transistors connected to the second node PD1.

[0295] In this example, the first terminals of the third transistor M3 and the fourth transistor M4 are connected to different clock terminals. That is, the first terminals of the third transistor M3 and the fourth transistor M4 are designed separately. For example, the high level provided by the second clock terminal CLKR2 is greater than the high level provided by the third clock terminal CLKR3, which can ensure that the first output terminal OUT1(n) provides a higher drive voltage. On the other hand, reducing the voltage of the second output terminal OUT2(n) can reduce the voltage withstand capability of the transistor connected to the second output terminal OUT2(n), thereby improving the reliability of the circuit.

[0296] This embodiment also provides a gate driving circuit, including multiple cascaded driving control circuits.

[0297] Figure 38 is a schematic diagram of a gate driving circuit according to at least one embodiment of the present disclosure. As shown in Figure 38, the gate driving circuit of this example may include multiple cascaded driving control circuits (e.g., including a first-stage driving control circuit GOA(1) to a fourth-stage driving control circuit GOA(4)). The structure of the driving control circuit can be as shown in the foregoing embodiments, and its implementation principle and effect are similar, so it will not be described again here.

[0298] In some examples, as shown in Figure 38, the input terminal INPUT of the first-stage drive control circuit GOA(1) is connected to the start signal line STV, and the input terminal INPUT of the (n+1)th-stage drive control circuit is electrically connected to the second output terminal OUT2(n) of the nth-stage drive control circuit. The first control terminal IN1 of the nth-stage drive control circuit is electrically connected to the second output terminal OUT2(n+1) of the (n+1)th-stage drive control circuit. The first control terminal of the last-stage drive control circuit can be electrically connected to the reset control line RST.

[0299] In some examples, the gate drive circuit can be electrically connected to the reset control line RST, the first power supply line VDL1, the second power supply line VDL2, the third power supply line VL1, the fourth power supply line VL2, and the fifth power supply line VH. The first power supply terminal VDD1 of each stage of the drive control circuit is electrically connected to the first power supply line VDL1; the second power supply terminal VDD2 of each stage of the drive control circuit is electrically connected to the second power supply line VDL2; the third power supply terminal VLG1 of each stage of the drive control circuit is electrically connected to the third power supply line VL1; the fourth power supply terminal VGL2 of each stage of the drive control circuit is electrically connected to the fourth power supply line VL2; the fifth power supply terminal VGH of each stage of the drive control circuit is electrically connected to the fifth power supply line VH; and the first reset terminal TRST of each stage of the drive control circuit is electrically connected to the reset control line RST.

[0300] In some examples, the gate drive circuit is electrically connected to four clock lines (e.g., the first clock line CLK1, the second clock line CLK2, the third clock line CLK3, and the fourth clock line CLK4). The timing of the clock signals provided by the first clock line CLK1 to the fourth clock line CLK4 is shown in Figure 26. To ensure the consistency of operation of each stage of the drive control circuit, the high and low levels provided by the start signal line STV, the reset control line RST, and the clock lines can be kept consistent.

[0301] In some examples, the second and third clock terminals of the 4k+1 level drive control circuit are electrically connected to the first clock line, and the first clock terminal of the 4k+1 level drive control circuit is electrically connected to the second clock line; the second and third clock terminals of the 4k+2 level drive control circuit are electrically connected to the second clock line, and the first clock terminal of the 4k+2 level drive control circuit is electrically connected to the third clock line; the second and third clock terminals of the 4k+3 level drive control circuit are electrically connected to the third clock line, and the first clock terminal of the 4k+3 level drive control circuit is electrically connected to the fourth clock line; the second and fourth clock terminals of the 4k+4 level drive control circuit are electrically connected to the fourth clock line, and the first clock terminal of the 4k+4 level drive control circuit is electrically connected to the first clock line, where k is an integer greater than or equal to 0.

[0302] For example, in the first-stage drive control circuit GOA(1), the first clock terminal CLKR1 is electrically connected to the second clock line CLK2, and the second clock terminal CLKR2 is electrically connected to the first clock line CLK1; in the second-stage drive control circuit GOA(2), the first clock terminal CLKR1 is electrically connected to the third clock line CLK3, and the second clock terminal CLKR2 is electrically connected to the second clock line CLK2; in the third-stage drive control circuit GOA(3), the first clock terminal CLKR1 is electrically connected to the fourth clock line CLK4, and the second clock terminal CLKR2 is electrically connected to the third clock line CLK3; in the fourth-stage drive control circuit GOA(4), the first clock terminal CLKR1 is electrically connected to the fourth clock line CLK4, and the second clock terminal CLKR2 is electrically connected to the first clock line CLK1. The connection relationship between the drive control circuits and clock lines after the fifth-stage drive control circuit can be cyclically repeated until the end.

[0303] In other examples, when the display boundary area of ​​the display substrate is provided with a second sub-pixel, the second clock terminal of the first-level driving control circuit can be electrically connected to a second clock line, a third clock line, or a fourth clock line. The second clock terminal of the driving control circuit connected to the first sub-pixel of the first row in the display center area can be electrically connected to the first clock line. This embodiment is not limited in this respect. In other examples, when the display boundary area of ​​the display substrate is provided with a second sub-pixel, the second clock terminal of the first-level driving control circuit can be electrically connected to the first clock line.

[0304] For example, if the display boundary area is set with two rows of second sub-pixels and the gate driving circuit adopts a bilateral driving method, then the second clock terminal of the first-level driving control circuit can be electrically connected to the third clock line CLK3, the second clock terminal of the second-level driving control circuit can be electrically connected to the fourth clock line CLK4, the third-level driving control circuit is connected to the first sub-pixel of the first row, and the second clock terminal of the third-level driving control circuit can be electrically connected to the first clock line.

[0305] In some examples, the gate driving circuit can be located in a non-display area, such as the left and right bezel areas of the non-display area. The gate driving circuit is electrically connected to multiple gate lines in the display area. The display substrate may also include a detection circuit and an electrostatic discharge circuit located in the non-display area. The detection circuit can be configured to write a detection signal provided by a detection signal line to a first output terminal of the driving control circuit under the control of a detection control line. The electrostatic discharge circuit may include a first electrostatic discharge circuit and a second electrostatic discharge circuit. The first electrostatic discharge circuit may be electrically connected to a common electrode and a short-circuit ring, and the second electrostatic discharge circuit may be electrically connected to the gate lines and the short-circuit ring.

[0306] Figure 39 is an equivalent circuit diagram of the drive control circuit and detection circuit of at least one embodiment of the present disclosure. In some examples, as shown in Figure 39, the detection circuit 291 includes a detection transistor MT. The gate of the detection transistor MT is electrically connected to the detection control line SW_G, the first terminal of the detection transistor MT is electrically connected to the detection signal line SIG, and the second terminal of the detection transistor MT is electrically connected to the first output terminal OUT1(n). The first output terminal of each stage of the drive control circuit is electrically connected to a corresponding detection circuit. When the detection control line SW_G provides a high-level signal, the detection transistor MT is turned on, and the detection signal transmitted by the detection signal line SIG can be written into the gate line connected to the drive control circuit of that stage. Under the control of multiple detection circuits, all gate lines can be synchronously written with detection signals. During the detection stage, when the data line writes the corresponding signal, without the need for complex gate drive control, the detection circuit can be used to achieve simple lighting of the display area. The structure of the drive control circuit can be referred to the description of the foregoing embodiments, and will not be repeated here.

[0307] Figure 40 is an equivalent circuit diagram of an electrostatic discharge circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 40, the electrostatic discharge circuit may include: a first electrostatic discharge transistor ET1, a second electrostatic discharge transistor ET2, a third electrostatic discharge transistor ET3, and a fourth electrostatic discharge transistor ET4. The gates of the first electrostatic discharge transistor ET1 and the third electrostatic discharge transistor ET3 are both electrically connected to the connection node EN. The first terminal of the first electrostatic discharge transistor ET1 is electrically connected to the gate line GL or the common voltage line COM. The second terminal of the first electrostatic discharge transistor ET1 is electrically connected to the connection node EN. The first terminal of the third electrostatic discharge transistor ET3 is electrically connected to the connection node EN, and the second terminal of the third electrostatic discharge transistor ET3 is electrically connected to the short-circuit ring SR. The gate and the first terminal of the second electrostatic discharge transistor ET2 are electrically connected to the gate line GL or the common voltage line COM, and the second terminal of the second electrostatic discharge transistor ET2 is electrically connected to the connection node EN. The gate and the second terminal of the fourth electrostatic discharge transistor ET4 are both electrically connected to the short-circuit ring SR, and the first terminal of the fourth electrostatic discharge transistor ET4 is electrically connected to the connection node EN.

[0308] In some examples, a first electrostatic discharge circuit may be electrically connected to the common voltage line COM and configured to discharge static electricity on the common voltage line COM; a second electrostatic discharge circuit may be electrically connected to the gate line GL and configured to discharge static electricity on the gate line GL. The common voltage line COM is electrically connected to the common electrode of the display area.

[0309] In some examples, when a high voltage is present on the gate line GL or the common voltage line COM, the second electrostatic discharge transistor ET2 turns on, and the high level propagates along ET2 to the connection node EN. At this time, the third electrostatic discharge transistor ET3 turns on, and the high level is propagated to the short-circuit ring SR. Subsequently, the high level on the short-circuit ring SR can turn on multiple fourth electrostatic discharge transistors ET4 connected to the short-circuit ring SR, allowing the high level to diffuse. During this process, the high level gradually decreases, which can mitigate the damage caused by static electricity to the display substrate.

[0310] Figures 41A to 41C are partial planar schematic diagrams of the non-display area of ​​a display substrate according to at least one embodiment of the present disclosure. Figures 41A to 41C illustrate a driving control circuit, a detection circuit, and a second electrostatic discharge circuit. Figures 41A to 41C can be sequentially stitched together along the first direction D1 to obtain a complete layout of the driving control circuit. The detection circuit and the second electrostatic discharge circuit are illustrated in Figure 41C. The detection circuit and the second electrostatic discharge circuit can be located on the side of the driving control circuit closer to the display area.

[0311] Figure 41A illustrates the first power line VDL1, the second power line VDL2, the reset control line RST, the fourth power line VL2, the fifth power line VH, the third clock line CLK3 and the fourth clock line CLK4, the input circuit (including the first transistors M1A and M1B), the fifth pull-down circuit (including the second transistors M2A and M2B), the second output circuit (including the fourth transistor M4 and the second capacitor C2), the first control circuit (including the fifth transistor M5), the first pull-down circuit (including the sixth transistor M6), the second control circuit (including the thirteenth transistor M13), the second pull-down circuit (including the fourteenth transistor M14), the first pull-up circuit (including the fifteenth transistor M15), the second pull-up circuit (including the sixteenth transistor M16), and the first reset circuit (including the seventeenth transistors M17A and M17B).

[0312] In some examples, as shown in Figure 41A, the third clock line CLK3, the fourth clock line CLK4, the fifth power supply line VH, the reset control line RST, the first power supply line VDL1, the second power supply line VDL2, and the fourth power supply line VL2 can extend along the second direction D2 and be arranged sequentially along the first direction D1. The fourth transistor M4, the thirteenth transistor M13, and the fifth transistor M5 are adjacent to the fourth power supply line VL2 in the first direction D1. The second output circuit, the second pull-up circuit, and the first pull-up circuit can be arranged sequentially along the first direction D1, wherein the fourth transistor M4, the second capacitor C2, the sixteenth transistor M16, and the fifteenth transistor M15 can be arranged sequentially along the first direction D1, and the first transistor M1B in the input circuit is located on the side closest to the fourth power supply line VL2. The first transistor M1B and the fifteenth transistor M15 are adjacent in the first direction D1. The first transistor M1B and M1A are arranged adjacent in the first direction D1. The second control circuit and the first control circuit are arranged adjacently along the second direction D2, wherein the thirteenth transistor M13 and the fifth transistor M5 are arranged adjacently along the second direction D2, and the thirteenth transistor M13 is located between the fifth transistor M5 and the fourth transistor M4 in the second direction D2. The seventeenth transistors M17A and M17B are arranged adjacently along the second direction D2 and are aligned with the second capacitor C2 in the second direction D2. The first pull-down circuit and the second pull-down circuit are arranged adjacently along the first direction D1, wherein the sixth transistor M6 and the fourteenth transistor M14 are arranged adjacently along the first direction D1 and are located between the fifth transistor M5 and the seventeenth transistor M17B. The fifth pull-down circuit is located between the first reset circuit and the input circuit in the first direction D1, wherein the second transistors M2A and M2B are arranged adjacently along the first direction D1 and are located between the seventh transistor M17B and the first transistor M1B.

[0313] Figure 41B illustrates the third pull-down circuit (including the seventh transistors M7A and M7B), the fourth pull-down circuit (including the eighth transistors M8A and M8B), the first noise reduction circuit (including the ninth transistor M9 and the eleventh transistor M11), the second noise reduction circuit (including the tenth transistor M10 and the twelfth transistor M12), the first node capacitor Cpu, the second node capacitor Cpd1, and the third node capacitor Cpd2.

[0314] In some examples, as shown in Figure 41B, the eighth transistor M8A, the third node capacitor Cpd2, the eighth transistor M8B, the second node capacitor Cpd1, the seventh transistor M7B, and the seventh transistor M7A are arranged sequentially along the first direction D1, and the tenth transistor M10, the twelfth transistor M12, the eleventh transistor M11, and the ninth transistor M9 are arranged sequentially along the first direction D1. The eighth transistor M8A and the tenth transistor M10 may be adjacent to the first transistor M1A in the first direction D1. The first node capacitor Cpd1 is adjacent to the seventh transistor M7A and the ninth transistor M9 in the first direction D1. The eighth transistor M8A is adjacent to the tenth transistor M10 and the twelfth transistor M12 in the second direction D2, the eighth transistor M8B is adjacent to the eleventh transistor M11 in the second direction D2, and the seventh transistor M7B is adjacent to the ninth transistor M9 in the second direction D2.

[0315] Figure 41C illustrates the first output circuit (including the third transistor M3 and the first capacitor C1), the detection circuit (including the detection transistor MT), the first electrostatic discharge circuit (including the first electrostatic discharge transistor ET1, the second electrostatic discharge transistor ET2, the third electrostatic discharge transistor ET3 and the fourth electrostatic discharge transistor ET4), and the third power supply line VL1.

[0316] In some examples, as shown in Figures 41 and 41C, the first capacitor C1 is adjacent to the first node capacitor Cpu in the first direction D1, and the third transistor M3 is located on the side of the first capacitor C1 away from the first node capacitor Cpu. The third power line VL1 extends along the second direction D2 and is located between the third transistor M3 and the detection transistor MT in the first direction D1. The first electrostatic discharge transistor ET1 and the second electrostatic discharge transistor ET2 are aligned along the first direction D1, and the third electrostatic discharge transistor ET3 and the fourth electrostatic discharge transistor ET4 are aligned along the first direction D1. The first electrostatic discharge transistor ET1 and the third electrostatic discharge transistor ET3 are aligned along the second direction D2, and the second electrostatic discharge transistor ET2 and the fourth electrostatic discharge transistor ET4 are aligned along the second direction D2. The first electrostatic discharge transistor ET1 and the third electrostatic discharge transistor ET3 are adjacent to the detection transistor MT in the first direction D1.

[0317] The setup of the drive control circuit in this example optimizes the spatial layout, reduces the space occupied by the drive control circuit, and facilitates signal transmission wiring.

[0318] In some examples, the circuit structure of the non-display area (including drive control circuitry, detection circuitry, and electrostatic discharge circuitry) can be fabricated synchronously with the sub-pixels of the display area. For example, the active layer of the transistor in the circuit structure of the non-display area can be located on a semiconductor layer, and the transistor in the non-display area can employ a dual-gate design, wherein the transistor can include a bottom gate located on the side of the active layer closer to the substrate and a top gate located on the side of the active layer farther from the substrate. The bottom gate of the transistor can be located on a first conductive layer, and the top gate of the transistor can be located on a second conductive layer. The top gate can be electrically connected to the bottom gate through vias formed in the second insulating layer and the first insulating layer.

[0319] Figure 42A is a schematic diagram of the first conductive layer in Figure 41A; Figure 42B is a schematic diagram of the first conductive layer in Figure 41B; Figure 42C is a schematic diagram of the first conductive layer in Figure 41C.

[0320] In some examples, as shown in Figures 42A to 42C, the first conductive layer in the non-display area may include: multiple traces (e.g., including the third clock line CLK3, the fourth clock line CLK4, the first power line VDL1, the second power line VDL2, the fourth power line VL2, the reset control line RST, and the fifth power line VH), the bottom gates of multiple transistors, the first electrodes of multiple capacitors, multiple interconnects (e.g., including the first interconnect 601 to the eighth interconnect 608), a short-circuit ring SR, and a detection control line SW_G.

[0321] In some examples, as shown in Figures 41A and 42A, the third clock line CLK3 may include two sub-lines extending along the second direction D2 and connected as a single structure; the fourth clock line CLK4 may include two sub-lines extending along the second direction D2 and connected as a single structure. The bottom gate 401A of the first transistor M1A and the bottom gate 401B of the first transistor M1B may be a single structure, and this single structure is a bent line extending along the first direction D1. The bottom gate 402A of the second transistor M2A, the bottom gate 402B of the second transistor M2B, and the fourth connection line 604 are a single structure. The single structure of the bottom gate 402A of the second transistor M2A and the bottom gate 402B of the second transistor M2B is U-shaped, and the fourth connection line 604 may extend along the first direction D1 to be adjacent to the fifth connection line 605. The fourth connection line 604 may be electrically connected to the second output terminal of the (n+1)th stage drive control circuit.

[0322] In some examples, as shown in Figures 41A and 42A, the bottom gate 404 of the fourth transistor M4 and the first electrode C2-1 of the second capacitor C can be a single integrated structure. The bottom gate 405 of the fifth transistor M5 and the bottom gate 413 of the thirteenth transistor M13 can be a single integrated structure. The bottom gate 406 of the sixth transistor M6 and the bottom gate 414 of the fourteenth transistor M14 can be a single integrated structure, which can be approximately U-shaped. The bottom gate 417A of the seventeenth transistor M17A, the bottom gate 417B of the seventeenth transistor M17B, and the second connection line 602 can be a single integrated structure, and the second connection line 602 can extend at least along the first direction D1. The bottom gate 415 of the fifteenth transistor M15 and the bottom gate 416 of the sixteenth transistor M16 can be a single integrated structure, which is U-shaped.

[0323] In some examples, as shown in Figures 41A and 42A, the first connection line 601 may extend along the first direction D1 and be located on the side of the bottom gate 404 of the fourth transistor M4 near the bottom gate 413 of the thirteenth transistor M13. The third connection line 603 may extend along the first direction D1 and be located on the side of the second connection line 602 away from the bottom gate 405 of the fifth transistor M5. The fifth connection line 605 and the sixth connection line 606 may extend at least along the second direction D2, and the fifth connection line 605 is located on the side of the sixth connection line 606 near the bottom gate 401A of the first transistor M1A in the first direction D1.

[0324] In some examples, as shown in Figures 41B and 42B, the bottom gate 408A of the eighth transistor M8A, the first electrode Cpd2-1 of the third node capacitor Cpd2, the bottom gate 408B of the eighth transistor M8B, the bottom gate 411 of the eleventh transistor M11, and the bottom gate 412 of the twelfth transistor M12 can be a single integrated structure. Similarly, the first electrode Cpd1-1 of the second node capacitor Cpd1, the bottom gate 407B of the seventh transistor M7B, the bottom gate 407A of the seventh transistor M407A, and the bottom gate 409 of the ninth transistor M9 can be a single integrated structure.

[0325] In some examples, as shown in Figures 41C and 42C, the first electrode C1-1 of the first capacitor C1, the first capacitor Cpd1-1 of the first node capacitor Cpd1, and the bottom gate 403 of the third transistor M3 can be a single integrated structure. The seventh connecting line 607 and the eighth connecting line 608 can be adjacent in the first direction D1. The bottom gate 425 of the detection transistor MT can be a bent line extending along the first direction D1. The bottom gates 421 of the first electrostatic discharge transistor, 422 of the second electrostatic discharge transistor, 423 of the third electrostatic discharge transistor, and 424 of the fourth electrostatic discharge transistor can be arranged in a 2×2 array along the first direction D1 and the second direction D2.

[0326] Figure 43A is a schematic diagram of the semiconductor layer in Figure 41A; Figure 43B is a schematic diagram of the semiconductor layer in Figure 41B; Figure 43C is a schematic diagram of the semiconductor layer in Figure 41C.

[0327] In some examples, as shown in Figures 43A to 43C, the semiconductor layer in the non-display area may include an active layer of multiple transistors.

[0328] In some examples, as shown in Figures 41A and 43A, the active layer 301A of the first transistor M1A includes a plurality (e.g., eleven) of active strips extending along a first direction D1 and arranged along a second direction D2, and the active layer 301B of the first transistor M1B includes a plurality (e.g., eleven) of active strips extending along a first direction D1 and arranged along a second direction D2. The eleven active strips of active layer 301A are connected one-to-one with the eleven active strips of active layer 301B. The active layer 302A of the second transistor M2A includes five active layers extending along a first direction D1 and arranged along a second direction D2, and the active layer 302B of the second transistor M2B includes five active strips extending along a first direction D1 and arranged along a second direction D2, and the five active layers of active layer 302A and the five active strips of active layer 302B are connected one-to-one. The active layer 304 of the fourth transistor M4 includes three active strips extending along a first direction D1 and arranged along a second direction D2. The active layer 305 of the fifth transistor M5 includes two active strips extending along a first direction D1 and arranged along a second direction D2. The active layer 313 of the thirteenth transistor M13 includes two active strips extending along a first direction D1 and arranged along a second direction D2. The two active strips of the active layer 305 and the two active strips of the active layer 313 are aligned in the second direction D2.

[0329] In some examples, as shown in Figures 41A and 43A, the active layer 306 of the sixth transistor M6 includes four active strips extending along a first direction D1 and arranged along a second direction D2. The active layer 314 of the fourteenth transistor M14 includes four active strips extending along a first direction D1 and arranged along a second direction D2. The four active strips of the active layer 306 are connected one-to-one with the four active strips of the active layer 314.

[0330] In some examples, as shown in Figures 41A and 43A, the active layer 317A of the seventeenth transistor M17A includes two active strips extending along a first direction D1 and arranged along a second direction D2. The active layer 317B of the seventeenth transistor M17B includes two active strips extending along a first direction D1 and arranged along a second direction D2. The two active strips of active layer 317A and the two active strips of active layer 317B are aligned in the second direction D2. The active layers 315 of the fifteenth transistor M15 and 316 of the sixteenth transistor M16 can be a single structure and extend along the first direction D1.

[0331] In some examples, as shown in Figures 41B and 43B, the active layer 308A of the eighth transistor M8A includes three active strips extending along a first direction D1 and arranged along a second direction D2; the active layer 308B of the eighth transistor M8B includes three active strips extending along a first direction D1 and arranged along a second direction D2; the active layer 307A of the seventh transistor M7A includes three active strips extending along a first direction D1 and arranged along a second direction D2; and the active layer 307B of the seventh transistor M7B includes three active strips extending along a first direction D1 and arranged along a second direction D2. The three active strips of active layer 308A, active layer 308B, active layer 307A, and active layer 307B can be aligned along the first direction D1.

[0332] In some examples, as shown in Figures 41B and 43B, the active layer 310 of the tenth transistor M10 includes three active strips extending along a first direction D1 and arranged along a second direction D2; the active layer 312 of the twelfth transistor M12 includes three active strips extending along a first direction D1 and arranged along a second direction D2. The three active strips of active layer 310 and the three active strips of active layer 312 are aligned along the first direction D1. The active layer 311 of the eleventh transistor M11 includes six active strips extending along a first direction D1 and arranged along a second direction D2; the active layer 309 of the ninth transistor M9 includes six active strips extending along a first direction D1 and arranged along a second direction D2. The six active strips of active layer 311 and the six active strips of active layer 309 are aligned along the first direction D1.

[0333] In some examples, as shown in Figures 41C and 43C, the active layer 303 of the third transistor M3 includes twelve active strips extending along a first direction D1 and arranged along a second direction D2. The active layer 325 of the detection transistor MT includes eight active strips extending along a first direction D1 and arranged along a second direction D2. The active layer 321 of the first electrostatic discharge transistor ET1 and the active layer 323 of the third electrostatic discharge transistor ET3 are integral structures and extend along the second direction D2; the active layer 322 of the second electrostatic discharge transistor ET2 and the active layer 324 of the fourth electrostatic discharge transistor ET4 can be integral structures and extend along the second direction D2.

[0334] Figure 44A is a schematic diagram of the semiconductor layer and the second conductive layer in Figure 41A; Figure 44B is a schematic diagram of the semiconductor layer and the second conductive layer in Figure 41B; Figure 44C is a schematic diagram of the semiconductor layer and the second conductive layer in Figure 41C.

[0335] In some examples, as shown in Figures 44A to 44C, the second conductive layer in the non-display area may include: top gates of multiple transistors, second electrodes of multiple capacitors, a third power line VL1, multiple connection lines (e.g., including the ninth connection line 609 to the twenty-second connection line 622), multiple connection electrodes (e.g., including the first connection electrode 701 to the eleventh connection electrode 711), an input terminal INPUT, a first output terminal OUT1(n), a second output terminal OUT2(n), and a common voltage line COM. The top gates of the transistors are electrically connected to the bottom gates, and the orthographic projections of the top gates onto the substrate and the bottom gates onto the substrate may at least partially overlap; for example, the orthographic projection of the top gates onto the substrate may be located within the orthographic projection range of the bottom gates onto the substrate.

[0336] In some examples, as shown in Figures 41A to 44A, the top gate 501A of the first transistor M1A, the top gate 501B of the first transistor M1B, and the input terminal INPUT can be a single integrated structure, connected to the active layer of the first transistor M1A, serving as the first electrode of the first transistor M1A. The input terminal INPUT can be electrically connected to the sixth connection line 606, which can be electrically connected to the second output terminal of the preceding stage drive control circuit. The first connection electrode 701 is connected to the active layers of the first transistors M1A and M1B, serving as the second electrode of the first transistor M1A and the first electrode of the first transistor M1B; it can also be connected to the active layer of the fifteenth transistor M15, serving as the second electrode of the fifteenth transistor M15. The orthographic projection of the first connection electrode 701 onto the substrate is approximately mountain-shaped. The second connection electrode 702 is connected to the active layer of the first transistor M1B, serving as the second electrode of the first transistor M1B. The second connection electrode 702 is integrated with the ninth connection line 609. The ninth connection line 609 can also extend to be adjacent to the second electrode C2-2 of the second capacitor C2, and be connected to the integrated structure of the bottom gate 404 of the fourth transistor M4 and the first electrode C2-1 of the second capacitor C2 located on the first conductive layer. The integrated structure of the bottom gate 404 of the fourth transistor M4 and the first electrode C2-1 of the second capacitor C2 can be electrically connected to the third connection electrode 703. The third connection electrode 703 can be connected to the active layer of the seventeenth transistor M17A and the active layer of the second transistor M2A, serving as the second electrode of the seventeenth transistor M17A and the second electrode of the second transistor M2A. The ninth connection electrode 609 can be equivalent to the first node.

[0337] In some examples, as shown in Figures 41A to 44A, the top gate 502A of the second transistor M2A and the top gate 502B of the second transistor M2B can be strips extending along the second direction D2. The tenth connection line 610 can be connected to the active layer of the second transistor M2B as the first electrode of the second transistor M2B, and can also be connected to the active layer of the seventeenth transistor M17B as the first electrode of the seventeenth transistor M17B. The tenth connection line 610 can also be connected to the third connection line 603 located on the first conductive layer, and the third connection line 603 can be electrically connected to the fourth power line VL2 located on the first conductive layer via the twentieth connection line 620 located on the second conductive layer.

[0338] In some examples, as shown in Figures 41A to 44A, the top gate 517A of the seventeenth transistor M17A and the top gate 517B of the seventeenth transistor M17B can be a single, integrated structure, which is a strip extending along the second direction D2. The fourth connection electrode 704 can be connected to the active layers of the seventeenth transistor M17A, the seventeenth transistor M17B, the second transistor M2A, the second transistor M2B, and the sixteenth transistor M16, serving as the first electrode of the seventeenth transistor M17A, the second electrode of the seventeenth transistor M17B, the first electrode of the second transistor M2A, the second electrode of the second transistor M2B, and the second electrode of the sixteenth transistor M16. The fourth connection electrode 704 can be connected to the eleventh connection line 611, which can correspond to the fourth node CB1.

[0339] In some examples, as shown in Figures 41A to 44A, the top gate 515 of the fifteenth transistor M15, the top gate 516 of the sixteenth transistor M16, the second electrode C2-2 of the second capacitor C2, the seventh connection electrode 707, and the second output terminal OUT2(n) can be an integral structure. The second electrode C2-2 of the second capacitor C2 can be a strip extending along the second direction D2. The seventh connection electrode 707 can be connected to the active layer of the fourth transistor M4, serving as the second electrode of the fourth transistor M4. The second output terminal OUT2(n) can be connected to the fifth connection line 605 located on the first conductive layer.

[0340] In some examples, as shown in Figures 41A to 44A, the fifth connection electrode 705 can be connected to the active layer of the fifteenth transistor M15 and the sixteenth transistor M16, serving as the first electrode of the fifteenth transistor M15 and the sixteenth transistor M16. The fifth connection electrode 705 can be connected to the first connection line 601 located on the first conductive layer, the first connection line 601 can be connected to the seventeenth connection line 617 located on the second conductive layer, and the seventeenth connection line 617 can be connected to the fifth power line VH located on the first conductive layer.

[0341] In some examples, as shown in Figures 41A to 44A, the sixth connection electrode 706 can be connected to the active layer of the sixth transistor M6 and the fourteenth transistor M14, serving as the first electrode of the sixth transistor M6 and the fourteenth transistor M14. The sixth connection electrode 706 can be connected to the bottom gate of the thirteenth transistor M13 located on the first conductive layer, and the bottom gate of the thirteenth transistor M13 can be connected to the sixteenth connection line 616 located on the second conductive layer. The sixteenth connection line 616 can be connected to the fourth clock line CLK4 located on the second conductive layer. The eighteenth connection line 618, projected onto the substrate, can be H-shaped. The eighteenth connection line 618 can be connected to the fourth clock line CLK4 located on the first conductive layer to help reduce the impedance of the fourth clock line CLK4.

[0342] In some examples, as shown in Figures 41A to 44A, the eighth connection electrode 708 can be connected to the active layer of the thirteenth transistor M13, serving as the first electrode of the thirteenth transistor M13. The eighth connection electrode 708 can also be connected to the second power line VDL2 located on the first conductive layer. The ninth connection electrode 709 can be connected to the active layer of the fifth transistor M5, serving as the first electrode of the fifth transistor M5. The ninth connection electrode 709 can also be connected to the first power line VDL1 located on the first conductive layer.

[0343] In some examples, as shown in Figures 41A to 44A, the top gate 504 of the fourth transistor M4 can be a bent line extending along the first direction D1. The top gate 505 of the fifth transistor M5 and the top gate 513 of the thirteenth transistor M13 can be a single structure, which is a strip extending along the second direction D2. The top gate 506 of the sixth transistor M6 and the top gate of the fourteenth transistor M14 can be a single structure, which can be U-shaped.

[0344] In some examples, as shown in Figures 41A to 44A, the twelfth connection line 612 can extend at least along the first direction D1 and connect to the active layer of the fourth transistor M4, serving as the first terminal of the fourth transistor M4. It can also be connected to the third clock line CLK3 located on the first conductive layer. The orthogonal projection of the thirteenth connection line 613 onto the substrate can be H-shaped. The thirteenth connection line 613 can be connected to the third clock line CLK3 located on the first conductive layer to help reduce the impedance of the third clock line CLK3.

[0345] In some examples, as shown in Figures 41A to 44A, the fourteenth connection line 614 can be connected to the active layer of the thirteenth transistor M13, serving as the second terminal of the thirteenth transistor M13; it can also be connected to the active layer of the fourteenth transistor M14, serving as the second terminal of the fourteenth transistor M14. The fourteenth connection line 614 is equivalent to the third node. The fifteenth connection line 615 can be connected to the active layer of the fifth transistor M5, serving as the second terminal of the fifth transistor M5; it can also be connected to the active layer of the sixth transistor M6, serving as the second terminal of the sixth transistor M6. The fifteenth connection line 615 is equivalent to the second node. The nineteenth connection line 619 can be connected to the reset control line RST located on the first conductive layer, and it can also be connected to the second connection line 602 located on the first conductive layer, realizing the electrical connection with the bottom gate of the seventeenth transistors M17A and M17B.

[0346] In some examples, as shown in Figures 41B to 44B, the top gate 508A of the eighth transistor M8A is connected to the bottom gate 408A, the top gate 508B of the eighth transistor M8B is connected to the bottom gate 408B, the top gate 507A of the seventh transistor M7A is connected to the bottom gate 407A, and the top gate 507B of the seventh transistor M7B is connected to the bottom gate 407B.

[0347] In some examples, as shown in Figures 41B to 44B, the top gate 510 of the tenth transistor M10 is connected to the bottom gate 410, and the top gate 509 of the ninth transistor M9 is connected to the bottom gate 409. The top gate 510 of the tenth transistor M10 and the fifteenth connection line 615 are integrally formed. The fifteenth connection line 615 is connected to the bottom gate 409 of the ninth transistor M9 located in the first conductive layer. The top gate 511 of the eleventh transistor M11 is connected to the bottom gate 411. The top gate 512 of the twelfth transistor M12 is connected to the bottom gate 412. The top gate 512 of the twelfth transistor M12 and the fourteenth connection line 614 are integrally formed. The bottom gate 411 of the eleventh transistor M11 and the bottom gate 412 of the twelfth transistor M12 are integrally formed.

[0348] In some examples, as shown in Figures 41B to 44B, the ninth connection line 609 can also be connected to the active layer of the eighth transistor M8A and the active layer of the seventh transistor M7A, serving as the first electrode of the eighth transistor M8A and the first electrode of the seventh transistor M7A. The tenth connection line 610 can be integrated with the second electrode Cpd2-2 of the third node capacitor Cpd2, the second electrode Cpd1-2 of the second node capacitor Cpd1, and the second electrode Cpu-2 of the first node capacitor Cpu. The tenth connection line 610 can also be connected to the active layers of the eighth transistor M8B, the seventh transistor M7B, the tenth transistor M10, and the twelfth transistor M12, serving as the second electrode of the eighth transistor M8B, the seventh transistor M7B, the tenth transistor M10, and the twelfth transistor M12. The eleventh connection line 611 can also be connected to the active layer of the eighth transistor M8A, the active layer of the eighth transistor M8B, the active layer of the seventh transistor M7A, and the active layer of the seventh transistor M7B, serving as the first terminal of the eighth transistor M8A, the second terminal of the eighth transistor M8B, the first terminal of the seventh transistor M7A, and the second terminal of the seventh transistor M7B.

[0349] In some examples, as shown in Figures 41B to 44B, the twenty-first connection line 621 can be connected to the active layers of the ninth transistor M9 and the eleventh transistor M11, serving as the first terminals of the ninth and eleventh transistors. The twenty-second connection line 622 can be connected to the active layers of the ninth transistor M9 and the eleventh transistor M11, serving as the second terminals of the ninth and eleventh transistors. The twenty-first connection line 621 can be located on the side of the twenty-second connection line 622 furthest from the first node capacitor Cpu.

[0350] In some examples, as shown in Figures 41B to 44B, the tenth connection electrode 710 can be connected to the active layer of the tenth transistor M10 and the active layer of the twelfth transistor M12, serving as the second electrode of the tenth transistor M10 and the twelfth transistor M12. The tenth connection electrode 710 can be connected to the fifth connection line 605 located in the first conductive layer to achieve an electrical connection with the second output terminal OUT2(n).

[0351] In some examples, as shown in Figures 41C to 44C, the top gate 503 of the third transistor M3 is connected to the bottom gate 403. The top gate 403 of the third transistor M3 is integrated with the ninth connection line 609. The twelfth connection line 612 can also be connected to the active layer of the third transistor M3, serving as the first electrode of the third transistor M3. The twenty-second connection line 622 can be integrated with the second electrode C1-2 of the first capacitor C1, and can also be connected to the active layer of the third transistor M3, serving as the second electrode of the third transistor. The twenty-second connection line 622 can be connected to the seventh connection line 607 located on the first conductive layer, and the seventh connection line 607 can be connected to the first output terminal OUT1(n) located on the second conductive layer. The seventh connection line 607 can be configured to be connected to the input terminal of the previous stage drive control circuit. The twenty-first connection line 621 can be integrated with the third power supply line VL1.

[0352] In some examples, as shown in Figures 41C to 44C, the top gate 525 of the detection transistor MT is connected to the bottom gate 425. The bottom gate 425 of the detection transistor MT is connected to the detection control line SW_G located on the first conductive layer via the eleventh connection electrode 711 located on the second conductive layer. The detection signal line SIG is connected to the active layer of the detection transistor MT, serving as the first electrode of the detection transistor MT. The detection signal line SIG can also be connected to the eighth connection line 608 located on the first conductive layer. The first output terminal OUT1(n) is connected to the active layer of the detection transistor MT, serving as the second electrode of the detection transistor MT.

[0353] In some examples, as shown in Figures 41C to 44C, the top gate 521 of the first electrostatic discharge transistor ET1 and the top gate 523 of the third electrostatic discharge transistor ET3 can be an integral structure, connected to the active layers of the first electrostatic discharge transistor ET1, the second electrostatic discharge transistor ET2, the third electrostatic discharge transistor ET3, and the fourth electrostatic discharge transistor ET4, serving as the second terminal of the first electrostatic discharge transistor ET1, the second terminal of the second electrostatic discharge transistor ET2, the first terminal of the third electrostatic discharge transistor ET3, and the first terminal of the fourth electrostatic discharge transistor ET4. The top gate 522 of the second electrostatic discharge transistor ET2 is an integral structure with the common voltage line COM, connected to the active layers of the first electrostatic discharge transistor ET1 and the second electrostatic discharge transistor ET2, serving as the first terminal of the first electrostatic discharge transistor ET1 and the first terminal of the second electrostatic discharge transistor ET2. The top gate 524 of the fourth electrostatic discharge transistor ET4 is connected to the active layers of the third electrostatic discharge transistor ET3 and the fourth electrostatic discharge transistor ET4, and can serve as the second terminal of the third electrostatic discharge transistor ET3 and the fourth electrostatic discharge transistor ET4. The top gate 524 of the fourth electrostatic discharge transistor ET4 can also be connected to the short-circuit ring SR located in the first conductive layer.

[0354] The following uses the structure of the tenth transistor as an example to illustrate the film layer relationship of the transistor.

[0355] Figure 45 is a schematic diagram of the tenth transistor in Figure 41B. Figure 46 is a partial cross-sectional view along the AA' direction in Figure 45. Figure 47 is a partial cross-sectional view along the BB' direction in Figure 45.

[0356] In some examples, as shown in Figures 45 to 47, the bottom gate 410 of the tenth transistor M10 is located in the first conductive layer, the active layer 310 of the tenth transistor M10 is located in the semiconductor layer, and the top gate 510, the tenth connection electrode 710, and the tenth connection line 610 of the tenth transistor M10 are located in the second conductive layer. The top gate 510 is connected to the bottom gate 410 through vias formed in the second insulating layer 102 and the first insulating layer 101. The tenth connection electrode 710 and the tenth connection line 610 are connected to the active layer 310 through vias formed in the second insulating layer 102. The tenth connection electrode 710 can serve as the second electrode of the tenth transistor M10, and the tenth connection line 610 can serve as the first electrode of the tenth transistor M10. The orthogonal projection of the second conductive layer onto the substrate can cover the orthogonal projection of the second insulating layer onto the substrate.

[0357] The film layer arrangement of the circuit structure in the non-display area of ​​this example can help save space, ensure transistor performance, and facilitate signal transmission wiring.

[0358] In some exemplary embodiments, the multiple transistors of the drive control circuit can employ two structures, such as a first-structure transistor and a second-structure transistor. In the first-structure transistor, the gate can be located on the side of the active layer away from the substrate. The second-structure transistor can include a top gate located on the side of the active layer away from the substrate, and a bottom gate located on the side of the active layer closer to the substrate, wherein the bottom gate is electrically connected to the top gate.

[0359] Figure 48A is a schematic diagram of a first-structure transistor according to at least one embodiment of the present disclosure. Figure 48B is a schematic diagram of a second-structure transistor according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 48A, the first-structure transistor T01 may include an active layer 010, a gate 013, first electrodes 011a and 011b, and a second electrode 012. The gate 013, the first electrodes 011a and 011b, and the second electrode 012 may be located in the same conductive layer and on the side of the active layer 010 away from the substrate. The first electrodes 011a and 011b and the second electrode 012 may be connected to the active layer 010.

[0360] In some examples, as shown in Figure 48B, the second-structure transistor T02 may include an active layer 020, a top gate 023, a bottom gate 024, first electrodes 021a and 021b, and a second electrode 022. The top gate 023, first electrodes 021a and 021b, and second electrode 022 may be located on the same conductive layer, and on the side of the active layer 020 away from the substrate. The bottom gate 024 may be located on the side of the active layer 020 closer to the substrate. The first electrodes 021a and 021b and the second electrode 022 may be connected to the active layer 020. The top gate 023 may be connected to the bottom gate 024.

[0361] In some examples, taking the drive control circuit shown in Figure 25 as an example, the transistors included in the first control circuit 221, the second control circuit 222, the first noise reduction circuit 241, the second noise reduction circuit 242, the first pull-down circuit 251, the second pull-down circuit 252, the third pull-down circuit 261, and the fourth pull-down circuit 262 can be first-structure transistors, while the remaining transistors can be second-structure transistors. Specifically, the fifth transistor M5, the thirteenth transistor M13, the sixth transistor M6, the fourteenth transistor M14, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, the seventh transistors M7A and M7B, and the eighth transistors M8A and M8B can be first-structure transistors. In this way, under prolonged forward bias stress (e.g., with a high level of 38V provided by VDD1, the gate-source voltage difference between the seventh transistor M7A and M7B, the tenth transistor M10 and the ninth transistor M9 remains at 76V for an extended period, and the drain-source voltage difference between the sixth transistor M6 remains at 76V for an extended period), by setting these transistors as first-structure transistors, transistor stability can be significantly improved. The remaining transistors have higher requirements for on-state current; using second-structure transistors can increase the on-state current.

[0362] Figure 49 is a cross-sectional structural diagram of a display device according to at least one embodiment of the present disclosure. Figure 50 is a connection structural diagram of a display device according to at least one embodiment of the present disclosure.

[0363] In some examples, as shown in FIG49, the display device may include a counter substrate 171, an electrophoretic solution 172, and a display substrate 173 as provided in any of the foregoing embodiments, wherein the electrophoretic solution 172 is located between the counter substrate 171 and the display substrate 173, and the second conductive layer of the display substrate 173 including the second pixel electrode EP2 may be located on the side of the substrate close to the electrophoretic solution 172.

[0364] In some examples, the electrophoresis solution 172 may include target particles LZ. These target particles may be electrophoretic particles, such as two-color, three-color, or four-color particles; or they may be liquid crystal molecules. In other examples, the electrophoresis solution 172 may be an electronic paper film.

[0365] In some examples, the opposing substrate 171 may include: opposing substrate 1711, and opposing electrode 1712 disposed on the side of opposing substrate 1711 near electrophoretic solution 172, the opposing electrode 1712 and the second pixel electrode EP2 together forming an electric field that drives the target particle LZ to move.

[0366] In some examples, as shown in FIG50, the display device may also include a driver chip IC bonded to a non-display area NA of the display substrate 173, which can be connected to an external circuit board 182 via a flexible circuit board 181.

[0367] In some examples, during the display process, the driver chip IC can be activated via an external circuit board 182. The driver chip IC provides control signals to the drive control circuit and data signals to the data line DL. The drive control circuit can generate a gate control signal input to the gate line GL. The gate line GL can control the activation of the corresponding transistor. The pixel electrode of the sub-pixel in the display area obtains the voltage required for the image and forms a voltage difference with the upper counter electrode 1712, thereby separating the white particles and black particles in the electrophoretic solution 172, and thus forming different display grayscale states.

[0368] In some examples, the display device can be a product with image display capabilities (including still images or moving images, where moving images can be video). For example, the display device can be: electronic paper, electronic price tags, electronic name tags, display modules, mobile phones, tablets, televisions, monitors, laptops, digital photo frames, in-vehicle display devices, smartwatches, fitness wristbands, personal digital assistants, and any other product or component with display capabilities.

[0369] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0370] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A display substrate, comprising: A substrate, a plurality of first sub-pixels disposed on the substrate, and a plurality of data lines; At least one of the first sub-pixels includes: a first switching transistor, a first pixel electrode, a second pixel electrode, a first common electrode, and a second common electrode; the first switching transistor includes a first active layer, the first active layer includes a first channel region, and a first region and a second region located on both sides of the first channel region, the first region is connected to the data line, the second region is connected to the first pixel electrode, the second pixel electrode is connected to the first pixel electrode, the orthographic projection of the first pixel electrode on the substrate at least partially overlaps with the orthographic projection of the first common electrode on the substrate, and the orthographic projection of the second pixel electrode on the substrate at least partially overlaps with the orthographic projection of the second common electrode on the substrate; The multiple data lines are located on the side of the first active layer near the substrate, and the multiple data lines are disposed in the same layer as the first common electrode.

2. The display substrate according to claim 1, further comprising: Multiple light-shielding electrodes are disposed on the substrate, wherein the orthographic projection of the first channel region on the substrate is located within the orthographic projection range of the light-shielding electrodes on the substrate, and the multiple light-shielding electrodes are disposed on the same layer as the multiple data lines.

3. The display substrate according to claim 1 or 2, wherein, The first pixel electrode is located on the side of the first common electrode away from the substrate, the second common electrode is located on the side of the first pixel electrode away from the substrate, and the second pixel electrode is located on the side of the second common electrode away from the substrate.

4. The display substrate according to claim 3, wherein, The gate of the first switching transistor and the first pixel electrode are disposed on the same layer.

5. The display substrate according to claim 3 or 4, wherein, The first region of the first switching transistor is connected to the data line through a first conductive block, the first common electrode is connected to the second common electrode through a second conductive block, and the first pixel electrode is connected to the second pixel electrode through a third conductive block. The first conductive block, the second conductive block, and the first pixel electrode are disposed on the same layer, and the third conductive block and the second common electrode are disposed on the same layer.

6. The display substrate according to claim 2, wherein, In a direction perpendicular to the display substrate, the display substrate includes: a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer, and a fourth conductive layer stacked on the substrate; The first conductive layer includes: the plurality of data lines, the plurality of light-shielding electrodes, and the first common electrode; The semiconductor layer includes: a first active layer of the first switching transistor; The second conductive layer includes: the gate of the first switching transistor and the first pixel electrode; The third conductive layer includes: the second common electrode; The fourth conductive layer includes: the second pixel electrode.

7. The display substrate according to claim 1, wherein, The plurality of first sub-pixels arranged along the first direction constitute a row of sub-pixels; the display substrate includes: a plurality of gate lines extending along the first direction, and a plurality of groups of sub-pixels arranged along the second direction, each group of sub-pixels including two adjacent rows of sub-pixels along the second direction, the first direction intersecting the second direction; The gate of the first switching transistor in each group of sub-pixels is connected to the same gate line; the gate line is located in the middle of two rows of sub-pixels within that group of sub-pixels.

8. The display substrate according to any one of claims 1 to 7, wherein, The substrate includes: a display center area and a display boundary area; The plurality of first sub-pixels are located in the display center area; The display substrate further includes: a plurality of second sub-pixels located in the display boundary area, at least one of the second sub-pixels including: a second switching transistor, a third pixel electrode, a fourth pixel electrode, a third common electrode that at least partially overlaps with the orthographic projection of the third pixel electrode on the substrate, and a fourth common electrode that at least partially overlaps with the orthographic projection of the fourth pixel electrode on the substrate; the first electrode of the second switching transistor is connected to the data line, the second electrode of the second switching transistor is not electrically connected to the third pixel electrode, and the fourth pixel electrode is not electrically connected to the third pixel electrode and the second electrode of the second switching transistor; The first and second electrodes of the second switching transistor, the third pixel electrode and the first pixel electrode are disposed on the same layer; the third common electrode is disposed on the same layer as the first common electrode; the fourth pixel electrode is disposed on the same layer as the second pixel electrode, and the fourth common electrode is disposed on the same layer as the second common electrode.

9. The display substrate according to any one of claims 1 to 7, wherein, The substrate includes: a display center area and a display boundary area; The plurality of first sub-pixels are located in the display center area; The display substrate further includes: a plurality of second sub-pixels located in the display boundary area, at least one of the second sub-pixels including: a second switching transistor, a fourth pixel electrode, and a fourth common electrode that at least partially overlaps with the orthographic projection of the fourth pixel electrode on the substrate; the first electrode of the second switching transistor is connected to the data line, and the second electrode of the second switching transistor is not electrically connected to the fourth pixel electrode; The fourth pixel electrode is disposed in the same layer as the second pixel electrode, and the fourth common electrode is disposed in the same layer as the second common electrode.

10. A display device, comprising: The opposing substrate, the electrophoretic solution, and the display substrate as described in any one of claims 1 to 9, wherein the electrophoretic solution is located between the opposing substrate and the display substrate.

11. A drive control circuit, comprising: An input circuit, electrically connected to an input terminal and a first node, is configured to write an input signal provided by the input terminal to the first node under the control of the input terminal; A first control circuit is electrically connected to a first clock terminal, a first power supply terminal, and a second node, and is configured to write a first power supply signal provided by the first power supply terminal to the second node under the control of the effective level of the first clock signal provided by the first clock terminal. The first output circuit is electrically connected to the first node, the second clock terminal, and the first output terminal, and is configured to control the first output terminal to output the second clock signal provided by the second clock terminal under the control of the first node. The second output circuit is electrically connected to the first node, the third clock terminal, and the second output terminal, and is configured to control the second output terminal to output the third clock signal provided by the third clock terminal under the control of the first node. The first noise reduction circuit is electrically connected to the second node, the first output terminal, the second output terminal, the third power supply terminal, and the fourth power supply terminal. It is configured to, under the control of the second node, control the first output terminal to output the third power supply signal provided by the third power supply terminal, and control the second output terminal to output the fourth power supply signal provided by the fourth power supply terminal. Specifically, during the time period when the input circuit writes the input signal to the first node, during the time period when the first output terminal outputs the second clock signal, and during the time period when the second output terminal outputs the third clock signal, the first clock signal provides an inactive level. After the period in which the first output terminal outputs the second clock signal and the second output terminal outputs the third clock signal, the first clock signal provides an effective level.

12. The drive control circuit according to claim 11, wherein, The effective level of the first clock signal accounts for 25% of a pulse cycle.

13. The drive control circuit according to claim 11 or 12, further comprising: The first node capacitor has its first electrode electrically connected to the first node, and its second electrode electrically connected to the fourth power supply terminal.

14. The drive control circuit according to any one of claims 11 to 13, further comprising: The second control circuit is electrically connected to the first clock terminal, the third node, and the second power supply terminal, and is configured to write the second power supply signal provided by the second power supply terminal to the third node under the control of the effective level of the first clock signal provided by the first clock terminal. The first power signal is different from the second power signal; The second noise reduction circuit is electrically connected to the third node, the first output terminal, the second output terminal, the third power supply terminal, and the fourth power supply terminal. It is configured to, under the control of the third node, control the first output terminal to output the third power supply signal provided by the third power supply terminal, and control the second output terminal to output the fourth power supply signal provided by the fourth power supply terminal.

15. The drive control circuit according to claim 14, wherein, The first control circuit includes: a fifth transistor, the gate of which is electrically connected to the first clock terminal, the first terminal of which is electrically connected to the first power supply terminal, and the second terminal of which is electrically connected to the second node; The second control circuit includes: a thirteenth transistor, the gate of which is electrically connected to the first clock terminal, the first terminal of which is electrically connected to the second power supply terminal, and the second terminal of which is electrically connected to the third node; The first noise reduction circuit includes: a ninth transistor and a tenth transistor, wherein the gate of the ninth transistor is electrically connected to the second node, the first terminal of the ninth transistor is electrically connected to the third power supply terminal, and the second terminal of the ninth transistor is electrically connected to the first output terminal; the gate of the tenth transistor is electrically connected to the second node, the first terminal of the tenth transistor is electrically connected to the fourth power supply terminal, and the second terminal of the tenth transistor is electrically connected to the second output terminal. The second noise reduction circuit includes an eleventh transistor and a twelfth transistor. The gate of the eleventh transistor is electrically connected to the third node, the first terminal of the eleventh transistor is electrically connected to the third power supply terminal, and the second terminal of the eleventh transistor is electrically connected to the first output terminal. The gate of the twelfth transistor is electrically connected to the third node, the first terminal of the twelfth transistor is electrically connected to the fourth power supply terminal, and the second terminal of the twelfth transistor is electrically connected to the second output terminal.

16. The drive control circuit according to claim 14 or 15, further comprising: The first pull-down circuit is electrically connected to the first node, the second node and the first clock terminal, and is configured to write the first clock signal provided by the first clock terminal to the second node under the control of the first node. Alternatively, it can be electrically connected to the first node, the second node, and the fourth power supply terminal, and configured to write the fourth power signal provided by the fourth power supply terminal to the second node under the control of the first node; The second pull-down circuit is electrically connected to the first node, the third node and the first clock terminal, and is configured to write the first clock signal provided by the first clock terminal to the third node under the control of the first node. Alternatively, it can be electrically connected to the first node, the third node, and the fourth power supply terminal, and configured to write the fourth power signal provided by the fourth power supply terminal to the third node under the control of the first node.

17. The drive control circuit according to claim 16, wherein, The first pull-down circuit includes: a sixth transistor, the gate of the sixth transistor being electrically connected to the first node, the first terminal of the sixth transistor being electrically connected to the first clock terminal or the fourth power supply terminal, and the second terminal of the sixth transistor being electrically connected to the second node; The second pull-down circuit includes: a fourteenth transistor, the gate of which is electrically connected to the first node, the first terminal of which is electrically connected to the first clock terminal or the fourth power supply terminal, and the second terminal of which is electrically connected to the third node.

18. The drive control circuit according to any one of claims 14 to 17, further comprising: Second node capacitor and third node capacitor; The first electrode of the second node capacitor is electrically connected to the second node, and the second electrode of the second node capacitor is electrically connected to the fourth power supply terminal. The first electrode of the third node capacitor is electrically connected to the third node, and the second electrode of the third node capacitor is electrically connected to the fourth power supply terminal.

19. The drive control circuit according to any one of claims 14 to 18, further comprising: The third pull-down circuit is electrically connected to the first node, the second node and the fourth power supply terminal, and is configured to write the fourth power supply signal provided by the fourth power supply terminal to the first node under the control of the second node. The fourth pull-down circuit is electrically connected to the first node, the third node and the fourth power supply terminal, and is configured to write the fourth power signal provided by the fourth power supply terminal to the first node under the control of the third node. The fifth pull-down circuit is electrically connected to the first node, the first control terminal, and the fourth power supply terminal, and is configured to write the fourth power signal provided by the fourth power supply terminal to the first node under the control of the first control terminal.

20. The drive control circuit according to claim 19, wherein, The third pull-down circuit includes: two seventh transistors, the gates of the two seventh transistors are electrically connected to the second node, the first terminal of the first seventh transistor is electrically connected to the second terminal of the second seventh transistor, the second terminal of the first seventh transistor is electrically connected to the first node, and the first terminal of the second seventh transistor is electrically connected to the fourth power supply terminal; The fourth pull-down circuit includes: two eighth transistors, the gates of the two eighth transistors are electrically connected to the third node, the first terminal of the first eighth transistor is electrically connected to the second terminal of the second eighth transistor, the second terminal of the first eighth transistor is electrically connected to the first node, and the first terminal of the second eighth transistor is electrically connected to the fourth power supply terminal. The fifth pull-down circuit includes: two second transistors, the gates of the two second transistors being electrically connected to the first control terminal, the first terminal of the first second transistor being electrically connected to the second terminal of the second second transistor, the second terminal of the first second transistor being electrically connected to the first node, and the first terminal of the second second transistor being electrically connected to the fourth power supply terminal.

21. The drive control circuit according to claim 20, further comprising: The first pull-up circuit is electrically connected to the fourth node, the second control terminal, and the fifth power supply terminal, and is configured to write the fifth power signal provided by the fifth power supply terminal to the fourth node under the control of the second control terminal. The first terminal of the first seventh transistor and the second terminal of the second seventh transistor, the first terminal of the first eighth transistor and the second terminal of the second eighth transistor, and the first terminal of the first second transistor and the second terminal of the second second transistor are all electrically connected to the fourth node.

22. The drive control circuit according to any one of claims 11 to 21, wherein, The input circuit includes: two first transistors, the gates of the two first transistors being electrically connected to the input terminal, the first electrode of the first first transistor being electrically connected to the input terminal, the second electrode of the first first transistor being electrically connected to the first electrode of the second first transistor, and the second electrode of the second first transistor being electrically connected to the first node.

23. The drive control circuit according to claim 22 further includes: The second pull-up circuit is electrically connected to the fifth node, the second control terminal, and the fifth power supply terminal, and is configured to write the fifth power signal provided by the fifth power supply terminal to the fifth node under the control of the second control terminal. The second terminal of the first transistor and the first terminal of the second transistor are both electrically connected to the fifth node.

24. The drive control circuit according to claim 21 or 23, wherein, The second control terminal is electrically connected to the first node.

25. The drive control circuit according to claim 21 or 23, wherein, The second control terminal is electrically connected to the second output terminal.

26. The drive control circuit according to any one of claims 11 to 25, wherein, The first output circuit includes: a third transistor, or a third transistor and a first capacitor; the gate of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second clock terminal, and the second electrode of the third transistor is electrically connected to the first output terminal; the first electrode of the first capacitor is electrically connected to the first node, and the second electrode of the first capacitor is electrically connected to the first output terminal. The second output circuit includes: a fourth transistor, or a fourth transistor and a second capacitor; the gate of the fourth transistor is electrically connected to the first node, the first electrode of the fourth transistor is electrically connected to the third clock terminal, and the second electrode of the fourth transistor is electrically connected to the second output terminal; the first electrode of the second capacitor is electrically connected to the first node, and the second electrode of the second capacitor is electrically connected to the second output terminal.

27. The drive control circuit according to any one of claims 11 to 26, further comprising: A first reset circuit is electrically connected to the first node, the first reset terminal, and the fourth power supply terminal, and is configured to write a fourth power supply signal provided by the fourth power supply terminal to the first node under the control of the first reset terminal.

28. The drive control circuit according to claim 27, wherein, The first reset circuit includes: two seventeenth transistors, the gates of the two seventeenth transistors being electrically connected to the first reset terminal, the first terminal of the first seventeenth transistor being electrically connected to the second terminal of the second seventeenth transistor, the second terminal of the first seventeenth transistor being electrically connected to the first node, and the first terminal of the second seventeenth transistor being electrically connected to the fourth power supply terminal.

29. The drive control circuit according to any one of claims 11 to 27, further comprising: The second reset circuit is electrically connected to the first control terminal, the first output terminal, and the third power supply terminal, and is configured to control the first output terminal to output the third power supply signal provided by the third power supply terminal under the control of the first control terminal.

30. The drive control circuit according to any one of claims 11 to 29, wherein, The second clock terminal and the third clock terminal provide the same signal; or, the effective level of the second clock signal provided by the second clock terminal is higher than the effective level of the third clock signal provided by the third clock terminal.

31. A gate drive circuit, comprising a plurality of cascaded drive control circuits as described in any one of claims 11 to 30; in, The input terminal of the first-stage drive control circuit is electrically connected to the start signal line, and the input terminal of the (i+1)th-stage drive control circuit is electrically connected to the second output terminal of the ith-stage drive control circuit, where i is an integer greater than 0.

32. The gate driving circuit according to claim 31, wherein, The first control terminal of the i-th stage drive control circuit is electrically connected to the second output terminal of the (i+1)-th stage drive control circuit, and the second control terminal of the i-th stage drive control circuit is electrically connected to the second output terminal or the first node of the i-th stage drive control circuit.

33. The gate driving circuit according to claim 32, wherein, The first control terminal of the last-stage drive control circuit is electrically connected to the first reset terminal.

34. The gate drive circuit according to any one of claims 31 to 33, wherein, The second and third clock terminals of the 4k+1 level drive control circuit are electrically connected to the first clock line, and the first clock terminal of the 4k+1 level drive control circuit is electrically connected to the second clock line. The second and third clock terminals of the 4k+2 level drive control circuit are electrically connected to the second clock line, and the first clock terminal of the 4k+2 level drive control circuit is electrically connected to the third clock line. The second and third clock terminals of the 4k+3 level drive control circuit are electrically connected to the third clock line, and the first clock terminal of the 4k+3 level drive control circuit is electrically connected to the fourth clock line. The second and fourth clock terminals of the 4k+4 level drive control circuit are electrically connected to the fourth clock line, and the first clock terminal of the 4k+4 level drive control circuit is electrically connected to the first clock line, where k is an integer greater than or equal to 0. The effective levels of the clock signals provided by the first clock line, the second clock line, the third clock line, and the fourth clock line are output sequentially without timing overlap.

35. A display substrate, comprising: A display area and a non-display area surrounding the display area. The non-display area is provided with a gate driving circuit. The gate driving circuit includes multiple cascaded driving control circuits. The driving control circuit includes an input circuit, a first control circuit, a first output circuit, a second output circuit, and a first noise reduction circuit. The input circuit is electrically connected to the input terminal and the first node, and is configured to write the input signal provided by the input terminal to the first node under the control of the input terminal; The first control circuit is electrically connected to the first clock terminal, the first power supply terminal, and the second node, and is configured to write the first power supply signal provided by the first power supply terminal to the second node under the control of the effective level of the first clock signal provided by the first clock terminal. The first output circuit is electrically connected to the first node, the second clock terminal, and the first output terminal, and is configured to control the first output terminal to output the second clock signal provided by the second clock terminal under the control of the first node; The second output circuit is electrically connected to the first node, the third clock terminal, and the second output terminal, and is configured to control the second output terminal to output the third clock signal provided by the third clock terminal under the control of the first node; The first noise reduction circuit is electrically connected to the second node, the first output terminal, the second output terminal, the third power supply terminal, and the fourth power supply terminal. It is configured to control the first output terminal to output the third power supply signal provided by the third power supply terminal under the control of the second node, and to control the second output terminal to output the fourth power supply signal provided by the fourth power supply terminal. The first control circuit, the input circuit, the first noise reduction circuit, and the first output circuit are arranged along a first direction, the second output circuit is located on one side of the first control circuit along a second direction, and the second output circuit and the first output circuit are located on both sides of the input circuit along the first direction; the first direction and the second direction intersect.

36. The display substrate according to claim 35, wherein, The drive control circuit further includes: a first node capacitor, the first electrode of the first node capacitor being electrically connected to the first node, and the second electrode of the first node capacitor being electrically connected to the fourth power supply terminal; The first node capacitor is located between the first noise reduction circuit and the first output circuit along the first direction, and is adjacent to the first output circuit in the first direction.

37. The display substrate according to claim 36, wherein, The first output circuit includes: a third transistor and a first capacitor; the gate of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second clock terminal, and the second electrode of the third transistor is electrically connected to the first output terminal; the first electrode of the first capacitor is electrically connected to the first node, and the second electrode of the first capacitor is electrically connected to the first output terminal. The first capacitor is located between the first node capacitor and the third crystal in the first direction; the first capacitor and the first node capacitor are adjacent to each other along the first direction, and the first electrode of the first capacitor and the first electrode of the first node capacitor are integral structures; the second electrode of the first capacitor and the second electrode of the third transistor are integral structures.

38. The display substrate according to claim 35, wherein, The second output circuit includes: a fourth transistor and a second capacitor; the gate of the fourth transistor is electrically connected to the first node, the first electrode of the fourth transistor is electrically connected to the third clock terminal, and the second electrode of the fourth transistor is electrically connected to the second output terminal; the first electrode of the second capacitor is electrically connected to the first node. The fourth transistor and the second capacitor are adjacent in the first direction. The gate of the fourth transistor and the first electrode of the second capacitor are integrally formed. The second electrode of the second capacitor and the second output terminal are integrally formed.

39. The display substrate according to claim 35, wherein, The drive control circuit also includes: The second control circuit is electrically connected to the first clock terminal, the third node, and the second power supply terminal, and is configured to write a second power signal provided by the second power supply terminal to the third node under the control of the effective level of the first clock signal provided by the first clock terminal; the first power signal is different from the second power signal. The second noise reduction circuit is electrically connected to the third node, the first output terminal, the second output terminal, the third power supply terminal, and the fourth power supply terminal. It is configured to, under the control of the third node, control the first output terminal to output the third power supply signal provided by the third power supply terminal, and control the second output terminal to output the fourth power supply signal provided by the fourth power supply terminal. The first pull-down circuit is electrically connected to the first node, the second node, and the first clock terminal, and is configured to write the first clock signal provided by the first clock terminal to the second node under the control of the first node; or, it is electrically connected to the first node, the second node, and the fourth power supply terminal, and is configured to write the fourth power supply signal provided by the fourth power supply terminal to the second node under the control of the first node. The second pull-down circuit is electrically connected to the first node, the third node, and the first clock terminal, and is configured to write the first clock signal provided by the first clock terminal to the third node under the control of the first node; or, it is electrically connected to the first node, the third node, and the fourth power terminal, and is configured to write the fourth power signal provided by the fourth power terminal to the third node under the control of the first node. The second control circuit is located between the first control circuit and the second output circuit in the second direction; The first pull-down circuit and the second pull-down circuit are arranged adjacent to each other in the first direction, and are located on the side of the first control circuit closer to the input circuit in the first direction; the transistors included in the second noise reduction circuit and the transistors included in the first noise reduction circuit are arranged at intervals in the first direction.

40. The display substrate according to claim 39, wherein, The first noise reduction circuit includes: a ninth transistor and a tenth transistor, wherein the gate of the ninth transistor is electrically connected to the second node, the first terminal of the ninth transistor is electrically connected to the third power supply terminal, and the second terminal of the ninth transistor is electrically connected to the first output terminal; the gate of the tenth transistor is electrically connected to the second node, the first terminal of the tenth transistor is electrically connected to the fourth power supply terminal, and the second terminal of the tenth transistor is electrically connected to the second output terminal. The second noise reduction circuit includes an eleventh transistor and a twelfth transistor. The gate of the eleventh transistor is electrically connected to the third node, the first terminal of the eleventh transistor is electrically connected to the third power supply terminal, and the second terminal of the eleventh transistor is electrically connected to the first output terminal. The gate of the twelfth transistor is electrically connected to the third node, the first terminal of the twelfth transistor is electrically connected to the fourth power supply terminal, and the second terminal of the twelfth transistor is electrically connected to the second output terminal. The tenth transistor, the twelfth transistor, the eleventh transistor, and the ninth transistor are arranged sequentially along the first direction.

41. The display substrate according to claim 39, wherein, The drive control circuit also includes: The third pull-down circuit is electrically connected to the first node, the second node and the fourth power supply terminal, and is configured to write the fourth power supply signal provided by the fourth power supply terminal to the first node under the control of the second node. The fourth pull-down circuit is electrically connected to the first node, the third node and the fourth power supply terminal, and is configured to write the fourth power signal provided by the fourth power supply terminal to the first node under the control of the third node. The fifth pull-down circuit is electrically connected to the first node, the first control terminal, and the fourth power supply terminal, and is configured to write the fourth power signal provided by the fourth power supply terminal to the first node under the control of the first control terminal. The third pull-down circuit and the fourth pull-down circuit are arranged adjacent to each other along the first direction, located between the input circuit and the first output circuit in the first direction, and located on the same side of the first noise reduction circuit and the second noise reduction circuit along the second direction. The fifth pull-down circuit is located between the second pull-down circuit and the input circuit along the first direction.

42. The display substrate according to claim 41, wherein, The drive control circuit further includes: a second node capacitor and a third node capacitor; the first electrode of the second node capacitor is electrically connected to the second node, and the second electrode of the second node capacitor is electrically connected to the fourth power supply terminal; the first electrode of the third node capacitor is electrically connected to the third node, and the second electrode of the third node capacitor is electrically connected to the fourth power supply terminal. The second node capacitor is located between the third pull-down circuit and the fourth pull-down circuit in the first direction; The third node capacitor is located in the middle of the two transistors included in the fourth pull-down circuit in the first direction; the second electrode of the second node capacitor and the second electrode of the third node capacitor are integral structures.

43. The display substrate according to claim 41, wherein, The drive control circuit also includes: The first pull-up circuit is electrically connected to the fourth node, the second control terminal, and the fifth power supply terminal, and is configured to write the fifth power signal provided by the fifth power supply terminal to the fourth node under the control of the second control terminal. The second pull-up circuit is electrically connected to the fifth node, the second control terminal, and the fifth power supply terminal, and is configured to write the fifth power signal provided by the fifth power supply terminal to the fifth node under the control of the second control terminal. The two transistors included in the input circuit are both electrically connected to the fifth node, and the third pull-down circuit, the fourth pull-down circuit, and the fifth pull-down circuit are all electrically connected to the fourth node; The first pull-up circuit and the second pull-up circuit are arranged adjacent to each other along the first direction, located between the input circuit and the second output circuit in the first direction, and on the same side of the fifth pull-down circuit along the second direction.

44. The display substrate according to claim 35, wherein, The drive control circuit includes: a plurality of transistors, wherein the gates of the transistors include a bottom gate and a top gate connected to each other; In a direction perpendicular to the display substrate, the display substrate includes: a substrate and a first conductive layer, a semiconductor layer, and a second conductive layer disposed on the substrate; The first conductive layer includes: the bottom gate of the plurality of transistors; The semiconductor layer includes: the active layer of the plurality of transistors; The second conductive layer includes the top gate of the plurality of transistors.

45. The display substrate according to claim 44, wherein, The drive control circuit is electrically connected to multiple clock lines and multiple power lines, wherein the multiple clock lines are located in the first conductive layer, and at least one of the multiple power lines is located in the first conductive layer or the second conductive layer.

46. ​​The display substrate according to claim 39, wherein, The drive control circuit includes: a first structure transistor and a second structure transistor, wherein the gate of the first structure transistor is located on the side of the active layer of the first structure transistor away from the substrate; the second structure transistor includes a top gate located on the side of the active layer of the second structure transistor away from the substrate, and a bottom gate located on the side of the active layer of the second structure transistor close to the substrate, wherein the bottom gate is electrically connected to the top gate.

47. The display substrate according to claim 46, wherein, The transistors included in the first control circuit, the second control circuit, the first noise reduction circuit, and the second noise reduction circuit are first structure transistors.

48. The display substrate according to claim 35, further comprising: A detection circuit is electrically connected to a detection control line, a detection signal line, and the first output terminal of the drive control circuit, and is configured to write the detection signal provided by the detection signal line to the first output terminal of the drive control circuit under the control of the detection control line. The detection circuit is located in the non-display area and is situated in the first direction on the side of the first output circuit of the drive control circuit closer to the display area.

49. The display substrate according to claim 48, further comprising: Multiple grid lines are located in the display area; The first electrostatic discharge circuit is connected to the common electrode and the short-circuit loop. The second electrostatic discharge circuit is electrically connected to the short-circuit ring and the gate line; The first electrostatic discharge circuit and the second electrostatic discharge circuit are located in the non-display area, and in the first direction, they are located on the side of the detection circuit closer to the display area.

50. A display device comprising a display substrate as claimed in any one of claims 35 to 49.

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