Information processing method and apparatus

Abstract

An information processing method and apparatus. The method comprises: acquiring first information bits; on the basis of the first information bits, obtaining N first blocks; on the basis of the N first blocks, obtaining C second blocks, each of A second blocks among the C second blocks comprising a plurality of first blocks; and, on the basis of the C second blocks and a coupled encoding matrix, obtaining C encoded code blocks, N being an integer greater than 1, C being an integer less than N, and A being an integer less than or equal to C. In the foregoing method, there may be coupling relationships between the first blocks as well as between the second blocks, thereby improving decoding performance.

Description

An information processing method and apparatus

[0001] This application claims priority to Chinese Patent Application No. 202411762333.8, filed with the China National Intellectual Property Administration on November 30, 2024, entitled "An Information Processing Method and Apparatus", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communications, and more specifically, to an information processing method and apparatus. Background Technology

[0003] Channel coding is one of the core technologies in the field of wireless communication. The complete channel coding process includes: adding cyclic redundancy check (CRC) codes, code block segmentation, error correction coding, rate adaptation, code block concatenation, data interleaving, and data scrambling. Among these, error correction coding is the most critical part. The purpose of error correction coding is to ensure that the receiving device can automatically correct errors that occur during data transmission with as little redundancy overhead as possible. At the same bit error rate, the smaller the redundancy overhead, the higher the coding efficiency.

[0004] In the field of channel coding, low-density parity check (LDPC) codes are one of the most mature and widely used coding schemes. LDPC codes are a channel coding scheme that is very close to the Shannon limit. LDPC codes have been adopted by the 3rd Generation Partnership Project (3GPP) as a data channel coding scheme.

[0005] With the continuous emergence of new services, higher demands are being placed on the peak throughput and area efficiency of encoding and decoding, with peak rates even requiring terabits per second (Tbps). Simultaneously, these emerging services demand further reductions in decoder power consumption. Current LDPC codes can no longer meet these needs. Therefore, improving the performance of LDPC codes has become an urgent problem to solve. Summary of the Invention

[0006] Embodiments of this application provide an information processing method and apparatus to improve the performance of LDPC codes.

[0007] In a first aspect, embodiments of this application provide an information processing method that can be applied to the encoding side, such as an encoding device, modules (e.g., circuits, chips, or chip systems such as modem chips, also known as baseband chips, or system-on-chip (SoC) chips or system-in-package (SIP) chips containing modem cores) within the encoding device, or logical nodes, logical modules, or software that can implement all or part of the encoding device. The encoding device can be a terminal or network device.

[0008] The method includes: acquiring a first information bit; obtaining N first blocks based on the first information bit, where N is an integer greater than 1; obtaining C second blocks based on the N first blocks, wherein each of the A second blocks in the C second blocks includes multiple first blocks, where C is an integer less than N and A is an integer less than or equal to C; and performing coupled encoding based on the C second blocks and a coupled encoding matrix to obtain C encoded code blocks.

[0009] The above method can create coupling relationships between the first blocks and between the second blocks, thereby improving decoding performance.

[0010] In conjunction with the first aspect, in some implementations, obtaining C second blocks based on the N first blocks includes: obtaining the C second blocks based on the overlap rate and the N first blocks, wherein the overlap rate is the ratio of a first value and a second value, the first value is the number of identical first blocks in two adjacent second blocks, the second value is the total number of first blocks included in the first second block of the two second blocks, and the overlap rate is a rational number greater than or equal to 0 and less than 1.

[0011] Based on the above implementation, the division into N first blocks to C second blocks can be flexibly configured through the overlap rate. Furthermore, when the overlap rate is not zero, retransmission is more flexible when the first block of the overlapping portion is decoded incorrectly.

[0012] In conjunction with the first aspect or any of its implementations, in some other implementations, obtaining the encoded C code blocks based on the C second blocks and the coupling coding matrix includes: adding cyclic redundancy check (CRC) bits to the C second blocks to obtain C third blocks; and uniformly dividing the i-th third block among the C third blocks into s... i The fourth piece, s i The first padding bit is added to each of the fourth blocks to obtain the fifth block, the length of which is K. SCB,padded Satisfy: K SCB,padded =K sub·Z, where each X column of the coupled coding matrix corresponds to a sub-matrix group, each sub-matrix group includes W sub-matrices, the W sub-matrices are of the same size and are non-zero matrices, and the row number of the first row of the first sub-matrix corresponding to each of the multiple sub-matrix groups is different, K sub Z represents the number of information columns in column X, and Z is the boost value. Based on the coupling coding matrix, different fifth blocks are encoded to obtain C encoded code blocks.

[0013] Based on the above implementation, when the overlap rate is not 0, the first overlapping block can participate in two CRC calculations, and the CRC result of the first overlapping block is more reliable.

[0014] In conjunction with the first aspect or any implementation thereof, in some other implementations, the first information bit includes a first null bit, the number of which is the same as the total number of CRC bits in the C second blocks; each of the C second blocks includes a second null bit, the number of which is the same as the number of CRC bits in the second block; adding cyclic redundancy check (CRC) bits to the C second blocks to obtain C third blocks includes: calculating CRC bits for the i-th second block of the C second blocks, and replacing the second null bit of the i-th second block with the calculated CRC bit to obtain C third blocks.

[0015] It should be understood that the CRC of a certain block can be interpreted as the CRC bits calculated based on that block.

[0016] Based on the above implementation, since the first information bits reserve space for the CRC bits of the second block, the resulting second block can definitely be used by s. i Integer division can prevent the second piece from being unable to be divided equally.

[0017] In conjunction with the first aspect or any of its implementations, in some other implementations, the positions of the first null bit and the second null bit are determined according to preset parameters.

[0018] In conjunction with the first aspect or any implementation thereof, in some other implementations, the method further includes: performing bit interleaving with each of the C code blocks as input; or performing bit interleaving with the C code blocks as input bits; or performing bit interleaving with each encoded fifth block as input.

[0019] Based on the above implementation method, bit interleaving within different ranges can be achieved.

[0020] In conjunction with the first aspect or any of its implementations, in some other implementations, the CRC bits in the i-th third block of the C third blocks are obtained based on the CRC bits in the i-th second block of the C second blocks and the (i-1)-th third block of the C third blocks, where i is an integer greater than 1.

[0021] In this implementation, for cases where the overlap rate is not zero, the overlapping portion participates in two CRC calculations, making the CRC result of the overlapping portion more reliable.

[0022] In conjunction with the first aspect or any of its implementations, in some other implementations, the CRC bits in the i-th third block of the C third blocks are obtained based on the i-th second block of the C second blocks, where i is an integer greater than 1.

[0023] In other words, the CRC bits of the current second block can be calculated based on the current second block. With this implementation, the CRC of each second block can be calculated in parallel, which is faster.

[0024] For example, the CRC bits in the i-th third block are distributed at the beginning, end, middle, or any position of the i-th third block. For example, the CRC bits in the i-th third block are distributed within the s... i The CRC bits in the i-th third block are distributed across the s first blocks included in the i-th third block. The number of CRC bits in each first block can be the same or different. For example, the CRC bits in the i-th third block are evenly distributed across the s first blocks included in the i-th third block.

[0025] In conjunction with the first aspect or any implementation thereof, in some other implementations, the encoding of each different fifth block based on the coupling coding matrix includes: obtaining the parity bits of the j-th fifth block based on x fifth blocks coupled to the j-th fifth block, the j-th fifth block, and the coupling coding matrix. Where x is less than or equal to m. c positive integers, m c =W-1, where j is a non-negative integer.

[0026] It should be understood that the parity bit of a block can be interpreted as the parity bit obtained by encoding that block.

[0027] In conjunction with the first aspect or any of its implementations, in some other implementations, obtaining the parity bit of the j-th fifth block based on the x fifth blocks coupled to the j-th fifth block, the j-th fifth block, and the coupling coding matrix includes: obtaining the parity bit of the j-th fifth block based on the x fifth blocks, the parity bits of the x fifth blocks, the j-th fifth block, and the coupling coding matrix.

[0028] That is, for the parity bit of the first fifth block, the information bits of the first fifth block can be encoded using a parity check matrix; for the parity bits of non-first fifth blocks, the parity bits of some fifth blocks coupled with this fifth block and these fifth blocks can be encoded using a coupling parity relationship, and the maximum number of these fifth blocks is m. c This implementation method produces good coding results.

[0029] In conjunction with the first aspect or any implementation thereof, in some other implementations, the method further includes: encoding the last y information bits and the last y parity bits of the fifth block according to the coupling coding matrix to obtain parity bits as a tail code block, wherein the size of the tail code block is α1m. sub ×α1m sub α1 is a preset value, m sub Let y be the number of rows in the submatrix, and y be a positive integer.

[0030] The above implementation introduces code blocks, which helps improve decoding performance.

[0031] In conjunction with the first aspect or any of its implementations, in some other implementations, the punching position of the i-th code block among the C code blocks is located in a fifth block that is different from the punching positions of the first i-1 code blocks among the C code blocks, where i is an integer greater than 1.

[0032] In conjunction with the first aspect or any of its implementations, in some other implementations, obtaining N first blocks based on the first information bit includes: adding a second padding bit to the first information bit to obtain a second information bit; and uniformly dividing the second information bit into the N first blocks.

[0033] In conjunction with the first aspect or any of its implementations, in some other implementations, obtaining N first blocks based on the first information bit includes: adding a second padding bit to the first information bit to obtain a second information bit; dividing the second information bit evenly into N sixth blocks; and adding a cyclic redundancy check (CRC) bit to each of the sixth blocks to obtain the N first blocks.

[0034] Based on the above implementation method, the first-level CRC check can be implemented, which helps to improve decoding performance.

[0035] It should be understood that the second padding bit can be located at the beginning, middle, end, or any position of the first information bit, without restriction.

[0036] In conjunction with the first aspect or any implementation thereof, in some other implementations, the length L of the second padding bit is... TB,padding Satisfy: LTB,padding = (C-1)c+sK TBCRC %[(C-1)c+s], where c is the number of first blocks that do not overlap in the second block, s is the number of first blocks included in the second block, and K TBCRC The length of the first information bit is denoted as .

[0037] In conjunction with the first aspect or any of its implementations, in some other implementations, when the C second blocks do not overlap and N is not divisible by C, before adding the second padding bit to the first information bit, the method further includes: adding a third padding bit to the first information bit, wherein the number P of the third padding bits satisfies K TBCRC Let L be the length of the first information bits, c be the number of the first blocks that do not overlap in the second block, and L be the length of the first information bits. CBCRC The length of the CRC bits in the second block level is given. Each X column of the coupled coding matrix corresponds to a sub-matrix group. Each sub-matrix group includes W sub-matrices, which are all of the same size and non-zero. The row number of the first row of the first sub-matrix in each of the multiple sub-matrix groups is different. K sub Z represents the number of information columns in column X. max This is to maximize the value. It should be understood that the third padding bit can be located at the beginning, middle, end, or any other position of the first information bit, without restriction.

[0038] In conjunction with the first aspect or any implementation thereof, in some other implementations, when the C second blocks comprise the same number of the first blocks, C satisfies:

[0039] When the C second blocks include different first blocks, C satisfies:

[0040] Where s is the number of the first blocks included in the second block, s i Let K be the number of first blocks included in the i-th second block, c be the number of first blocks in the second block that do not overlap, and K be the number of first blocks in the second block that do not overlap. TBCRC For the length of the first information bit, each X column of the coupled coding matrix corresponds to a sub-matrix group, and each sub-matrix group includes W sub-matrices. The W sub-matrices are of the same size and are non-zero matrices. The row number of the first row of the first sub-matrix corresponding to each of the multiple sub-matrix groups is different, and K sub Z represents the number of information columns in column X. max To maximize the boost value, γ is the number of first blocks that overlap between two adjacent second blocks.

[0041] Secondly, embodiments of this application provide a communication device that has the function of implementing the first aspect or any of its implementations. For example, the communication device includes modules, units or means corresponding to the operations involved in the first aspect or any of its implementations. These modules, units or means can be implemented by software, hardware or a combination of software and hardware.

[0042] Thirdly, embodiments of this application provide a communication device including an interface circuit and one or more processors. The one or more processors are coupled to a memory. The memory stores part or all of the necessary computer program or instructions for implementing the functions involved in the first aspect or any of its implementations. The one or more processors can execute the computer program or instructions, causing the communication device to implement the methods in the first aspect or any of its implementations when executed. The interface circuit is used to implement the communication functions within the communication device and / or the communication functions between the communication device and other devices or components.

[0043] In one possible implementation, the processor is used to communicate with other devices or components through the interface circuit.

[0044] In one possible implementation, the communication device may also include the memory.

[0045] The aforementioned communication device may be a terminal, or a communication module in a terminal, or a chip in a terminal that is responsible for communication functions, such as a modem chip or a SoC or SIP chip containing a modem module.

[0046] The aforementioned communication device may also be a network device, a module (e.g., a circuit, chip, or chip system) within a network device, or a logical node, logical module, or software that can implement all or part of a network device.

[0047] Fourthly, embodiments of this application provide a communication system including the encoding device described above. Optionally, the communication system further includes a decoding device for decoding information from the encoding device.

[0048] Fifthly, embodiments of this application provide a computer-readable storage medium storing computer-readable instructions, which, when read and executed by a computer, cause the computer to perform the methods described in any of the above aspects or any of their implementations.

[0049] Sixthly, embodiments of this application provide a computer program product that, when read and executed by a computer, causes the computer to perform the methods described in any of the above aspects or any of their implementations.

[0050] Seventhly, embodiments of this application provide a computer program that, when run on a computer, causes the methods provided in any of the above aspects or their possible implementations to be executed. Attached Figure Description

[0051] Figure 1 is a schematic diagram of a network architecture applicable to embodiments of this application.

[0052] Figure 2 is a schematic diagram of a communication scenario applicable to embodiments of this application.

[0053] Figure 3 is a schematic architecture diagram of a mobile communication chip system applicable to embodiments of this application.

[0054] Figure 4 is a schematic architecture diagram of an encoder chip applicable to embodiments of this application.

[0055] Figure 5 is a schematic architecture diagram of a decoder chip applicable to embodiments of this application.

[0056] Figure 6 is the Tanner plot of the parity-check matrix H.

[0057] Figure 7 is a schematic diagram of the encoding scheme of spatially-coupled low-density parity check (SC-LDPC) code.

[0058] Figure 8 is a schematic diagram of the existing fifth-generation (5G) LDPC code encoding scheme.

[0059] Figure 9 is a schematic flowchart of the information processing method 900 provided in this application.

[0060] Figure 10 is a schematic diagram of overlap depth and overlap rate.

[0061] Figure 11 is another schematic diagram of overlap depth and overlap rate.

[0062] Figure 12 is a schematic diagram of the coupling degree α.

[0063] Figure 13 is another schematic diagram of the coupling degree α.

[0064] Figure 14 shows an example of the overlap rate β.

[0065] Figure 15 shows another example of the overlap rate β.

[0066] Figure 16 shows another example of the overlap rate β.

[0067] Figure 17 is a schematic diagram of bit interleaving.

[0068] Figure 18 is a schematic diagram of the parity bits for the tail code block.

[0069] Figure 19 is a specific example of an embodiment of this application.

[0070] Figure 20 is an example of the coupling relationship between code blocks and between SC blocks within a code block.

[0071] Figure 21 is a schematic diagram of a device provided in an embodiment of this application.

[0072] Figure 22 is another structural schematic diagram of the device provided in an embodiment of this application.

[0073] Figure 23 is a schematic diagram of a chip system provided in an embodiment of this application. Detailed Implementation

[0074] To facilitate understanding of the embodiments of this application, the following points will be explained before introducing the embodiments of this application.

[0075] "System" and "network" can be used interchangeably. "At least one" refers to one or more, and "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the related objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, "at least one of A, B, or C" includes A, B, C, AB, AC, BC, or ABC, and "at least one of A, B, and C" can also be understood as including A, B, C, AB, AC, BC, or ABC. And, unless otherwise specified, the ordinal numbers such as "first" and "second" mentioned in the embodiments of this application are used to distinguish multiple objects and are not used to limit the order, sequence, priority, or importance of multiple objects. The term "protocol" can refer to standard protocols in the field of communications, such as Long Term Evolution (LTE) protocols, New Radio (NR) protocols, and related protocols applied to future communication systems. This application does not limit this. Words such as "exemplary," "for example," "exemplarily," and "as another example" are used to indicate that something is being described as an example, illustration, or description. Any embodiment or design described as "exemplary" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. The terms "comprising," "including," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized. The character " / " generally indicates that the preceding and following objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of a single item or a plurality of items. For example, at least one of a, b, and c can mean: a, or, b, or, c, or, a and b, or, a and c, or, b and c, or, a, b, and c. a, b, and c can be a single or multiple.

[0076] In this application, "sending information" can be understood as one device sending information to another device, or it can also be understood as one logic module within a device sending information to another logic module. For example, "the encoding device sending information" can be understood as the encoding device sending information to another device (such as a decoding device), or it can be understood as logic module 1 in the encoding device sending information to logic module 2 in the encoding device.

[0077] In this application, "receiving information" can be understood as one device receiving information from another device, or it can also be understood as a logic module within a device receiving information from another logic module. For example, "decoding device receiving information" can be understood as the decoding device receiving information from another device (such as an encoding device), or it can be understood as logic module 1 in the decoding device receiving information from logic module 2 in the decoding device.

[0078] In this application, the phrase "sending information to... (e.g., a decoding device)" or the related illustrations in the accompanying drawings can be understood as the destination of the information being a decoding device. This can include sending information directly or indirectly to a terminal. Similarly, the phrases "receiving information from... (e.g., an encoding device)," "receiving information from... (e.g., an encoding device)," or "receiving information sent (e.g., by an encoding device)," or the related illustrations in the accompanying drawings, can be understood as the source of the information being an encoding device. This can include receiving information directly or indirectly from an encoding device. Information may undergo necessary processing between the source and destination, such as format changes, but the destination can understand the valid information from the source. Similar expressions in this application can be interpreted similarly, and will not be elaborated further here.

[0079] Furthermore, the network architecture and business scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0080] The following describes a communication system to which embodiments of this application can be applied.

[0081] The embodiments of this application can be applied to various communication systems, including but not limited to: 5G or NR systems, LTE systems, Long Term Evolution-Advanced (LTE-A) systems, LTE Frequency Division Duplex (FDD) systems, LTE Time Division Duplex (TDD) systems, etc. They can also be applied to future communication systems. Furthermore, they can be applied to device-to-device (D2D) communication, vehicle-to-everything (V2X) communication, machine-to-machine (M2M) communication, machine-type communication (MTC), Internet of Things (IoT) communication systems, narrowband Internet of Things (NB-IoT) systems, or other communication systems. Furthermore, it can be extended to similar wireless communication systems, such as wireless-fidelity (WiFi), worldwide interoperability for microwave access (WIMAX), deep space communications, and communication systems related to the 3rd generation partnership project (3GPP), without limitation.

[0082] The communication system applicable to embodiments of this application may include one or more transmitting devices and one or more receiving devices. Optionally, one of the transmitting device and the receiving device may be a terminal, and the other may be a network device. Optionally, both the transmitting device and the receiving device may be terminals. Optionally, both the transmitting device and the receiving device may be network devices.

[0083] In this application, the transmitting device can be understood as a device that transmits data or information, and can also be called an encoding device. The receiving device can be understood as a device that receives data or information, and can also be called a decoding device. The following uses the terms encoding device and decoding device to describe the scheme of this application.

[0084] For example, Figure 1 shows a schematic diagram of a network architecture to which embodiments of this application may be applied.

[0085] Figure 1 illustrates a possible, non-limiting system diagram. As shown in Figure 1, the communication system 10 includes a radio access network (RAN) 100 and a core network (CN) 200. RAN 100 includes at least one RAN node (110a and 110b in Figure 1, collectively referred to as 110) and at least one terminal (120a-120j in Figure 1, collectively referred to as 120). RAN 100 may also include other RAN nodes, such as wireless relay devices and / or wireless backhaul devices (not shown in Figure 1). Terminal 120 is wirelessly connected to RAN node 110. RAN node 110 is wirelessly or wired connected to core network 200. The core network equipment in core network 200 and RAN node 110 in RAN 100 can be different physical devices, or they can be the same physical device integrating core network logical functions and radio access network logical functions.

[0086] RAN 100 can be a cellular system related to the 3rd Generation Partnership Project (3GPP), such as 4G, 5G mobile communication systems, or future-oriented evolution systems. RAN 100 can also be an open RAN (O-RAN or ORAN), a cloud radio access network (CRAN), or a wireless fidelity (WiFi) system. RAN 100 can also be a communication system that integrates two or more of the above systems.

[0087] RAN node 110, sometimes also referred to as access network equipment, RAN entity, or access node, constitutes part of the communication system and is used to help terminals achieve wireless access. Multiple RAN nodes 110 in communication system 10 can be of the same type or different types. In some scenarios, the roles of RAN node 110 and terminal 120 are relative. For example, network element 120i in Figure 1 can be a helicopter or drone, which can be configured as a mobile base station. For terminals 120j accessing RAN 100 through network element 120i, network element 120i is a base station; but for base station 110a, network element 120i is a terminal. RAN node 110 and terminal 120 are sometimes both referred to as communication devices. For example, network elements 110a and 110b in Figure 1 can be understood as communication devices with base station functions, and network elements 120a-120j can be understood as communication devices with terminal functions.

[0088] In one possible scenario, the RAN node can be a base station, an evolved NodeB (eNodeB), an access point (AP), a transmission reception point (TRP), a next-generation NodeB (gNB), a base station in a future mobile communication system, or an access node in a WiFi system. The RAN node can be a macro base station (as shown in Figure 1, 110a), a micro base station or indoor station (as shown in Figure 1, 110b), a relay node or donor node, or a radio controller in a CRAN scenario. Optionally, the RAN node can also be a server, wearable device, vehicle, or in-vehicle equipment. For example, the access network equipment in vehicle-to-everything (V2X) technology can be a roadside unit (RSU). All or part of the functions of the RAN node in this application can also be implemented through software functions running on hardware, or through virtualization functions instantiated on a platform (e.g., a cloud platform). The RAN node can also be equipped with communication modules, circuits, or chips that perform corresponding communication functions. The RAN node can also be configured with program instructions for performing corresponding communication functions, as well as corresponding program instructions. The RAN node in this application can also be a logical node, logical module, or software capable of implementing all or part of the RAN node's functions.

[0089] In another possible scenario, multiple RAN nodes collaborate to assist the terminal in achieving wireless access, with each RAN node performing a portion of the base station's functions. For example, RAN nodes can be central units (CUs), distributed units (DUs), CU-control plane (CPs), CU-user plane (UPs), or radio units (RUs), etc. CUs and DUs can be separate entities or included in the same network element, such as a baseband unit (BBU). RUs can be included in radio frequency equipment or radio frequency units, such as remote radio units (RRUs), active antenna units (AAUs), or remote radio heads (RRHs).

[0090] In different systems, CU (or CU-CP and CU-UP), DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an ORAN system, CU can also be called O-CU (open CU), DU can also be called O-DU, CU-CP can also be called O-CU-CP, CU-UP can also be called O-CU-UP, and RU can also be called O-RU. For ease of description, this application uses CU, CU-CP, CU-UP, DU, and RU as examples. Any of the units among CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented through software modules, hardware modules, or a combination of software and hardware modules.

[0091] In the embodiments of this application, the access network device may also be simply referred to as a network device.

[0092] A terminal can be a device or module that accesses the aforementioned communication system and has corresponding communication functions. A terminal can also be called a terminal device, user equipment (UE), mobile station, mobile terminal, etc. Terminals can be widely used in various scenarios, such as device-to-device (D2D), vehicle-to-everything (V2X) communication, machine-type communication (MTC), Internet of Things (IoT), virtual reality, augmented reality, industrial control, autonomous driving, telemedicine, smart grids, smart furniture, smart offices, smart wearables, smart transportation, smart cities, etc. Terminals can be mobile phones, tablets, computers with wireless transceiver capabilities, wearable devices, vehicles, drones, helicopters, airplanes, ships, robots, robotic arms, smart home devices, transportation vehicles with wireless communication capabilities, communication modules, etc. The embodiments of this application do not limit the device form of the terminal. A terminal typically contains a communication module, circuit, or chip that performs the corresponding communication function. The terminal can also be configured with program instructions for performing the corresponding communication function.

[0093] Furthermore, the embodiments of this application can be applied to various application scenarios, such as high-throughput scenarios, high-reliability scenarios, low-latency scenarios, high-reliability low-latency scenarios, or low-power scenarios. High-throughput scenarios can be, for example, enhanced mobile broadband (eMBB) scenarios, extended-reality (XR) scenarios, cloud gaming (CG) scenarios, or augmented reality (AR) scenarios. High-reliability low-latency scenarios can be, for example, ultra-reliable low-latency communication (URLLC) scenarios or hyper-reliable low-latency communication (HRLLC) scenarios. Low-power scenarios can be, for example, M2M scenarios, MTC scenarios, massive MTC (mMTC) scenarios, IoT scenarios, narrowband Internet of Things (NB-IoT) scenarios, advanced Internet of Things (A-IoT) scenarios, low-power wide-area (LPWA) scenarios, etc.

[0094] The embodiments of this application can be applied to various mobile communication scenarios, such as multi-hop or multi-relay transmission between network devices and terminal devices, dual connectivity (DC) or multiple connectivity between multiple network devices and terminal devices, etc.

[0095] Figure 2 is a schematic diagram of a communication scenario applicable to embodiments of this application.

[0096] Figure 2(a) shows a point-to-point single connection between a network device and a terminal device; Figure 2(b) shows a multi-hop single connection between a network device and a terminal device; Figure 2(c) shows a DC dual connection between a network device and a terminal device; and Figure 2(d) shows a multi-hop multi-connection between a network device and a terminal device.

[0097] It should be noted that Figure 2 is merely exemplary and does not limit the network architecture applicable to this application. Any network architecture in a cellular network where one device charges other devices is applicable to this application. Communication scenarios applicable to this application include, but are not limited to: network devices charging terminal devices, network devices charging network devices, network devices charging relays, relay network devices charging terminal devices, multiple network devices charging one terminal device, multiple network devices charging multiple terminal devices, and any scenario where one or more devices charge one or more other devices.

[0098] Unless otherwise specified, the means for implementing the functions of a terminal or network device in this application can refer to the terminal or network device itself, or it can refer to a means that enables the terminal or network device to implement the function, such as a system-on-a-chip (SoC) or a chip, specifically a SoC or a modem. This means can be installed in the terminal or network device. In the embodiments of this application, the SoC can be composed of chips, or it can include chips and other discrete devices.

[0099] It should also be noted that some embodiments in this article use a 5G system as an example to illustrate specific solution details. It is understood that when this solution is used in other communication systems, such as LTE systems or future communication systems, the messages, channels, or information in the solution can be replaced with messages, channels, or information in other communication systems that can achieve the corresponding functions, and this application does not limit this.

[0100] The technical solutions provided in the embodiments of this application can be applied to channel coding / decoding between communication devices. Channel coding / decoding between communication devices can include: channel coding / decoding between network devices and terminal devices, channel coding / decoding between network devices, and channel coding / decoding between terminal devices. The term "channel coding" can also be abbreviated as "coding," "network coding," "source-channel joint coding," etc., and the term "channel decoding" can also be abbreviated as "decoding," "network decoding," "source-channel joint decoding," etc.

[0101] Figure 3 is a schematic architecture diagram of a mobile communication chip system applicable to embodiments of this application.

[0102] As shown in Figure 3, the mobile communication chip system is divided into downlink processing and uplink processing. In downlink processing, layer 2 (L2) data is encoded, modulated, layer mapped, precoded, framed, and subjected to inverse fast Fourier transform (IFFT), and finally processed into an over-the-air signal by the intermediate radio frequency (IRF) module. In uplink processing, the received signal is processed by the IRF module to obtain baseband data, and physical layer signal processing is completed through fast Fourier transform (FFT), deframing, equalization, de-mapping, demodulation, and decoding. The embodiments of this application are applied to the encoding and decoding modules in the mobile communication chip system architecture and are important components of the baseband processing system. Exemplarily, the encoding module can be an encoder chip, and the decoding module can be a decoder chip.

[0103] Figure 4 is a schematic architecture diagram of an encoder chip applicable to embodiments of this application.

[0104] The encoder chip architecture, as shown in Figure 4, consists of three main components: a computing unit, a control unit, and a storage unit. These three components are coupled together. The computing unit is responsible for processing the encoder's logical operations, the storage unit is responsible for storing the data generated during the computation process, and the control unit is responsible for scheduling and controlling the computing unit and storage resources. Taking LDPC encoding as an example, the encoder's computation is completed through transport block (TB) cyclic redundancy check (CRC) calculation, BG selection, code block segmentation, code block (CB) CRC calculation, LDPC encoding, and code block concatenation. The encoder chip can perform corresponding encoding according to the encoding scheme provided in the embodiments of this application.

[0105] Figure 5 is a schematic architecture diagram of a decoder chip applicable to embodiments of this application.

[0106] The decoder chip architecture, as shown in Figure 5, consists of three main components: a computing unit, a control unit, and a storage unit. These three components are interconnected. The computing unit is responsible for handling the decoder's logical operations, the storage unit is responsible for storing data generated during the computation process, and the control unit is responsible for scheduling and controlling the computing unit and storage resources. Taking LDPC decoding as an example, the decoding process is completed through rate matching, hybrid automatic repeat-request (HARQ) merging, LDPC decoding, CB CRC check, and TB CRC check. The decoder chip can perform corresponding decoding according to the encoding scheme provided in the embodiments of this application.

[0107] The encoding and / or decoding shown in Figures 3 to 5 can be implemented in hardware or software. When the throughput requirement for encoding / decoding is high, a hardware accelerator (HAC) can be used.

[0108] To facilitate understanding of the embodiments of this application, several concepts or terms involved in the embodiments of this application are briefly described. The concepts or terms described below are based on the concepts or terms specified in the agreement, but do not mean that the embodiments of this application can only be applied to existing systems. The concepts or terms involved in the embodiments of this application can be applied to future systems. Furthermore, the specific names of the concepts or terms (e.g., concepts or terms involving functional descriptions) can be adjusted as the system develops in the future.

[0109] 1. LDPC code

[0110] LDPC codes are linear block codes with sparse parity-check matrices. The proportion of non-zero elements in the parity-check matrix of an LDPC code is extremely small; in other words, the row and column weights of the parity-check matrix are very small compared to the code length of the LDPC. For an LDPC code with K information bits and a code length of N, its parity-check matrix H has dimensions (NK) × N, and the corresponding codeword c can be defined by the parity-check matrix H as: c = {c|Hc} T =0, c∈{0,1} N}

[0111] .

[0112] In the parity-check matrix H, each row corresponds to a parity-check equation of the LDPC code, and the NK parity-check equations correspond to the NK parity-check nodes of the LDPC code; each column corresponds to a symbol of the LDPC code, and the N symbols correspond to the N variable nodes of the LDPC code. The non-zero elements h in the parity-check matrix H... i,j This indicates that the i-th check node and the j-th variable node are connected. In the check matrix, the number of non-zero elements in each row represents the degree of the check node, and the number of non-zero elements in each column represents the degree of the variable node. If all check nodes have the same degree, all variable nodes also have the same degree; the corresponding LDPC code is a regular code. Otherwise, it is an irregular code. For example, the check matrix H of a regular LDPC code with a code length of 10 and a code rate of 1 / 2 can be as follows:

[0113] Where v0, v1, ..., v9 represent variable nodes, and c0, c1, ..., c4 represent check nodes.

[0114] LDPC codes can be represented using graph models. Commonly used graph models include Tanner graphs, factor graphs, and tree graphs, among which Tanner graphs offer the most concise and intuitive representation. The Tanner graph of the parity-check matrix H is shown in Figure 6. The degree in Figure 6 corresponds to the definition of degree in the parity-check matrix H, where the degree of a node can be defined as the number of edges connected to it.

[0115] 2. Quasi-cyclic low-density parity check (QC-LDPC) code

[0116] The parity-check matrix of QC-LDPC code has quasi-cyclic properties, and the parity-check matrix can be simplified according to the quasi-cyclic structure.

[0117] For a (N, K) QC-LDPC code, the number of check bits (or check nodes, rows) is M = NK, and the check matrix H can be represented as:

[0118] Where N = n b ×Z, M=m b ×Z, Z≥1, P i,j This represents a Z×Z cyclic shift matrix or a Z×Z all-zero matrix, which can be represented by the corresponding cyclic shift coefficient p. i,j To simplify the representation, Z represents the lifting size, also known as the expansion factor, expansion value, expansion coefficient, or lifting dimension. Here, the cyclic shift matrix is ​​defined as a cyclic right shift matrix of an identity matrix. The shift factor is determined by the number of bits shifted to the right of the first element, and its value ranges from p. i,j ∈[-1,Z max -1], where Z max It is the maximum value of Z, Z≤Z max p i,j =-1 represents a matrix of all zeros, p i,j =0 represents the identity matrix, 1≤p i,j ≤Z max -1 indicates that each element of the identity matrix is ​​cyclically shifted right by 1 by p. i,j The matrix obtained by the bit transformation function g(p) i,j (Z) usually has the following form:

[0119] Where % represents the modulo operation, with Z=4, Z max For example, with a value of 8, the p of LDPC i,j The corresponding matrix is:

[0120] The matrix obtained by simplifying the parity-check matrix based on a quasi-cyclic structure can be called the basis matrix. Based on the basis matrix and the boost value Z, the basis matrix H can be expanded into a complete parity-check matrix for encoding or decoding. The basis matrix can also be called the base graph (BG). The base graph can also be called the basic pattern graph.

[0121] 3. SC-LDPC code

[0122] SC-LDPC codes are a special type of LDPC code widely used in various communication fields, such as optical communication. The parity-check matrix of an SC-LDPC code is constructed from multiple coupled submatrices, with the basis matrix B based on a basis graph. SC-LDPC It can be represented as:

[0123] Among them, B SC-LDPC The number of columns is the coupling length L, and each column m represents time t. c +1 sub-BG blocks, each of size m0×n0, and all BG blocks at time t are considered as one SC block. SC-LDPC The BG blocks in two adjacent columns will be coupled, and the coupling depth is denoted by m. c The code is represented by the time-invariant SC-LDPC code. When the sub-BG blocks of two adjacent SC blocks are the same, it is called time-invariant SC-LDPC; otherwise, it is time-varying SC-LDPC. For ease of description, this application uses time-invariant SC-LDPC codes for illustration.

[0124] Similar to QC-LDPC, the parity-check matrix H of the SC-LDPC code can also be obtained by expanding the parity-check matrix using the offset matrix. SC-LDPC H SC-LDPC The size is [m0(m c +L)·Z]×(n0L·Z). B SC-LDPC The corresponding offset matrix can be denoted as P SC-LDPC Each element p in i,j To satisfy p i,j Integers ≥-1. If p i,j =-1, it can be expanded into a zero matrix of size Z×Z; otherwise, it can be expanded into a cyclic shift matrix of size Z×Z identity matrix, p i,j This represents the cyclic displacement to the right. It should be noted that "-1" in the basis matrix can also be expressed in other forms, such as using "-" or a null value.

[0125] To ensure H SC-LDPC Decoding performance is typically in B SC-LDPCA tail parity matrix I is introduced in the lower right corner, where I is an m0×m0 square matrix. I can be an identity matrix or a lower triangular matrix. In this case, the basis matrix B SC-LDPC It can be represented as:

[0126] The basis matrix B of the SC-LDPC code SC-LDPC Each column can be viewed as an LDPC code, which can contain information bits and check bits.

[0127] The following uses coupling depth m c Taking 1 as an example, the encoding process of SC-LDPC code is described.

[0128] Figure 7 is a schematic diagram of the SC-LDPC code encoding scheme.

[0129] As shown in Figure 7, the encoding scheme of SC-LDPC code can be expressed as: Input length K TB The information bit sequence is evenly divided into each SC block. For information bit 1 in SC block 1, the parity bit of SC block 1 is obtained by encoding according to the parity check matrix. For information bits in SC block 2 and subsequent SC blocks, the information bits in the current SC block, the information bits of the previous SC block, and the parity bit of the previous SC block are used together as information bits to obtain the parity bit of the current SC block, and so on. For the last tail SC block, it is obtained by encoding according to the information bits and parity bits of the previous SC block.

[0130] The above coding scheme enables connections between adjacent SC blocks. These connections allow for the full utilization of more effective information at the same signal-to-noise ratio. Furthermore, fewer decoding iterations can be used, resulting in higher throughput.

[0131] 4. Encoding scheme for 5G LDPC codes

[0132] The embodiments of this application include replacing the 5G LDPC code in the existing 5G LDPC code encoding scheme with the SC-LDPC code. For ease of comparison, the existing 5G LDPC code encoding scheme is described below.

[0133] Figure 8 is a schematic diagram of the existing 5G LDPC code encoding scheme.

[0134] As shown in Figure 8, existing 5G LDPC code encoding schemes include:

[0135] 1) Transport block (TB) - Cyclic redundancy check (CRC) appending: For an input of length K information bits, append a length of L to the end. TBCRC The TB-CRC bits are used to obtain a length of K. TBCRC =K+L TBCRC Total information bits.

[0136] 2) Code block (CB) segmentation: Given the maximum length K of the information bits of the currently used LDPC code. (CB,max) If K TBCRC ≤K (CB,max) Then no code block segmentation is required; if K TBCRC >K (CB,max) Then the total information bits are divided into C CBs.

[0137] 3) TB padding: If the above segmentation cannot ensure that each CB contains the same number of information bits, then add an L to the beginning of the total information bits. TBpadding The number of padding bits allows the total number of information bits after padding to be evenly divided into C C B bits.

[0138] 4) Add CB-CRC: If C=1, no CB-CRC bits are added; if C>1, 16 or 24 CB-CRC bits are added to the end of the information bits of each CB.

[0139] 5) Padded the end of the information bits of each CB, and traversed the lookup table of the expansion factor Z until the actual length K of the CB was reached. CB Z is determined when it is exactly divisible by the expansion factor Z.

[0140] 6) Each CB is independently encoded using LDPC code to obtain the encoded information bits, which are then used for rate matching.

[0141] The relevant terms used in the embodiments of this application have been described above, and will not be explained further below.

[0142] As described above, existing 5G LDPC code encoding schemes encode a single code block (CB) without considering establishing coupling relationships between CBs to enhance decoding performance. Furthermore, since coupled codes have a multi-block coupling structure, they can be used to encode both individual CBs and entire code blocks (CBs can be coupled using coupled code structures). Therefore, embodiments of this application consider applying coupled code encoding schemes to 5G LDPC codes to improve LDPC code performance.

[0143] The embodiments of this application do not limit the encoding method of the subcodes of the coupled code. For example, it can be a spatially coupled low-density parity-check code or a spatially coupled polar code. The encoding matrix of the coupled code can be simply referred to as the coupled encoding matrix. Each X column of the coupled encoding matrix can correspond to a submatrix group, and each submatrix group includes W submatrices. The W submatrices are of the same size and are non-zero matrices. The row numbers of the first row of the first submatrix corresponding to each of the multiple submatrix groups are different. In the following text, BG blocks are used to represent the submatrix of the coupled code, and SC blocks are used to represent the submatrix group. For example, when the subcode of the coupled code is an LDPC code, that is, when the coupled code is an SC-LDPC basis matrix, X = n0, W = m c +1, the first row of the first submatrix corresponding to each of the multiple submatrix groups is increased by m0 in turn.

[0144] The method embodiments of this application are described below with reference to the accompanying drawings.

[0145] Figure 9 is a schematic flowchart of the information processing method 900 provided in this application.

[0146] It is understood that method 900 is illustrated using an encoding device as the execution subject, but the embodiments of this application do not limit the execution subject of method 900. For example, the method executed by the encoding device in method 900 can also be implemented by a module in the encoding device, or a logical node, logical module, or software that can implement all or part of the functions of the encoding device. A module in the encoding device can be, for example, a circuit, a chip, or a chip system (such as a modem chip, also known as a baseband chip, or a SoC chip or SIP chip containing a modem core, etc.). The encoding device can be a terminal device or a network device.

[0147] Method 900 may include at least a portion of the following.

[0148] Step 901: The encoding device acquires the first information bit.

[0149] In the embodiments of this application, the first information bit includes TB, TB CRC bits, and all CB CRC bits. The CB CRC bits in the first information bit can be empty; they are filled with the calculated value after the CB is divided and the CB CRC bits are calculated. The method for calculating the TB CRC bits based on TB can refer to existing schemes and will not be detailed further.

[0150] It should be understood that if the total number of information bits to be encoded (i.e., TB) is greater than the number of information bits that the encoding matrix of the coupled code can encode, the total information bits can be divided into multiple sub-information bits, and then the encoding scheme provided in the embodiments of this application can be implemented for each sub-information bit.

[0151] In other words, if the encoding device needs to communicate with the decoding device, that is, if the encoding device needs to send a signal to the decoding device, the encoding device needs to first obtain the information bits corresponding to the signal to be sent to the decoding device.

[0152] The process of the encoding device acquiring the first information bit can refer to: the encoding device performing source encoding on the source symbol to generate the first information bit. Alternatively, it can refer to: the encoding device receiving the first information bit from another communication device. In step 902, the encoding device obtains N first blocks based on the first information bit, where N is an integer greater than 1.

[0153] Step 903: The encoding device obtains C second blocks based on N first blocks.

[0154] In this context, each of the A second blocks out of the C second blocks includes multiple first blocks. C is an integer less than N, such as C can be 1, 2, 3, 4, ... A is an integer less than or equal to C. In other words, some or all of the C second blocks may include multiple first blocks.

[0155] The number of first blocks included in each of the C second blocks can be the same or different, without restriction.

[0156] In some implementations, the first blocks included in the C second blocks do not overlap; in other words, no two second blocks contain the same first block. For example, the encoding device obtains 5 second blocks based on 10 first blocks, and each of the 5 blocks includes 2 of the 10 first blocks. For instance, second block #1 includes first block #1 and first block #2, second block #2 includes first block #3 and first block #4, second block #3 includes first block #5 and first block #6, second block #4 includes first block #7 and first block #8, and second block #5 includes first block #9 and first block #10.

[0157] In some implementations, within A second blocks, the first blocks included in adjacent second blocks overlap; in other words, adjacent second blocks include one or more identical first blocks. For example, the encoding device derives 4 second blocks from 10 first blocks. Second block #1 includes first block #1, first block #2, first block #3, and first block #4; second block #2 includes first block #3, first block #4, first block #5, and first block #6; second block #3 includes first block #5, first block #6, first block #7, and first block #8; and second block #4 includes first block #7, first block #8, first block #9, and first block #10. For example, the encoding device obtains 4 second blocks based on 10 first blocks. Second block #1 includes first block #1, second block #2 includes first block #2, first block #3, first block #4, first block #5 and first block #6, second block #3 includes first block #5, first block #6, first block #7 and first block #8, and second block #4 includes first block #7, first block #8, first block #9 and first block #10.

[0158] In some implementations, the encoding device can obtain C second blocks based on the overlap rate and N first blocks. The overlap rate represents the percentage of the bit length overlapping between two adjacent second blocks relative to the total length of the first second block. For example, the overlapping bit length can be granular with the length of the first block. In this case, the overlap rate can be represented as the ratio of a first value and a second value, where the first value is the number of identical first blocks in two adjacent second blocks, and the second value is the total number of first blocks included in the first of the two second blocks. The overlap rate is a rational number greater than or equal to 0 and less than 1. When the overlap rate is 0, it means that no two adjacent second blocks overlap. When the overlap rate is not 0, there is overlap between adjacent second blocks containing multiple first blocks.

[0159] The following example, with the first block corresponding to SC block and the second block to CB, provides a detailed explanation of the process from the first information bit to N first blocks and from N first blocks to C second blocks.

[0160] Define s SC blocks as a CB. The number of SC blocks in C CBs can be the same or different. When the number of SC blocks in C CBs is the same, s can be used to represent the number of SC blocks included in each CB, or s... i This represents the number of SC blocks included in the i-th CB among C CBs, where s i =s i+1 When the number of SC blocks in C CBs is not the same, s can be used. i This represents the number of SC blocks included in the i-th CB among the C CBs.

[0161] Define the overlapping depth γ, where γ represents the length of the overlapping part included between CB i and CB i+1 Exemplarily, the unit of the overlapping depth can be an SC block. At this time, 0 < γ < s i CB i is the i-th CB among C CBs, and CB i+1 is the (i + 1)-th CB among C CBs. Similarly, define the overlapping rate β of CB, which represents the percentage of the bit length of the overlap between CB i and CB i+1 in the total length of CB i , 0 ≤ β < 1, and β is a rational number.

[0162] Figure 10 is a schematic diagram of the overlapping depth and the overlapping rate. As shown in Figure 10, the overlapping depth γ between the i-th CB and the (i + 1)-th CB is 1 SC block, and the overlapping rate β = 1 / 3.

[0163] Figure 11 is another schematic diagram of the overlapping depth and the overlapping rate. As shown in Figure 11, the overlapping depth γ between the i-th CB and the (i + 1)-th CB is 2 SC blocks, and the overlapping rate β = 2 / 3.

[0164] When the number of SC blocks in each CB is the same, there is S = C·s, 0 < s < S, where C is the number of CBs, which can be preset or configured through indication parameters, and C satisfies c is the number of SC blocks in CB that do not participate in the overlap. K TBCRC is the length of the information bits after adding the TB CRC. L CBCRC is the length of the CRC bits at the CB level, generally 16 or 24, and this length can be preset or configured through indication parameters. When s > 1, the overlapping depth γ satisfies γ < s. Let γ = s - c. When there is an overlap, the number of CBs and the number of CBCRCs C satisfy C = (S - s) / c + 1; when s = 1, there is no overlapping CB at this time, which is equivalent to γ = 0.

[0165] When the number of SC blocks included in each CB is different, use s i to represent the number of SC blocks included in the i-th CB. In this case, C satisfies

[0166] Combined with Figure 11, when c = 1, the overlapping depth reaches the deepest, the number of CB CRCs reaches the maximum, and the information bits of each SC block belong to multiple CBs at the same time. When there are errors in multiple SC blocks, the flexibility of retransmission is higher.

[0167] The above s and si The parameters s and s can be preset according to the modulation coding scheme (MCS), TPayloadSize, etc., or configured by indication parameters. i C and S are all positive integers.

[0168] In some implementations, the encoding device can uniformly divide the first information bit into N SC blocks. If the first information bit cannot be uniformly divided into N SC blocks, the encoding device can add a second padding bit to the first information bit to obtain a second information bit, and then uniformly divide the second information bit into N SC blocks.

[0169] In some other implementations, a CRC bit can be added to each SC block. In this case, the encoding device can add a second padding bit to the first information bit to obtain a second information bit, and then divide the second information bit evenly into N SC blocks. Then, a CRC bit is added to each SC block to obtain N first blocks, which are the SC blocks after adding the CRC bit.

[0170] In other implementations, the encoding device can divide the first information bit into N SC blocks of different sizes without restriction.

[0171] It should be understood that the second padding bit can be located at the beginning, middle, end, or any position of the first information bit, without restriction.

[0172] The number of CBs, C, can be 1 or greater than 1. The following explains the scheme of obtaining C second blocks from N first blocks in these two cases.

[0173] 1. C = 1

[0174] At this point, there is only one CB containing s SC blocks. TB partitioning and placement can be performed according to the following rules:

[0175] 1) Divide the first information bits (including TBCRC), i.e. the total information bits, into K information bits in s SC blocks. SCB That is, N = s, and all s SC blocks belong to one CB. Since there is only one CB, there can be no CB CRC. The number of information bits in the s SC blocks can be the same or different. When the number of information bits in the s SC blocks is the same, the number of information bits in each SC block is... If the number of information bits in the s SC blocks is the same, and the first information bit cannot be evenly divided into s SC blocks, then the first information bit can be padded. Specifically, L can be added to the first information bit. TB,padding =sK TBCRC %s padding bits to make it evenly divided into s parts, where K TBCRC The length of the first information bit. For example, the padding bits can be 0 bits.

[0176] 2) Then, the divided information bits are placed into each SC block. The divided information bits can be located at the beginning, middle, end, or any other position of the SC block, without restriction. The maximum number of information bits placed in each SC block does not exceed the maximum information bit length k of the SC block. SCB,max =k sub ·z max .

[0177] 2. C>1

[0178] TB partitioning and placement can be performed according to the following rules:

[0179] 1) Divide the first information bit (including TBCRC and all CBCRC, with CBCRC positions initially reserved as empty) into (C-1)c+s parts, with the length of each part denoted as L1. If the first information bit cannot be evenly divided into (C-1)c+s parts, padding bits can be added to the first information bit to make it evenly divided into (C-1)c+s parts. Specifically, L1 can be added to the first information bit. TB,padding = (C-1)c+sK TBCRC %[(C-1)c+s] padding bits make it possible to divide it into a sequence of length L1. For example, the padding bits can be 0 bits.

[0180] Optionally, when the overlap rate is 0 and the number of evenly distributed SC blocks cannot be divided by a preset C, TB-level padding can be performed. Specifically, P bits (i.e., the third padding bits) can be padded into the first information bit until... Among them, L CBCRC Z is the length of the CRC bits in CB. max To maximize the boost value, k sub This represents the number of columns in the BG block of the coupled coding matrix. It should be understood that the third padding bit can be located at the beginning, middle, end, or any other position of the first information bit, without restriction.

[0181] 2) Then, the first information bits are sequentially placed into each SC block in each CB. The last SC block of each CB reserves space for CBCRC verification. Specifically, for each CB: the number of information bits placed in the first s-1 SC blocks is L1 / s, and the length of information bits placed in the last SC block is L1 / s–L. CBCRC .

[0182] Step 904: The encoding device performs coupled encoding based on the C second blocks and the coupled encoding matrix to obtain the C encoded code blocks.

[0183] In some implementations, the encoding device can add CRC bits to C second blocks to obtain C third blocks; then, the i-th third block among the C third blocks is evenly divided into s. i The fourth piece, s i The first bit is a positive integer; then, the first padding bit is added to each fourth block to obtain the fifth block, and the length of the fifth block is K. SCB,padded Satisfy: K SCB,padded =K sub ·Z, where K sub Z represents the number of information columns in a BG block of the coupled coding matrix, and Z is the boost value. Then, based on the coupled coding matrix, each of the different fifth blocks is encoded to obtain C encoded code blocks. For example, Z can satisfy K... SCB,padded =K sub • The minimum increase value of Z.

[0184] Alternatively, when C=1, the encoding device may not add CRC bits to the C second blocks.

[0185] It should be understood that the second block can be CB, because the first information bits have reserved space for CB-level CRC bits, so the resulting second block can definitely be s. i Divisible by.

[0186] The embodiments of this application do not limit the implementation of determining the CRC bits of the second block.

[0187] In some implementations, the encoding device can obtain the CRC bit of the i-th third block from the C third blocks based on the CRC bits of the i-th second block out of the C second blocks and the (i-1)-th third block out of the C third blocks, where i is an integer greater than 1. That is, the CRC bit of the current second block can be calculated based on the CRC bits of the current second block, the previous second block, and the CRC bits of the previous second block (i.e., the CRC bits in the corresponding third block). In this implementation, for cases where the overlap rate is not zero, the overlapping portion participates in two CRC calculations, making the CRC result of the overlapping portion more reliable.

[0188] In other implementations, the encoding device can obtain the CRC bits of the i-th third block out of the C third blocks based on the i-th second block out of the C second blocks, where i is an integer greater than 1. That is, the CRC bits of the current second block can be calculated based on the current second block. In this implementation, the CRC of each second block can be calculated in parallel, resulting in faster speed.

[0189] The embodiments of this application do not limit the position of the CRC bits at the second block level in the third block. Exemplarily, the CRC bits in the i-th third block are distributed at the beginning, end, middle, or any position within the i-th third block. Exemplarily, the CRC bits in the i-th third block are distributed within the s... i The CRC bits in the i-th third block are distributed across the s first blocks included in the i-th third block. The number of CRC bits in each first block can be the same or different. For example, the CRC bits in the i-th third block are evenly distributed across the s first blocks included in the i-th third block.

[0190] The embodiments of this application are not limited to the implementation of the fifth block encoding.

[0191] In some implementations, the parity bits of the j-th fifth block are obtained based on x fifth blocks coupled to the j-th fifth block, the j-th fifth block itself, and the coupling coding matrix, where x is less than or equal to m. c positive integers, m c =W-1, where j is a non-negative integer. In this implementation, multiple fifth blocks can be encoded in parallel, resulting in high encoding efficiency.

[0192] For example, the parity bits of the j-th fifth block can be obtained based on the previous x fifth blocks, the j-th fifth block, and the coupling coding matrix. Where j is less than m... c When x = j; when j is greater than or equal to m c When x = m c Where j is a non-negative integer.

[0193] In other implementations, the parity bit of the j-th fifth block is obtained based on x fifth blocks coupled to the j-th fifth block, the parity bits of those x fifth blocks, the j-th fifth block, and the coupling coding matrix, where x is less than or equal to m. c positive integers, m c=W-1, where j is a non-negative integer. That is, for the parity bit of the first fifth block, the information bits of the first fifth block can be encoded using a parity check matrix; for the parity bits of non-first fifth blocks, a coupling parity check relationship can be used to encode some fifth blocks coupled to this fifth block, as well as the parity bits of these fifth blocks. The maximum number of these fifth blocks can be m. c This implementation method produces good coding results.

[0194] For example, the parity bits of the j-th fifth block can be obtained based on the previous x fifth blocks, the parity bits of the previous x fifth blocks, the j-th fifth block, and the coupling coding matrix. Where j is less than m... c When x = j; when j is greater than or equal to m c When x = m c Where j is a non-negative integer.

[0195] It should be understood that the x fifth blocks preceding the j-th fifth block can be either the x fifth blocks that are positionally preceding the j-th fifth block or the x fifth blocks that are sequentially preceding the j-th fifth block; there are no restrictions.

[0196] In the embodiments of this application, the degree of coupling between the SC block and the SC blcok can be determined by the coupling depth m. c It can also be described by coupling degree α, which is the proportion of coupled sub-blocks in the total number of blocks in SC blcok.

[0197] Figures 12 and 13 are two schematic diagrams of the coupling degree α. The dashed boxes represent the coupling of the bit sequences corresponding to the two SC blcok.

[0198] Similarly, the coupling degree α can also be used to represent the coupling degree between CBs. Figures 14 to 16 show examples with s = 3, coupling degree α = 2 / 3, and overlap rates of 0 / s, 1 / s, and 2 / s, respectively. The dashed boxes indicate that the bit sequences corresponding to SC blcok are coupled, thereby achieving coupling between CBs.

[0199] Based on coupling degree α and overlap rate β, the encoding of the fifth block can also be described as follows: the parity bit corresponding to the first SC block of the first CB is calculated from its own information bits through its corresponding parity equation; the parity bit corresponding to the i-th SC block of the first CB is calculated from the information bits and parity bits corresponding to the i-1 SC blocks coupled to it through the above-mentioned parity equations corresponding to the SC blocks, where 2≤i<1+(m c +1)*α. The parity bit corresponding to the j-th SC block of the first CB is coupled with (m)c The information bits and check bits corresponding to the +1)*α SC blocks are calculated using the check equations corresponding to the SC blocks mentioned above, where 1+(m c +1)*α≤j<s*(1-β). For the parity bit corresponding to the iith SC block that is not the first CB, it is coupled with (m) c The information bits and check bits corresponding to the +1)*α SC blocks are calculated by the check equation corresponding to the above SC blocks, where 1≤ii<s*(1-β).

[0200] In other implementations of the embodiments of this application, the encoding device may also punch holes in the C code blocks obtained in step 904 to achieve rate compatibility, that is, punch holes in the fifth block after encoding. The embodiments of this application do not limit the number of punched columns in the fifth block after encoding; for example, it can be 0, 1, 2, etc. The number of punched columns in each fifth block can be the same or different. When punching the C code blocks, each fifth block cannot be punched repeatedly. Specifically, the punching position of the i-th code block in the C code blocks is located in a different fifth block than the punching positions of the first i-1 code blocks in the C code blocks, where i is an integer greater than 1. That is, for the first CB, holes can be punched in any SC block within the CB; for non-first CBs, overlapping SC blocks cannot be punched repeatedly, and holes within overlapping CBs can be shared by the CBs.

[0201] In other implementations of the embodiments of this application, the encoding device may further perform bit-level interleaving on the encoded C code blocks. The embodiments of this application do not limit the scope of bit interleaving. Exemplarily, each of the C code blocks can be used as input for bit interleaving. Exemplarily, the C code blocks can be used as input bits for bit interleaving. Exemplarily, each encoded fifth block can be used as input for bit interleaving.

[0202] Figure 17 is a schematic diagram of bit interleaving. As shown, bit interleaving can be performed using row-write-column-read or column-write-row-read, where the number of rows is r and the number of columns is q. The input bit length I = r * q of the interleaver can be selected in different ways; for example, interleaving can be performed independently for each SC block (I = K). sub *Z), or interleaving can be applied to the entire TB (I=N). When the overlap rate between CBs is 0, interleaving can also be applied independently to each CB (I=K). sub *Z*s).

[0203] In other implementations of the embodiments of this application, to improve decoding performance, the encoding device may further encode the last y information bits and the last y parity bits of the fifth block according to the coupling encoding matrix, obtaining the parity bits as the tail code block, where y is a positive integer. The size of the tail code block is α1m. sub ×α1m sub α1 is a preset value, m sub y is the row number of a BG block in the coupled coding matrix. The tail block may contain only parity bits. The tail block may be placed in the lower left or lower right corner of the entire coupled coding matrix. For example, y = m c .

[0204] Figure 18 is a schematic diagram of the check bits for the tail code block. As shown in the figure, the tail code block consists of the last m bits of the (C-1)th CB. c One SC block is obtained.

[0205] Referring to Figure 19 below, m is given. c When = 1, the process of constructing transport blocks when encoding the entire TB with SC-LDPC code.

[0206] Figure 19 is a specific example of an embodiment of this application.

[0207] As shown in Figure 19, the process of constructing a transport block when encoding the entire TB using SC-LDPC code includes:

[0208] 1) Add TB CRC

[0209] The first information bit can correspond to the sequence after TBCRC addition, where a space can be reserved for all CB CRC bits. The location of the reserved space is not shown in the figure.

[0210] 2) TB filling + SC block partitioning

[0211] In Figure 9, the first information bit can be divided into 10 SC blocks. The N first blocks can correspond to SC blocks 1 to 10 after TB padding and SC block division. Similarly, each SC block has a reserved position for the CB CRC bit of that block. The location of the reserved position is not shown in the figure.

[0212] 3) Add CB CRC

[0213] In Figure 19, SC blocks 1 to 10 can be divided into 4 CBs, with two adjacent CBs overlapping two SC blocks. The C third blocks can correspond to the 4 CBs in the CB CRC addition part of the figure, and the C second blocks can correspond to the 4 CBs without CB CRC addition.

[0214] 4) CB partitioning + SC block filling

[0215] Taking the first CB partition as an example, the first CB partition results in 4 SC blocks, and each SC block corresponds to the fourth block. After bit stuffing of the SC blocks, 4 fifth blocks are obtained.

[0216] 5) SC-LDPC encoding is used to obtain the encoded codeword.

[0217] Method 900 enables bit coupling between code blocks and between SC blocks within a code block, thereby improving decoding performance. Figure 20 shows an example of the coupling relationship between code blocks and between SC blocks within a code block. The dashed boxes indicate that the coupling check matrix of the coupled code is used to create bit coupling between code blocks and between SC blocks within a code block. Method 900 also provides a TB-level coding scheme for P-coupled codes based on CB overlap, including information bit placement, CB-CRC placement, bit stuffing, puncturing, interleaving, and tail bit settings. Furthermore, Method 900 supports flexible encoding configuration based on the total information bit length, the number of SC blocks in a single CB, the overlap rate, and the number of CBs.

[0218] It should be noted that the decoding device can perform corresponding decoding operations according to the encoding-side scheme provided in the embodiments of this application, such as determining the position of various bits of the corresponding encoding. The embodiments of this application do not limit the specific decoding method, as long as the codeword sequence obtained by the encoding method provided in the embodiments of this application can be used for decoding, such as sliding window decoding.

[0219] The method embodiments provided in this application have been described in detail above with reference to Figures 1 to 20. The device embodiments of this application will be described below with reference to Figures 21 to 23.

[0220] It is understood that, in order to achieve the functions in the above embodiments, the devices in Figures 21 to 23 include hardware structures and / or software modules corresponding to each function. These devices can be used to implement the functions of the encoding or decoding devices in the above method embodiments, and thus can also achieve the beneficial effects of the above method embodiments. Those skilled in the art should readily recognize that, based on the units and method steps of the various examples described in conjunction with the embodiments disclosed in this application, this application can be implemented in hardware or a combination of hardware and computer software.

[0221] Figure 21 is a schematic diagram of a device provided in an embodiment of this application.

[0222] This application embodiment can divide the encoding or decoding device into functional units according to the above method examples. For example, each function can be divided into different functional units, or two or more functions can be integrated into one unit. Each function can be implemented in hardware or as a software functional module. It should be noted that the division shown in Figure 21 is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods.

[0223] As shown in Figure 21, the device 10 includes a transceiver unit 11 and a processing unit 12.

[0224] When device 10 is used to implement the function of the encoding device in the above method embodiments, transceiver unit 11 is used to execute the transceiver steps of the encoding device, and processing unit 12 is used to execute the processing steps 901-904 of the encoding device. When device 10 is used to implement the function of the decoding device in the above method embodiments, transceiver unit 11 is used to execute the transceiver steps of the decoding device, and processing unit 12 is used to execute the processing steps of the decoding device.

[0225] Optionally, the device 10 also includes a storage unit 13 for storing instructions and / or data.

[0226] For a more detailed description of the transceiver unit 11 and the processing unit 12, please refer to the relevant descriptions in the above method embodiments, which will not be repeated here.

[0227] Figure 22 is another structural schematic diagram of the device provided in an embodiment of this application.

[0228] The device 20 includes a processing circuit 21. The processing circuit 21 is coupled to a memory 23, which stores instructions. When the device 20 is used to implement the method described above, the processing circuit 21 executes the instructions in the memory 23 to implement the function of the processing unit 12 described above.

[0229] Optionally, the device 20 further includes a memory 23 for implementing the functions of the aforementioned memory unit 13.

[0230] Optionally, the device 20 further includes a transceiver circuit 22. The transceiver circuit can be referred to as a communication interface. The processing circuit 21 and the transceiver circuit 22 are coupled to each other. It is understood that the transceiver circuit 22 can be a transceiver or an input / output interface. When the device 20 is used to implement the method described above, the processing circuit 21 executes instructions to implement the function of the processing unit 12, and the transceiver circuit 22 implements the function of the transceiver unit 11.

[0231] Optionally, device 20 can be an encoding device or a decoding device, and correspondingly, the transceiver circuit can be a transceiver.

[0232] Optionally, the device 20 can be a chip used in encoding or decoding equipment, and correspondingly, the transceiver circuit can be an input / output interface.

[0233] For example, when device 20 is a chip applied to an encoding or decoding device, the chip implements the functions of the encoding or decoding device in the above method embodiments. The chip receives information from other modules (such as radio frequency modules or antennas) in the encoding or decoding device, which is sent to the encoding or decoding device by other devices; or, the chip sends information to other modules (such as radio frequency modules or antennas) in the encoding or decoding device, which is sent to other devices by the encoding or decoding device.

[0234] Figure 23 is a schematic diagram of a chip system provided in an embodiment of this application. The chip system 30 (or may also be called a processing system) includes logic circuitry 31 and an input / output interface 32.

[0235] The logic circuit 31 can be a processing circuit in the chip system 30. The logic circuit 31 can be coupled to a memory unit, calling instructions from the memory unit, enabling the chip system 30 to implement the methods and functions of the embodiments of this application. The input / output interface 32 can be an input / output circuit in the chip system 30, outputting processed information from the chip system 30, or inputting data or signaling information to be processed into the chip system 30 for processing.

[0236] As an alternative, the chip system 30 may also include a memory unit.

[0237] As one approach, the chip system 30 is used to implement the operations performed by the encoding or decoding device in the various method embodiments described above.

[0238] For example, logic circuit 31 is used to implement processing-related operations performed by the encoding or decoding device in the above method embodiments; input / output interface 32 is used to implement sending and / or receiving-related operations performed by the encoding or decoding device in the above method embodiments.

[0239] This application also provides a communication device including a processing circuit coupled to a memory for storing computer programs or instructions and / or data. The processing circuit is used to execute the computer programs or instructions stored in the memory, or to read the data stored in the memory, to perform the methods in the above-described method embodiments. Optionally, the processing circuit may be one or more. Optionally, the communication device includes a memory. Optionally, the memory may be one or more. Optionally, the memory may be integrated with the processing circuit, or may be separately disposed.

[0240] This application also provides a chip including a processing circuit coupled to a memory. The memory is used to store computer programs or instructions, and the processing circuit is used to execute the computer programs or instructions stored in the memory to implement the methods executed by the encoding or decoding device in the above-described method embodiments. The memory may be located within the chip or independently of the chip, located outside the chip; this is not limited thereto.

[0241] This application also provides a computer-readable storage medium having stored thereon computer instructions for implementing the methods executed by an encoding device or a decoding device in the above-described method embodiments.

[0242] This application also provides a computer program product comprising instructions which, when executed by a computer, implement the methods performed by an encoding or decoding device in the above-described method embodiments.

[0243] This application also provides a computer program that, when executed by a computer, implements the methods performed by the encoding or decoding device in the above-described method embodiments.

[0244] This application also provides a communication system that includes at least one of the encoding or decoding devices described in the above embodiments.

[0245] The explanations and beneficial effects of the relevant contents in any of the devices provided above can be found in the corresponding method embodiments provided above, and will not be repeated here.

[0246] It is understood that the processing circuit in the embodiments of this application may be a processor or a circuit in a processor for performing processing operations. The processor may include one or more of the following: a central processing unit (CPU), a digital signal processor (DSP), a microprocessor unit (MPU), a microcontroller unit (MCU), a graphics processing unit (GPU), a field programmable gate array (FPGA), an artificial intelligence processor (AI processor), or a neural processing unit (NPU).

[0247] The aforementioned memory may include one or more of the following storage media: random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), phase-change memory (PCM), resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), cache, register, read-only memory (ROM), flash memory, erasable programmable read-only memory (EPROM), hard disk, etc. In one example, computer program instructions for executing the above embodiments may be stored in non-volatile memory, such as the aforementioned memory 23 or at least a portion of the storage cells (e.g., one or more of ROM, flash memory, EPROM, or hard disk).

[0248] The method steps in the embodiments of this application can be implemented in hardware or by a processor executing software instructions. The software instructions can consist of corresponding software modules, which can be stored in random access memory, flash memory, read-only memory, programmable read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, hard disks, portable hard disks, compact disc read-only memory (CD-ROM), or any other form of storage medium well known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and storage medium can reside in an application-specific integrated circuit (ASIC). Furthermore, the ASIC can reside in an encoding or decoding device. Alternatively, the processor and storage medium can exist as discrete components in the encoding or decoding device.

[0249] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of this application are performed entirely or partially. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user equipment, or other programmable device. The computer program or instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, the computer program or instructions can be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a digital video optical disc; or it can be a semiconductor medium, such as a solid-state drive.

[0250] In the various embodiments of this application, unless otherwise specified or in case of logical conflict, the terminology and / or descriptions of different embodiments are consistent and can be referenced by each other. The technical features of different embodiments can be combined to form new embodiments according to their inherent logical relationship.

[0251] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing specific embodiments only and is not intended to limit the scope of this application. It should be understood that the above are illustrative examples, and the examples above are merely to help those skilled in the art understand the embodiments of this application, and are not intended to limit the embodiments of the application to the specific numerical values ​​or specific scenarios exemplified. Those skilled in the art can obviously make various equivalent modifications or variations based on the examples given above, and such modifications and variations also fall within the scope of the embodiments of this application.

Claims

1. An information processing method, characterized in that, The method includes: Obtain the first information bit; Based on the first information bits, N first blocks are obtained, where N is an integer greater than 1; Based on the N first blocks, C second blocks are obtained, wherein each of the A second blocks among the C second blocks includes multiple first blocks, C is an integer less than N, and A is an integer less than or equal to C; Coupled coding is performed based on the C second blocks and the coupling coding matrix to obtain the C encoded code blocks.

2. The method according to claim 1, characterized in that, The process of obtaining C second blocks based on the N first blocks includes: Based on the overlap rate and the N first blocks, the C second blocks are obtained, wherein the overlap rate is the ratio of a first value and a second value, the first value is the number of identical first blocks in two adjacent second blocks, the second value is the total number of first blocks included in the first second block of the two second blocks, and the overlap rate is a rational number greater than or equal to 0 and less than 1.

3. The method according to claim 1 or 2, characterized in that, The process of obtaining the C encoded code blocks based on the C second blocks and the coupling coding matrix includes: Add cyclic redundancy check (CRC) bits to the C second blocks to obtain C third blocks; Divide the i-th third block among the C third blocks into s equal parts. i The fourth piece, s i It is a positive integer; Add a first padding bit to each of the fourth blocks to obtain a fifth block, the length of which is K. SCB,padded Satisfy: K SCB,padded =K sub ·Z, where each X column of the coupled coding matrix corresponds to a sub-matrix group, each sub-matrix group includes W sub-matrices, the W sub-matrices are of the same size and are non-zero matrices, and the row number of the first row of the first sub-matrix corresponding to each of the multiple sub-matrix groups is different, K sub X represents the number of information columns in column X, and Z is the boost value. Based on the coupling coding matrix, different fifth blocks are encoded to obtain C encoded code blocks.

4. The method according to claim 3, characterized in that, The first information bit includes a first null bit, the number of which is the same as the total number of CRC bits in the C second blocks; each of the C second blocks includes a second null bit, the number of which is the same as the number of CRC bits in the second block. The step of adding cyclic redundancy check (CRC) bits to the C second blocks to obtain C third blocks includes: calculating CRC bits for the i-th second block among the C second blocks, and replacing the second null bit of the i-th second block with the calculated CRC bits to obtain C third blocks.

5. The method according to claim 3 or 4, characterized in that, The method further includes: Each of the C code blocks is used as input for bit interleaving; or... The C code blocks are used as input bits for bit interleaving; or... Each encoded fifth block is used as input for bit interleaving.

6. The method according to any one of claims 3 to 5, characterized in that, The CRC bits in the i-th third block of the C third blocks are obtained based on the CRC bits in the i-th second block of the C second blocks and the (i-1)-th third block of the C third blocks, where i is an integer greater than 1; or, The CRC bits in the i-th third block of the C third blocks are obtained based on the i-th second block of the C second blocks, where i is an integer greater than 1.

7. The method according to any one of claims 3 to 6, characterized in that, The encoding of each different fifth block based on the coupled coding matrix includes: Based on x fifth blocks coupled to the j-th fifth block, the j-th fifth block, and the coupling coding matrix, the parity bits of the j-th fifth block are obtained, where x is less than or equal to m. c positive integers, m c =W-1, where j is a non-negative integer.

8. The method according to claim 7, characterized in that, The step of obtaining the check bits of the j-th fifth block based on x fifth blocks coupled to the j-th fifth block, the j-th fifth block, and the coupling coding matrix includes: The check bits of the j-th fifth block are obtained based on the x fifth blocks, the check bits of the x fifth blocks, the j-th fifth block, and the coupling coding matrix.

9. The method according to claim 7 or 8, characterized in that, The method further includes: The last y information bits and the last y parity bits of the fifth block are encoded according to the coupling coding matrix to obtain the parity bits as the tail code block, and the size of the tail code block is α1m. sub ×α1m sub α1 is a preset value, m sub Let y be the number of rows in the submatrix, and y be a positive integer.

10. The method according to any one of claims 3 to 9, characterized in that, The punch position of the i-th code block in the C code blocks is located in a fifth block that is different from the punch positions of the first i-1 code blocks in the C code blocks, where i is an integer greater than 1.

11. The method according to any one of claims 1 to 10, characterized in that, The process of obtaining N first blocks based on the first information bits includes: Add a second padding bit to the first information bit to obtain a second information bit; divide the second information bit evenly into the N first blocks; or... Add a second padding bit to the first information bit to obtain a second information bit; divide the second information bit evenly into N sixth blocks; add a cyclic redundancy check (CRC) bit to each sixth block to obtain the N first blocks.

12. The method according to claim 11, characterized in that, The length L of the second padding bit TB,padding Satisfy: L TB,padding = (C-1)c+sK TBCRC %[(C-1)c+s], where c is the number of first blocks that do not overlap in the second block, s is the number of first blocks included in the second block, and K TBCRC The length of the first information bit is denoted as .

13. The method according to claim 11 or 12, characterized in that, When the C second blocks do not overlap and N is not divisible by C, the method further includes, before adding the second padding bit to the first information bit: Add a third padding bit to the first information bit, wherein the number P of the third padding bits satisfies K TBCRC Let L be the length of the first information bits, c be the number of the first blocks that do not overlap in the second block, and L be the length of the first information bits. CBCRC The length of the CRC bits in the second block level is given. Each X column of the coupled coding matrix corresponds to a sub-matrix group. Each sub-matrix group includes W sub-matrices, which are all of the same size and non-zero. The row number of the first row of the first sub-matrix in each of the multiple sub-matrix groups is different. K sub Z represents the number of information columns in column X. max This is the maximum value for the boost.

14. The method according to any one of claims 1 to 13, characterized in that, When the C second blocks comprise the same number of the first blocks, C satisfies: When the C second blocks include different first blocks, C satisfies: Where s is the number of the first blocks included in the second block, s i Let K be the number of first blocks included in the i-th second block, c be the number of first blocks in the second block that do not overlap, and K be the number of first blocks in the second block that do not overlap. TBCRC For the length of the first information bit, each X column of the coupled coding matrix corresponds to a sub-matrix group, and each sub-matrix group includes W sub-matrices. The W sub-matrices are of the same size and are non-zero matrices. The row number of the first row of the first sub-matrix corresponding to each of the multiple sub-matrix groups is different, and K sub Z represents the number of information columns in column X. max To maximize the boost value, γ is the number of first blocks that overlap between two adjacent second blocks.

15. A communication device, characterized in that, Includes modules or units for performing the method as described in any one of claims 1 to 14.

16. A communication device, characterized in that, The device includes a processor and an interface circuit, wherein the interface circuit is used to receive signals from other communication devices besides the communication device and transmit them to the processor, or to send signals from the processor to other communication devices besides the communication device, and the processor is used to implement the method as described in any one of claims 1 to 14 through logic circuits or execution code instructions.

17. The communication device according to claim 16, characterized in that, The communication device is a terminal device, network device, chip, or chip system.

18. A computer-readable storage medium, characterized in that, The storage medium stores a computer program or instructions, which, when executed by a communication device, implement the method as described in any one of claims 1 to 14.

19. A computer program product, characterized in that, Includes a computer program that, when run, implements the method as described in any one of claims 1 to 14.

20. A communication system, characterized in that, include: An encoding device for performing the method as described in any one of claims 1 to 14, and a decoding device for decoding information from said encoding device.

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