Back-contact cell and photovoltaic module

Abstract

The present application relates to the technical field of photovoltaics. Disclosed are a back-contact cell and a photovoltaic module, which aim to improve the manufacturing efficiency of back-contact cells, increase the manufacturing capacity of the back-contact cells, and reduce the risk of the cells undergoing electric leakage. The back-contact cell comprises: a semiconductor substrate, a first doped silicon layer and a second doped silicon layer. The semiconductor substrate comprises a first surface and a second surface, which are opposite each other. The first surface has a first area and a second area distributed at an interval, and a spacing area located between the first area and the second area. The first doped silicon layer is disposed in the first area. The materials of the first doped silicon layer include polycrystalline silicon and / or monocrystalline silicon. The second doped silicon layer is disposed in the second area. The electrical conductivity type of the second doped silicon layer is the opposite of that of the first doped silicon layer. The extinction coefficient corresponding to the first doped silicon layer is greater than that corresponding to the second doped silicon layer.

Description

Back contact batteries and photovoltaic modules Technical Field

[0001] This application relates to the field of photovoltaic technology, and more particularly to a back contact battery and a photovoltaic module. Background Technology

[0002] A solar cell is a device that converts sunlight into electrical energy. A solar cell with both the positive and negative electrodes located on the back side is called a back-contact solar cell. Compared to bifacial contact solar cells, the front side of a back-contact solar cell is not obstructed by metal electrodes, resulting in higher light utilization on the light-facing side. Therefore, back-contact solar cells have higher short-circuit current and photoelectric conversion efficiency, making them one of the current technological directions for achieving high-efficiency crystalline silicon solar cells.

[0003] However, the existing back-contact battery manufacturing efficiency is low, which is not conducive to increasing the production capacity of back-contact batteries. Summary of the Invention

[0004] The purpose of this application is to provide a back-contact battery and a photovoltaic module to improve the manufacturing efficiency of the back-contact battery, increase the manufacturing capacity of the back-contact battery, and reduce the risk of battery leakage.

[0005] To achieve the above objectives, in a first aspect, this application provides a back contact battery, comprising: a semiconductor substrate, a first doped silicon layer, and a second doped silicon layer. The semiconductor substrate includes a first surface and a second surface opposite to each other. The first surface has a first region and a second region spaced apart, and a spacer region located between the first region and the second region. The first doped silicon layer is disposed on the first region. The material of the first doped silicon layer includes polycrystalline silicon and / or monocrystalline silicon. The second doped silicon layer is disposed on the second region. The conductivity type of the second doped silicon layer is opposite to that of the first doped silicon layer. The extinction coefficient corresponding to the first doped silicon layer is greater than the extinction coefficient corresponding to the second doped silicon layer.

[0006] In the back contact battery provided in this application, where the above technical solution is adopted, a first doped silicon layer is disposed on a first region of the first surface, and a second doped silicon layer is disposed on a second region of the first surface, with the first and second doped silicon layers having opposite conductivity types. Based on this, when the back contact battery is in operation, the electron-hole pairs generated after the semiconductor substrate absorbs photons are separated by the shunting effect of the first doped silicon layer in the first region and the second doped silicon layer in the second region. One of the electrons and holes is collected and discharged by the first doped silicon layer in the first region, and the other is collected and discharged by the second doped silicon layer in the second region, forming a photocurrent. Because the first and second regions have opposite doping types and different doping concentrations (e.g., the doping concentration of the first doped silicon layer is lower than that of the second doped silicon layer), different metal electrodes need to be selected to form an ohmic contact. This requires the first and second doped silicon layers to have different densities to avoid the metal electrodes burning through the first or second doped silicon layer during ohmic contact formation.

[0007] Compared to amorphous silicon, polycrystalline and monocrystalline silicon materials have several advantages. First, they possess higher conductivity and crystallinity. Therefore, when the first doped silicon layer comprises polycrystalline and / or monocrystalline silicon, its conductivity and field passivation effect are improved, thus enhancing the conversion efficiency of the back contact battery. Second, when the first doped silicon layer comprises polycrystalline and / or monocrystalline silicon, the process temperature for manufacturing the first doped silicon layer is relatively high. After doping the intrinsic silicon layer using diffusion or other doping processes, a doped silicon glass layer is easily formed on the first doped silicon layer. Based on this, after patterning, this doped silicon glass layer can serve as a mask layer for selective etching of the entire first doped silicon layer, providing protection. Furthermore, it eliminates the need for additional deposition to form other mask layers, further improving the manufacturing efficiency of the back contact battery. In the above process, since the extinction coefficient of the first doped silicon layer is greater than that of the second doped silicon layer, the density of the first doped silicon layer is relatively higher than that of the second doped silicon layer. Consequently, the etching of the portion of the first doped silicon layer located in the second region is more difficult. Furthermore, the density of the doped silicon glass layer formed by oxidizing the first doped silicon layer is also relatively high. Therefore, before selective etching, it is usually necessary to selectively treat the relatively dense doped silicon glass layer using processes such as laser engraving. It is necessary to completely remove the portion of the doped silicon glass layer corresponding to the second region. This facilitates the complete removal of the portion of the first doped silicon layer corresponding to the second region under the protection of the untreated portion of the doped silicon glass layer, while retaining the portion of the first doped silicon layer corresponding to the first region. This prevents the portion of the highly dense first doped silicon layer located in the second region from being incompletely removed due to the influence of the doped silicon glass layer residue, thus reducing the risk of leakage.

[0008] As one possible implementation, the area of ​​the first region on the first surface is greater than or equal to 35% and less than or equal to 60%. As mentioned above, the extent of the first region on the first surface determines the formation range of the first doped silicon layer, thus affecting the range of selective processing of the entire first doped silicon layer and the entire doped silicon glass layer. Therefore, when the area of ​​the first region on which the first doped silicon layer is disposed is greater than or equal to 35% and less than or equal to 60% on the first surface, the area of ​​the first doped silicon layer on the first surface in the back contact battery is also relatively large. Correspondingly, when selectively processing the entire doped silicon glass layer using processes such as laser engraving, and selectively etching the first doped silicon layer using processes such as wet etching, only the doped silicon glass layer and the first doped silicon layer on the smaller areas of the first surface other than the first region need to be removed. This shortens the processing time for the denser doped silicon glass layer and the first doped silicon layer, improves the manufacturing efficiency of the back contact battery, reduces production costs, increases the manufacturing capacity of the back contact battery, and simultaneously reduces the leakage risk in the second region. Furthermore, since the extinction coefficient of the second doped silicon layer is smaller and its density is relatively smaller compared to the first doped silicon layer, even if the area of ​​the second region on which the second doped silicon layer is disposed is relatively small in the first surface, resulting in a large etching amount when selectively etching the entire second doped silicon layer, the high manufacturing efficiency of the back contact battery can be ensured because the etching difficulty of the second doped silicon layer is relatively low.

[0009] Furthermore, if the area ratio of the first region on the first surface meets the above-mentioned range, it can also improve the manufacturing capacity of the back contact battery while controlling the area ratio of the first doped silicon layer and the second doped silicon layer on the first surface, thereby regulating the area ratio of the PN junction region, achieving effective diversion of charge carriers, so that the manufacturing capacity of the back contact battery and the effective collection of charge carriers can be balanced, which is conducive to cost reduction and efficiency improvement.

[0010] As one possible implementation, the second region occupies an area of ​​20% or more and 35% or less on the first surface, and / or the spacer region occupies an area of ​​10% or more and 20% or less on the first surface. In this case, since the second region has relatively lower density, in order to increase the area of ​​the spacer region and improve the bifaciality of the module, the area of ​​the second region can be appropriately reduced without affecting the patterning capacity. However, the area of ​​the second region cannot be too low, and the field passivation effect of the second region must also be taken into account. The first region, the second region, and the spacer region are all located on the first surface. When the area proportions of the second region and the spacer region are within the above range, it can be ensured that the first region has a large proportion on the first surface, shortening the processing time for the denser doped silicon glass layer and the first doped silicon layer, while reducing the risk of leakage. Furthermore, the area proportion of the PN region can be adjusted to achieve effective shunting of charge carriers, further reducing the risk of leakage.

[0011] As one possible implementation, the first doped silicon layer includes a P-type doped polycrystalline silicon layer, wherein the extinction coefficient of the P-type doped polycrystalline silicon layer is greater than or equal to 0.01 and less than or equal to 1.5.

[0012] When the above technical solution is adopted, if the first doped silicon layer includes a P-type doped silicon layer, after the formation of the first doped silicon layer, a doped silicon glass layer formed on the side of the first doped silicon layer away from the semiconductor substrate is doped with P-type impurities such as boron. Because P-type impurities such as boron have lower electron affinity than N-type impurities such as phosphorus, they are less likely to accept electrons. Furthermore, the doped silicon glass layer and the first doped silicon layer, both doped with P-type impurities such as boron, are less likely to react with alkaline wet etching solutions, making etching more difficult. Therefore, when the first doped silicon layer includes a P-type doped polycrystalline silicon layer, the back contact battery provided in this application can further shorten the processing time for the P-type doped polycrystalline silicon layer and the borosilicate glass layer by increasing the area ratio of the P-type doped polycrystalline silicon layer on the first surface, thereby improving the manufacturing efficiency of the back contact battery, reducing production costs, and increasing the manufacturing capacity of the back contact battery. Furthermore, having an extinction coefficient within the aforementioned range for the P-type doped polysilicon layer prevents problems such as electrode burn-through due to excessively low density caused by an excessively low extinction coefficient, ensuring good performance of the back contact cell. Conversely, an excessively high extinction coefficient prevents the high density of the P-type doped polysilicon layer and the doped silicon glass layer, which would increase the difficulty of selective etching, further shortening the processing time for the doped silicon glass layer and the first doped silicon layer, improving manufacturing efficiency, reducing production costs, and increasing production capacity. Moreover, since the extinction coefficient of the P-type doped polysilicon layer is also related to its doping concentration, a coefficient within the aforementioned range allows for a higher doping concentration, which is beneficial for improving the field passivation effect of the P-type doped polysilicon layer and reducing the contact resistance between the P-type doped polysilicon layer and the corresponding conductive material.

[0013] As one possible implementation, the second doped silicon layer includes an N-type doped polycrystalline silicon layer, wherein the extinction coefficient of the N-type doped polycrystalline silicon layer is greater than or equal to 0.01 and less than or equal to 1.5.

[0014] When using the above technical solution, compared with the P-type doped polycrystalline silicon layer, the extinction coefficient and density of the N-type doped polycrystalline silicon layer are relatively small. When the second doped silicon layer includes the N-type doped polycrystalline silicon layer, even though the area of ​​the second region with the N-type doped polycrystalline silicon layer on it in the first surface is relatively small, resulting in a larger etching amount when selectively etching the entire N-type doped polycrystalline silicon layer and the phosphosilicate glass layer, the etching difficulty of the N-type doped polycrystalline silicon layer and the phosphosilicate glass layer is relatively low, thus ensuring a high manufacturing efficiency of the back contact cell. The application principle of the beneficial effect of the extinction coefficient of the N-type doped polycrystalline silicon layer being greater than or equal to 0.01 and less than or equal to 1.5 is similar to that of the P-type doped polycrystalline silicon layer, and will not be elaborated here.

[0015] As one possible implementation, the crystallinity of the second doped silicon layer is greater than that of the first doped silicon layer.

[0016] When employing the above technical solution, the density of the doped silicon layer is related to its crystallinity. Specifically, within a certain range, increasing the crystallinity of the doped silicon layer improves its density; conversely, decreasing the crystallinity reduces its density. In this case, when the crystallinity of the second doped silicon layer is greater than that of the first doped silicon layer, the density of both layers can be controlled by adjusting their crystallinity. This, in turn, controls the density of the doped silicon glass layer formed by oxidizing a portion of the first doped silicon layer, reducing the selective etching difficulty of both layers, further shortening the processing time, improving the manufacturing efficiency of the back contact battery, reducing production costs, and increasing the manufacturing capacity of the back contact battery.

[0017] As one possible implementation, the sum of the areas of the first region of the first number and the interval region of the second number is S1, the sum of the areas of the second region of the first number and the interval region of the second number is S2, the ratio between S1 and S2 is greater than or equal to 1 and less than or equal to 2, the first number is equal to the second number, or the first number is not equal to the second number.

[0018] When the above technical solution is adopted, the ratio of the areas of S1 and S2 is within the aforementioned range. This helps prevent the area of ​​the second doped silicon layer disposed on the first surface from being too large due to a small ratio, ensuring that the PN junction has a large junction area, which is beneficial for effective carrier separation. Additionally, it also prevents the area of ​​the first doped silicon layer disposed on the first surface from being too large due to a large ratio, preventing excessively long lateral carrier transport distances and ensuring that the second doped silicon layer has high carrier collection efficiency. Furthermore, the magnitude of this ratio also affects the area proportion of the denser first doped silicon layer and the relatively looser second doped silicon layer on the first surface, thus affecting the etching capacity for selective etching of the first and second doped silicon layers. Reducing the difference in etching capacity between the two selective etching processes eliminates the capacity bottleneck. Therefore, when this ratio is within the aforementioned range, it also helps to ensure that the back contact battery has both high conversion efficiency and manufacturing capacity, which is beneficial for cost reduction and efficiency improvement.

[0019] As one possible implementation, the sum of the widths of the first region of the third number and the interval regions of the fourth number is W1, and the sum of the widths of the second region of the third number and the interval regions of the fourth number is W2. The ratio between W1 and W2 is greater than or equal to 1 and less than or equal to 2. The third number is equal to the fourth number, or the third number is not equal to the fourth number. The application principle of the beneficial effect in this case is similar to the application principle of the beneficial effect described above where the ratio between S1 and S2 is greater than or equal to 1 and less than or equal to 2, and will not be repeated here.

[0020] As one possible implementation, the sum of the widths of a first region and a spacing region is W3, and the sum of the widths of a second region and a spacing region is W4. The ratio between W3 and W4 is greater than the ratio between S1 and S2. In this case, compared to the ratio between W3 and W4 being equal to the ratio between S1 and S2, when the ratio between W3 and W4 is greater than the ratio between S1 and S2, the ratio between W3 and W4 is relatively large, and / or the ratio between S1 and S2 is relatively small. This ensures that the first doped silicon layer has a high area ratio on the first surface, further shortening the processing time for the denser doped silicon glass layer and the first doped silicon layer, improving the manufacturing efficiency of the back contact cell, reducing production costs, and increasing the manufacturing capacity of the back contact cell.

[0021] As one possible implementation, the aspect ratio of the first doped silicon layer located in the first region is greater than that of the second doped silicon layer located in the second region, and the spacing between two adjacent first regions or between two adjacent second regions is greater than 1 mm. In this case, it is advantageous to increase the width of the first doped silicon layer located in the first region, increase the area ratio of the first doped silicon layer on the first surface, further shorten the processing time for the denser doped silicon glass layer and the first doped silicon layer, improve the manufacturing efficiency of the back contact battery, reduce production costs, and increase the manufacturing capacity of the back contact battery. Simultaneously, if the first doped silicon layer is located at the emitter of the battery, it can also increase the PN junction area, which is beneficial for achieving effective carrier separation, reducing the carrier recombination rate, and improving the conversion efficiency of the back contact battery.

[0022] As one possible implementation, the aspect ratio of the second doped silicon layer located in the second region is greater than that of the first doped silicon layer located in the first region, and the spacing between two adjacent first regions or between two adjacent second regions is less than or equal to 1 mm. In this case, it is advantageous to increase the width of the second doped silicon layer located in the second region, increase the area ratio of the second doped silicon layer on the first surface, further shorten the processing time for the less dense doped silicon glass layer and the second doped silicon layer, improve the manufacturing efficiency of the back contact battery, reduce production costs, and increase the manufacturing capacity of the back contact battery. Simultaneously, if the second doped silicon layer serves as the field region of the battery, its passivation effect is better than that of the first doped silicon layer, improving the carrier separation capability of the field region, reducing the carrier recombination rate, and improving the conversion efficiency of the back contact battery.

[0023] As one possible implementation, the aforementioned back-contact battery further includes a plurality of first current collectors disposed on a first doped silicon layer, each first current collector being in ohmic contact with the first doped silicon layer. The plurality of first current collectors extend along a first direction and are spaced apart along a second direction, the first direction being different from the second direction. A second doped silicon layer is also disposed above a portion of the first doped silicon layer located in a first region, and the second doped silicon layer located in the first region is spaced apart from both the first doped silicon layer and the first current collectors.

[0024] In the above-mentioned technical solution, during the actual manufacturing process, the second doped silicon layer is selectively etched onto the entire layer, ensuring that the second doped silicon layer in the back contact battery is only located in a localized area of ​​the first surface. Before selective etching, a mask material formed on the side of the second doped silicon layer away from the semiconductor substrate needs to be selectively processed using processes such as laser engraving. This allows the untreated portion of the mask material to form a mask layer that protects the second doped silicon layer. Therefore, the formation range of the second doped silicon layer determines the range of mask material that needs to be processed. Based on this, when the second doped silicon layer is not only located in the second region but also above a portion of the first doped silicon layer in the first region, it is unnecessary to engrave the portion of the second doped silicon layer above the first doped silicon layer. This shortens the processing time for the mask material and the second doped silicon layer, further improving the manufacturing efficiency of the back contact battery, reducing production costs, and increasing the manufacturing capacity of the back contact battery. Simultaneously, the second doped silicon layer in the first region is spaced apart from the first doped silicon layer and the first current collector electrode, preventing short circuits, reducing leakage risk, and ensuring high electrical reliability of the back contact battery.

[0025] As one possible implementation, the aforementioned back-contact battery further includes a plurality of second current collectors disposed on a second doped silicon layer, each second current collector in ohmic contact with the second doped silicon layer. The plurality of second current collectors extend along a first direction, and the second current collectors and first current collectors are alternately distributed along a second direction. At least a portion of the plurality of second current collectors are discontinuous second current collectors. The second doped silicon layer located in the first region is disposed at the break in the discontinuous second current collector. At least a portion of the plurality of first current collectors are discontinuous first current collectors, and the second doped silicon layer located in the first region is symmetrically arranged with respect to the centerline of the current collector segment included in the discontinuous first current collector in the second direction.

[0026] When the above technical solution is adopted, the first and second collector electrodes are used to collect and extract charge carriers of the corresponding conductivity type within the first and second doped silicon layers, respectively. The formation range of the two electrodes is proportional to their respective charge carrier collection capabilities. Furthermore, the in-string interconnects such as solder ribbons extend generally along the second direction and are electrically connected to the first collector electrode, and are electrically insulated from the discontinuous second collector electrode of opposite polarity through the break point of the discontinuous second collector electrode. Simultaneously, the in-string interconnects such as solder ribbons are electrically connected to the first doped silicon layer through the first collector electrode, but do not directly contact the first doped silicon layer. Therefore, when the second doped silicon layer located in the first region is positioned at the break point of the discontinuous second collector electrode, not only can the processing time for the mask material and the second doped silicon layer be shortened by retaining the portion of the second doped silicon layer above the first doped silicon layer, thus improving the manufacturing capacity of the back contact battery, but the formation range of the first collector electrode for collecting and extracting charge carriers of the corresponding conductivity type within the first doped silicon layer will not be affected, ensuring that the first collector electrode has a high charge carrier collection capability and reducing the charge carrier recombination rate. In addition, the second doped silicon layer located in the first region is symmetrically arranged with respect to the collector electrode segment included in the discontinuous first collector electrode along the centerline in the second direction. At this time, the leakage distance between the two ends of the second doped silicon layer in the first region and the edge of the first doped silicon layer, and the edge of the second doped silicon layer in the second region, is approximately the same. This prevents the leakage risk on one side from being higher due to the positional shift of the second doped silicon layer in the first region at the break point, and ensures that the back contact battery has a high conversion efficiency.

[0027] As one possible implementation, along the second direction, the first surface includes a central region and edge regions located on both sides of the central region. The first and second collector electrodes located in the central region are respectively continuous first and second collector electrodes, while the first and second collector electrodes located in the edge regions are respectively discontinuous first or discontinuous second collector electrodes. Furthermore, the aforementioned back contact battery also includes a first interconnect structure and a first bus electrode segment. The first bus electrode segment is disposed on the edge region and extends along the second direction. The discontinuous first collector electrode is electrically connected to the first bus electrode segment, and the discontinuous second collector electrode is disconnected near the first bus electrode segment. The first interconnect structure is disposed at one end of the first bus electrode segment near the central region and is electrically connected to the first bus electrode segment. The second doped silicon layer located in the first region includes a first sub-doped portion and a second sub-doped portion. The first sub-doped portion is disposed below the first bus electrode segment, and the second sub-doped portion is disposed at least below the first interconnect structure. Along the first direction, the width of the second sub-doped portion is greater than the width of the first sub-doped portion.

[0028] As one possible implementation, along the first direction, the width of the first sub-doped portion is greater than or equal to 0.3 times the width of the portion of the first doped silicon layer located below the first sub-doped portion and less than the width of the portion of the first doped silicon layer located below the first sub-doped portion; and / or, along the first direction, the width of the second sub-doped portion is greater than the width of the first interconnect structure and less than or equal to 0.95 times the width of the portion of the first doped silicon layer located below the second sub-doped portion.

[0029] When the above technical solution is adopted, along the first direction, when the width of the second sub-doped portion and / or the first sub-doped portion is within the above range, the width extension range of the first sub-doped portion and / or the second sub-doped portion at the corresponding break is larger, which is beneficial to further shorten the processing time of the mask material and the second doped silicon layer, further improve the manufacturing efficiency of the back contact battery, reduce the production cost, and increase the manufacturing capacity of the back contact battery.

[0030] As one possible implementation, the second sub-doped portion is further disposed below the side of the first bus electrode segment near the first interconnect structure, and / or, along the direction away from the first interconnect structure of the first bus electrode segment, the width of the second sub-doped portion and the width of the first sub-doped portion gradually decrease. In this case, it is understood that, along the first direction, the width of the first interconnect structure is larger than the width of the first bus electrode segment. To reduce the risk of leakage, the break distance of the discontinuous second collector electrode where the extension line intersects the first bus electrode segment and is close to the first interconnect structure is greater than the break distance of the discontinuous second collector electrode where the extension line intersects the first bus electrode segment and is away from the first interconnect structure. Based on this, when the wider second sub-doped portion is also located below the side of the first busbar electrode segment near the first interconnect structure, or along the direction away from the first interconnect structure of the first busbar electrode segment, and the width of the second sub-doped portion and the width of the first sub-doped portion gradually decrease, the wider disconnection gap can be further utilized to further increase the setting range of the second doped silicon layer in the first region while preventing leakage, thereby shortening the processing time for the denser doped silicon glass layer and the first doped silicon layer and improving the manufacturing efficiency of the back contact cell.

[0031] As one possible implementation, the back contact battery further includes an interconnect electrically connected to the first interconnect structure, wherein along the first direction, the width of the first sub-doped portion is greater than the width of the interconnect and less than or equal to the width of the portion of the first doped silicon layer located below the first sub-doped portion. Multiples; and / or, along the first direction, the width of the second sub-doped portion is greater than the width of the first interconnect structure and less than or equal to the width of the portion of the first doped silicon layer located below the second sub-doped portion. In this case, selecting the width of the first sub-doped portion and / or the second sub-doped portion within the aforementioned corresponding range not only maximizes the utilization of the dead space at the disconnection position of the current collector electrode, thus significantly improving the manufacturing capacity of the back contact battery, but also avoids the risk of leakage caused by the interconnection of dissimilar doped regions due to excessively wide widths of the first sub-doped portion and / or the second sub-doped portion, thereby improving the electrical reliability of the back contact battery.

[0032] As one possible implementation, along the second direction, the ratio of the total length of all second sub-doped portions to the total length of all first sub-doped portions is greater than or equal to 2:1 and less than or equal to 5:1. In this case, the length extension range of the first and second sub-doped portions at the corresponding break points is relatively large, which is beneficial to further shorten the processing time of the mask material and the second doped silicon layer, further improve the manufacturing efficiency of the back contact cell, reduce production costs, and increase the manufacturing capacity of the back contact cell. In addition, it can also prevent the spacing between the first and second sub-doped portions and the first current collector electrode from being too small due to excessive length, reduce the risk of leakage, and improve the electrical reliability of the back contact cell.

[0033] Secondly, this application provides a photovoltaic module including a back contact cell provided in the first aspect and various implementations thereof.

[0034] The beneficial effects of the second aspect and its various implementations in this application can be found in the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here. Attached Figure Description

[0035] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0036] Figure 1 is a longitudinal sectional view of the structure of the back contact battery provided in an embodiment of this application.

[0037] Figure 2 is a longitudinal sectional view of the back contact battery provided in an embodiment of this application.

[0038] Figure 3 is a longitudinal sectional view of the structure of the back contact battery provided in an embodiment of this application.

[0039] Figure 4 is a longitudinal sectional view of the back contact battery provided in an embodiment of this application.

[0040] Figure 5 is a longitudinal sectional view of the back contact battery provided in an embodiment of this application.

[0041] Figure 6 is a longitudinal sectional view of the back contact battery provided in an embodiment of this application.

[0042] Figure 7 is a schematic diagram of the structural distribution of the back contact battery on the first side according to an embodiment of this application;

[0043] Figure 8 is a schematic diagram of the structural distribution of the back contact battery on the first side according to an embodiment of this application.

[0044] Reference numerals: 11 is a semiconductor substrate, 12 is a first region, 13 is a second region, 14 is a spacer region, 15 is a first doped silicon layer, 16 is a second doped silicon layer, 17 is a first collector electrode, 18 is a second collector electrode, 19 is a first interconnect structure, 20 is a first bus electrode segment, 21 is a first sub-doped portion, 22 is a second sub-doped portion, 23 is an insulating layer, 24 is a first interface passivation layer, and 25 is a second interface passivation layer. Detailed Implementation

[0045] The embodiments of this application will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of this application. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of this application.

[0046] The accompanying drawings show various structural schematic diagrams according to embodiments of this application. These drawings are not drawn to scale, and some details have been enlarged and may have been omitted for clarity. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0047] In the context of this application, when a layer / element is referred to as being "on top of" another layer / element, the layer / element can be directly on top of the other layer / element, or there can be an intermediate layer / element between them. Furthermore, if a layer / element is "on top of" another layer / element in one orientation, then when the orientation is reversed, the layer / element can be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0048] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise expressly specified. "Several" means one or more, unless otherwise expressly specified.

[0049] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0050] A solar cell is a device that converts sunlight into electrical energy. A solar cell with both the positive and negative electrodes located on the back side is called a back-contact solar cell. Compared to bifacial contact solar cells, the front side of a back-contact solar cell is not obstructed by metal electrodes, resulting in higher light utilization on the light-facing side. Therefore, back-contact solar cells have higher short-circuit current and photoelectric conversion efficiency, making them one of the current technological directions for achieving high-efficiency crystalline silicon solar cells.

[0051] Existing back-contact solar cells typically include a semiconductor substrate, a first doped silicon layer, and a second doped silicon layer. The semiconductor substrate has a first side and a second side facing each other. The first and second doped silicon layers are alternately distributed on the first side of the semiconductor substrate. Furthermore, the first and second doped silicon layers have opposite conductivity types to collect and export electrons and holes, respectively, which is beneficial for forming photocurrent. The material of the first doped silicon layer includes polycrystalline silicon and / or monocrystalline silicon to improve the conductivity and field passivation effect of the first doped silicon layer, which is beneficial for improving the conversion efficiency of the back-contact solar cell. However, the manufacturing efficiency of existing back-contact solar cells is relatively low, which is not conducive to increasing the production capacity of back-contact solar cells.

[0052] Specifically, in the actual manufacturing process, during the formation of the first doped silicon layer on a portion of the first surface of the semiconductor substrate, a complete intrinsic silicon layer is first formed, and then the intrinsic silicon layer is doped through processes such as diffusion to form the first doped silicon layer. Simultaneously, a doped silicon glass layer is formed on the side of the first doped silicon layer facing away from the semiconductor substrate. Then, at least a portion of the first doped silicon layer corresponding to the area where the second doped silicon layer is to be formed needs to be completely removed. In existing manufacturing methods, this selective etching is typically achieved using a mask combined with wet etching, or a laser engraving combined with wet etching. In the mask combined with wet etching method, a mask resist is printed in the area requiring protection. During wet etching, the area under the mask resist is protected and preserved, while the area without mask resist is etched by a chemical solution. In the laser engraving combined with wet etching method, a laser is used to engrave the doped silicon glass layer formed on the first doped silicon layer according to a pattern. After wet etching, the area of ​​the first doped silicon layer corresponding to the laser-etched area will be etched by the chemical solution. The area of ​​the doped silicon glass layer that is not laser-etched has high density and can protect the first doped silicon layer located below it from the chemical solution, thus forming the first doped silicon layer disposed on a local area on the back of the battery.

[0053] Specifically, compared to laser engraving combined with wet etching, mask combined with wet etching offers higher manufacturing efficiency. However, this method is currently limited by factors such as the composition of the mask adhesive and the stability of screen printing, preventing large-scale mass production. In the aforementioned laser engraving combined with wet etching method, laser engraving benefits from the stability of the laser, making it a viable mass-production solution. However, when the density of the first doped silicon layer is high, the density of the doped silicon glass layer formed on top of it is also relatively high. This requires the laser to completely dissolve the doped silicon glass layer on the portion of the first doped silicon layer to be removed, facilitating the subsequent wet etching process to completely remove the exposed first doped silicon layer. Furthermore, the lasers used to obtain the lasers for back contact batteries are expensive, and the laser engraving patterns used in manufacturing back contact batteries are complex, resulting in long engraving times per cell. This leads to lower manufacturing efficiency and increased production costs for back contact batteries, hindering efforts to improve their production capacity.

[0054] To address the aforementioned technical problems, in a first aspect, embodiments of this application provide a back-contact battery. As shown in FIG1, the back-contact battery includes: a semiconductor substrate 11, a first doped silicon layer 15, and a second doped silicon layer 16. The semiconductor substrate 11 includes a first surface and a second surface opposite to each other. The first surface has a first region 12 and a second region 13 spaced apart, and a spacer region 14 located between the first region 12 and the second region 13. The first doped silicon layer 15 is disposed on the first region 12. The material of the first doped silicon layer 15 includes polycrystalline silicon and / or monocrystalline silicon. The second doped silicon layer 16 is disposed on the second region 13. The conductivity type of the second doped silicon layer 16 is opposite to that of the first doped silicon layer 15. The extinction coefficient corresponding to the first doped silicon layer 15 is greater than the extinction coefficient corresponding to the second doped silicon layer 16.

[0055] It should be noted that in practical applications, the extinction coefficient k of the first and second doped silicon layers can be obtained by measuring with instruments such as an ellipsometer. During the testing of the extinction coefficient k of the first and second doped silicon layers, other films (such as doped silicon glass layers and / or surface passivation layers) located on the side of the first doped silicon layer facing away from the semiconductor substrate and on the side of the second doped silicon layer facing away from the semiconductor substrate need to be removed. Furthermore, the measurements must be performed under the same test conditions, especially for different films for which data comparison is required, to improve the accuracy of the measurement and comparison results. Specific test conditions can be: a test wavelength range of 220nm to 1000nm; for example, the test wavelength corresponding to the data range of the extinction coefficients of the first and second doped silicon layers is 632nm. The test location can be the position where the first and second doped silicon layers are connected by interconnect structures (such as solder joints).

[0056] As shown in FIG1, in the back contact battery provided in the embodiment of this application, a first doped silicon layer 15 is disposed on a first region 12 on the first surface, and a second doped silicon layer 16 is disposed on a second region 13 on the first surface. The conductivity types of the first doped silicon layer 15 and the second doped silicon layer 16 are opposite. Based on this, when the back contact battery is in operation, the electron and hole pairs generated by the semiconductor substrate 11 after absorbing photons are separated by the shunting effect of the first doped silicon layer 15 on the first region 12 and the second doped silicon layer 16 on the second region 13. One of the electrons and holes is collected and discharged by the first doped silicon layer 15 on the first region 12, and the other of the electrons and holes is collected and discharged by the second doped silicon layer 16 on the second region 13, forming a photocurrent. Since the first and second regions have opposite doping types and different doping concentrations, for example, the doping concentration of the first doped silicon layer is less than that of the second doped silicon layer, different metal electrodes need to be selected to form ohmic contacts. This requires the first and second doped silicon layers to match different densities in order to avoid the metal electrodes burning through the first or second doped silicon layer when forming ohmic contacts.

[0057] Furthermore, compared to amorphous silicon, polycrystalline and monocrystalline silicon materials have higher conductivity and higher crystallinity. Therefore, when the material of the first doped silicon layer 15 includes polycrystalline silicon and / or monocrystalline silicon, the conductivity and field passivation effect of the first doped silicon layer 15 can be improved, which is beneficial to improving the conversion efficiency of the back contact battery. Secondly, when the material of the first doped silicon layer 15 includes polycrystalline silicon and / or monocrystalline silicon, the process temperature corresponding to the first doped silicon layer 15 is relatively high during the actual manufacturing process. After the intrinsic silicon layer of the first doped silicon layer 15 is doped using diffusion and other doping processes, a doped silicon glass layer is easily formed on the first doped silicon layer 15. Based on this, after patterning, the doped silicon glass layer can be used as a mask layer in the subsequent selective etching process of the entire first doped silicon layer 15, playing a protective role; and there is no need to use additional deposition to form other mask layers, which is beneficial to improving the manufacturing efficiency of the back contact battery. In the above process, because the extinction coefficient of the first doped silicon layer 15 is greater than that of the second doped silicon layer 16, the density of the first doped silicon layer 15 is relatively higher than that of the second doped silicon layer 16. Consequently, etching the portion of the first doped silicon layer 15 located at least in the second region 13 is more difficult. Furthermore, the density of the doped silicon glass layer formed by oxidizing the first doped silicon layer 15 is also relatively high. Therefore, before selective etching, it is usually necessary to selectively process the relatively dense doped silicon glass layer using processes such as laser engraving. It is necessary to completely remove at least the portion of the doped silicon glass layer corresponding to the second region 13. This facilitates the subsequent removal of the portion of the first doped silicon layer 15 corresponding to at least the second region 13, while retaining the portion of the first doped silicon layer 15 corresponding to at least the first region 12. This prevents the portion of the highly dense first doped silicon layer 15 located in the second region 13 from being incompletely removed due to the presence of residual doped silicon glass layer material, thus reducing the risk of leakage. Furthermore, as described above, the extent of the first region 12 on the first surface determines the formation range of the first doped silicon layer 15, thereby affecting the range of selective processing of the entire first doped silicon layer 15 and the entire doped silicon glass layer.Based on this, when the area of ​​the first region 12 on which the first doped silicon layer 15 is disposed is greater than or equal to 35% and less than or equal to 60% in the first surface, for example, when its area in the first surface is greater than or equal to 50% and less than or equal to 60%, the area of ​​the first doped silicon layer 15 in the back contact battery is also relatively large. Correspondingly, when selectively processing the entire layer of doped silicon glass layer by laser engraving and selectively etching the first doped silicon layer 15 by wet etching and other processes, it is only necessary to remove the doped silicon glass layer and the first doped silicon layer 15 in the smaller areas of the first surface other than the first region 12. This can shorten the processing time for the denser doped silicon glass layer and the first doped silicon layer 15, improve the manufacturing efficiency of the back contact battery, reduce production costs, increase the manufacturing capacity of the back contact battery, and at the same time reduce the leakage risk of the second region 13. Furthermore, because the extinction coefficient of the second doped silicon layer 16 is smaller and its density is relatively lower than that of the first doped silicon layer 15, even though the area of ​​the second region 13 on which the second doped silicon layer 16 is disposed is relatively small, resulting in a larger etching amount when selectively etching the entire second doped silicon layer 16, the etching difficulty of the second doped silicon layer 16 is relatively low, thus ensuring a high manufacturing efficiency of the back contact cell. In addition, the area ratio of the first region 12 on the first surface meets the above-mentioned range, which can improve the manufacturing capacity of the back contact cell while controlling the area ratio of the first doped silicon layer 15 and the second doped silicon layer 16 on the first surface, thereby controlling the area ratio of the PN junction region, achieving effective shunting of charge carriers, and balancing the manufacturing capacity of the back contact cell with the effective collection of charge carriers, which is conducive to cost reduction and efficiency improvement.

[0058] In practical applications, the embodiments of this application do not specifically limit the material of the semiconductor substrate. The semiconductor substrate can be any semiconductor material such as silicon substrate, germanium silicon substrate, germanium substrate or gallium arsenide substrate.

[0059] It is understood that the first surface of the semiconductor substrate corresponds to the back side of the back contact battery, and the second surface of the semiconductor substrate corresponds to the front side of the back contact battery. Furthermore, the specific locations of the aforementioned first region, second region, and spacing region on the first surface can be determined based on the distribution of the first doped silicon layer and the second doped silicon layer included in the back contact battery on the first surface, and are not specifically limited here.

[0060] For example, as shown in FIG1, a first doped silicon layer 15 may be disposed on a first region 12, and a second doped silicon layer 16 may be disposed on a second region 13, with the first doped silicon layer 15 and the second doped silicon layer 16 separated by a spacer region 14. In this case, one of the first region 12 and the second region 13 in the first surface corresponds to an N-region, and the other corresponds to a P-region, with the spacer region 14 being the region located between the N-region and the P-region in the first surface. Optionally, both the first doped silicon layer 15 and the second doped silicon layer 16 may include a doped polycrystalline silicon layer, such as a tunnel oxide passivated contact back contact cell (i.e., a TBC cell).

[0061] For example, as shown in FIG2, a first doped silicon layer 15 may be disposed on a first region 12 and a spacer region 14. A second doped silicon layer 16 is disposed on a second region 13 and extends over the first doped silicon layer 15 located in the spacer region 14. In this case, the back contact cell may also include an insulating layer 23 located between the first doped silicon layer 15 and the second doped silicon layer 16 to reduce the risk of leakage between the first doped silicon layer 15 and the second doped silicon layer 16. In this case, one of the first region 12 and the second region 13 in the first surface corresponds to the N-region and the other corresponds to the P-region, and the spacer region 14 is the overlapping region in the first surface located between the N-region and the P-region. The material of the insulating layer 23 may include any non-conductive material such as silicon oxide, silicon nitride, aluminum oxide, and intrinsic silicon. Optionally, the first doped silicon layer 15 includes a doped polycrystalline silicon layer, and the second doped silicon layer 16 includes a doped amorphous silicon layer, for example, a hybrid back contact cell combining a tunnel oxide passivation contact structure and a heterogeneous contact structure.

[0062] As described above, the area ratio of the second region and the spacer region on the first surface affects the area ratio of the first doped silicon layer (at least on the first region) and the second doped silicon layer (at least on the second region) on the first surface, thereby affecting the area ratio of the P-region and N-region on the first surface of the back contact battery, and thus affecting the separation and collection of charge carriers. Furthermore, it also affects the etching efficiency, etching capacity, and leakage risk of at least the first doped silicon layer, the doped silicon glass layer, and the second doped silicon layer during actual manufacturing. Therefore, the specific values ​​of the area ratio of the first region, the second region, and the spacer on the first surface can be determined according to the requirements of the conversion efficiency and manufacturing capacity of the back contact battery in the actual application scenario, as long as they can be used in the back contact battery provided in this application embodiment.

[0063] For example, the area percentage of the first region on the first surface can be 35%, 36%, 37%, 38%, 39%, 40%, 41%, 42%, 43%, 44%, 45%, 46%, 47%, 48%, 49%, 50%, 51%, 52%, 53%, 54%, 55%, 56%, 57%, 58%, 59%, or 60%, etc.

[0064] For example, the area of ​​the second region on the first surface can be greater than or equal to 20% and less than or equal to 35%. For instance, the area of ​​the second region on the first surface can be 20%, 21%, 22%, 23%, 24%, 25%, 28%, 30%, 32%, or 35%, etc. Since the density of the second region is relatively lower, in order to increase the area of ​​the spacing region and improve the bifaciality of the module, the area of ​​the second region can be appropriately reduced without affecting the patterning capacity. However, the area of ​​the second region cannot be too low; the field passivation effect of the second region must also be considered.

[0065] For example, the area proportion of the spacer region on the first surface is greater than or equal to 10% and less than or equal to 20%. For instance, the area proportion of the spacer region on the first surface can be 10%, 11%, 12%, 14%, 15%, 16%, 18%, or 20%, etc. The first region, the second region, and the spacer region are all located on the first surface. When the area proportions of the second region and the spacer region are within the above range, it can be ensured that the first region has a large proportion on the first surface, shortening the processing time for the denser doped silicon glass layer and the first doped silicon layer, while reducing the risk of leakage. Furthermore, the area proportion of the PN region can be adjusted to achieve effective shunting of charge carriers, further reducing the risk of leakage.

[0066] For example, the sum of the areas of the first number of first regions and the second number of interval regions is S1, and the sum of the areas of the first number of second regions and the second number of interval regions is S2. The ratio between S1 and S2 can be greater than or equal to 1 and less than or equal to 2. The first number can be equal to or different from the second number. The ratio between S1 and S2 can be 1, 1.1, 1.2, 1.3, 1.4, 1.5, 1.51, 1.55, 1.6, 1.65, 1.7, 1.75, 1.8, 1.85, 1.9, 1.95, 1.99, or 2, etc. In this case, the ratio of S1 and S2 is within the above range, which helps to prevent the area ratio of the second doped silicon layer disposed on the second region from being too large due to the small ratio. This ensures that the PN junction has a large junction area when the conductivity type of the first doped silicon layer is opposite to that of the semiconductor substrate, which is beneficial for achieving effective separation of charge carriers. Furthermore, this ratio can prevent the first doped silicon layer on the first surface from having an excessively large area proportion due to a large ratio, thus preventing excessively long lateral carrier transport distances and ensuring that the second doped silicon layer has a high carrier collection efficiency. Simultaneously, the magnitude of this ratio also affects the area proportions of the denser first doped silicon layer and the relatively looser second doped silicon layer on the first surface, thereby affecting the etching capacity for selective etching of the first and second doped silicon layers. Therefore, a ratio within the aforementioned range is also beneficial for achieving both high conversion efficiency and manufacturing capacity in the back contact battery, contributing to cost reduction and efficiency improvement.

[0067] The above S1 and S2 can be calculated based on various numbers of regions. For example, the following different calculation methods are possible. When calculating for a single region, in one method, the sum of the areas of a first region and an interval region is S1, and the sum of the areas of a second region and an interval region is S2. When calculating for all regions, a rough calculation result can be obtained using the following method: the sum of the areas of a first region and two interval regions is S1, and the sum of the areas of a second region and two interval regions is S2. When calculating for all regions, a precise calculation result can also be obtained using the following method: the sum of the areas of all first regions and all interval regions is S1, and the sum of the areas of all second regions and all interval regions is S2.

[0068] It is understandable that, given a fixed size of the semiconductor substrate, the lengths of the first and second regions are approximately the same (the length directions of the first and second regions are approximately parallel to the series connection directions of the different back-contact batteries). Based on this, when the area ratios of the first and second regions on the first surface are different, the widths of the first and second regions are also different; correspondingly, the difference in width between the first and second regions can be referenced to the difference in area ratios of the first and second regions described above. The specific dimensions referred to by the width of the first and second regions can be determined based on their morphology. For example, when the first and second regions are distributed in a strip-like interval, the width of the first and second regions refers to the width of the strip-like areas included in the first and second regions. As another example, when the first and second regions are distributed in an interdigitated interval, the width of the first and second regions can refer to the width of the finger-like areas included in the first and second regions. When the first and second regions have non-uniform widths, the width refers to the average width.

[0069] For example, the sum of the widths of the first region of the third number and the interval regions of the fourth number is W1, and the sum of the widths of the second region of the third number and the interval regions of the fourth number is W2. The ratio between W1 and W2 can be greater than or equal to 1 and less than or equal to 2. The third number can be equal to or not equal to the fourth number. The first number can be equal to or not equal to the third number. The second number can be equal to or not equal to the fourth number. Optionally, the first, second, third, and fourth numbers can all be equal. For example, the ratio between W1 and W2 can be 1, 1.1, 1.2, 1.3, 1.4, 1.5, 1.51, 1.55, 1.6, 1.65, 1.7, 1.75, 1.8, 1.85, 1.9, 1.95, 1.99, or 2, etc. The application principle of the beneficial effect in this case is similar to the application principle of the beneficial effect when the ratio between S1 and S2 is greater than or equal to 1 and less than or equal to 2 as described above, and will not be repeated here.

[0070] Similar to the descriptions of S1 and S2 above, W1 and W2 can be calculated based on various numbers of regions. For example, the following different calculation methods are possible: When calculating for a single region, in one method, the sum of the widths of a first region and an interval region is W1, and the sum of the widths of a second region and an interval region is W2. When calculating for all regions, a rough calculation result can be obtained using the following method: the sum of the widths of a first region and two interval regions is W1, and the sum of the widths of a second region and two interval regions is W2. When calculating for all regions, a precise calculation result can also be obtained using the following method: the sum of the widths of all first regions and all interval regions is W1, and the sum of the widths of all second regions and all interval regions is W2.

[0071] For example, the sum of the widths of a first region and an interval region is W3, and the sum of the widths of a second region and an interval region is W4. The ratio between W3 and W4 is greater than the ratio between S1 and S2.

[0072] The ratios between W1 and W2, and between S1 and S2, can be selected within a range greater than or equal to 1 and less than or equal to 2. The ratio between W1 and W2 can be equal to the ratio between S1 and S2. The ratio between W3 and W4 can be greater than the ratio between S1 and S2. In this case, compared to the ratio between W3 and W4 being equal to the ratio between S1 and S2, when the ratio between W3 and W4 is greater than the ratio between S1 and S2, the ratio between W3 and W4 is relatively large, and / or the ratio between S1 and S2 is relatively small. This ensures that the first doped silicon layer has a high area ratio on one side of the first surface, further shortening the processing time for the denser doped silicon glass layer and the first doped silicon layer, improving the manufacturing efficiency of the back contact cell, reducing production costs, and increasing the manufacturing capacity of the back contact cell. For example, one side of the edge of the first surface has a P-type doped silicon layer, and the other three sides of the edge have N-type doped silicon layers.

[0073] Regarding the first and second doped silicon layers mentioned above, in terms of conductivity type, the first doped silicon layer can be P-type, in which case the second doped silicon layer is N-type; or, the first doped silicon layer is N-type, in which case the second doped silicon layer is P-type. Furthermore, the conductivity type of the first doped silicon layer can be opposite to that of the semiconductor substrate. In this case, the first doped silicon layer serves as the emitter region of the back contact battery, and the first region has a relatively large area proportion on the first surface, resulting in a larger area proportion of the emitter region at least in the first region. This facilitates the effective separation and collection of charge carriers, improving the conversion efficiency of the back contact battery.

[0074] In terms of materials, the first doped silicon layer can be made of polycrystalline silicon and / or monocrystalline silicon. Specifically, the first doped silicon layer can be a doped polycrystalline silicon layer made solely of polycrystalline silicon; the first doped silicon layer can also be a doped monocrystalline silicon layer made solely of monocrystalline silicon; the first doped silicon layer can also be a doped crystalline silicon layer that includes both polycrystalline silicon and monocrystalline silicon. The distribution of polycrystalline silicon and monocrystalline silicon in this doped crystalline silicon layer can be determined according to actual needs and is not specifically limited here.

[0075] As for the second doped silicon layer, the crystal orientation of the second doped silicon layer may include at least one of single crystal, polycrystalline, microcrystalline, nanocrystalline or amorphous, as long as the extinction coefficient of the second doped silicon layer is less than the extinction coefficient of the first doped silicon layer.

[0076] Optionally, both the first doped silicon layer and the second doped silicon layer can be doped polycrystalline silicon layers. In this case, the conductivity type of the first doped silicon layer can be P-type, and the conductivity type of the second doped silicon layer can be N-type.

[0077] Optionally, the first doped silicon layer can be a doped polycrystalline silicon layer, and the second doped silicon layer can be a doped silicon layer made of at least one of amorphous silicon, microcrystalline silicon, and nanocrystalline silicon. In this case, the back contact cell is a hybrid cell. Optionally, the conductivity type of the doped polycrystalline silicon layer can be N-type, and the conductivity type of the second doped silicon layer can be P-type. Compared with P-type doped amorphous silicon, microcrystalline silicon, or nanocrystalline silicon materials, P-type doped polycrystalline silicon materials have higher contact resistance with the electrode and poorer field passivation effect. Therefore, when the conductivity type of the first doped silicon layer is set to N-type and the conductivity type of the second doped silicon layer is set to P-type, the field passivation effect of the first doped silicon layer can be further improved, while the contact resistance between the first doped silicon layer and the electrode can be reduced, which is beneficial to improving the electrical performance of the back contact cell.

[0078] Regarding the formation location, as shown in Figures 1 and 2, the first doped silicon layer 15 can be directly disposed on the semiconductor substrate 11. Alternatively, as shown in Figure 3, the back contact cell may further include a first interface passivation layer 24, which is disposed between the semiconductor substrate 11 and the first doped silicon layer 15. In this case, the passivated contact structure composed of the first interface passivation layer 24 and the first doped silicon layer 15 has excellent interface passivation effect and can achieve selective collection of charge carriers, reducing the carrier recombination rate in the first region 12 of the first surface of the semiconductor substrate 11, and further improving the photoelectric conversion efficiency of the back contact cell. The material and thickness of the first interface passivation layer 24 can be set according to actual needs and are not specifically limited here. For example, the material of the first interface passivation layer may include tunneling passivation materials such as silicon oxide, aluminum oxide, or titanium oxide.

[0079] As for the second doped silicon layer, as shown in Figure 3, the second doped silicon layer 16 can be directly disposed on the second region 13. Alternatively, as shown in Figures 4 and 5, the back contact cell may also include a second interface passivation layer 25, which is disposed between the semiconductor substrate 11 and the second doped silicon layer 16 (when the second doped silicon layer 16 extends above the first doped silicon layer 15 located in the spacer region 14, the second interface passivation layer 25 also extends from the second region 13 to the space between the first doped silicon layer 15 and the second doped silicon layer 16). In this case, the passivated contact structure composed of the second interface passivation layer 25 and the second doped silicon layer 16 can achieve selective collection of charge carriers and reduce the carrier recombination rate in the second region 13 of the first surface of the semiconductor substrate 11. The material and thickness of the second interface passivation layer 25 can be set according to the material of the second doped silicon layer 16 and actual needs, and are not specifically limited here. For example, when the material of the second doped silicon layer is doped polycrystalline silicon, the second interface passivation layer is a tunneling passivation layer. For example, when the material of the second doped silicon layer includes at least one of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon, the second interface passivation layer is an intrinsic amorphous silicon layer, an intrinsic microcrystalline silicon layer, an intrinsic nanocrystalline silicon layer, or a mixture of the above three.

[0080] In terms of film properties, as mentioned earlier, the extinction coefficient of the first doped silicon layer is greater than that of the second doped silicon layer. Furthermore, the extinction coefficient of the doped silicon layer varies depending on the material used. The magnitude of the extinction coefficients of the first and second doped silicon layers can be determined based on the specific application requirements, such as the material of the doped silicon layer and the manufacturing capacity of the back contact battery.

[0081] For example, when the first doped silicon layer includes a P-type doped polysilicon layer, the extinction coefficient of the P-type doped polysilicon layer can be greater than or equal to 0.01 and less than or equal to 1.5. Optionally, the extinction coefficient of the P-type doped polysilicon layer can be greater than or equal to 0.6 and less than or equal to 1.2. For example, the extinction coefficient of the P-type doped polysilicon layer can be 0.01, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 1.0, 1.1, 1.2, or 1.5, etc. The extinction coefficient of the P-type doped polysilicon layer is also related to its own film density. Specifically, within a certain range, the extinction coefficient of the P-type doped polysilicon layer is directly proportional to its own film density. The film density affects its resistance to etchants. It can be understood that the higher the film density, the lower the etching rate of the etchant and the higher the etching difficulty. In this case, when the first doped silicon layer includes a P-type doped silicon layer, after the formation of the first doped silicon layer, the doped silicon glass layer formed on the side of the first doped silicon layer away from the semiconductor substrate is doped with P-type impurities such as boron. Because P-type impurities such as boron have lower electron affinity than N-type impurities such as phosphorus, they are less likely to accept electrons, further affecting their susceptibility to etching by the etchant. The doped silicon glass layer and the first doped silicon layer, both doped with P-type impurities such as boron, are less likely to react with alkaline wet etching solutions, making their etching more difficult. Therefore, when the first doped silicon layer includes a P-type doped polycrystalline silicon layer, in the back contact battery provided in this application embodiment, the processing time for the P-type doped polycrystalline silicon layer and the borosilicate glass layer can be shortened by increasing the area ratio of the P-type doped polycrystalline silicon layer on the first surface, thereby improving the manufacturing efficiency of the back contact battery, reducing production costs, and increasing the manufacturing capacity of the back contact battery. Furthermore, having an extinction coefficient within the aforementioned range for the P-type doped polysilicon layer can prevent problems such as electrode burn-through due to excessively low density caused by an excessively low extinction coefficient, ensuring good performance of the back contact cell. It also prevents excessively high density of the P-type doped polysilicon layer and the doped silicon glass layer due to an excessively high extinction coefficient, which would make selective etching of both difficult, further shortening the processing time for the doped silicon glass layer and the first doped silicon layer, improving the manufacturing efficiency of the back contact cell, reducing production costs, and increasing manufacturing capacity. In addition, since the extinction coefficient of the P-type doped polysilicon layer is also related to its doping concentration, when the extinction coefficient is within the aforementioned range, it allows for a higher doping concentration, which is beneficial for improving the field passivation effect of the P-type doped polysilicon layer and reducing the contact resistance between the P-type doped polysilicon layer and the corresponding conductive material.

[0082] For example, when the second doped silicon layer includes an N-type doped polysilicon layer, the extinction coefficient of the N-type doped polysilicon layer can be greater than or equal to 0.01 and less than or equal to 1.5. Optionally, the extinction coefficient of the N-type doped polysilicon layer can be greater than or equal to 0.05 and less than or equal to 0.3. For example, the extinction coefficient of the N-type doped polysilicon layer can be 0.01, 0.05, 0.08, 0.1, 0.12, 0.15, 0.18, 0.2, 0.22, 0.25, 0.28, 0.3, 0.5, 0.8, 1, 1.2, or 1.5, etc. In this case, compared with the P-type doped polycrystalline silicon layer, the extinction coefficient and density of the N-type doped polycrystalline silicon layer are relatively small. When the second doped silicon layer includes the N-type doped polycrystalline silicon layer, even though the area of ​​the second region with the N-type doped polycrystalline silicon layer on it in the first surface is relatively small, resulting in a larger etching amount when selectively etching the entire N-type doped polycrystalline silicon layer and the phosphosilicate glass layer, the etching difficulty of the N-type doped polycrystalline silicon layer and the phosphosilicate glass layer is relatively low, thus ensuring a high manufacturing efficiency of the back contact cell. The application principle of the beneficial effect of the extinction coefficient of the N-type doped polycrystalline silicon layer being greater than or equal to 0.01 and less than or equal to 1.5 is similar to that of the P-type doped polycrystalline silicon layer, and will not be elaborated here.

[0083] It should be noted that the extinction coefficients of both the P-type and N-type doped polysilicon layers can be selected within a range greater than or equal to 0.01 and less than or equal to 1.5. This range of extinction coefficients applies to doped polysilicon layers doped only with Group III-V elements, and also to stacked structures formed by doped polysilicon layers simultaneously doped with Group III-V elements and doped polysilicon layers doped with C or N. Specifically, the extinction coefficient of the doped polysilicon layer solely doped with Group III-V elements is greater than the extinction coefficient of the stacked structure formed by doped polysilicon layers with C or N and having the same conductivity type. The aforementioned doped polysilicon layers doped with C or N refer to polysilicon layers simultaneously doped with B or P, and C and / or N.

[0084] Furthermore, in practical applications, the density of the doped silicon layer is related to its degree of crystallization. Specifically, within a certain range, increasing the degree of crystallization of the doped silicon layer is beneficial to improving its density; conversely, decreasing the degree of crystallization of the doped silicon layer is beneficial to reducing its density. In the above case, the relationship and specific range between the degrees of crystallization of the first and second doped silicon layers can be determined based on the required extinction coefficients of the first and second doped silicon layers; no specific limitations are made here.

[0085] For example, the crystallinity of the second doped silicon layer can be greater than that of the first doped silicon layer. In this case, the film density of the second and first doped silicon layers can be controlled by adjusting the film density, thereby controlling the density of the doped silicon glass layer formed by oxidizing part of the first doped silicon layer. This reduces the selective etching difficulty of the first and doped silicon layers, further shortens the processing time of the doped silicon glass layer and the first doped silicon layer, improves the manufacturing efficiency of the back contact battery, reduces production costs, and increases the manufacturing capacity of the back contact battery.

[0086] In terms of film dimensions, the aspect ratio of the first doped silicon layer located in the first region can be greater than that of the second doped silicon layer located in the second region, and the spacing between two adjacent first regions or two adjacent second regions is greater than 1 mm. This increases the width of the first doped silicon layer in the first region, increases its area proportion on the first surface, further shortens the processing time for the denser doped silicon glass layer and the first doped silicon layer, improves the manufacturing efficiency of the back contact battery, reduces production costs, and increases the manufacturing capacity of the back contact battery. Simultaneously, if the first doped silicon layer is located at the emitter of the battery, it can also increase the PN junction area, facilitating effective carrier separation, reducing the carrier recombination rate, and improving the conversion efficiency of the back contact battery. The height direction of the first and second doped silicon layers refers to their thickness direction. The width direction of the first doped silicon layer in the first region and the width direction of the second doped silicon layer in the second region are consistent with the width directions of the first and second regions, respectively. The specific dimensions of the widths of the first doped silicon layer in the first region and the second doped silicon layer in the second region can be referred to as the dimensions of the widths of the first and second regions mentioned above, and will not be repeated here. Furthermore, the aspect ratio of the first doped silicon layer in the first region can be equal to or less than the aspect ratio of the second doped silicon layer in the second region. For example, the aspect ratio of the second doped silicon layer in the second region can be greater than that of the first doped silicon layer in the first region, and the spacing between two adjacent first regions or between two adjacent second regions can be less than or equal to 1 mm. In this case, it is advantageous to increase the width of the second doped silicon layer in the second region, increase the area ratio of the second doped silicon layer on the first surface, further shorten the processing time for the less dense doped silicon glass layer and the second doped silicon layer, improve the manufacturing efficiency of the back contact battery, reduce production costs, and increase the manufacturing capacity of the back contact battery. Simultaneously, if the second doped silicon layer serves as the field region of the battery, its passivation effect is better than that of the first doped silicon layer, improving the carrier separation capability of the field region, reducing the carrier recombination rate, and improving the conversion efficiency of the back contact battery.

[0087] Regarding the second doped silicon layer, as shown in FIG4, the second doped silicon layer 16 may be disposed only on the second region 13 of the semiconductor substrate 11; or, as shown in FIG5, the second doped silicon layer 16 may be disposed on the second region 13 of the semiconductor substrate 11 and extend above the portion of the first doped silicon layer 15 corresponding to the spacing region 14; or, as shown in FIG6, the second doped silicon layer 16 is disposed not only on the second region 13 of the semiconductor substrate 11, but also above the portion of the first doped silicon layer 15 located in the first region 12, and the second doped silicon layer 16 in the first region 12 is spaced apart from the first doped silicon layer 15, that is, the first doped silicon layer 15 has a dielectric layer on the side facing away from the semiconductor substrate 11, so as to form an isolation between the first doped silicon layer 15 and the second doped silicon layer 16 located in the first region 12. In this case, in the actual manufacturing process, the second doped silicon layer 16 is selectively etched on the entire layer, so that the second doped silicon layer 16 in the back contact battery is only located on a local area of ​​the first surface. Before selective etching, the mask material formed on the side of the second doped silicon layer 16 away from the semiconductor substrate 11 needs to be selectively processed using processes such as laser engraving. This allows the untreated portion of the mask material to form a mask layer that protects the second doped silicon layer 16. Therefore, the formation range of the second doped silicon layer 16 determines the range of mask material that needs to be processed. Based on this, when the second doped silicon layer 16 is not only disposed on the second region 13 but also on a portion of the first doped silicon layer 15 located in the first region 12, it is unnecessary to engrave the portion of the second doped silicon layer 16 above the first doped silicon layer 15. This shortens the processing time for the mask material and the second doped silicon layer 16, further improving the manufacturing efficiency of the back contact battery, reducing production costs, and increasing the manufacturing capacity of the back contact battery. Simultaneously, the spacing between the second doped silicon layer 16 and the first doped silicon layer 15 in the first region 12 prevents short circuits, reduces leakage risk, and ensures high electrical reliability of the back contact battery.

[0088] It is understood that, in practical applications, as shown in Figure 7, the aforementioned back contact battery may further include a plurality of first collector electrodes 17 disposed on the first doped silicon layer 15. Each first collector electrode 17 is in ohmic contact with the first doped silicon layer 15 to conduct the charge carriers collected by the first doped silicon layer 15, thereby facilitating the formation of photocurrent. The aforementioned back contact battery also includes a plurality of second collector electrodes 18 disposed on the second doped silicon layer 16. Each second collector electrode 18 is in ohmic contact with the second doped silicon layer 16 to conduct the charge carriers collected by the second doped silicon layer 16, thereby facilitating the formation of photocurrent. Specifically, the plurality of first collector electrodes 17 and the plurality of second collector electrodes 18 extend along a first direction, and the second collector electrodes 18 and the first collector electrodes 17 are alternately distributed along a second direction. The first direction is different from the second direction (the embodiments of this application do not specifically limit the directions referred to by the first and second directions. Optionally, when the surface of the semiconductor substrate is rectangular, one of the first and second directions may be parallel to the long side of the rectangle, and the other may be parallel to the short side of the rectangle). The second doped silicon layer 16 located in the first region 12 is spaced apart from the first collector electrode 17 to prevent leakage (specifically, the second doped silicon layer 16 located in the first region 12 can be spaced apart from the first collector electrode 17 by the insulating material of the surface passivation layer). The first collector electrode and the second collector electrode can be a continuous first collector electrode and a continuous second collector electrode, respectively. In this case, collector electrodes with the same polarity located in the same row along the first direction are one first collector electrode or one second collector electrode.

[0089] Alternatively, the first and second current collector electrodes can be discontinuous first and second current collector electrodes, respectively. In this case, multiple spaced-apart current collector electrode segments of the same polarity are located in the same row along the first direction, for example, multiple spaced-apart first current collector electrode segments or multiple spaced-apart second current collector electrode segments. In this scenario, the back contact battery may further include a first and second bus electrode extending along the second direction and alternately spaced along the first direction. The first bus electrode is electrically connected to the discontinuous first current collector electrode, and is electrically insulated from the discontinuous second current collector electrode through a break in the discontinuous second current collector electrode. The second bus electrode is electrically connected to the discontinuous second current collector electrode, and is electrically insulated from the discontinuous first current collector electrode through a break in the discontinuous first current collector electrode.

[0090] Alternatively, as shown in Figure 7, along the second direction, the first surface includes a central region and edge regions located on both sides of the central region. The first current collector 17 and the second current collector 18 located in the central region are respectively a continuous first current collector and a continuous second current collector, while the first current collector 17 and the second current collector 18 located in the edge regions are respectively a discontinuous first current collector or a discontinuous second current collector. Furthermore, the aforementioned back contact battery also includes a first interconnect structure 19 and a first bus electrode segment 20. The first bus electrode segment 20 is disposed on the edge region and extends along the second direction. The discontinuous first current collector is electrically connected to the first bus electrode segment 20, and the discontinuous second current collector is disconnected near the first bus electrode segment 20. In other words, the discontinuous second current collector is disconnected at the position where it would originally intersect with the first bus electrode segment 20, and the discontinuous second current collector does not intersect with the first bus electrode segment 20. It is understood that the extension line of the discontinuous second collector electrode at the break position along the first direction intersects with the first bus electrode segment 20. The discontinuous second collector electrode is broken at the position where it would have intersected with the first bus electrode segment 20 to isolate it from the first bus electrode segment 20. The first interconnect structure 19 is disposed at one end of the first bus electrode segment 20 near the middle region and is electrically connected to the first bus electrode segment 20. In this case, compared to all first collector electrodes 17 and all second collector electrodes 18 being discontinuous first collector electrodes and discontinuous second collector electrodes respectively, when some first collector electrodes 17 and some second collector electrodes 18 are continuous first collector electrodes and continuous second collector electrodes respectively, the number of dead zones in the first doped silicon layer 15 and the second doped silicon layer 16 can be reduced, which is beneficial to improving carrier collection efficiency and further improving the conversion efficiency of the back contact cell. In addition, in this case, the back contact cell may also include a second interconnect structure and a second bus electrode segment. The second bus electrode segment is disposed on the edge region and extends along the second direction. Similarly, the discontinuous second collector electrode is electrically connected to the second bus electrode segment, and the discontinuous first collector electrode is disconnected near the second bus electrode segment. The second interconnect structure is disposed at one end of the second bus electrode segment near the middle region and is electrically connected to the second bus electrode segment.

[0091] Furthermore, as shown in Figure 7, it can be understood that when the second doped silicon layer 16 is also disposed above a portion of the first doped silicon layer 15 located in the first region 12, the first doped silicon layer 15 in the first region 12 not only has the second doped silicon layer 16 disposed thereon, but also needs to have a first current collector electrode 17 for collecting and discharging charge carriers. The charge carrier collection capability of the first current collector electrode 17 is related to its formation range. Therefore, the specific position and range of the second doped silicon layer 16 above the first doped silicon layer 15 in the first region 12 can be determined based on the requirements of the first current collector electrode 17's charge carrier collection capability, the manufacturing capacity of the back contact battery, and the actual manufacturing precision in the actual application scenario. No specific limitations are made here.

[0092] For example, as shown in FIG7, when at least some of the second collector electrodes 18 are discontinuous second collector electrodes, the second doped silicon layer 16 located in the first region 12 can be disposed at the break point of the discontinuous second collector electrode. In the above case, the first collector electrode 17 and the second collector electrode 18 are used to collect and discharge carriers of corresponding conductivity types in the first doped silicon layer 15 and the second doped silicon layer 16, respectively, and the formation range of the two is proportional to their own carrier collection capacity. Furthermore, the in-string interconnect such as the solder ribbon extends substantially along the second direction and is electrically connected to the first collector electrode 17, and is electrically insulated from the discontinuous second collector electrode of opposite polarity through the break point of the discontinuous second collector electrode. Meanwhile, the interconnecting components such as solder strips are electrically connected to the first doped silicon layer 15 through the first current collector 17, and do not directly contact the first doped silicon layer 15. Therefore, when the second doped silicon layer 16 located in the first region 12 is set at the break of the discontinuous second current collector, not only can the processing time of the mask material and the second doped silicon layer 16 be shortened by retaining the second doped silicon layer 16 located above the portion of the first doped silicon layer 15, thereby improving the manufacturing capacity of the back contact battery, but it will also not affect the formation range of the first current collector 17 that collects and extracts the corresponding conductivity type of charge carriers in the first doped silicon layer 15, ensuring that the first current collector 17 has a high charge carrier collection capability and reducing the charge carrier recombination rate.

[0093] Specifically, as shown in Figure 7, when the second doped silicon layer 16 located in the first region can be disposed at the break point of the discontinuous second collector electrode, the second doped silicon layer 16 located in the first region can be disposed at the middle position along the first direction at the break point. Specifically, when at least some of the first collector electrodes 17 are discontinuous first collector electrodes, the second doped silicon layer 16 located in the first region can be symmetrically disposed with respect to the centerline of the collector electrode segment included in the discontinuous first collector electrode in the second direction. In this case, the leakage distances between the two ends of the second doped silicon layer 16 located in the first region and the edges of the first doped silicon layer 15, and between the ends of the second doped silicon layer 16 located in the first region and the edges of the second doped silicon layer 16 located in the second region, are approximately the same, preventing a higher leakage risk on one side due to the positional offset of the second doped silicon layer 16 located in the first region at the break point, and ensuring that the back contact battery has a high conversion efficiency. Of course, the centerline of the second doped silicon layer 16 located in the first region along the second direction can also be offset by a certain distance with respect to the centerline of the collector electrode segment included in the discontinuous first collector electrode in the second direction. The specific location of the second doped silicon layer 16 in the first region at the break point can be determined according to the actual manufacturing precision, and is not specifically limited here.

[0094] As shown in Figure 7, when the back contact battery also includes the aforementioned first interconnect structure 19 and first bus electrode segment 20, the second doped silicon layer 16 located in the first region may include a first sub-doped portion 21 and a second sub-doped portion 22. The first sub-doped portion 21 is disposed below the first bus electrode segment 20, and the second sub-doped portion 22 is disposed at least below the first interconnect structure 19. In addition to forming an isolation between the first doped silicon layer 15 and the second doped silicon layer 16 located in the first region through the aforementioned dielectric layer, it is also necessary to form an isolation between the second doped silicon layer 16 located in the first region and the electrode in the first region. The electrode in the first region includes any one of the first current collector electrode, the first bus electrode segment 20, and the first interconnect structure 19 to ensure sufficient collection of charge carriers by the electrode in the first region, while avoiding ohmic contact between the electrode in the first region and the second doped silicon layer 16, which could lead to leakage and reduce the risk of hot spots.

[0095] For example, the second doped silicon layer and the first collector electrode located in the first region are spaced apart in the in-plane direction of the semiconductor substrate; no ohmic contact is formed or very few are formed between the first sub-doped portion and the first bus electrode segment, and no ohmic contact is formed or very few are formed between the second sub-doped portion and the first interconnect structure, for example, the first bus electrode segment and the first interconnect structure both use non-burn-through materials.

[0096] As shown in Figures 7 and 8, along the first direction, the width of the second sub-doped portion 22 is greater than the width of the first sub-doped portion 21. This fully utilizes the dead area of ​​the first doped silicon layer 15 beneath the first bus electrode segment 20 and the first interconnect structure 19, thereby improving production capacity. Specifically, the width and length of the first sub-doped portion 21 and the second sub-doped portion 22 can be determined based on the size of the disconnection point, the manufacturing capacity of the back contact battery in the actual application scenario, and the carrier collection capability of the first current collector electrode 17; no specific limitations are made here.

[0097] For example, along the first direction, the width of the first sub-doped portion can be greater than or equal to 0.3 times the width of the portion of the first doped silicon layer located below the first sub-doped portion, and less than the width of the portion of the first doped silicon layer located below the first sub-doped portion. And / or, along the first direction, the width of the second sub-doped portion is greater than the width of the first interconnect structure, and less than or equal to 0.95 times the width of the portion of the first doped silicon layer located below the second sub-doped portion. In this case, when the widths of the second sub-doped portion and / or the first sub-doped portion are within the above ranges along the first direction, the width extension range of the first sub-doped portion and / or the second sub-doped portion at the corresponding break is larger, which is beneficial for further shortening the processing time of the mask material and the second doped silicon layer, further improving the manufacturing efficiency of the back contact battery, reducing production costs, and increasing the manufacturing capacity of the back contact battery.

[0098] For example, along the first direction, the width of the first sub-doped portion can be greater than the width of the interconnect (e.g., solder strip) and less than or equal to the width of the portion of the first doped silicon layer located below the first sub-doped portion. Multiples; and / or, along the first direction, the width of the second sub-doped portion may be greater than the width of the first interconnect structure (e.g., a pad) and less than or equal to the width of the portion of the first doped silicon layer located below the second sub-doped portion. This configuration, where the widths of the first and / or second sub-doped portions are selected within the aforementioned range, not only maximizes the utilization of the dead space at the disconnection point of the current collector electrode, thus significantly improving the manufacturing capacity of the back contact battery, but also avoids the risk of leakage caused by the interconnection of dissimilar doped regions due to excessively wide widths of the first and / or second sub-doped portions, thereby enhancing the electrical reliability of the back contact battery.

[0099] For example, along the second direction, the length of the first sub-doped portion can be less than or equal to 2.4 mm. For instance, the width of the first sub-doped portion can be 1 mm, 1.2 mm, 1.5 mm, 1.8 mm, 2 mm, 2.2 mm, or 2.4 mm, etc.

[0100] For example, along the second direction, the length of the second sub-doped portion can be less than or equal to 0.9 mm. For instance, the width of the second sub-doped portion can be 0.1 mm, 0.2 mm, 0.3 mm, 0.5 mm, 0.6 mm, 0.8 mm, or 0.9 mm, etc.

[0101] For example, along the second direction, the ratio of the total length of all second sub-doped portions to the total length of all first sub-doped portions is greater than or equal to 2:1 and less than or equal to 5:1. For instance, the ratio of the total length of all second sub-doped portions to the total length of all first sub-doped portions can be 2:1, 5:2, 3:1, 7:2, 4:1, 9:2, or 5:1, etc. In this case, the first and second sub-doped portions have a larger length extension range at the corresponding break points, which helps to further shorten the processing time for the mask material and the second doped silicon layer, further improve the manufacturing efficiency of the back contact battery, reduce production costs, and increase the manufacturing capacity of the back contact battery. Additionally, it can prevent the spacing between the first and second sub-doped portions and the first current collector electrode from being too small due to excessive length, reducing the risk of leakage and improving the electrical reliability of the back contact battery.

[0102] Furthermore, the location of the second sub-doped portion can be determined based on the break distance of the discontinuous second collector electrode where the extension line intersects the first bus electrode segment and is close to the first interconnect structure; no specific limitation is made here. As shown in Figure 7, when the break distance of the discontinuous second collector electrode where the extension line intersects the first bus electrode segment 20 and is close to the first interconnect structure 19 is approximately the same as the break distance of the discontinuous second collector electrode where the extension line intersects the first bus electrode segment 20 and is far away from the first interconnect structure 19, the second sub-doped portion 22 can be located only below the first interconnect structure 19.

[0103] Alternatively, as shown in Figure 8, the second sub-doped portion 22 can also be disposed below the side of the first busbar segment 20 near the first interconnect structure 19. In this case, it is understood that the width of the first interconnect structure 19 is larger than the width of the first busbar segment 20 along the first direction. To reduce the risk of leakage, the break distance of the discontinuous second collector electrode that intersects the first busbar segment 20 and is close to the first interconnect structure 19 is greater than the break distance of the discontinuous second collector electrode that intersects the first busbar segment 20 and is far away from the first interconnect structure 19. Based on this, when the wider second sub-doped portion 22 is also disposed below the side of the first busbar segment 20 near the first interconnect structure 19, the wider break distance can be further utilized to further increase the placement range of the second doped silicon layer 16 in the first region while preventing leakage, shortening the processing time for the denser doped silicon glass layer and the first doped silicon layer 15, and improving the manufacturing efficiency of the back contact battery. The disconnection distance of the non-continuous second collector electrode that intersects with the first bus electrode segment 20 and is close to the first interconnection structure 19 can be determined according to the requirements for leakage prevention in the actual application scenario, and no specific limitation is made here.

[0104] Secondly, embodiments of this application provide a photovoltaic module, which includes a back contact battery provided in the first aspect and its various implementations.

[0105] The beneficial effects of the second aspect and its various implementations in the embodiments of this application can be found by referring to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0106] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0107] The embodiments of this application have been described above. However, these embodiments are merely for clarity and are not intended to limit the scope of this application. The scope of this application is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this application, and all such substitutions and modifications should fall within the scope of this application.

Claims

1. A back contact cell, comprising: a semiconductor substrate comprising opposite first and second faces; the first face having first and second regions distributed with intervals, and interval regions between the first and second regions; a first doped silicon layer disposed on the first regions; the material of the first doped silicon layer comprising polycrystalline silicon and / or monocrystalline silicon; a second doped silicon layer disposed on the second regions; the second doped silicon layer having a conductivity type opposite to that of the first doped silicon layer; the first doped silicon layer having a corresponding extinction coefficient greater than that of the second doped silicon layer.

2. The back contact cell of claim 1, wherein, The first regions have an area ratio in the first face greater than or equal to 35% and less than or equal to 60%.

3. The back contact cell of claim 1, wherein, The second regions have an area ratio in the first face greater than or equal to 20% and less than or equal to 35%. And / or, the interval regions have an area ratio in the first face greater than or equal to 10% and less than or equal to 20%.

4. The back contact cell of claim 1, wherein, The first doped silicon layer comprises a P-type doped polycrystalline silicon layer having an extinction coefficient greater than or equal to 0.01 and less than or equal to 1.

5. And / or, the second doped silicon layer comprises an N-type doped polycrystalline silicon layer having an extinction coefficient greater than or equal 0.01 and less than or equal to 1.

5.

5. The back contact cell of claim 1, wherein, The second doped silicon layer has a crystallization degree greater than that of the first doped silicon layer.

6. The back contact cell of claim 1, wherein, The sum of the areas of a first number of the first regions and a second number of the interval regions is S1, the sum of the areas of a first number of the second regions and a second number of the interval regions is S2, the ratio between S1 and S2 is greater than or equal to 1 and less than or equal to 2, the first number is equal to the second number, or the first number is not equal to the second number. And / or, the sum of the widths of a third number of the first regions and a fourth number of the interval regions is W1, the sum of the widths of a third number of the second regions and a fourth number of the interval regions is W2, the ratio between W1 and W2 is greater than or equal to 1 and less than or equal to 2, the third number is equal to the fourth number, or the third number is not equal to the fourth number.

7. The back contact cell of claim 1, wherein, The sum of the widths of one of the first regions and one of the interval regions is W3, the sum of the widths of one of the second regions and one of the interval regions is W4, the ratio between W3 and W4 is greater than the ratio between S1 and S2.

8. The back contact cell of claim 1, wherein, The aspect ratio of the first doped silicon layer on the first regions is greater than that of the second doped silicon layer on the second regions, and the spacing between two adjacent first regions or the spacing between two adjacent second regions is greater than 1 mm.

9. The back contact cell of claim 1, wherein, The aspect ratio of the second doped silicon layer on the second regions is greater than that of the first doped silicon layer on the first regions, and the spacing between two adjacent first regions or the spacing between two adjacent second regions is less than or equal to 1 mm.

10. The back contact cell of claim 1, wherein, The back contact cell further comprises a plurality of first current collecting electrodes disposed on the first doped silicon layer, each of the first current collecting electrodes being in ohmic contact with the first doped silicon layer; the plurality of first current collecting electrodes extend along a first direction and are spaced apart along a second direction, the first direction being different from the second direction; The second doped silicon layer is further disposed above a portion of the first doped silicon layer on the first region, and the second doped silicon layer on the first region is spaced apart from the first doped silicon layer and the first current collecting electrodes, respectively.

11. The back contact cell of claim 10, wherein, The back contact cell further comprises a plurality of second current collecting electrodes disposed on the second doped silicon layer, each of the second current collecting electrodes being in ohmic contact with the second doped silicon layer; the plurality of second current collecting electrodes extend along the first direction, and the second current collecting electrodes and the first current collecting electrodes are alternately spaced apart along the second direction; Among the plurality of second current collecting electrodes, at least a portion of the second current collecting electrodes are discontinuous second current collecting electrodes; the second doped silicon layer on the first region is disposed at a break of the discontinuous second current collecting electrodes; among the plurality of first current collecting electrodes, at least a portion of the first current collecting electrodes are discontinuous first current collecting electrodes, and the second doped silicon layer on the first region is symmetrically disposed relative to a center line of a current collecting electrode segment included in the discontinuous first current collecting electrodes in the second direction.

12. The back contact cell of claim 11, wherein, Along the second direction, the first surface comprises a middle region and edge regions on both sides of the middle region; the first current collecting electrodes and the second current collecting electrodes on the middle region are continuous first current collecting electrodes and continuous second current collecting electrodes, respectively; and the first current collecting electrodes and the second current collecting electrodes on the edge regions are the discontinuous first current collecting electrodes or the discontinuous second current collecting electrodes, respectively. The back contact cell further comprises a first interconnection structure and a first busbar segment; the first busbar segment is disposed on the edge region and extends along the second direction; the discontinuous first current collecting electrodes are electrically connected to the first busbar segment, and the discontinuous second current collecting electrodes are broken near the first busbar segment; the first interconnection structure is disposed at an end of the first busbar segment near the middle region and is electrically connected to the first busbar segment; the second doped silicon layer on the first region comprises a first sub-doped portion and a second sub-doped portion; the first sub-doped portion is disposed below the first busbar segment, and the second sub-doped portion is disposed below at least the first interconnection structure; along the first direction, a width of the second sub-doped portion is greater than a width of the first sub-doped portion.

13. The back contact cell of claim 12, wherein, Along the first direction, a width of the first sub-doped portion is greater than or equal to 0.3 times a width of a portion of the first doped silicon layer below the first sub-doped portion and less than the width of the portion of the first doped silicon layer below the first sub-doped portion. and / or, along the first direction, a width of the second sub-doped portion is greater than a width of the first interconnection structure and less than or equal to 0.95 times a width of a portion of the first doped silicon layer located below the second sub-doped portion; and / or, the second sub-doped portion is also disposed below a side of the first busbar segment proximate to the first interconnection structure; and / or, along a direction of the first busbar segment away from the first interconnection structure, a width of the second sub-doped portion and a width of the first sub-doped portion gradually decrease.

14. The back contact cell of claim 12, wherein, The back contact cell further includes an interconnect electrically connected with the first interconnection structure, and along the first direction, a width of the first sub-doped portion is greater than a width of the interconnect and less than or equal to a width of a portion of the first doped silicon layer located below the first sub-doped portion times. and / or, along the first direction, a width of the second sub-doped portion is greater than a width of the first interconnection structure and less than or equal to a width of a portion of the first doped silicon layer located below the second sub-doped portion times.

15. The back contact cell of claim 12, wherein, along the second direction, a ratio of a sum of lengths of all the second sub-doped portions to a sum of lengths of all the first sub-doped portions is greater than or equal to 2:1 and less than or equal to 5:

1.

16. A photovoltaic module comprising the back contact cell of any one of claims 1-15.

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