Gallium oxide fin power device and manufacturing method therefor

Abstract

The present application discloses a gallium oxide fin power device and a manufacturing method therefor. The manufacturing method for the gallium oxide fin power device comprises: providing, on a substrate, a mask provided with at least one nano-pattern window, and forming metal gallium on the substrate exposed from the nano-pattern window; performing first annealing treatment on the metal gallium, and during the first annealing treatment, adjusting the temperature of the first annealing treatment, so that the metal gallium located within the nano-pattern window diffuses on the substrate to form gallium droplets having a specified shape, radial size and thickness, wherein the shape of the orthographic projections of the gallium droplets is the same as the shape of the orthographic projection of a fin structure to be formed; and using the gallium droplets as a catalyst to epitaxially grow gallium oxide on the substrate exposed from the nano-pattern window, growing the gallium oxide longitudinally to form the fin structure, and manufacturing a field-effect transistor on the substrate provided with the fin structure.

Description

Gallium oxide finned power devices and their fabrication methods

[0001] This application is based on and claims priority to Chinese patent application No. 202411749159.3, filed on November 30, 2024, entitled "Gallium oxide fin power device and method for fabrication thereof". Technical Field

[0002] This application specifically relates to a gallium oxide fin-type power device and its fabrication method, belonging to the field of semiconductor technology. Background Technology

[0003] Gallium oxide (Ga2O3) has attracted widespread attention due to its unique physical properties and large bandgap. As an emerging ultra-wide bandgap semiconductor material, it achieves a breakdown electric field of 8 MV / cm, demonstrating significant advantages in the fabrication of high-power devices with high breakdown voltages. Its applications include important industries such as power transmission, fast charging, and new energy vehicles. With the growth of global energy demand and the continuous development of new energy technologies, the need for efficient and durable power devices is becoming increasingly urgent, and Ga2O3 is one of the ideal materials to meet this demand.

[0004] Among all gallium oxide crystal forms, the stable phase β-Ga₂O₃ exhibits the most superior performance, especially in terms of evaluation metrics for power device applications. First, its bandgap is as high as 4.9 eV, meaning that β-Ga₂O₃ can withstand higher peak electric fields than traditional semiconductor materials, significantly improving the device's breakdown voltage. Second, β-Ga₂O₃ possesses a high Baliga's figure of merit (BFOM) of 3444, a crucial indicator of a semiconductor material's potential in power devices. This value is ten times that of SiC (silicon carbide) and three times that of GaN (gallium nitride), fully demonstrating the significant advantages of β-Ga₂O₃ in low-frequency, high-power devices.

[0005] In addition to the superior properties of the material itself, significant progress has been made in the fabrication technology of β-Ga2O3 single crystal substrates in recent years. Advanced single crystal growth techniques such as the guided-mode method, Czochralski method, and floating-zone method not only enable the production of large-size, uniformly thick Ga2O3 single crystal substrates but also ensure high-quality crystal structures. The maturity of these technologies has laid a solid foundation for the large-scale development and commercial application of Ga2O3 power devices. With these high-quality single crystal substrates, researchers can fabricate more stable and efficient power devices, further promoting the application of Ga2O3 in modern power electronic systems.

[0006] In recent years, both lateral and vertical power switch devices have been reported to have good performance parameters. However, increasing the withstand voltage of lateral devices requires increasing the channel size, which not only sacrifices wafer area but also introduces new surface states, affecting device reliability. For vertical devices, the voltage-bearing drift layer is mainly in the vertical direction, and simply increasing the drift layer thickness can improve the device's withstand voltage without sacrificing chip area.

[0007] Although Ga2O3 cannot be p-type doped due to its material properties, preventing the formation of pn junctions to manage the internal electric field of devices like traditional semiconductors, there are currently two main methods to achieve enhancement-mode performance without p-type materials: The first involves introducing a high barrier layer in a specific region to effectively block current flow, thereby controlling charge carriers and achieving enhancement-mode devices. Based on this, Ga2O3 vertical transistors have been developed into vertical current aperture structures (CAVET) and U-groove metal-oxide-semiconductor field-effect transistors (UMOS transistors). ] The first type is the vertical fin transistor, formed by controlling the channel geometry. The existing structures of vertical Ga2O3 field-effect transistors are shown in Figures 1a, 1b, and 1c. These structures not only improve device performance but also pave new paths for future high-power, high-frequency applications. However, manufacturing complexity, thermal management, and interface quality remain key challenges that need further resolution.

[0008] For enhanced performance using ion implantation, a high-resistivity current-blocking layer needs to be precisely introduced into the device to effectively block or regulate current. This precise control requires optimization of ion implantation energy, dose, implantation depth, and doping concentration to ensure the blocking layer effectively performs its intended function. However, even minor deviations can lead to instability or inconsistency in device performance, increasing fabrication complexity and difficulty. Secondly, ion implantation can cause localized damage to the gallium oxide crystal structure, forming defects and trapped states. These defects can lead to performance degradation over time, such as increased leakage current or decreased breakdown voltage. Especially under high-temperature operating conditions, defect evolution can further worsen, affecting the long-term stability of the device.

[0009] Vertical fin transistors employ fin-shaped channels, increasing the channel surface area to enhance gate control over the channel. They utilize channel geometry control instead of ion implantation, managing the electric field distribution and carrier flow within the device through fin size design. However, the manufacturing process is complex, particularly requiring high-precision photolithography and etching techniques for precise fin control. Fin formation is typically achieved through plasma dry etching. Plasma dry etching offers high anisotropy, enabling precise definition of the fin's geometry and size. However, this etching process can introduce etching damage and impurity ions, which can form interface states, negatively impacting the device's electrical performance. Summary of the Invention

[0010] The main objective of this application is to provide a gallium oxide fin-type power device and its fabrication method, thereby overcoming the shortcomings of the prior art.

[0011] To achieve the aforementioned objectives, the technical solution adopted in this application includes:

[0012] The first aspect of this application provides a method for fabricating a gallium oxide finned power device, comprising:

[0013] A mask having at least one nanopatterned window is disposed on a substrate, and metallic gallium is formed on the substrate exposed from the nanopatterned window;

[0014] The gallium metal is subjected to a first annealing process, and during the first annealing process, the temperature of the first annealing process is adjusted to allow the gallium metal located within the nano-pattern window to diffuse on the substrate to form gallium droplets with a specified shape, radial size and thickness, wherein the orthographic projection shape of the gallium droplets is the same as the orthographic projection shape of the fin structure to be formed.

[0015] Using the gallium droplet as a catalyst, gallium oxide is epitaxially grown on the substrate exposed from the nano-pattern window, and the gallium oxide is grown longitudinally to form a fin structure. During the epitaxial growth of gallium oxide, the molar flow ratio of the oxygen source and the gallium source is adjusted to maintain the diameter of the gallium droplet.

[0016] After removing the mask and the remaining catalyst, a field-effect transistor is formed on a substrate with a fin structure, wherein the top heavily doped layer of the fin structure serves as the ohmic contact layer of the field-effect transistor.

[0017] A second aspect of this application provides a gallium oxide fin power device prepared by the method described above.

[0018] Compared with the prior art, the advantages of this application include:

[0019] This application provides a method for fabricating a gallium oxide finned power device, which combines masking technology and selective area catalytic epitaxy (SATE) technology to precisely define the finned region and achieve precise control over the width, height, and position of the finned structure, ensuring that the structure meets design requirements.

[0020] The method for fabricating gallium oxide fin power devices provided in this application simplifies the fabrication process of gallium oxide fin power devices. It allows for the direct definition and growth of fin structures on the substrate, eliminating the cumbersome implantation and etching steps in the traditional fin field-effect transistor manufacturing process and greatly simplifying the manufacturing process.

[0021] The method for fabricating a gallium oxide finned power device provided in this application embodiment can obtain a higher quality crystal structure. Since it does not require plasma etching and high-energy ion implantation, it avoids crystal defects that may be introduced during the etching process, and ensures that the grown finned structure has a high-quality crystal structure and interface.

[0022] The method for fabricating a gallium oxide fin power device provided in this application improves the performance of the gallium oxide fin power device. By reducing the density of interface states, the electrical performance of the device is optimized, further enhancing the overall performance and reliability of the fin field-effect transistor.

[0023] The method for fabricating a gallium oxide finned power device provided in this application embodiment can be applied to different types of substrates, has wide applicability and flexibility, and can meet the needs of various device structures.

[0024] The method for fabricating gallium oxide fin-type power devices provided in this application realizes channel controllability. During the growth of the fin structure, different doping sources are introduced to flexibly control the doping of nanotubes, thereby effectively controlling the position of functional boundaries such as pn junctions and heterojunctions, thus realizing the application of nanoarrays and devices with heterogeneous integrated structures. Attached Figure Description

[0025] Figures 1a, 1b, and 1c are schematic diagrams of existing vertical Ga2O3 field-effect transistors.

[0026] Figure 2 is a schematic diagram of the process of forming a fin structure on a substrate in a typical embodiment of this application;

[0027] Figures 3a, 3b, 3c, and 3d are top views of a substrate with a fin structure obtained in a typical embodiment of this application.

[0028] Figure 4 is a schematic diagram of the process of forming a gallium oxide-based enhancement-type fin field-effect transistor on a substrate with a fin structure in a typical embodiment of this application. Detailed Implementation

[0029] In view of the shortcomings of the prior art, the inventors of this application, through long-term research and extensive practice, have come up with the technical solution of this application. The following will further explain the technical solution, its implementation process, and its principles.

[0030] The first aspect of this application provides a method for fabricating a gallium oxide finned power device, comprising:

[0031] A mask having at least one nanopatterned window is disposed on a substrate, and metallic gallium is formed on the substrate exposed from the nanopatterned window;

[0032] The gallium metal is subjected to a first annealing process, and during the first annealing process, the temperature of the first annealing process is adjusted to allow the gallium metal located within the nano-pattern window to diffuse on the substrate to form gallium droplets with a specified shape, radial size and thickness, wherein the orthographic projection shape of the gallium droplets is the same as the orthographic projection shape of the fin structure to be formed.

[0033] Using the gallium droplet as a catalyst, gallium oxide is epitaxially grown on the substrate exposed from the nano-pattern window, and the gallium oxide is grown longitudinally to form a fin structure. During the epitaxial growth of gallium oxide, the molar flow ratio of the oxygen source and the gallium source is adjusted to maintain the diameter of the gallium droplet.

[0034] After removing the mask and the remaining catalyst, a field-effect transistor is formed on a substrate with a fin structure, wherein the top heavily doped layer of the fin structure serves as the ohmic contact layer of the field-effect transistor.

[0035] In a more specific embodiment, the method for fabricating the gallium oxide fin-type power device includes: depositing gallium metal onto a substrate exposed from the nanopattern window by means of metal-organic source deposition, coating metal particles, sputtering or coating metal thin film, wherein the gallium metal influx flow rate is 1 sccm to 1 slm and the temperature conditions are 300℃ to 450℃.

[0036] Furthermore, the annealing temperature of the first annealing treatment is 400℃~800℃, preferably 550℃~600℃, the annealing time is 1min~10min, and the gas pressure is 1KPa~1MPa. The atmosphere of the first annealing treatment is an oxygen atmosphere or a mixed atmosphere of oxygen and nitrogen / argon. During the first annealing treatment, when the annealing temperature increases, the diffusion length of gallium atoms increases, and when the annealing temperature decreases, the diffusion length of gallium atoms decreases. Through the first annealing treatment, the metal gallium droplets on the substrate are collected according to the nano-patterned windows on the substrate patterned mask.

[0037] Furthermore, the epitaxial temperature for gallium oxide growth is 450℃~550℃, and the molar flow rate ratio of oxygen source to gallium source is 1~1000.

[0038] In a more specific embodiment, the method for fabricating the gallium oxide fin power device further includes: introducing doping impurities during the epitaxial growth of gallium oxide, such that at least the gallium oxide formed at the end of the gallium oxide epitaxial growth is heavily doped, and the heavily doped gallium oxide serves as the ohmic contact layer of the field-effect transistor. The doping impurities can be n-type impurities, such as Si impurities.

[0039] In a more specific embodiment, the method for fabricating the gallium oxide fin power device further includes: firstly performing a second annealing treatment on the substrate exposed from the nanopattern window, optimizing the lattice rearrangement of the substrate exposed from the nanopattern window to exhibit atomic-level steps, and then forming metallic gallium on the substrate.

[0040] Furthermore, the annealing temperature of the second annealing treatment is 800℃~1000℃, the annealing time is 10min~30min, and the gas pressure is 10KPa-1MPa. The annealing atmosphere is a nitrogen atmosphere, an argon atmosphere, or a nitrogen-argon mixed atmosphere. Through the second annealing treatment, the lattice quality of the patterned region on the gallium oxide surface is optimized, so that the surface exhibits atomic-level steps, which is beneficial to the subsequent gallium metal droplet aggregation and subsequent gallium oxide crystal growth.

[0041] Furthermore, the substrate includes, but is not limited to, a silicon substrate, a sapphire substrate, a silicon carbide substrate, a gallium nitride substrate, or a gallium oxide substrate.

[0042] Furthermore, the material of the mask includes SiN or SiO2, but is not limited to these.

[0043] Furthermore, the thickness of the mask is 1 nm to 10 μm.

[0044] Furthermore, the shape of the nano-graphic window is the same as the shape of the orthographic projection of the fin-shaped structure to be formed.

[0045] Furthermore, the method for fabricating the gallium oxide fin-type power device includes: forming the gate and epitaxial layer of the field-effect transistor on the surface of the substrate and the side of the fin structure, and forming the source and drain of the field-effect transistor on the top of the fin structure.

[0046] A second aspect of this application provides a gallium oxide fin power device prepared by the method described above.

[0047] Furthermore, the gallium oxide finned power device includes a detector or a light-emitting device.

[0048] The following will further explain the technical solution, its implementation process and principle in conjunction with the accompanying drawings and specific implementation examples. Unless otherwise specified, the epitaxial growth, photolithography, etching and other equipment used in the embodiments of this application are known in the art and are not specifically limited here.

[0049] In a typical embodiment, a method for fabricating a gallium oxide-based enhancement-mode fin field-effect transistor specifically includes the following steps:

[0050] 1) Fabricating a fin-shaped structure on a substrate, as shown in Figure 2, specifically including:

[0051] (a) Substrate cleaning: The substrate is sequentially immersed in acetone, isopropanol and deionized water and sonicated for 5 minutes each. Then, the substrate is cleaned with a piranha solution of concentrated sulfuric acid:water = 7:3. The substrate can be a silicon (Si) substrate, a sapphire substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate or a gallium oxide (Ga2O3) substrate, but is not limited to these.

[0052] (b) Mask deposition: A hard mask with a thickness of 1 nm to 10 μm is grown on the substrate using plasma-enhanced chemical vapor deposition (PECVD) or inductively coupled plasma chemical vapor deposition (plasma CVD). The hard mask can be a SiN or SiO2 hard mask, but is not limited to these.

[0053] (c) Photoresist coating: Spin-coat an electron beam photoresist with a thickness of 1 nm to 10 μm onto the mask. The electron beam lithography effect is affected by the conductivity of the substrate. If the substrate has poor conductivity, a conductive layer with a thickness of 10 nm can be spin-coated onto the hard mask before spin-coating the electron beam photoresist, or a conductive layer with a thickness of 10 nm can be sputtered onto the electron beam photoresist by magnetron sputtering after baking the spin-coated electron beam photoresist. The electron beam photoresist can be polymethyl methacrylate (PMMA) or the like, and the conductive layer can be nano-metals such as Cr.

[0054] (d) Defining the fin region: Electron beam lithography is used for exposure at a metering of 200–1000 microcubic centimeters to obtain the desired fin pattern on the electron beam photoresist. After exposure, the fin is developed for 120 seconds with an electron beam developer (isopropanol:tetramethyldipentanone = 3:1), followed by fixing with isopropanol for 30 seconds. If Cr forms a conductive layer on the electron beam photoresist surface in the previous step, it must be removed with a Cr etchant before development. The fin pattern includes single and multiple strip-shaped fin patterns or single and multiple circular or polygonal fin patterns. Top views of the various defined fin patterns are shown in Figures 3a, 3b, 3c, and 3d, respectively.

[0055] (e) Mask etching: Selective etching (conventional dry etching or wet etching) is used to transfer the fin pattern on the patterned PMMA onto the mask, forming a nano-pattern window on the mask. After mask patterning, the substrate is subjected to one or more annealing processes. The annealing temperature is 800℃~1000℃, the time is 10~30min, the pressure is 1KPa~1MPa, and the atmosphere is an oxygen atmosphere or a mixture of oxygen and nitrogen / argon to achieve cleaning and optimize the lattice quality of the patterned area on the gallium oxide surface, so that the surface exhibits atomic-level steps, which is conducive to the subsequent gallium metal droplet collection and subsequent gallium oxide crystal growth.

[0056] (f) Ga catalyst deposition: Ga metal is deposited on the substrate surface exposed from the nano-pattern window to form a thin layer of gallium by means of metal-organic source deposition, coating of metal particles, sputtering or coating of metal thin film, etc. The inlet flow rate of Ga metal is 1 sccm to 1 s lm, and the temperature conditions are 300℃ to 450℃.

[0057] After coating the surface with Ga metal, the Ga metal is annealed at a temperature of 400℃ to 800℃, preferably 550℃ to 600℃, for 1 min to 10 min at a pressure of 1 kPa to 1 MPa. The atmosphere for the first annealing treatment is an oxygen atmosphere or a mixture of oxygen and nitrogen / argon. By adjusting the annealing temperature of the Ga metal, the size of the Ga metal droplets can be precisely controlled by utilizing the characteristic that the diffusion length of Ga atoms on the substrate or dielectric surface changes with temperature. This process involves the diffusion behavior of Ga metal at different temperatures: at higher temperatures, the diffusion length of Ga atoms increases, resulting in larger droplets; while at lower temperatures, the diffusion length of Ga atoms decreases, and the size of the droplets decreases accordingly. Through precise temperature control and flexible adjustment of the Ga metal droplet size, the Ga metal droplets on the substrate are collected according to the patterned mask of the substrate, and the Ga metal condenses in the fin-defined area to form strip-shaped Ga metal catalyst lines. Furthermore, by controlling the width of the Ga metal droplets, the size of the fin structure can be precisely adjusted.

[0058] (g) Fin-shaped structure growth: Adjust the temperature inside the reaction chamber of the epitaxial growth equipment to the epitaxial temperature, preferably 450℃~550℃. Simultaneously, introduce a gallium source and an oxygen source into the reaction chamber. The gallium source can be TEGa or other Ga-containing metal sources or pure gallium metal sources. The oxygen source can be N2O, H2O, O2, O3, CO2, etc. The molar flow rate ratio of the gallium source to the oxygen source is 1-1000. Using the gallium droplets as a catalyst, gallium oxide is epitaxially grown on the substrate exposed from the nano-pattern window, and the gallium oxide grows longitudinally to form a fin-shaped structure.

[0059] Furthermore, during the epitaxial growth of gallium oxide, the molar flow rate ratio of the gallium source and the oxygen source is adjusted to regulate the radial width of the Ga metal droplet. At the end of the epitaxial growth, an n-type doping source (e.g., an n-type impurity containing Si) is introduced into the reaction chamber to form heavily doped n-type gallium oxide near the top of the fin structure. The heavily doped n-type gallium oxide serves as an ohmic contact layer with a thickness of 50 nm to 200 nm. It should be noted that the carrier concentration of the fin structure can be adjusted by adjusting the doping ratio of the growth source.

[0060] (h) Catalyst removal: Remove residual Ga catalyst. This step can be omitted if the Ga catalyst is completely consumed in the previous growth process.

[0061] (i) Mask removal: After removing the mask, the desired fin structure can be obtained; if the mask in the previous step is silicon oxide or silicon nitride, it can be left unremoved to increase the voltage withstand capability of the device.

[0062] The key process node for conventional catalytic epitaxy is the precise control of catalyst material thickness and position, often requiring high-precision alignment deposition. This application uses Ga metal droplets as a catalyst, which allows for control of the migration of Ga metal droplets on the substrate surface by controlling growth conditions. This enables the Ga metal droplet catalyst to occupy the top of the patterned fin, achieving high-precision fin morphology control. Furthermore, Ga metal is also the source material for crystal growth, avoiding the introduction of additional catalyst contamination. Simultaneously, the growth height of the fin can be precisely controlled using the Ga metal droplet catalyst.

[0063] The material, thickness, and distribution of the catalyst significantly affect the quality and morphology of epitaxial growth. However, controlling the uniformity and precise positioning of the catalyst at the micro-nano scale is extremely difficult. Excessive catalyst or uneven distribution can lead to growth defects, such as uneven steps and fin structure distortion. Precise control of the shape and geometry of the fin structure is challenging in conventional epitaxial growth methods, as the growth rate and directionality of the material are difficult to control, resulting in fin geometric deviations and ultimately affecting device consistency. This application employs Ga metal droplet catalysts, achieving precise control of crystal size by controlling the migration and merging of metal droplets. The patterned mask combined with the controlled migration of Ga metal droplets in this application enables uniform distribution of the metal droplets and allows for the acquisition of smaller Ga metal droplet catalyst patterns.

[0064] Selective catalytic epitaxy (SCE) requires the introduction of a catalyst into a specific region while ensuring its uniformity and accurate positioning. However, in practice, the distribution of the catalyst material may be non-uniform, leading to suboptimal epitaxial growth or distortion of the fin shape. The control of catalyst thickness, distribution, and edge effects significantly impacts growth accuracy, and this process complexity exceeds the understanding of traditional methods. This application first deposits Ga metal droplets on a substrate, and then achieves self-aligned patterning of the catalyst by controlling the migration of the Ga droplets into a nano-patterned window.

[0065] Conventional selected area epitaxy (SAE) relies primarily on the blocking effect of masks. However, in fin structures, due to their high aspect ratio requirements, conventional masking methods are prone to edge effects (e.g., crystal morphology is affected by mask size). This application combines Ga metal droplet formation with the definition of fin-shaped structural patterns, resulting in a much higher crystal growth rate in the fin-shaped pattern region than in the mask region, which is beneficial for achieving high aspect ratio fins.

[0066] 2) After the fin structure is formed, the subsequent fabrication process begins. The specific process steps are shown in Figure 4.

[0067] (a) The substrate with fin structure obtained by growth needs to undergo subsequent process steps after post-annealing and cleaning to realize the function of enhanced fin field-effect transistor.

[0068] (b) An insulating dielectric layer (SiO2, SiN, Al2O3, BN, etc.) is grown on the surface of the grown fin structure using atomic layer deposition (ALD) or low pressure chemical vapor deposition (LPCVD), and then a gate metal material (Ni, Cr, Mo, etc.) is sputtered on the insulating dielectric layer using magnetron sputtering technology with good sidewall coverage.

[0069] (c) The top of the fin structure is exposed by selective window etching through electron beam lithography to expose the opening or by etching the photoresist after homogenization to expose the top area.

[0070] (d) To isolate the gate source metal, an insulating dielectric layer (SiO2, SiN, Al2O3, BN, etc.) can also be grown using atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), or plasma-assisted chemical vapor deposition (PECVD) as the space layer isolation gate source metal.

[0071] (e) Repeat step (c) to open the growth space layer to expose the ohmic contact area at the top of the fin structure.

[0072] (f) Finally, the source and drain electrodes are grown. The source and drain electrodes are both made of Ti / Au. After annealing, the vertical fin field-effect transistor is fabricated.

[0073] This application provides a novel fabrication pathway for gallium oxide-based enhanced fin field-effect transistors (FFETs). By utilizing the catalytic properties of Ga catalysts, selective catalytic epitaxy of fin structures and fin arrays is achieved, avoiding channel damage in conventional device fabrication processes and providing an effective and controllable nanoarray structure for device fabrication. Furthermore, based on this, device fabrication is performed, achieving channel-free plasma-induced enhanced fin field-effect transistors without p-type materials. The resulting devices exhibit strong process compatibility and significantly improved device uniformity and reliability.

[0074] This application has a wide range of applicability, enabling the precise definition and growth of desired fin structures on various substrate types. It offers exceptional flexibility, allowing for the precise definition and growth of high-quality fin structures on silicon, gallium nitride (GaN), and other novel material substrates. Therefore, this application not only holds significant application potential in semiconductor device manufacturing but also provides an innovative technological path for the development of future novel electronic devices, thereby driving the advancement of semiconductor device manufacturing technology.

[0075] Specifically, this application combines selective epitaxy technology to precisely fill catalysts within predefined areas and grow fin-shaped structures that meet design requirements within these areas. Combined with masking technology, this application enables precise control over the width, height, and position of the fin-shaped structures, ensuring that each fin-shaped structure strictly conforms to design specifications.

[0076] Traditional fin field-effect transistor (FET) manufacturing processes typically rely on complex etching steps, which not only increase the complexity of the manufacturing process but may also introduce interface defects, affecting device performance. This application utilizes selective area catalytic epitaxy (SAI) technology to directly define and grow fin structures on the substrate without etching, greatly simplifying the process, reducing manufacturing costs, and improving production efficiency.

[0077] This application completely eliminates the plasma etching process, thus avoiding crystal defects and interface damage that may be introduced during etching. Since the fin structure is grown directly on the substrate, the quality of the crystal structure is effectively guaranteed, and the density of interface states is significantly reduced. This improvement directly enhances the electrical performance of the device, including increasing carrier mobility and reducing leakage current, thereby resulting in fin field-effect transistor devices with higher reliability and performance. Furthermore, this application employs a modulation doping method in the later stages of fin structure growth to grow a high-concentration Si-doped gallium oxide layer on top of the fin structure as an ohmic contact layer, replacing the traditional ion implantation at the top of the fin field-effect transistor. This reduces lattice damage caused by high-energy ion implantation and improves device reliability.

[0078] It should be understood that the above embodiments are merely illustrative of the technical concept and features of this application, and are intended to enable those skilled in the art to understand the content of this application and implement it accordingly. They should not be construed as limiting the scope of protection of this application. All equivalent changes or modifications made in accordance with the spirit and essence of this application should be included within the scope of protection of this application.

Claims

1. A method for fabricating a gallium oxide fin-type power device, characterized in that, include: A mask having at least one nanopatterned window is disposed on a substrate, and metallic gallium is formed on the substrate exposed from the nanopatterned window; The gallium metal is subjected to a first annealing process, and during the first annealing process, the temperature of the first annealing process is adjusted to allow the gallium metal located within the nano-pattern window to diffuse on the substrate to form gallium droplets with a specified shape, radial size and thickness, wherein the orthographic projection shape of the gallium droplets is the same as the orthographic projection shape of the fin structure to be formed. Using the gallium droplet as a catalyst, gallium oxide is epitaxially grown on the substrate exposed from the nano-pattern window, and the gallium oxide is grown longitudinally to form a fin structure. During the epitaxial growth of gallium oxide, the molar flow ratio of the oxygen source and the gallium source is adjusted to maintain the diameter of the gallium droplet. After removing the mask and the remaining catalyst, a field-effect transistor is formed on a substrate with a fin structure, wherein the top heavily doped layer of the fin structure serves as the ohmic contact layer of the field-effect transistor.

2. The method for fabricating the gallium oxide finned power device according to claim 1, characterized in that, include: Gallium is deposited on a substrate exposed from the nanopatterned window by means of metal-organic source deposition, coating of metal particles, sputtering or coating of metal thin film, with a gallium influx flow rate of 1 sccm to 1 slm and a temperature condition of 300℃ to 450℃.

3. The method for fabricating the gallium oxide finned power device according to claim 1, characterized in that: The annealing temperature of the first annealing treatment is 400℃~800℃, preferably 550℃~600℃, the time is 1min~10min, and the gas pressure is 1KPa~1MPa. The atmosphere of the first annealing treatment is an oxygen atmosphere or a mixed atmosphere of oxygen and nitrogen / argon. The annealing process is to collect the gallium droplets on the substrate according to the substrate patterned mask.

4. The method for fabricating a gallium oxide finned power device according to claim 1, characterized in that: The epitaxial temperature for gallium oxide growth is 450℃~550℃, and the molar flow ratio of oxygen source to gallium source is 1~1000.

5. The method for fabricating the gallium oxide finned power device according to claim 1 or 4, characterized in that, Also includes: Doping impurities are introduced during the epitaxial growth of gallium oxide, such that at least the gallium oxide formed at the end of the gallium oxide epitaxial growth is heavily doped, and the heavily doped gallium oxide serves as the ohmic contact layer of the field-effect transistor.

6. The method for fabricating a gallium oxide finned power device according to claim 1, characterized in that, Also includes: First, the substrate exposed from the nanopattern window undergoes a second annealing process to optimize the lattice arrangement of the substrate exposed from the nanopattern window, resulting in atomic-level steps, and then metallic gallium is formed on the substrate.

7. The method for fabricating the gallium oxide finned power device according to claim 6, characterized in that: The annealing temperature of the second annealing treatment is 800℃~1000℃, the annealing time is 10min~30min, and the gas pressure is 10KPa-1MPa. The annealing atmosphere is a nitrogen atmosphere, an argon atmosphere, or a nitrogen-argon mixed atmosphere. The annealing process is to optimize the lattice quality of the patterned region on the gallium oxide surface, so that the surface exhibits atomic-level steps, which is conducive to the subsequent collection of gallium metal droplets and the subsequent growth of gallium oxide crystals.

8. The method for fabricating a gallium oxide finned power device according to claim 1, characterized in that: The substrate includes a silicon substrate, a sapphire substrate, a silicon carbide substrate, a gallium nitride substrate, or a gallium oxide substrate; And / or, the material of the mask includes SiN or SiO2; Preferably, the thickness of the mask is 1 nm to 10 μm; Preferably, the shape of the nano-graphic window is the same as the shape of the orthographic projection of the fin-shaped structure to be formed.

9. The method for fabricating a gallium oxide finned power device according to claim 1, characterized in that, include: The gate and epitaxial layer of the field-effect transistor are formed on the surface of the substrate and the side of the fin structure, and the source and drain of the field-effect transistor are formed on the top of the fin structure.

10. A gallium oxide fin power device prepared by the method of any one of claims 1-9; Preferably, the gallium oxide finned power device includes a detector or a light-emitting device.

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