Semiconductor device, method of manufacturing same, optical integrated circuit device, and optical network system
By employing a silicon oxide sacrificial layer and selective etching for InP-based compound semiconductors, the method addresses the challenge of maintaining device flatness and consistency during transfer, enabling efficient integration and reduced costs in optical integrated circuits.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- NT T INC
- Filing Date
- 2024-11-27
- Publication Date
- 2026-06-04
AI Technical Summary
Existing transfer printing methods for integrating compound optical semiconductor devices with silicon photonics face challenges in achieving both back surface flatness and throughput while maintaining consistent device characteristics before and after transfer, due to the trade-off between etching selectivity and rate, leading to changes in photoconfinement and refractive index.
A method involving the use of a silicon oxide sacrificial layer with an InP-based compound semiconductor as the bottom layer, combined with a protective layer and tether resist layer, allows for selective etching at low temperatures to maintain device flatness and consistency, enabling transfer without altering device characteristics.
This approach ensures both back surface flatness and high throughput with consistent device characteristics before and after transfer, facilitating cost-effective integration and mounting by allowing pre-selection based on on-wafer inspection.
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Figure JP2024041916_04062026_PF_FP_ABST
Abstract
Description
Semiconductor Device, Method for Manufacturing the Same, Optical Integrated Circuit Device, and Optical Network System
[0001] The present disclosure relates to a semiconductor device, a method for manufacturing the same, an optical integrated circuit device, and an optical network system.
[0002] In order to increase the speed, capacity, and miniaturize an optical transceiver for optical communication, the integration of a compound optical semiconductor device and a silicon photonics optical circuit has been progressing. For example, in Non-Patent Document 1, between a compound semiconductor (particularly an InP-based semiconductor) device for manufacturing a laser or an optical modulator and a silicon photonics optical circuit, a low-loss optical coupling is realized by adiabatically transitioning the optical mode using a tapered waveguide structure (FIG. 2). Such a heterogeneous integration technology that combines a compound semiconductor device and silicon photonics has attracted attention, and a small and high-performance optical integrated circuit has been realized.
[0003] In particular, the transfer printing method (also known as the Micro transfer printing method) among heterogeneous integration technologies has attracted attention as a technology that can integrate a completed compound optical semiconductor device and a silicon photonics optical circuit with high positional accuracy, high throughput, and low cost (Non-Patent Document 2).
[0004] For example, as shown in FIG. 3A, using epitaxial crystal growth, a first sacrificial layer 302 and a second sacrificial layer 303 are formed on a source substrate 301, and a semiconductor layer 310 for forming a device is laminated on the second sacrificial layer 303. Next, the semiconductor layer 310 is processed to form a device structure 304 as shown in FIG. 3B, a protective layer 305 covering the device structure 304 is formed, and a tether resist layer 306 including legs 306a is formed. The protective layer 305 is formed in a state where the surface of the second sacrificial layer 303 is exposed to the surroundings. Also, the tether resist layer 306 is formed in a state where the legs 306a reach the exposed surface of the source substrate 301 on the sides of the first sacrificial layer 302 and the second sacrificial layer 303.
[0005] Next, the first sacrificial layer 302 and the second sacrificial layer 303 are removed using selective wet etching, so that the device structure 304 is supported on the original substrate 301 by the legs 306, as shown in Figure 3C. After this, as shown in Figure 3D, the device structure 304 supported on the original substrate 301 by the legs 306 is picked up from the original substrate 301 using a transfer stamp 307 and transferred onto the mounting substrate.
[0006] In this transfer technique, it is common to construct the sacrificial layer from a material with selectivity that allows for a high etching rate for the etchant during wet etching relative to the semiconductor material constituting the device structure. For InP-based materials used in compound semiconductor devices, InGaAs or InAlAs are commonly used. Furthermore, FeCl3 (iron(III) chloride) is known to be used as the etchant.
[0007] Here, the flatness of the back surface of the device structure after the removal of the sacrificial layer (the interface between the sacrificial layer and the device structure) depends on the selectivity ratio of InP and InGaAs (or InAlAs) and the etching time during the etching of the sacrificial layer. For example, over-etching during the removal of the sacrificial layer reduces the flatness of the back surface of the device structure exposed by the removal of the sacrificial layer. Therefore, it is important to increase the selectivity ratio of InP and InGaAs (or InAlAs) in order to suppress over-etching.
[0008] The etching selectivity ratio of InP and InGaAs or InAlAs with FeCl3 is highly dependent on the etching temperature, as shown in Fig. 2 of Non-Patent Document 1. To increase the etching selectivity, etching of the sacrificial layer is generally performed under low temperature conditions (0°C to 6°C), but such conditions lead to a decrease in the etching rate.
[0009] Y. Maeda et al., "Micro-transfer-printed InP-based Membrane Photonic Devices on Thin-film Lithium Niobate Platform", Journal of Lightwave Technology, DOI:10.1109 / JLT.2024.3366579, 2024. J. O'Callaghan et al., "Comparison of InGaAs and InAlAs sacrificial layers for release of InP-based 7, no. 12, pp. 4408-4414, 2017.T. Fujii et al., "Multiwavelength membrane laser array using selective area growth on directly bonded InP on SiO2 / Si", Optica, vol. 7, no. 7, pp. 838-846, 2020.
[0010] As mentioned above, there is a trade-off between selectivity and etching rate in wet etching, making it difficult to achieve both back surface flatness and throughput of the InP-based device structure after the etching process to remove the sacrificial layer is complete.
[0011] Furthermore, one of the advantages of the transfer printing method in mass production of devices is that good products can be selected through on-wafer inspection before transfer, and the device characteristics after transfer can be predicted, which is expected to reduce device integration and mounting costs through pre-selection.
[0012] However, in thin-film device structures such as conventional silicon-based membrane optical devices (Non-Patent Literature 3), the underside of the device structure changes from a compound semiconductor such as InP to a dielectric such as silicon oxide before and after transfer. Therefore, the photoconfinement rate to the active layer of the device structure and the effective refractive index of the excitation modes differ before and after transfer (Figures 4A and 4B). Figure 4A shows the mode distribution before transfer, and Figure 4B shows the mode distribution after transfer.
[0013] Therefore, the device characteristics extracted by on-wafer inspection before transfer differed from the device characteristics after transfer, making it difficult to reduce device integration and mounting costs through pre-selection by using the transfer printing method.
[0014] This disclosure was made to resolve the above-mentioned problems, and aims to suppress changes in device characteristics before and after transfer, thereby achieving both back surface flatness and throughput of the device structure.
[0015] A method for manufacturing a semiconductor device according to this disclosure comprises: a first step of forming a sacrificial layer made of silicon oxide on a substrate; a second step of forming a device structure made of an InP-based compound semiconductor with an InP semiconductor layer as the bottom layer on the sacrificial layer in such a state that the surface of the sacrificial layer around the device structure is exposed; a third step of forming a protective layer on the sacrificial layer that covers the device structure in such a state that the surface of the sacrificial layer is exposed around it; a fourth step of removing a portion of the sacrificial layer around the protective layer to form a substrate exposed region in which the surface of the substrate is exposed; a fifth step of forming a tether resist layer that covers the protective layer and has legs that reach the substrate exposed region from the side of the sacrificial layer in the substrate exposed region; and a sixth step of using the tether resist layer as a mask to remove the sacrificial layer from the sacrificial layer exposed around the legs and from the sides of the sacrificial layer, so that the device structure is supported on the substrate by the legs.
[0016] The semiconductor device according to this disclosure comprises a sacrificial layer made of silicon oxide, a device structure formed on the sacrificial layer with an InP-based compound semiconductor and an InP semiconductor layer as the bottom layer, and a protective layer formed on the sacrificial layer covering the device structure, wherein the device structure and the protective layer are formed on the sacrificial layer in such a way that the surface of the sacrificial layer around the device structure is exposed.
[0017] The optical integrated circuit device according to this disclosure comprises a silicon photonic optical circuit, a device structure integrated on the silicon photonic optical circuit and composed of an InP-based compound semiconductor with a semiconductor layer made of InP as the bottom layer, the surface of the bottom layer having a flatness of Ra of 0.5 nm or less, and a driver and amplifier, which are electronic circuits and are integrated on the silicon photonic optical circuit.
[0018] The optical network system relating to this disclosure includes the above-mentioned optical integrated circuit device.
[0019] As explained above, according to this disclosure, a device structure is formed on a sacrificial layer made of silicon oxide, with a semiconductor layer made of InP, composed of an InP-based compound semiconductor, as the bottom layer. This suppresses changes in device characteristics before and after transfer, making it possible to achieve both back surface flatness and throughput of the device structure.
[0020] Figure 1A is a cross-sectional view showing the state of a semiconductor device in an intermediate step for illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 1B is a cross-sectional view showing the state of a semiconductor device in an intermediate step for illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 1C is a cross-sectional view showing the state of a semiconductor device in an intermediate step for illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 1D is a cross-sectional view showing the state of a semiconductor device in an intermediate step for illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 1E is a cross-sectional view showing the state of a semiconductor device in an intermediate step for illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 1F is a cross-sectional view showing the state of a semiconductor device in an intermediate step for illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 1G is a cross-sectional view showing the state of a semiconductor device in an intermediate step for illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 2 is a perspective view showing the configuration of a device disclosed in Non-Patent Document 1. Figure 3A is a cross-sectional view showing the state of a semiconductor device in an intermediate step for illustrating a conventional method for manufacturing a semiconductor device. Figure 3B is a cross-sectional view showing the state of a semiconductor device in an intermediate step for illustrating a conventional method for manufacturing a semiconductor device. Figure 3C is a cross-sectional view showing the state of a semiconductor device in an intermediate step for illustrating a conventional method for manufacturing a semiconductor device. Figure 3D is a cross-sectional view showing the state of a semiconductor device in an intermediate step to illustrate a conventional semiconductor device manufacturing method. Figure 4A is a distribution diagram showing the mode distribution around the active layer before transfer. Figure 4B is a distribution diagram showing the mode distribution around the active layer after transfer.
[0021] The method for manufacturing a semiconductor device according to the embodiments of this disclosure will be described below with reference to Figures 1A to 1G.
[0022] First, as shown in Figure 1A, a sacrificial layer 102 made of silicon oxide is formed on a substrate 101 made of Si (first step). For example, the sacrificial layer 102 can be formed by depositing silicon oxide on the Si substrate 101 by sputtering or the like. Alternatively, the sacrificial layer 102 can be formed by thermal oxidation of the surface of the Si substrate 101.
[0023] Next, as shown in Figure 1B, the device structure 120 is formed on the sacrificial layer 102 with the surface of the sacrificial layer 102 surrounding the device structure 120 exposed (second step). The device structure 120 is composed of an InP-based compound semiconductor, with a semiconductor layer 121 made of InP as the bottom layer. The device structure 120 includes, for example, a semiconductor layer 121, an active layer 122, a p-type region 121a, an n-type region 121b, a p-contact layer 123a, an n-contact layer 123b, a p-electrode 124a, and an n-electrode 124b. It also includes a protective film 125 formed on the semiconductor layer 121.
[0024] The active layer 122 is formed embedded in the semiconductor layer 121 and extends from the foreground to the background in Figure 1B. The active layer 122 can be a multiple quantum well structure consisting of well layers and barrier layers, each composed of InGaAlAs, InGaAs, InGaAsP, etc., each with a different composition. The p-type region 121a and the n-type region 121b are formed on either side of the active layer 122. For example, the p-type region 121a can be formed by introducing p-type impurities into the semiconductor layer 121. The n-type region 121b can be formed by introducing n-type impurities into the semiconductor layer 121. The semiconductor layers 121 above and below the active layer 122 are undoped.
[0025] The p-contact layer 123a can be made of, for example, InGaAs with a high concentration of p-type impurities introduced. The n-contact layer 123b can be made of, for example, InGaAs with a high concentration of n-type impurities introduced. The protective film 125 can be made of, for example, silicon oxynitride (SiON).
[0026] For example, a semiconductor layer structure is formed by sequentially epitaxially growing compound semiconductor layers for forming each of the above-mentioned layers on another substrate made of InP. In this epitaxial growth, the semiconductor layer that will be the bottom layer constituting the device structure 120 is grown as the top layer. This semiconductor layer structure is bonded to the sacrificial layer 102 by wafer bonding technology. In this bonding, the bottom semiconductor layer constituting the device structure 120 and the sacrificial layer 102 are bonded. After this, the other substrate is removed, and the above-mentioned device structure 120 can be manufactured by a known semiconductor device manufacturing process.
[0027] The device structure 120 is a known waveguide-type optical element with an active layer 122 as its core. For example, by using a p electrode 124a and an n electrode 124b, and applying a predetermined voltage to the p-type region 121a and the n-type region 121b via the p-contact layer 123a and the n-contact layer 123b, it can be configured as an optical modulator.
[0028] Furthermore, by forming a diffraction grating (not shown) on the upper part of the active layer 122, and injecting current into the p-type region 121a and the n-type region 121b via the p-contact layer 123a and the n-contact layer 123b using the p-electrode 124a and the n-electrode 124b, the device structure 120 can be made into a semiconductor laser.
[0029] Next, as shown in Figure 1C, a protective layer 103 covering the device structure 120 is formed on the sacrificial layer 102, with the surface of the sacrificial layer 102 exposed around it (third step).
[0030] Next, as shown in Figure 1D, a portion of the sacrificial layer 102 around the protective layer 103 is removed to form a substrate exposed region 111 where the surface of the substrate 101 is exposed (fourth step).
[0031] The semiconductor device manufactured as described above comprises a sacrificial layer 102 made of silicon oxide, a device structure 120 made of an InP-based compound semiconductor with an InP semiconductor layer as the bottom layer formed on the sacrificial layer 102, and a protective layer 103 formed on the sacrificial layer 102 covering the device structure 120. Furthermore, the device structure 120 and the protective layer 103 are formed on the sacrificial layer 102 in such a way that the surface of the sacrificial layer 102 around the device structure 120 is exposed.
[0032] Next, as shown in Figure 1E, a tether resist (tether) layer 104 is formed that covers the protective layer 103 and has legs 104a that reach the substrate exposed region 111 on the side of the sacrificial layer 102 (fifth step).
[0033] Next, as shown in Figure 1F, the sacrificial layer 102 is removed from the side surface of the sacrificial layer 102 exposed around the leg portion 104a, using the tether resist layer 104 as a mask. This removal leaves the device structure 120 supported on the substrate 101 by the leg portion 104a (sixth step). In the sixth step, the sacrificial layer 102 is removed by an etching process in which silicon oxide is selectively etched from the InP-based compound semiconductor. For example, the sacrificial layer 102 can be selectively removed by a wet etching process using hydrofluoric acid or buffered hydrofluoric acid as the etching solution. In this sixth step, the sacrificial layer 102 is removed, exposing the entire lower surface of the bottom semiconductor layer of the device structure 120 facing the substrate 101.
[0034] In the wet etching described above, the compound semiconductor constituting the device structure 120 is hardly etched. Therefore, to increase the selectivity of etching, low-temperature conditions (0°C to 6°C) can be used, allowing the process to be carried out without causing a decrease in the etching rate. Furthermore, sufficient back surface flatness of the device structure 120 after the removal of the sacrificial layer 102 can be ensured. For example, the surface of the exposed bottom layer after the removal of the sacrificial layer 102 can have a flatness of Ra of 0.5 nm or less at the stage when the device structure was manufactured.
[0035] Next, as shown in Figure 1G, the device structure 120, which is supported on the substrate 101 by legs 104a and has a protective layer 103 formed on it, is removed from the substrate 101 using a transfer stamp 105 (seventh step). The device structure 120 can be picked up from the substrate 101 by attaching the transfer stamp 105 to the upper surface of the tether resist layer 104 and pulling it up. This pickup can be carried out, for example, by separating the legs 104a from the tether resist layer 104.
[0036] Furthermore, the picked-up device structure 120 can be transferred (released) and integrated onto, for example, a silicon photonic optical circuit. Since the underside of the device structure is a silicon oxide layer both before and after the transfer, the photoconfinement rate to the active layer and the effective refractive index of the excitation mode of the device structure do not differ before and after the transfer. Therefore, by selecting good products through on-wafer inspection before transfer and predicting the device characteristics after transfer, it becomes possible to reduce the cost of device integration and mounting through pre-selection.
[0037] Furthermore, an optical integrated circuit device that integrates a driver and amplifier, which are electronic circuits, into a silicon photonic optical circuit, which integrates the device structure, can be used, for example, in an optical network system.
[0038] As described above, according to the embodiments of this disclosure, a device structure is formed on a sacrificial layer made of silicon oxide, with a semiconductor layer made of InP, composed of an InP-based compound semiconductor, as the bottom layer. This suppresses changes in device characteristics before and after transfer, making it possible to achieve both back surface flatness and throughput of the device structure.
[0039] It should be noted that this disclosure is not limited to the embodiments described above, and it is evident that many modifications and combinations are possible within the technical concept of this disclosure by a person with ordinary skill in the art.
[0040] 101...Substrate, 102...Sacrificial layer, 103...Protective layer, 104...Tether resist (tether) layer, 104a...Legs, 105...Transfer stamp, 111...Substrate exposed area, 120...Device structure.
Claims
1. A method for manufacturing a semiconductor device, comprising: a first step of forming a sacrificial layer made of silicon oxide on a substrate; a second step of forming a device structure made of an InP-based compound semiconductor with an InP semiconductor layer as the bottom layer on the sacrificial layer in such a state that the surface of the sacrificial layer around the device structure is exposed; a third step of forming a protective layer on the sacrificial layer that covers the device structure in such a state that the surface of the sacrificial layer is exposed around the device structure; a fourth step of removing a portion of the sacrificial layer around the protective layer to form a substrate exposed region in which the surface of the substrate is exposed; a fifth step of forming a tether resist layer that covers the protective layer and has legs that reach the substrate exposed region from the side of the sacrificial layer in the substrate exposed region; and a sixth step of removing the sacrificial layer from the sacrificial layer exposed around the legs and from the sides of the sacrificial layer using the tether resist layer as a mask, so that the device structure is supported on the substrate by the legs.
2. A method for manufacturing a semiconductor device according to claim 1, wherein the second step is to bond the lowest semiconductor layer constituting the device structure to the sacrificial layer, thereby forming the device structure on the sacrificial layer.
3. A method for manufacturing a semiconductor device according to claim 1, wherein the sixth step is a method for manufacturing a semiconductor device in which the sacrificial layer is removed by an etching process in which silicon oxide is selectively etched from an InP-based compound semiconductor.
4. A method for manufacturing a semiconductor device according to claim 3, wherein the sixth step is a wet etching process in which the sacrificial layer is removed using hydrofluoric acid or buffered hydrofluoric acid as the etching solution.
5. A method for manufacturing a semiconductor device according to claim 1, further comprising a seventh step of removing the device structure, which is supported on the substrate by the legs and has the protective layer formed on it, from the substrate using a transfer stamp.
6. A semiconductor device comprising a sacrificial layer made of silicon oxide, a device structure formed on the sacrificial layer with an InP-based compound semiconductor and an InP semiconductor layer as the bottom layer, and a protective layer formed on the sacrificial layer covering the device structure, wherein the device structure and the protective layer are formed on the sacrificial layer in such a state that the surface of the sacrificial layer around the device structure is exposed.
7. An optical integrated circuit device comprising: a silicon photonic optical circuit; a device structure integrated on the silicon photonic optical circuit and composed of an InP-based compound semiconductor, with a semiconductor layer made of InP as the bottom layer, the surface of the bottom layer having a flatness of Ra of 0.5 nm or less; and a driver and amplifier, which are electronic circuits, integrated on the silicon photonic optical circuit.
8. An optical network system comprising the optical integrated circuit device according to claim 7.