Trench gate type switching element

Abstract

This switching element includes a semiconductor substrate, a trench, a gate insulating film, a gate electrode, and an upper electrode. The semiconductor substrate has an upper n-type region in contact with the gate insulating film, a p-type body contact region adjacent to the upper n-type region, a p-type body region in contact with the gate insulating film below the upper n-type region, and an n-type drift region in contact with the gate insulating film below the body region. The distance from a bottom end of the trench in the thickness direction of the semiconductor substrate to an interface between the upper n-type region and the body region is defined as L1, and the shortest distance, in a plane along a top surface of the semiconductor substrate, from the position farthest from the body contact region within a range where the upper n-type region contacts the gate insulating film to the body contact region is defined as L2, and the relationship L2 ≤ 0.429L1 − 0.318 is satisfied.

Description

Trench gate type switching element

[0001] (Cross-reference of related applications) This application is a related application to Japanese Patent Application No. 2024-208834, filed on 29 November 2024, and claims priority based on the said Japanese Patent Application. All contents of the said Japanese Patent Application are incorporated herein by reference as constituting this specification.

[0002] The technology disclosed herein relates to a trench gate type switching element.

[0003] A trench-gate type switching element is known. The trench-gate type switching element has a semiconductor substrate, a trench provided on the upper surface of the semiconductor substrate, a gate insulating film and a gate electrode disposed inside the trench, and an upper electrode provided on the upper surface of the semiconductor substrate. Inside the semiconductor substrate, there is an upper n-type region, a p-type body contact region, a p-type body region, and an n-type drift region. The upper n-type region is in contact with the upper electrode and the gate insulating film. The body contact region is in contact with the upper electrode and is adjacent to the upper n-type region. The body region is located below the upper n-type region and the body contact region, is in contact with the gate insulating film below the upper n-type region, and has a lower p-type impurity concentration than the body contact region. The drift region is in contact with the gate insulating film below the body region and is separated from the upper n-type region by the body region. Japanese Patent Application Publication No. 2017-17222 discloses an insulated-gate bipolar transistor (IGBT) as an example of a trench-gate type switching element. In IGBTs, the upper n-type region is called the emitter region. Another example of a trench-gate switching element is the MOSFET (metal-oxide-semiconductor field effect transistor). In MOSFETs, the upper n-type region is called the source region.

[0004] In a trench gate type switching element, when an instantaneously excessive voltage (dv / dt) is applied, the electric field at the lower end of the trench increases, and holes are generated by impact ionization at the lower end. Also, when an instantaneously excessive voltage (dv / dt) is applied, a displacement current flows through the output capacitance (for example, collector-emitter capacitance) in the switching element. These holes are discharged to the upper electrode through the body contact region. The potential (base potential) in the p-type body region on the path of these holes rises due to an increase in the hole current and an increase in the base resistance. When the potential difference between this base potential and the potential of the upper n-type region (for example, base-emitter potential) becomes equal to or greater than the built-in potential, a parasitic transistor composed of the upper n-type region, the p-type body region, and the n-type drift region operates, which may lead to latch-up breakdown. In order to suppress the operation of the parasitic transistor, it is necessary to consider both the hole current density and the base resistance, and the dv / dt tolerance can be used as an index to evaluate the effect. In this specification, a technique capable of suppressing latch-up in a trench gate type switching element is proposed.

[0005] The trench gate switching element disclosed herein comprises a semiconductor substrate, a trench provided on the upper surface of the semiconductor substrate, a gate insulating film covering the inner surface of the trench, a gate electrode disposed in the trench and insulated from the semiconductor substrate by the gate insulating film, and an upper electrode in contact with the upper surface of the semiconductor substrate. The semiconductor substrate has an upper n-type region in contact with the upper electrode and the gate insulating film, a p-type body contact region in contact with the upper electrode and adjacent to the upper n-type region, a p-type body region located below the upper n-type region and the body contact region, in contact with the gate insulating film below the upper n-type region, and having a lower p-type impurity concentration than the body contact region, and an n-type drift region located below the body region, in contact with the gate insulating film below the body region, and separated from the upper n-type region by the body region. L1 is the distance from the lower end of the trench in the thickness direction of the semiconductor substrate to the interface between the upper n-type region and the body region, and L2 is the shortest distance from the position furthest from the body contact region within the range in which the upper n-type region contacts the gate insulating film, in the plane along the upper surface of the semiconductor substrate, satisfying the relationship L2 ≤ 0.429 L1 - 0.318.

[0006] Since this switching element satisfies the above relationship, it can suppress the increase in Hall current and base resistance in the p-type body region, and as a result, the rise in base potential is suppressed, thereby suppressing the operation of parasitic transistors.

[0007] A plan view of the switching element 10 of Example 1. A cross-sectional view along line II-II in Figure 1. An enlarged cross-sectional view of the trench, emitter region, and surrounding area in Figure 2. A graph showing the measured results of dv / dt withstand voltage for the shortest EN distance at a predetermined depth. A graph showing the critical point where the dv / dt withstand voltage decreases sharply at each depth and each shortest EN distance. A plan view of the switching element 100 of Example 2. A cross-sectional view along line VII-VII in Figure 6. A plan view of the switching element 200 of Example 3. A plan view of the switching element 300 of Example 4. A plan view of the switching element 400 of Example 5. A cross-sectional view along line XI-XI in Figure 10. A plan view of the switching element 500 of Example 6. A plan view of the switching element 600 of Example 7. An enlarged plan view of the rectangular region 650 in Figure 13. An enlarged plan view of the rectangular region 750 of the switching element 700 of Example 8. An enlarged plan view of the rectangular region 850 of the switching element 800 of Example 9. Plan view of the switching element 900 of Example 10.

[0008] (Example 1) The switching element 10 of Example 1 shown in Figures 1 and 2 is a trench gate type IGBT. The switching element 10 has a semiconductor substrate 12 and electrodes, an insulating film, etc., provided on the upper surface 12a and lower surface 12b of the semiconductor substrate 12. In each figure, the z direction is the thickness direction of the semiconductor substrate 12, the x direction is a direction parallel to the upper surface 12a of the semiconductor substrate 12, and the y direction is a direction parallel to the upper surface 12a and perpendicular to the x direction. The semiconductor substrate 12 is made of a semiconductor material such as Si (silicon) or SiC (silicon carbide).

[0009] Multiple trenches 22 are provided on the upper surface 12a of the semiconductor substrate 12. As shown in Figure 1, each trench 22 extends parallel to each other along the y-direction. Each trench 22 is spaced apart in the x-direction. As shown in Figure 2, the inner surface of each trench 22 is covered with a gate insulating film 24. A gate electrode 26 is located inside each trench 22. The gate electrode 26 is insulated from the semiconductor substrate 12 by the gate insulating film 24. The upper surface of the gate electrode 26 is covered with an interlayer insulating film 28.

[0010] An emitter electrode 70 is provided on the upper surface 12a of the semiconductor substrate 12. The emitter electrode 70 is in contact with the upper surface 12a of the semiconductor substrate 12 in the area where the interlayer insulating film 28 is not provided. A collector electrode 72 is provided on the lower surface 12b of the semiconductor substrate 12. The collector electrode 72 is in contact with the entire lower surface 12b of the semiconductor substrate 12.

[0011] As shown in Figure 2, the semiconductor substrate 12 has an emitter region 30, a body contact region 32, a body region 33, a drift region 34, and a collector region 36 formed inside it.

[0012] The emitter region 30 is an n-type region containing a high concentration of n-type impurities. The emitter region 30 is exposed on the upper surface 12a of the semiconductor substrate 12. The emitter region 30 is in contact with the gate insulating film 24 at the upper end of the trench 22. The emitter region 30 is in ohmic contact with the emitter electrode 70.

[0013] The body contact region 32 is a p-type region containing a high concentration of p-type impurities. The body contact region 32 is exposed on the upper surface 12a of the semiconductor substrate 12. The body contact region 32 is adjacent to the emitter region 30. As shown in Figures 1 and 2, the body contact region 32 is located in the area sandwiched between the two emitter regions 30. The body contact region 32 is separated from the gate insulating film 24 by the emitter region 30. The body contact region 32 is in ohmic contact with the emitter electrode 70.

[0014] The body region 33 is a p-type region containing a lower concentration of p-type impurities than the body contact region 32. The body region 33 is located below the emitter region 30 and the body contact region 32. The body region 33 is in contact with the gate insulating film 24 below the emitter region 30.

[0015] The drift region 34 is an n-type region containing a lower concentration of n-type impurities than the emitter region 30. The drift region 34 is located below the body region 33. The drift region 34 is separated from the emitter region 30 by the body region 33. The drift region 34 is in contact with the gate insulating film 24 near the lower end of the trench 22, below the body region 33.

[0016] The collector region 36 is a p-type region containing a high concentration of p-type impurities. The collector region 36 is located below the drift region 34. The collector region 36 is separated from the body region 33 by the drift region 34. The collector region 36 is exposed on the lower surface 12b of the semiconductor substrate 12. The collector region 36 is in ohmic contact with the collector electrode 72.

[0017] Next, the operation of the switching element 10 will be described. When the switching element 10 is in use, a voltage is applied between the collector electrode 72 and the emitter electrode 70 such that the collector electrode 72 is at a higher potential than the emitter electrode 70. When a voltage above the gate threshold is applied to the gate electrode 26, the body region 33 in contact with the gate insulating film 24 is inverted to n-type, and a channel is formed. Once the channel is formed, electrons flow from the emitter electrode 70 to the collector electrode 72 via the emitter region 30, the channel, the drift region 34, and the collector region 36. Also, holes flow from the collector electrode 72 to the emitter electrode 70 via the drift region 34, the body region 33, and the body contact region 32. As a result, the switching element 10 is turned on. When the voltage of the gate electrode 26 falls below the gate threshold, the channel disappears, and the switching element 10 is turned off.

[0018] When an excessively large voltage (dv / dt) is instantaneously applied to the off-state switching element 10 in a direction in which the collector electrode 72 is at a higher potential than the emitter electrode 70, an electric field concentrates at the lower end 22a of the trench 22. As a result, holes are generated at this lower end due to impact ionization. Also, when an excessively large voltage (dv / dt) is instantaneously applied, a displacement current flows through the output capacitance (collector-emitter capacitance) within the switching element 10. These holes are discharged to the emitter electrode 70 via the p-type body region 33 and body contact region 32. The shorter the distance L1, the easier it is for holes to flow into the body region 33, increasing the hole current in the body region 33 and raising the base potential. Conversely, the longer the distance L2, the greater the base resistance of the body region 33 and raising the base potential. When the difference between the base potential and the emitter region 30 (base-emitter potential) exceeds the internal potential, the parasitic transistor, which consists of the emitter region 30, the p-type body region 33, and the n-type drift region 34, activates, leading to latch-up failure.

[0019] In the switching element 10 of this embodiment, the decrease in dv / dt withstand capability can be suppressed by adjusting the distances L1 and L2.

[0020] Based on these considerations, the inventors have found that latch-up failure of the switching element 10 can be suppressed by defining the relationship between the distance L1 from the lower end of the trench 22 in the thickness direction (z direction) of the semiconductor substrate 12 to the interface between the emitter region 30 and the body region 33, and the distance L2 from the gate insulating film 24 to the body contact region 32 in the in-plane (xy plane) along the upper surface 12a of the semiconductor substrate 12. More specifically, distance L2 is the shortest distance from the position C1 (see Figure 1) furthest from the body contact region 32 within the range where the emitter region 30 is in contact with the gate insulating film 24 to the body contact region 32. In the switching element 10 of Embodiment 1, as shown in Figure 1, the emitter region 30 and the body contact region 32 extend parallel to the trench 22 along the y direction. Therefore, in this embodiment, the shortest distance L2 is the distance along the x direction from position C1 (in other words, the gate insulating film 24) to the body contact region 32. In the following, distance L1 may be referred to as "depth distance L1," and distance L2 may be referred to as "EN shortest distance L2."

[0021] Figure 4 is a graph showing the measured dv / dt tolerance with respect to the shortest EN distance L2 when the depth distance L1 is approximately 4 μm. As shown in Figure 4, when the depth distance L1 is approximately 4 μm, it can be seen that the dv / dt tolerance decreases significantly when the shortest EN distance L2 exceeds approximately 1.35 μm. In other words, as mentioned above, latch-up occurs. The point at which the dv / dt tolerance decreases sharply, as in the case where the shortest EN distance L2 is 1.35 μm in Figure 4, will be referred to as the critical point below.

[0022] Figure 5 is a graph plotting the critical point at which the dv / dt tolerance decreases sharply when the depth distance L1 and the shortest EN distance L2 are changed, respectively. As shown in Figure 5, the longer the depth distance L1, the longer the shortest EN distance L2 at the critical point. Even when the shortest EN distance L2 is long, by ensuring a long depth distance L1, the number of holes flowing into the body region 33 is reduced, thus suppressing the decrease in dv / dt tolerance. Conversely, even when the depth distance L1 is short, by shortening the shortest EN distance L2, the distance the holes travel within the body region 33 is shortened, and the resistance to the holes is reduced, thus suppressing the decrease in dv / dt tolerance.

[0023] Line A1 in Figure 5 represents the approximate line for each plot and can be expressed as L2 = 0.429L1 - 0.318. By setting distances L1 and L2 such that the relationship L2 ≤ 0.429L1 - 0.318 (i.e., within the hatched region in Figure 5), latch-up can be effectively suppressed.

[0024] (Example 2) In the switching element 100 of Example 2 shown in Figures 6 and 7, the configuration of the emitter region 130 and the body contact region 132 differs from that of Example 1. As shown in Figures 6 and 7, when viewed along the z-direction, a part of the emitter region 130 and a part of the body contact region 132 overlap. In the area where the emitter region 130 and the body contact region 132 overlap, the emitter region 130 is in contact with the emitter electrode 70, and the body contact region 132 is in contact with the emitter region 130 from below. That is, the width of the emitter region 130 in the x-direction is narrower near the body region 33 than near the upper surface 12a of the semiconductor substrate 12. On the other hand, the width of the body contact region 132 in the x-direction is wider near the body region 33 than near the upper surface 12a of the semiconductor substrate 12. The other configurations (drift region 34, collector region 36, etc.) are the same as in Example 1.

[0025] In Example 2, distance L2 is the shortest distance from the body contact region 132 to the body contact region 132, which is the furthest point from the body contact region 132 within the range where the emitter region 130 is in contact with the gate insulating film 24, in the xy plane. That is, in Example 2, as shown in Figures 6 and 7, distance L2 is the shortest distance from position C2 to the lower part of the body contact region 132 (i.e., the wider part in the x direction), and is shorter than distance L2 in Example 1. Even with this configuration, by setting distances L1 and L2 to satisfy the relational expression described in Example 1, latch-up of the switching element 100 can be suppressed and a high dv / dt withstand capability can be ensured.

[0026] Furthermore, in Example 2, a larger contact area can be secured between the emitter region 130 and the emitter electrode 70. Therefore, the contact resistance of the emitter region 130 with respect to the emitter electrode 70 can be reduced.

[0027] (Example 3) In the switching element 200 of Example 3 shown in Figure 8, the configuration of the emitter region 230 and the body contact region 232 differs from that of Example 1. In Example 1, the body contact region 32 extended for a long distance in the y direction within the range between the two emitter regions 30, but in Example 3, as shown in Figure 8, the body contact regions 232 are intermittently arranged along the y direction. The emitter region 230 is in contact with the periphery of each body contact region 232. Each body contact region 232 is separated from the gate insulating film 24 by the emitter region 230. The other configurations (body region 33, drift region 34, collector region 36, etc.) are the same as in Example 1. As shown in Figure 8, the distance L2 is the shortest distance from the position C3 furthest from the body contact region 232 within the range where the emitter region 230 is in contact with the gate insulating film 24, to the body contact region 232 in the xy plane. In other words, in Example 3, the position of position C3 in the y-direction is the midpoint between two adjacent body contact regions 232. Even with this configuration, by setting distances L1 and L2 to satisfy the relational expression described in Example 1, latch-up of the switching element 200 can be suppressed and a high dv / dt withstand capability can be ensured.

[0028] (Example 4) In the switching element 300 of Example 4 shown in Figure 9, the configuration of the emitter region 330 and the body contact region 332 differs from that of Example 3. As shown in Figure 9, when viewed along the z direction, a part of the emitter region 330 and a part of the body contact region 332 overlap. In the area where the emitter region 330 and the body contact region 332 overlap, the emitter region 330 is in contact with the emitter electrode 70, and the body contact region 332 is in contact with the emitter region 330 from below. That is, the width of the emitter region 330 in the x and y directions is narrower near the body region than near the top surface of the semiconductor substrate. On the other hand, the width of the body contact region 332 in the x and y directions is wider near the body region than near the top surface of the semiconductor substrate. That is, the configuration of the xz cross section in the area where the emitter region 330 is provided is the same as in Figure 7. Other configurations (drift region 34, collector region 36, etc.) are the same as in Example 3.

[0029] In Example 4, as shown in Figure 9, distance L2 is the shortest distance in the xy plane from position C4, which is the furthest point from the body contact region 332 within the range where the emitter region 330 contacts the gate insulating film 24, to the lower part of the body contact region 332 (i.e., the wider part in the x direction). In other words, in Example 4, the y-direction position of position C4 is the midpoint between two adjacent body contact regions 332. Even with this configuration, by setting distances L1 and L2 to satisfy the relational expression described in Example 1, latch-up of the switching element 300 can be suppressed and a high dv / dt withstand capability can be ensured.

[0030] Furthermore, in Example 4, a larger contact area can be secured between the emitter region 330 and the emitter electrode 70. As a result, the contact resistance of the emitter region 330 with respect to the emitter electrode 70 can be reduced.

[0031] (Example 5) In the switching element 400 of Example 5 shown in Figures 10 and 11, the configuration of the emitter region 430 and the body region 433 differs from that of Example 1. As shown in Figures 10 and 11, a part of the body region 433 is exposed on the upper surface 12a of the semiconductor substrate 12. The emitter region 430 is divided by the body region 433 and the body contact region 432. Multiple emitter regions 430 are arranged with spacing along the y-direction in the range between two adjacent trenches 22.

[0032] In Example 5, as shown in Figure 10, distance L2 is the shortest distance from position C5, which is the furthest point from the body contact region 432 within the range where the emitter region 430 is in contact with the gate insulating film 24, to the body contact region 432 in the xy plane. That is, in Example 5, the position of position C5 in the y direction is the center of the emitter region 430. Even with this configuration, by setting distances L1 and L2 to satisfy the relational expression described in Example 1, latch-up of the switching element 500 can be suppressed and a high dv / dt withstand capability can be ensured.

[0033] (Example 6) In the switching element 500 of Example 6 shown in Figure 12, the configuration of the emitter region 530 and the body contact region 532 differs from that of Example 5. As shown in Figure 12, when viewed along the z-direction, a part of the emitter region 530 and a part of the body contact region 532 overlap. In the area where the emitter region 530 and the body contact region 532 overlap, the emitter region 530 is in contact with the emitter electrode 70, and the body contact region 532 is in contact with the emitter region 530 from below. That is, the width of the emitter region 530 in the y-direction is narrower near the body region than near the top surface of the semiconductor substrate. On the other hand, the width of the body contact region 532 in the y-direction is wider near the body region than near the top surface of the semiconductor substrate. The other configurations (drift region 34, collector region 36, etc.) are the same as in Example 5.

[0034] In Example 6, as shown in Figure 12, distance L2 is the shortest distance from position C6, which is the furthest point from the body contact region 532 within the range where the emitter region 530 is in contact with the gate insulating film 24, to the body contact region 532 in the xy plane. That is, in Example 6, the position of position C6 in the y direction is the center of the emitter region 530. Also, in Example 6, distance L2 is the distance from position C6 to the lower part of the body contact region 532 (i.e., the corner P6 of the wider part in the y direction), and is shorter than distance L2 in Example 5. Even with this configuration, by setting distances L1 and L2 to satisfy the relational expression described in Example 1, latch-up of the switching element 400 can be suppressed and a high dv / dt withstand capability can be ensured.

[0035] Furthermore, in Example 6, a larger contact area can be secured between the emitter region 530 and the emitter electrode 70. As a result, the contact resistance of the emitter region 530 with respect to the emitter electrode 70 can be reduced.

[0036] (Example 7) In the switching element 600 of Example 7 shown in Figure 13, a plurality of trenches 621 and a plurality of trenches 622 are formed on the upper surface of the semiconductor substrate. Each trench 622 extends linearly in the x direction. The plurality of trenches 622 are arranged with spacing in the y direction. Each trench 621 extends linearly in the y direction. A plurality of trenches 621 are arranged in each range sandwiched between two trenches 622. Both ends of each trench 621 are connected to the trenches 622 on either side of it. Each trench 621 is positioned so as to be offset in the x direction from other trenches 621 adjacent to it in the x direction. At each end of the trench 621, it intersects with each trench 622 in a three-way intersection. The upper surface of the semiconductor substrate is divided into rectangular regions by the trenches 621 and 622. Hereinafter, the rectangular semiconductor region divided by each side of the trenches 621 and 622 will be referred to as the rectangular region 650. The inner surfaces (i.e., the bottom and sides) of each trench 621, 622 are covered with a gate insulating film 624. A gate electrode 626 is positioned inside each trench 621, 622. The gate electrode 626 spans the interior of trench 621 and the interior of trench 622. Therefore, the gate electrode 626 extends in a rectangular shape along the shape of the trenches 621, 622. Thus, as shown in Figure 13, when viewed from above in plan, the periphery of each rectangular region 650 is surrounded by the gate electrode 626. The upper surface of the gate electrode 626 is covered with an interlayer insulating film (not shown). In addition, the upper surface of the semiconductor substrate and the upper surface of the interlayer insulating film are covered with an emitter electrode (not shown).

[0037] The structure of each rectangular region 650 will now be described. Since the structure of each rectangular region 650 is the same as that of the others, the structure of one rectangular region 650 will be described below. Figure 14 shows an enlarged plan view of one rectangular region 650. As shown in Figure 14, the emitter region 630, the body contact region 632, and the body region 633 are arranged inside the rectangular region 650 in the area exposed on the upper surface of the semiconductor substrate. The structure below the emitter region 630 and the body contact region 632 inside the semiconductor substrate is the same as in Embodiment 1.

[0038] Within the rectangular region 650, two emitter regions 630 are provided. Each emitter region 630 is in contact with the gate insulating film 624 and the emitter electrode at a position where it is in contact with two of the four sides 621a, 621b, 622a, and 622b of the trenches 621 and 622 that constitute the rectangular region 650, namely sides 621a and 621b. The emitter region 630 is in contact with the gate insulating film 624 at the center of sides 621a and 621b.

[0039] The body region 633 is positioned to be in contact with the gate insulating film 624 in the area where the emitter region 630 is not provided. That is, the body region 633 is in contact with the gate insulating film 624 on two sides 622a and 622b, and on two sides 621a and 621b in the area where the emitter region 630 is not provided.

[0040] The body contact region 632 is located in the center of the rectangular region 650. The body contact region 632 is separated from the gate insulating film 624 by the emitter region 630 and the body region 633.

[0041] The distance L2 in Example 7 will now be explained. In Example 7, distance L2 is the distance from the position C7 furthest from the body contact region 632 within the range R1 (shown by a thick line) in which the emitter region 630 is in contact with the gate insulating film 624, to the body contact region 632 (i.e., the position P7 closest to the above position C7 within the range R2 (shown by a thick line) in which the emitter region 630 is in contact with the body contact region 632). In other words, in Example 7, the position of position C7 in the y direction is the center of the emitter region 630. Distance L1 is the distance from the lower end of the trenches 621 and 622 in the z direction to the interface between the emitter region 630 and the body region 633, similar to Example 1. In Example 7 as well, by setting distances L1 and L2 to satisfy the relational expression explained in Example 1, latch-up of the switching element 600 can be suppressed and a high dv / dt withstand voltage can be ensured.

[0042] (Example 8) In the switching element 700 of Example 8 shown in FIG. 15, in the rectangular region 750, the configurations of the emitter region 730 and the body contact region 732 are different from those of Example 7. As shown in FIG. 15, when viewed along the z direction, a part of the emitter region 730 and a part of the body contact region 732 overlap. In the overlapping range of the emitter region 730 and the body contact region 732, the emitter region 730 is in contact with the emitter electrode, and the body contact region 732 is in contact with the emitter region 730 from below. That is, when viewed along the z direction, the area of the emitter region 730 is smaller near the body region 633 than near the upper surface of the semiconductor substrate. On the other hand, when viewed along the z direction, the area of the body contact region 732 is larger near the body region 633 than near the upper surface of the semiconductor substrate. Other configurations (drift region 34, collector region 36, etc.) are the same as those of Example 7.

[0043] In Example 8, as shown in FIG. 15, the distance L2 is the shortest distance in the xy plane from the position C8, which is the farthest position from the body contact region 732 in the range R3 (indicated by the thick line) where the emitter region 730 contacts the gate insulating film 624, to the body contact region 732 (that is, the position P8, which is the closest position to the position C8 among the ranges where the emitter region 730 contacts the body contact region 732). That is, in Example 8, the y-direction position of the position C8 is the center of the emitter region 730. Also, in Example 8, the distance L2 is the distance from the position C8 to the lower part of the body contact region 732 (that is, the position P8 indicated by the broken line), and is shorter than the distance L2 of Example 7. Even with such a configuration, by setting the distance L1 and the distance L2 so as to satisfy the relational expression described in Example 1, the latch-up of the switching element 700 can be suppressed, and a high dv / dt tolerance can be ensured.

[0044] Also, in Example 8, a wide area where the emitter region 730 contacts the emitter electrode can be ensured. Therefore, the contact resistance of the emitter region 730 with respect to the emitter electrode can be reduced.

[0045] (Example 9) In the switching element 800 of Example 9 shown in Figure 16, the configuration of the emitter region 830 and the body contact region 832 in the rectangular region 850 differs from that of Example 7. In Example 9, as explained in Example 8, distance L2 is the distance from the position C9 furthest from the body contact region 832 in the range R4 (shown by a thick line) where the emitter region 830 is in contact with the gate insulating film 624 in the xy plane, to the body contact region 832 (i.e., the position P9 closest to position C9 in the range where the emitter region 830 is in contact with the body contact region 832), and is shorter than the distance L2 in Example 7. Even with this configuration, by setting distances L1 and L2 to satisfy the relational expression explained in Example 1, latch-up of the switching element 800 can be suppressed and a high dv / dt withstand capability can be ensured.

[0046] Furthermore, in Example 9, a large contact area between the emitter region 830 and the emitter electrode can be secured. Therefore, the contact resistance of the emitter region 830 with respect to the emitter electrode can be reduced.

[0047] (Example 10) In the switching element 900 of Example 10 shown in Figure 17, the configuration of the emitter region 930 and the body region 933 differs from that of Example 1. As shown in Figure 17, a part of the body region 933 is exposed on the upper surface 12a of the semiconductor substrate 12. The emitter region 930 is divided by the body region 933. Multiple emitter regions 930 are arranged at intervals along the y-direction.

[0048] In Example 10, as shown in FIG. 17, the distance L2 is the shortest distance from the position C10, which is the farthest from the body contact region 932 among the ranges where the emitter region 930 contacts the gate insulating film 24 in the xy plane, to the body contact region 932. That is, in Example 10, the distance L2 is the distance along the x direction from the position C10 (in other words, the gate insulating film 24) to the body contact region 932. Even with such a configuration, by setting the distance L1 and the distance L2 so as to satisfy the relational expression described in Example 1, the latch-up of the switching element 900 can be suppressed and a high dv / dt tolerance can be ensured.

[0049] (Corresponding relationship) The emitter regions 30, 130, 230, 330, 430, 530, 630, 730, 830, 930 are examples of the "upper n-type region". The emitter electrode 70 and the collector electrode 72 are examples of the "upper electrode" and the "lower electrode", respectively.

[0050] In the above-described examples, the IGBT is exemplified as the switching element, but the switching element may be, for example, a MOSFET.

[0051] The configurations of the trench gate type switching elements disclosed herein are listed below. (Configuration 1) A trench gate type switching element (10, 100, 200, 300, 400, 500, 600, 700, 800, 900) comprising: a semiconductor substrate (12); trenches (22, 621, 622) provided on the upper surface of the semiconductor substrate; a gate insulating film (24, 624) covering the inner surface of the trenches; gate electrodes (26, 626) disposed within the trenches and insulated from the semiconductor substrate by the gate insulating film; and an upper electrode (70) in contact with the upper surface of the semiconductor substrate, wherein the semiconductor substrate has an upper n-type region (30, 130, 230, 330, 430, 530, 630, 730, 830, 930) in contact with the upper electrode and the gate insulating film, The semiconductor substrate has: p-type body contact regions (32, 132, 232, 332, 432, 532, 632, 732, 832, 932) in contact with the upper electrode and adjacent to the upper n-type region; p-type body regions (33, 433, 533, 633, 933) located below the upper n-type region and the body contact regions, in contact with the gate insulating film below the upper n-type region, and having a lower p-type impurity concentration than the body contact regions; and n-type drift regions (34) located below the body regions, in contact with the gate insulating film below the body regions, and separated from the upper n-type region by the body regions, wherein the distance from the lower end of the trench in the thickness direction of the semiconductor substrate to the interface between the upper n-type region and the body region is L1. A trench gate type switching element in which, within the plane along the upper surface of the semiconductor substrate, the shortest distance from the position furthest from the body contact region within the range in which the upper n-type region contacts the gate insulating film to the body contact region is L2, and the relationship L2 ≤ 0.429 L1 - 0.318 is satisfied.(Configuration 2) The trench gate type switching element according to Configuration 1, wherein when the semiconductor substrate is viewed from above, the trench is rectangular in shape with four sides (621a, 621b, 622a, 622b), the upper n-type region is in contact with the upper electrode and the gate insulating film at a position in contact with a first set of two opposing sides of the four sides within the rectangular region (650, 750, 850) enclosed by the rectangular shape, the body region is in contact with the upper electrode and the gate insulating film at a position in contact with a second set of two sides other than the first set of sides of the four sides within the rectangular region, the body contact region is in contact with the upper electrode in the central part of the rectangular region and is separated from the gate insulating film by the upper n-type region and the body region. (Configuration 3) A trench gate type switching element according to Configuration 1 or 2, further comprising a lower electrode (72) in contact with the lower surface of the semiconductor substrate, wherein the semiconductor substrate is located below the drift region, separated from the body region by the drift region, and further comprises a p-type collector region (36) in contact with the lower electrode.

[0052] Although the examples have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness.

Claims

1. A trench gate type switching element (10, 100, 200, 300, 400, 500, 600, 700, 800, 900) comprising: a semiconductor substrate (12); trenches (22, 621, 622) provided on the upper surface of the semiconductor substrate; a gate insulating film (24, 624) covering the inner surface of the trenches; gate electrodes (26, 626) disposed within the trenches and insulated from the semiconductor substrate by the gate insulating film; and an upper electrode (70) in contact with the upper surface of the semiconductor substrate, wherein the semiconductor substrate has an upper n-type region (30, 130, 230, 330, 430, 530, 630, 730, 830, 930) in contact with the upper electrode and the gate insulating film, The semiconductor substrate has: p-type body contact regions (32, 132, 232, 332, 432, 532, 632, 732, 832, 932) in contact with the upper electrode and adjacent to the upper n-type region; p-type body regions (33, 433, 533, 633, 933) located below the upper n-type region and the body contact regions, in contact with the gate insulating film below the upper n-type region, and having a lower p-type impurity concentration than the body contact regions; and n-type drift regions (34) located below the body regions, in contact with the gate insulating film below the body regions, and separated from the upper n-type region by the body regions, wherein the distance from the lower end of the trench in the thickness direction of the semiconductor substrate to the interface between the upper n-type region and the body region is L1. A trench gate type switching element in which, within the plane along the upper surface of the semiconductor substrate, the shortest distance from the position furthest from the body contact region within the range in which the upper n-type region contacts the gate insulating film to the body contact region is L2, and the relationship L2 ≤ 0.429 L1 - 0.318 is satisfied.

2. The trench gate type switching element according to claim 1, wherein, when the semiconductor substrate is viewed from above, the trench is rectangular in shape having four sides (621a, 621b, 622a, 622b), the upper n-type region is in contact with the upper electrode and the gate insulating film at a position in contact with a first set of two opposing sides of the four sides within the rectangular region (650, 750, 850) enclosed by the rectangular shape, the body region is in contact with the upper electrode and the gate insulating film at a position in contact with a second set of two sides of the four sides other than the first set, within the rectangular region, the body contact region is in contact with the upper electrode in the central part of the rectangular region and is separated from the gate insulating film by the upper n-type region and the body region.

3. The trench gate type switching element according to claim 1 or 2, further comprising a lower electrode (72) in contact with the lower surface of the semiconductor substrate, wherein the semiconductor substrate is located below the drift region, separated from the body region by the drift region, and further comprises a p-type collector region (36) in contact with the lower electrode.

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