Multilayer ceramic capacitor
By adding Dy, Ti, or Zr, and Ba to the dielectric regions of multilayer ceramic capacitors with controlled ratios and grain sizes, the capacitors achieve enhanced high-temperature load reliability and improved capacitance.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- MURATA MFG CO LTD
- Filing Date
- 2025-11-26
- Publication Date
- 2026-06-04
AI Technical Summary
Existing multilayer ceramic capacitors face challenges in maintaining high-temperature load reliability over a prolonged period, despite improvements in insulation and lifespan characteristics through grain particle size reduction.
Incorporating Dy, Ti, or Zr, and Ba into the dielectric regions of multilayer ceramic capacitors, with specific ratios of these components and adjusted average grain sizes, to restrict oxygen vacancy movement and enhance high-temperature load reliability.
The solution effectively maintains high-temperature load reliability by improving effective capacitance and reducing structural defects, ensuring reliable performance over extended periods.
Smart Images
Figure JP2025041090_04062026_PF_FP_ABST
Abstract
Description
Multilayer ceramic capacitor
[0001] This invention relates to a multilayer ceramic capacitor.
[0002] Multilayer ceramic capacitors, which consist of a laminate in which dielectric layers and internal electrode layers are alternately stacked, and external electrodes electrically connected to the internal electrode layers, are a type of electronic component used in a wide range of fields, including communications, IoT, automotive, and medical.
[0003] In recent years, there has been a growing need for miniaturization and increased capacitance, and multilayer ceramic capacitors have been developed to maintain insulation even when miniaturized (Patent Documents 1 and 2). In particular, Patent Document 2 describes the development of a multilayer ceramic capacitor that improves insulation and lifespan characteristics by reducing the particle size of the grains in the dielectric layer.
[0004] Japanese Patent Publication No. 2023-124814 Japanese Patent Publication No. 2008-078593
[0005] However, even when the lifespan characteristics of multilayer ceramic capacitors are improved by adjusting the grain particle size, the high-temperature load reliability is not necessarily sufficient, and there is a need to develop multilayer ceramic capacitors that can maintain high-temperature load reliability over a longer period of time.
[0006] The present invention aims to provide a multilayer ceramic capacitor that can maintain high-temperature load reliability over a long period of time.
[0007] The inventors of the present invention have discovered that high-temperature load reliability can be maintained over a long period of time by adding Dy, Ti or Zr, and Ba to the dielectric region constituting a multilayer ceramic capacitor, and by adjusting the content of these components and the average grain size of the dielectric region, thereby completing the present invention.
[0008] In other words, the present invention provides a laminate having an inner layer portion formed by laminating an inner electrode layer and an inner dielectric layer; a main surface side dielectric region forming two opposing main surfaces sandwiching the inner layer portion from the lamination direction; and a side side dielectric region forming two opposing sides sandwiching the inner layer portion and the main surface side dielectric region from a width direction intersecting the lamination direction; and an external electrode disposed on two opposing end faces in the length direction intersecting the lamination direction and the width direction of the laminate, and connected to the inner electrode layer, wherein the inner dielectric layer, the main surface side dielectric region, and the side side dielectric region each contain Dy, Ti or Zr, and Ba, and the ratio of the content of Dyi to the average particle size D50i of dielectric grains in the inner dielectric layer, Dyi / D50i, is greater than the ratio of the content of Dyw to the average particle size D50w of dielectric grains in the side side dielectric region, Dyw / D50w. In the multilayer ceramic capacitor, the ratio of the content of Ba (Bai) to the sum of the content of Ti (Tii) and Zr (Zri) in the internal dielectric layer, Bai / (Tii + Zri), is greater than the ratio of the content of Ba (Baw) to the sum of the content of Ti (Tiw) and Zr (Zrw) in the side dielectric region, Baw / (Tiw + Zrw).
[0009] According to the present invention, by restricting oxygen vacancy movement in the internal dielectric layer of the inner layer constituting the multilayer ceramic capacitor, it becomes possible to maintain high-temperature load reliability over a long period of time.
[0010] This is a perspective view showing a multilayer ceramic capacitor according to this embodiment. This is a cross-sectional view (LT section) of the multilayer ceramic capacitor shown in Figure 1, taken along line II-II. This is a cross-sectional view (WT section) of the multilayer ceramic capacitor shown in Figure 1, taken along line III-III. This is a cross-sectional view (LW section) of the multilayer ceramic capacitor shown in Figure 3, taken along line IV-IV. This shows the internal electrode pattern formed on the dielectric sheet. This shows the internal electrode pattern formed on the dielectric sheet. This is a diagram illustrating the process of forming the multilayer ceramic capacitor shown in Figure 1. This is a diagram illustrating the process of forming the multilayer ceramic capacitor shown in Figure 1.
[0011] The following describes embodiments of the multilayer ceramic capacitor of the present invention, but the present invention is not limited thereto. Furthermore, the drawings may be schematically simplified to illustrate the content of the invention, and the ratios of dimensions of the depicted components or between components may not match the ratios of those dimensions described in the specification. Also, components described in the specification may be omitted in the drawings, or their quantities may be omitted.
[0012] (Multilayer Ceramic Capacitor) Figure 1 is a perspective view showing a multilayer ceramic capacitor, Figure 2 is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 1 along line II-II, and Figure 3 is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 1 along line III-III. Figure 4 is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 3 along line IV-IV. The multilayer ceramic capacitor 1 shown in Figures 1 to 4 comprises a laminate 10 and external electrodes 40. The external electrodes 40 include a first external electrode 41 and a second external electrode 42.
[0013] Figures 1 to 4 show the XYZ Cartesian coordinate system. The X direction is the length direction L of the multilayer ceramic capacitor 1 and the laminate 10, the Y direction is the width direction W of the multilayer ceramic capacitor 1 and the laminate 10, and the Z direction is the stacking direction T of the multilayer ceramic capacitor 1 and the laminate 10. Accordingly, the cross section shown in Figure 2 is also called the LT cross section, the cross section shown in Figure 3 is also called the WT cross section, and the cross section shown in Figure 4 is also called the LW cross section.
[0014] Furthermore, the length direction L, width direction W, and stacking direction T are not necessarily orthogonal to each other; they may intersect.
[0015] The laminate 10 has a substantially rectangular parallelepiped shape and includes a first main surface TS1 and a second main surface TS2 facing the stacking direction T, a first side surface WS1 and a second side surface WS2 facing the width direction W, and a first end surface LS1 and a second end surface LS2 facing the length direction L. The surface of each face may have irregularities or be rough.
[0016] When there is no need to distinguish between the first main surface TS1 and the second main surface TS2, they are collectively referred to as the main surface TS; when there is no need to distinguish between the first side surface WS1 and the second side surface WS2, they are collectively referred to as the side surface WS; and when there is no need to distinguish between the first end surface LS1 and the second end surface LS2, they are collectively referred to as the end surface LS.
[0017] It is preferable that the edges and corners of the laminate 10 are rounded. The edges are the parts where two faces of the laminate 10 intersect, and the corners are the parts where three faces of the laminate 10 intersect.
[0018] As shown in Figures 2 and 3, the laminate 10 has a plurality of internal dielectric layers 20i and a plurality of internal electrode layers 30 stacked in the stacking direction T. The laminate 10 also has an inner layer portion 100 and a first outer layer portion 201 and a second outer layer portion 202 arranged to sandwich the inner layer portion 100 in the stacking direction T.
[0019] The inner layer 100 includes a plurality of internal dielectric layers 20i and a plurality of internal electrode layers 30. The inner layer 100 is a region sandwiched between the internal electrode layers 30 located at both ends in the stacking direction T, where the internal dielectric layers 20i and internal electrode layers 30 are stacked alternately. The inner layer 100 is a portion in which the plurality of internal electrode layers 30 are arranged facing each other via the internal dielectric layers 20i, generating capacitance and functioning substantially as a capacitor.
[0020] The thickness of the internal dielectric layer 20i is not particularly limited, but is preferably 0.2 μm or more and 10 μm or less, and more preferably 0.4 μm or more and 7 μm or less.
[0021] The first outer layer 201 is positioned on the side of the first main surface TS1 of the laminate 10, and the second outer layer 202 is positioned on the side of the second main surface TS2 of the laminate 10. More specifically, the first outer layer 201 is positioned between the internal electrode layer 30 closest to the first main surface TS1 and the first main surface TS1, and the second outer layer 202 is positioned between the internal electrode layer 30 closest to the second main surface TS2 and the second main surface TS2.
[0022] The material of the dielectric region 20, which includes the internal dielectric layer 20i and the main surface side dielectric region 20t, is, for example, BaTiO ３ CaTiO ３ SrTiO ３ , or CaZrO ３ A dielectric ceramic containing the above as its main component can be used. The dielectric region 20, including the internal dielectric layer 20i and the main surface side dielectric region 20t, contains, in addition to the above main component, Dy, Ti or Zr, and Ba as additives. The dielectric region 20 may also contain glass. The glass is SiO ２ It can be the main component, but is not limited to this.
[0023] The multiple internal electrode layers 30 include a plurality of first internal electrode layers 31 and a plurality of second internal electrode layers 32.
[0024] The first internal electrode layer 31 includes a facing portion 311 and a leading portion 312, and the second internal electrode layer 32 includes a facing portion 321 and a leading portion 322.
[0025] The opposing portion 311 of the first internal electrode layer 31 and the opposing portion 321 of the second internal electrode layer 32 face each other via the internal dielectric layer 20i in the stacking direction T of the laminate 10. The shapes of the opposing portions 311 and 321 are not particularly limited and may be, for example, substantially rectangular. The opposing portions 311 and 321 are parts that generate capacitance and function substantially as capacitors.
[0026] The lead-out portion 312 of the first internal electrode layer 31 extends from the opposing portion 311 toward the first end face LS1 of the laminate 10 and is exposed at the first end face LS1. The lead-out portion 322 of the second internal electrode layer 32 extends from the opposing portion 321 toward the second end face LS2 of the laminate 10 and is exposed at the second end face LS2.
[0027] As a result, the first internal electrode layer 31 is connected to the first external electrode 41, and a gap is provided between the first internal electrode layer 31 and the second end face LS2 of the laminate 10, i.e., the second external electrode 42. Also, the second internal electrode layer 32 is connected to the second external electrode 42, and a gap is provided between the second internal electrode layer 32 and the first end face LS1 of the laminate 10, i.e., the first external electrode 41.
[0028] The first internal electrode layer 31 and the second internal electrode layer 32 may contain, for example, at least one of the following as a main component or as a component other than the main component: a metal such as Ni, Cu, Ag, Pd, or Au, or an Ag-Pd alloy. Furthermore, the first internal electrode layer 31 and the second internal electrode layer 32 may also contain dielectric particles of the same composition system as the ceramic contained in the internal dielectric layer 20i as a component other than the main component. In this specification, the main component metal refers to the metal component with the highest weight %. In addition, a layer of metal components other than the main component of the first internal electrode layer 31 and the second internal electrode layer 32 (for example, Sn, etc.) may be arranged around the first internal electrode layer 31 and the second internal electrode layer 32.
[0029] The thickness of the first internal electrode layer 31 and the second internal electrode layer 32 is not particularly limited, but is preferably 0.30 μm or more and 1.50 μm or less, and more preferably 0.30 μm or more and 1.35 μm or less. The number of the first internal electrode layer 31 and the second internal electrode layer 32 is not particularly limited, but is preferably 10 or more and 1000 or less.
[0030] Furthermore, a method for measuring the thickness of the internal dielectric layer 20i and the internal electrode layer 30 is, for example, to observe the LT cross-section near the center in the width direction of the laminate exposed by polishing using a scanning electron microscope. In addition, each value may be the average of measurements taken at multiple locations in the length direction, or further, the average of measurements taken at multiple locations in the lamination direction.
[0031] As shown in FIG. 3, in the width direction W, the laminate 10 has an electrode facing portion W30 where the internal electrode layer 30 faces, and a first side margin portion WG1 and a second side margin portion WG2 arranged so as to sandwich the electrode facing portion W30. The electrode facing portion W30 is composed of an inner layer portion 100 where the internal electrode layer 30 and the internal dielectric layer 20i are laminated, and two outer layer portions 200 arranged so as to sandwich the inner layer portion 100 from the lamination direction T. That is, the first side margin portion WG1 and the second side margin portion WG2 are arranged so as to sandwich the inner layer portion 100 and the two outer layer portions 200 from the width direction W.
[0032] The first side margin portion WG1 is located between the electrode facing portion W30 and the first side surface WS1, and the second side margin portion WG2 is located between the electrode facing portion W30 and the second side surface WS2. More specifically, the first side margin portion WG1 is located between the end on the first side surface WS1 side of the internal electrode layer 30 and the first side surface WS1, and the second side margin portion WG2 is located between the end on the second side surface WS2 side of the internal electrode layer 30 and the second side surface WS2. The first side margin portion WG1 and the second side margin portion WG2 are formed by a side surface side dielectric region 20w. Incidentally, the first side margin portion WG1 and the second side margin portion WG2 are also referred to as a side gap or a W gap.
[0033] As the material of the side surface side dielectric region 20w that forms the first side margin portion WG1 and the second side margin portion WG2, for example, dielectric ceramics containing, as a main component, BaTiO ３ , CaTiO ３ , SrTiO ３ , or CaZrO ３ etc. can be used. In addition to the above main components, the side surface side dielectric region 20w contains Dy, Ti or Zr, and Ba as additives.
[0034] The side surface side dielectric region 20w may contain glass. The glass is SiO ２Although it can be the main component, it is not limited thereto. The glass content in the side dielectric region 20w is preferably more than the glass content in the internal dielectric layer 20i.
[0035] The thickness of the side dielectric region 20w is not particularly limited, but for example, it is preferably 2 μm or more and 40 μm or less, and more preferably 4 μm or more and 30 μm or less.
[0036] FIG. 3 shows the side margin portion WG formed by the inner region WGi and the outer region WGo, but it is not limited to being two regions. The side margin portion WG may be formed by one region or may be formed by three or more regions.
[0037] The side margin portion WG can include an inner region and an outer region arranged in the width direction W (not shown). The inner region can be the region located on the innermost layer portion 100 side when the side margin portion is divided into five regions by dividing it into five equal parts in the width direction W. The outer region can be the region located on the most side surface WS side when the side margin portion is divided into five regions by dividing it into five equal parts in the width direction W.
[0038] The porosity of the outer region is preferably higher than the porosity of the inner region. By making the porosity of the outer region higher than the porosity of the inner region, it becomes possible to stably mold the laminate 10. Note that the porosity is the area ratio occupied by pores in the visual field when the WT cross section of the laminate 10 is observed with a scanning electron microscope.
[0039] As will be described later, the side margin portion WG can be formed by attaching side covering portions SC for forming the side margin portion WG to both side surfaces in the width direction W of the laminate chip 10T for forming the inner layer portion 100 and the outer layer portion 200.
[0040] As shown in Figure 2, the laminate 10 has, in the longitudinal direction L, an electrode-facing portion L30 where the first internal electrode layer 31 and the second internal electrode layer 32 of the internal electrode layer 30 face each other, a first end margin portion LG1, and a second end margin portion LG2. The first end margin portion LG1 is located between the electrode-facing portion L30 and the first end face LS1, and the second end margin portion LG2 is located between the electrode-facing portion L30 and the second end face LS2. More specifically, the first end margin portion LG1 is located between the end of the second internal electrode layer 32 on the first end face LS1 side and the first end face LS1, and the second end margin portion LG2 is located between the end of the first internal electrode layer 31 on the second end face LS2 side and the second end face LS2.
[0041] The first end margin portion LG1 includes the first internal electrode layer 31 and the dielectric region 20, but does not include the second internal electrode layer 32. Therefore, a dielectric region 20z with a thickness corresponding to the thickness of the second internal electrode layer 32 can be placed, eliminating the step at the end of the second internal electrode layer 32 on the first end face LS1 side. The second end margin portion LG2 includes the second internal electrode layer 32 and the dielectric region 20, but does not include the first internal electrode layer 31. Therefore, a dielectric region 20z with a thickness corresponding to the thickness of the first internal electrode layer 31 can be placed, eliminating the step at the end of the first internal electrode layer 31 on the second end face LS2 side. Note that the dielectric region 20z is not necessarily required, and the laminate 10 may be formed without the dielectric region 20z.
[0042] The first end margin portion LG1 functions as an extension electrode portion to the first end face LS1 of the first internal electrode layer 31, and the second end margin portion LG2 functions as an extension electrode portion to the second end face LS2 of the second internal electrode layer 32. The first end margin portion LG1 and the second end margin portion LG2 are also called L-gap.
[0043] Note that in the electrode facing portion L30, the facing portion 311 of the first internal electrode layer 31 and the facing portion 321 of the second internal electrode layer 32 described above are located. Further, in the first end margin portion LG1, the lead-out portion 312 of the first internal electrode layer 31 described above is located, and in the second end margin portion LG2, the lead-out portion 322 of the second internal electrode layer 32 described above is located.
[0044] As a method for measuring the thickness of each part of the laminate 10, for example, a method of observing an LT cross section near the center in the width direction of the laminate exposed by polishing or a WT cross section near the center in the length direction of the laminate exposed by polishing with a scanning electron microscope can be mentioned. Also, each value may be an average value of measurement values at a plurality of locations in the length direction or the width direction. Similarly, as a method for measuring the length of each part of the laminate 10, for example, a method of observing an LT cross section near the center in the width direction of the laminate exposed by polishing with a scanning electron microscope can be mentioned. Also, each value may be an average value of measurement values at a plurality of locations in the stacking direction. Similarly, as a method for measuring the width of each part of the laminate 10, for example, a method of observing a WT cross section near the center in the length direction of the laminate exposed by polishing with a scanning electron microscope can be mentioned. Also, each value may be an average value of measurement values at a plurality of locations in the stacking direction.
[0045] The external electrode 40 includes a first external electrode 41 and a second external electrode 42.
[0046] The first external electrode 41 is disposed on the first end face LS1 of the laminate 10 and is connected to the first internal electrode layer 31. The first external electrode 41 may extend from the first end face LS1 to a part of the first main face TS1 and a part of the second main face TS2. Also, the first external electrode 41 may extend from the first end face LS1 to a part of the first side face WS1 and a part of the second side face WS2.
[0047] The second external electrode 42 is positioned on the second end face LS2 of the laminate 10 and is connected to the second internal electrode layer 32. The second external electrode 42 may extend from the second end face LS2 to a part of the first main surface TS1 and a part of the second main surface TS2. The second external electrode 42 may also extend from the second end face LS2 to a part of the first side surface WS1 and a part of the second side surface WS2.
[0048] The first external electrode 41 has a base electrode layer 415 and a plating layer 416, and the second external electrode 42 has a base electrode layer 425 and a plating layer 426. The first external electrode 41 may consist only of the plating layer 416, and the second external electrode 42 may consist only of the plating layer 426.
[0049] The base electrode layers 415 and 425 may be fired layers containing metal and glass. Examples of glass include glass components containing at least one selected from B, Si, Ba, Mg, Al, or Li. Borosilicate glass can be used as a specific example. The metal mainly contains Cu. Alternatively, the metal may mainly contain at least one selected from metals such as Ni, Ag, Pd, or Au, or alloys such as Ag-Pd alloys, or may be included as a component other than the main component.
[0050] The fired layer is a layer obtained by applying a conductive paste containing metal and glass to the laminate using a dip method and then firing it. It may be fired after the firing of the internal electrode layer, or it may be fired simultaneously with the internal electrode layer. Furthermore, there may be multiple fired layers.
[0051] Alternatively, the base electrode layers 415 and 425 may be resin layers containing conductive particles and a thermosetting resin. The resin layer may be formed on the above-described firing layer, or it may be formed directly on the laminate without forming a firing layer.
[0052] The resin layer is a layer obtained by coating a laminate with a conductive paste containing conductive particles and a thermosetting resin using a coating method and then firing it. It may be fired after the firing of the internal electrode layer, or it may be fired simultaneously with the internal electrode layer. Furthermore, the resin layer may consist of multiple layers.
[0053] The thickness of each layer of the base electrode layers 415, 425, which are a fired layer or a resin layer, is not particularly limited and may be 1 μm or more and 10 μm or less.
[0054] Alternatively, the base electrode layers 415 and 425 may be thin films of 1 μm or less in thickness, formed by a thin film formation method such as sputtering or vapor deposition, and in which metal particles are deposited.
[0055] The plating layer 416 covers at least a portion of the underlying electrode layer 415, and the plating layer 426 covers at least a portion of the underlying electrode layer 425. The plating layers 416 and 426 include, for example, at least one selected from metals such as Cu, Ni, Ag, Pd, or Au, or alloys such as Ag-Pd alloys.
[0056] The plating layers 416 and 426 may each be formed from multiple layers. Preferably, they are a two-layer structure of Ni plating and Sn plating. The Ni plating layer can prevent the underlying electrode layer from being corroded by the solder when mounting ceramic electronic components, and the Sn plating layer improves the wettability of the solder when mounting ceramic electronic components, making mounting easier. The plating layers 416 and 426 can also be a three-layer structure by stacking Sn plating, Ni plating and Sn plating, respectively. The outermost layer may be Au plating.
[0057] The thickness of each plating layer 416, 426 is not particularly limited and may be 1 μm or more and 10 μm or less.
[0058] (Relationship between the internal dielectric layer and the side dielectric region) The ratio of the content of Dyi to the average particle size D50i of dielectric grains in the internal dielectric layer 20i, Dyi / D50i (mol% / nm), is greater than the ratio of the content of Dyw to the average particle size D50w of dielectric grains in the side dielectric region 20w, Dyw / D50w (mol% / nm).
[0059] Thus, by making Dyi / D50i (mol% / nm) larger than Dyw / D50w (mol% / nm), high-temperature load reliability can be improved. Specifically, by reducing the average particle size D50i of the dielectric grains in the internal dielectric layer 20i, the effective capacitance can be improved. Furthermore, by increasing the amount of Dy dissolved in the dielectric grains, oxygen vacancy movement is restricted and degradation can be suppressed, thus improving high-temperature load reliability.
[0060] Here, the Dy content is the amount of Dy dissolved in the dielectric grain (mol%) measured within a field of view of 0.5 μm × 0.5 μm, and does not include the amount of Dy at the dielectric grain interface. In addition, the average particle size D50 of the dielectric grain is measured within the same field of view, and the ratio of the Dy content to the average particle size D50 of the dielectric grain is calculated.
[0061] (Measurement of average particle size D50) The average particle size D50 can be measured, for example, by the following method. The multilayer ceramic capacitor 1 is placed vertically so that one external electrode 40 is exposed, and the area around the multilayer ceramic capacitor 1 is solidified with resin. Then, the multilayer ceramic capacitor 1 is polished with a polishing machine to approximately the height of the center. The obtained cross section is photographed using a scanning electron microscope (SEM) with a field of view of 0.5 μm × 0.5 μm, and the average particle size D50 of the dielectric grain is determined using image processing software. For example, the obtained cross section can be a WT cross section or an LT cross section. The average particle size D50 is the area circle equivalent diameter that represents 50% of the cumulative distribution of the area circle equivalent diameter of the dielectric grain, based on the number of grains. In addition, in the SEM image, the image can be binarized using a predetermined threshold to extract only the dielectric grains, and their particle size (area circle equivalent diameter) can be evaluated.
[0062] The average particle size D50i of the dielectric grains in the internal dielectric layer 20i is preferably 50 to 250 nm, and more preferably 75 to 200 nm.
[0063] The ratio of the content of Ba (Bai) to the sum of the content of Ti (Tii) and Zr (Zri) in the internal dielectric layer 20i, Bai / (Tii + Zri), is greater than the ratio of the content of Ba (Baw) to the sum of the content of Ti (Tiw) and Zr (Zrw) in the side dielectric region 20w, Baw / (Tiw + Zrw).
[0064] The ratio of Dyi / D50i to Dyw / D50w, (Dyi / D50i) / (Dyw / D50w), is preferably 1.47 or more and 2.70 or less.
[0065] If (Dyi / D50i) / (Dyw / D50w) is less than 1.47, the average particle size D50i of the dielectric grains in the internal dielectric layer 20i tends to be large, and the amount of Dy dissolved in the dielectric grains tends to be small, making it impossible to obtain good high-temperature load reliability. On the other hand, if it exceeds 2.70, the average particle size D50w of the dielectric grains in the internal dielectric layer 20i tends to be small, and the amount of Dy dissolved in the dielectric grains tends to be large, making it impossible to obtain sufficient capacitance for good high-temperature load reliability.
[0066] The ratio of Bai / (Tii+Zri) to Baw / (Tiw+Zrw) [Bai / (Tii+Zri)] / [Baw / (Tiw+Zrw)] is preferably 1.0030 or more and 1.0070 or less.
[0067] In this way, by setting [Bai / (Tii+Zri)] / [Baw / (Tiw+Zrw)] to between 1.0030 and 1.0070, the average particle size of dielectric grains in the internal dielectric layer 20i and the side dielectric region 20w becomes appropriate, enabling better improvement in effective capacitance and maintenance of high-temperature load reliability over a long period of time.
[0068] Preferably, the Dy content Dyi in the internal dielectric layer 20i is 0.9 times or more and 1.1 times or less than the Dy content Dyw in the side dielectric region 20w.
[0069] In this way, by setting the Dy content Dyi in the internal dielectric layer 20i to 0.9 times or more and 1.1 times or less of the Dy content Dyw in the side dielectric region 20w, the difference in sinterability between the internal dielectric layer 20i and the side dielectric region 20w can be reduced, thereby suppressing structural defects that occur in the internal dielectric layer 20i or the side dielectric region 20w.
[0070] (Relationship between main surface dielectric region and side surface dielectric region) The ratio of the content of Ba (Bat) to the sum of the content of Ti (Tit) and Zr (Zrt) in the main surface dielectric region 20t, Bat / (Tit + Zrt), is preferably 0.9 times or more and 1.1 times or less than the ratio of Baw / (Tiw + Zrw) in the side surface dielectric region 20w.
[0071] The internal dielectric layer 20i, the main surface dielectric region 20t, and the side dielectric region 20w preferably each contain Ni. This improves insulation reliability.
[0072] (Manufacturing Method) An example of the manufacturing method for the multilayer ceramic capacitor 1 described above will be explained. First, a dielectric sheet for the dielectric region 20 and a conductive paste for the internal electrode layer 30 are prepared. The dielectric sheet and conductive paste contain a binder and a solvent. Known materials can be used as the binder and solvent. The dielectric sheet contains Dy, Ti or Zr, and Ba, and the dielectric sheet for forming the internal dielectric layer 20i and the dielectric sheet for forming the main surface side dielectric region 20t are prepared such that the content of these components satisfies a predetermined relationship in the internal dielectric layer 20i and the main surface side dielectric region 20t in which they are formed.
[0073] An internal electrode pattern is formed on a dielectric sheet for forming the internal dielectric layer 20i by printing a conductive paste onto the dielectric sheet in a predetermined pattern, for example. Screen printing or gravure printing can be used as the method for forming the internal electrode pattern.
[0074] In mass production, dielectric sheets with two internal electrode patterns as shown in Figures 5A and 5B can be prepared. The coated portions 30N to which conductive paste is applied are spaced apart in the longitudinal direction L, and ceramic paste is applied between adjacent coated portions 30N to form height adjustment portions 20N. The height adjustment portions 20N are applied to approximately the same thickness as the thickness of the conductive paste in the coated portions 30N, canceling out the steps on the dielectric sheet caused by the application of the conductive paste and making the surface of the dielectric sheet to which the conductive paste is applied smooth. The two internal electrode layer patterns are printed offset in the longitudinal direction L, as shown in Figures 5A and 5B, and as will be described later, when the dielectric sheets of the two internal electrode patterns are alternately stacked in the stacking direction T and cut along the cutting lines x and y in the stacking direction T, an inner layer portion 100 can be formed.
[0075] The coated portion 30N to which conductive paste is applied forms the first internal electrode layer 31 and the second internal electrode layer 32 of the inner layer portion 100 in the laminated body 10 after firing, the height adjustment portion 20N forms the dielectric region 20z of the inner layer portion 100, and the dielectric sheet forms the internal dielectric layer 20i of the inner layer portion 100.
[0076] To form the main surface-side dielectric region 20t of the outer layer 200, a predetermined number of dielectric sheets for the second outer layer 202, which do not have the internal electrode pattern printed on them, are stacked. On top of that, dielectric sheets for the inner layer 100, which have two internal electrode patterns printed on them, are stacked alternately. Then, a predetermined number of dielectric sheets for the first outer layer 201, which do not have the internal electrode pattern printed on them, are stacked. This creates a laminated sheet.
[0077] Next, the laminated sheets are pressed in the lamination direction using means such as a hydrostatic press to produce a laminated block. Then, the laminated block is cut to a predetermined size in the lamination direction T along the cutting lines x and y shown in Figures 5A and 5B to cut out the laminated chip 10T.
[0078] As shown in Figure 6, the laminated chip 10T is formed in a substantially rectangular parallelepiped shape by alternately stacking multiple material sheets on the surface of a ceramic green sheet 120 for lamination, which will become the internal dielectric layer 20i, with a conductive pattern 131 that will become the first internal electrode layer 31 printed on it and a conductive pattern 132 that will become the second internal electrode layer 32 printed on it.
[0079] On one of the pair of end faces 10Ta of the laminated chip 10T, a conductive pattern 131 is exposed, and on the other end face, a conductive pattern 132 is exposed.
[0080] Furthermore, on the side surface 10Tp3 of the laminated chip 10T, all ends in the width direction W of the laminated conductive patterns 131 and 132 are aligned along the lamination direction T.
[0081] Similarly, on the side surface 10Tp4 of the laminated chip 10T, all ends in the width direction W of the laminated conductive patterns 131 and 132 are aligned along the lamination direction T.
[0082] Side covering portions SC are attached to the side surfaces 10Tp3 and 10Tp4 of the laminated chip 10T to form a first side margin portion WG1 and a second side margin portion WG2, respectively, so as to cover them.
[0083] Figure 6 shows an embodiment in which the side covering portion SC is composed of two members, an inner side covering portion SC1 and an outer side covering portion SC2. However, it is not limited to this, and can be composed of a single member or three or more members.
[0084] The ceramic slurry for forming the side coating portion SC contains Dy, Ti or Zr, and Ba, and is prepared such that the content of these components in the side dielectric region 20w formed by the side coating portion SC satisfies a predetermined relationship with the content of these components in the internal dielectric layer 20i and the main surface dielectric region 20t. Additives such as binder resin, organic solvent, plasticizer, and dispersant can be mixed into the ceramic slurry in predetermined proportions.
[0085] A ceramic slurry that forms the outer side coating SC2 is applied to the surface of a resin film and dried to obtain a ceramic green sheet that forms the outer side coating SC2.
[0086] Next, a ceramic slurry, which will form the inner side coating SC1, is applied to the surface of the ceramic green sheet, which will form the outer side coating SC2, and dried to obtain the ceramic green sheet that will form the inner side coating SC1. In this way, a ceramic green sheet that will form the side coating SC is obtained.
[0087] Although the above describes a method for forming a ceramic green sheet that forms a two-layer side covering SC, it is possible to create a ceramic green sheet with three or more layers of side coverings by further overlapping the side coverings.
[0088] Next, the ceramic green sheet that will become the inner side coating SC1 of the peeled side coating SC is placed facing the side 10Tp3 of the laminate chip 10T and punched out to attach the side coating SC. The same procedure is followed to attach the side coating SC to the side 10Tp4.
[0089] As a result of the above steps, an unfired laminated chip 10T with a side coating SC is formed, as shown in Figure 7. Next, this laminated chip 10T is fired to produce the laminate 10. The firing temperature depends on the dielectric and internal electrode materials, but is preferably between 900°C and 1400°C. Annealing is performed after firing. The annealing temperature is preferably between 1000°C and 1200°C.
[0090] Next, the conductive paste for the base electrode layer 415 is applied to the first end face LS1 of the laminate 10 by dipping it into a conductive paste, which is the electrode material for the base electrode layer, using the dipping method. Similarly, the conductive paste for the base electrode layer 425 is applied to the second end face LS2 of the laminate 10 by dipping it into a conductive paste, which is the electrode material for the base electrode layer, using the dipping method. After that, the base electrode layers 415 and 425, which are fired layers, are formed by firing these conductive pastes. The firing temperature is preferably 600°C or higher and 900°C or lower.
[0091] As described above, the base electrode layers 415 and 425, which are resin layers, may be formed by applying a conductive paste containing conductive particles and a thermosetting resin by a coating method and firing it, or the base electrode layers 415 and 425, which are thin films, may be formed by a thin film formation method such as sputtering or vapor deposition.
[0092] Subsequently, a plating layer 416 is formed on the surface of the base electrode layer 415 to form the first external electrode 41, and a plating layer 426 is formed on the surface of the base electrode layer 425 to form the second external electrode 42. Through these steps, the multilayer ceramic capacitor 1 described above is obtained.
[0093] (Evaluation Tests) The following evaluation tests were conducted to confirm the effects of the multilayer ceramic capacitor according to the present invention. Note that the present invention is not limited to these experimental examples.
[0094] (High-Temperature Load Reliability Test) Under the condition of applying 6.3V at 150°C, the time it took for the insulation resistance IR to fall below 10,000Ω was measured. Samples that took 10 hours or less to fall below 10,000Ω were counted as defective, and the defect rate relative to the total number of samples (n=100) was calculated.
[0095] (Measurement of elemental content) The amounts of Ba, Ti, Zr, and Dy contained in the internal dielectric layer and the side dielectric region were measured by elemental analysis in a WT cross section at the center of the length L. The amount of each element was measured based on the light intensity in the elemental analysis. The amount of Dy was calculated as a molar ratio based on the Ti content. The amount of Ba was calculated as a molar ratio based on the Ti and Zr content.
[0096] Next, from the average particle size D50 of dielectric grains in the internal dielectric layer and the side dielectric region, Dyi / D50i of the internal dielectric layer and Dyw / D50w of the side dielectric region were determined, and (Dyi / D50i) / (Dyw / D50w) was calculated. In addition, from the values of Bai / (Tii+Zri) of the internal dielectric layer and Baw / (Tiw+Zrw) of the side dielectric region, [Bai / (Tii+Zri)] / [Baw / (Tiw+Zrw)] was calculated.
[0097]
[0098] As shown in Table 1, experimental examples 1 to 6 showed good results in terms of high-temperature load reliability. In particular, experimental examples 2 to 6 showed good results, confirming that (Dyi / D50i) / (Dyw / D50w) was between 1.47 and 2.70, and [Bai / (Tii+Zri)] / [Baw / (Tiw+Zrw)] was between 1.0030 and 1.0070.
[0099] Although embodiments of the present invention have been described above, the present invention is not limited to these embodiments and can be implemented in various forms without departing from the spirit of the invention.
[0100] 1 Multilayer ceramic capacitor 10 Laminate 20 Dielectric region 20i Internal dielectric layer 20t Main surface dielectric region 20w Side dielectric region 20z Dielectric region 30 Internal electrode layer 31 First internal electrode layer 311 Opposing portion 312 Lead-out portion 32 Second internal electrode layer 321 Opposing portion 322 Lead-out portion 40 External electrode 41 First external electrode 415 Underlay electrode layer 416 Plating layer 42 Second external electrode 425 Underlay electrode layer 426 Plating layer 100 Inner layer 200 Outer layer 201 First outer layer 202 Second outer layer L30 Electrode opposing portion LG1 First end margin portion LG2 Second end margin portion W30 Electrode opposing portion WG1 First side margin portion WG2 Second side margin L Length direction T Lamination direction W Width direction TS Main surface TS1 First main surface TS2 Second main surface WS Side surface WS1 First side surface WS2 Second side surface LS End surface LS1 First end surface LS2 Second end surface
Claims
1. A laminate comprising: an inner layer having an inner electrode layer and an inner dielectric layer laminated together; a main surface-side dielectric region forming two opposing main surfaces sandwiching the inner layer from the lamination direction; and a side-side dielectric region forming two opposing sides sandwiching the inner layer and the main surface-side dielectric region from a width direction intersecting the lamination direction; and external electrodes arranged on two opposing end faces in the length direction intersecting the lamination direction and the width direction of the laminate, and connected to the inner electrode layer, wherein the inner dielectric layer, the main surface-side dielectric region, and the side-side dielectric region each contain Dy, Ti or Zr, and Ba, and the ratio of the content of Dy in the inner dielectric layer to the average particle size D50i of dielectric grains Dyi / D50i is greater than the ratio of the content of Dy in the side-side dielectric region to the average particle size D50w of dielectric grains Dyw / D50w. A multilayer ceramic capacitor in which the ratio of the content of Ba (Bai) to the sum of the content of Ti (Tii) and Zr (Zri) in the internal dielectric layer (Bai / (Tii + Zri)) is greater than the ratio of the content of Ba (Baw) to the sum of the content of Ti (Tiw) and Zr (Zrw) in the side dielectric region (Baw / (Tiw + Zrw)).
2. The multilayer ceramic capacitor according to claim 1, wherein the ratio of Dyi / D50i to Dyw / D50w (Dyi / D50i) / (Dyw / D50w) is 1.47 or more and 2.70 or less.
3. The multilayer ceramic capacitor according to claim 1 or 2, wherein the ratio of Bai / (Tii+Zri) to Baw / (Tiw+Zrw) [Bai / (Tii+Zri)] / [Baw / (Tiw+Zrw)] is 1.0030 or more and 1.0070 or less.
4. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein the content Dyi of Dy in the internal dielectric layer is 0.9 times or more and 1.1 times or less of the content Dyw of Dy in the side dielectric region.
5. The multilayer ceramic capacitor according to claim or claim 2, wherein the ratio of the content of Ba (Bat) to the sum of the content of Ti (Tit) and the content of Zr (Zrt) in the main surface dielectric region (Bat / (Tit+Zrt)) is 0.9 times or more and 1.1 times or less than the ratio of Baw / (Tiw+Zrw) in the side dielectric region.
6. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein the internal dielectric layer, the main surface dielectric region, and the side surface dielectric region each contain Ni.