Apparatus for counting number of defective logical units of ONFI-standard NAND flash memory

Abstract

The present invention relates to an apparatus for counting the number of defective logical units of an ONFI-standard NAND flash memory. The apparatus for counting the number of defective logical units of an ONFI-standard NAND flash memory, according to an aspect of the present invention, comprises: a chip activation latch unit having input / output terminals connected to respective chip activation pins of a plurality of logical units belonging to any one channel of the NAND flash memory; a data queue input / output unit connected to a data queue pin for data input / output for a channel of the NAND flash memory; and a processor that generates a chip activation control signal for activating only one logical unit among the plurality of logical units and deactivating the remaining logical units to control the logical units of the NAND flash memory by using the chip activation latch unit, transmits a predetermined command through the data queue input / output unit, and controls a counting unit to increase a counting number if a bit-by-bit value of data received in response to the command transmission does not correspond to a preset bit-by-bit value or if no data is received.

Description

Counting device for the number of defective logical units of ONFI standard NAND flash memory

[0001] The present invention relates to a technology for counting the number of defective logical units of a NAND flash memory of the ONFI standard.

[0002] Flash memory is a semiconductor memory that can read and write data using electrical signals and retains stored data even after the power is cut off. It has the characteristic that while reading and writing are possible in specific units within the memory, erasing must be done in block units, so an area that has been written once must be erased before it can be written again.

[0003] These flash memories can be broadly classified into the parallel NOR method and the serial NAND method. Among these, while the NAND method has slower data read speeds compared to the NOR method, it offers faster write and erase speeds because the memory blocks are divided into multiple pages, and it also boasts superior integration density per unit compared to NOR; for these reasons, it is primarily used in SSDs (Solid State Drives) and USB memory devices.

[0004] Storage devices equipped with NAND flash memory are configured such that the NAND flash memory and controller are separated into individual chips and integrated onto a single board. In the event of physical damage or failure to the device, the memory chip corresponding to the NAND flash memory is detached from the device board and installed in a recovery device equipped with a data recovery program. Data recovery is then performed by reconstructing the dumped data using the memory chip's parameter data through the recovery program.

[0005] In NAND flash memory, a Logical Unit (LU) is a logical unit that manages data. Logical Units are mapped to physical addresses to efficiently manage and optimize data, and they group physical blocks to perform address mapping, wear leveling, garbage collection, etc.

[0006] Memory chips can be damaged in various ways, such as when the epoxy packaging forming the surface is physically damaged, when internal circuits are damaged by electrical shock, or when they are submerged in water. Depending on the extent of the damage, only some of the logical units within the memory chip may be damaged. By identifying the undamaged logical units and inputting a signal to read data according to the memory chip's specifications, the data inherent in those units can be extracted. To identify the undamaged logical units, each logical unit must be tested according to the memory chip's specifications to determine whether it is producing a non-defective response. To implement a judgment method applicable to all NAND flash memory, not limited to specific memory chips, a method for identifying defective units based on unified NAND flash specifications is required.

[0007] The objective of the present invention is to solve the above problem by providing a device for counting the number of defective logical units of an ONFI standard NAND flash memory, which can count the number of defective logical units of an ONFI standard NAND flash memory when attempting recovery through a data recovery program due to physical damage or failure of the NAND flash memory.

[0008] Another objective of the present invention is to provide a device for counting the number of defective logical units in an ONFI standard NAND flash memory, which sequentially activates logical units in an ONFI standard NAND flash memory and counts the number of defective logical units with abnormal responses by utilizing the received data transmitted by a Read ID command.

[0009] The objectives of the present invention are not limited to those mentioned above, and other unmentioned objectives will be clearly understood from the description below.

[0010] A counting device for the number of defective logical units of a NAND flash memory of ONFI specifications according to one aspect of the present invention includes a chip activation latch unit having an input / output terminal connected to each chip activation pin of a plurality of logical units belonging to one channel of the NAND flash memory, a data queue input / output unit connected to a data queue pin for data input / output for a channel of the NAND flash memory, and a processor that controls the logical units of the NAND flash memory through the chip activation latch unit by generating a chip activation control signal to activate only one of the plurality of logical units and deactivate the remaining logical units, transmits a predetermined command through the data queue input / output unit, and controls a counting unit to increase the counting count when the bit value of the data received in response to the command transmission does not correspond to a preset bit value or when there is no received data.

[0011] According to the present invention, there is an advantage in that the number of defective logical units of an ONFI standard NAND flash memory can be counted in the case where a portion of the logical unit is damaged due to physical damage or failure in the NAND flash memory.

[0012] FIG. 1 is a block diagram showing a counting device for the number of defective logical units of a NAND flash memory of ONFI specifications according to one embodiment of the present invention.

[0013] FIG. 2 is a diagram illustrating a logical unit of an ONFI standard NAND flash memory to which a counting device for the number of defective logical units of an ONFI standard NAND flash memory according to one embodiment of the present invention is connected.

[0014] Figure 3 is a timing diagram of the Read ID command according to the ONFI standard.

[0015] FIG. 4 is a timing diagram for transmitting a Read ID command to a logical unit and receiving data in a counting device for the number of defective logical units of a NAND flash memory of ONFI specifications according to one embodiment of the present invention.

[0016] A counting device for the number of defective logical units of a NAND flash memory of ONFI specifications according to one aspect of the present invention includes a chip activation latch unit having an input / output terminal connected to each chip activation pin of a plurality of logical units belonging to one channel of the NAND flash memory, a data queue input / output unit connected to a data queue pin for data input / output for a channel of the NAND flash memory, and a processor that controls the logical units of the NAND flash memory through the chip activation latch unit by generating a chip activation control signal to activate only one of the plurality of logical units and deactivate the remaining logical units, transmits a predetermined command through the data queue input / output unit, and controls a counting unit to increase the counting count when the bit value of the data received in response to the command transmission does not correspond to a preset bit value or when there is no received data.

[0017] The advantages and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the claims. Meanwhile, the terms used in this specification are for describing the embodiments and are not intended to limit the present invention. In this specification, the singular form includes the plural form unless specifically stated otherwise in the text.

[0018]

[0019] Hereinafter, with reference to the drawings, a counting device for the number of defective logical units of an ONFI standard NAND flash memory according to an embodiment of the present invention will be described.

[0020] FIG. 1 is a block diagram showing a counting device for the number of defective logical units of an ONFI standard NAND flash memory according to one embodiment of the present invention, and FIG. 4 is a timing diagram for transmitting a Read ID command to a logical unit and receiving data in a counting device for the number of defective logical units of an ONFI standard NAND flash memory according to one embodiment of the present invention.

[0021] Referring to FIG. 1, a counting device (10) for the number of defective logical units of an ONFI standard NAND flash memory according to one embodiment of the present invention includes a chip activation latch unit (101a, 101b, 101z), a data queue input / output unit (103a, 103b, 103z), a processor (105), a counting unit (107), and a memory (109).

[0022] Standards related to NAND flash memory include JEDEC and ONFI. Here, ONFI (Open NAND Flash Interface) is an interface specification that guarantees compatibility between NAND flash memory devices.

[0023] A counting device (10) for the number of defective logical units of an ONFI standard NAND flash memory according to one embodiment of the present invention is connected to a NAND flash memory (80) having an ONFI standard structure and can count defective logical units when some of the logical units (83a, 83b, 83z) are damaged.

[0024] A NAND flash memory (80) having an ONFI standard structure connected to a counting device (10) for the number of defective logical units of an ONFI standard NAND flash memory according to one embodiment of the present invention has a plurality of channels (81a, 81b, 81z) as an outer chip, and a plurality of logical units (LU) (83a, 83b, 83z) as inner chips belonging to each channel. Each channel has a data queue (DQ) pin as a data pin for data input / output, and the data queue pin is connected to a data bus (87a, 87b, 87z) provided for each channel of the flash memory.

[0025] A logical unit (83a, 83b, 83z) of a NAND flash memory (80) having an ONFI standard structure connected to a counting device (10) for the number of defective logical units of an ONFI standard NAND flash memory according to one embodiment of the present invention has a chip enable (CE) pin, and the logical unit can be enabled or deactivated by receiving a signal through a chip enable signal line (85a, 85b, 85z).

[0026] In a counting device (10) for the number of defective logical units of an ONFI standard NAND flash memory according to one embodiment of the present invention, a chip activation latch portion (101a, 101b, 101z) has an input / output terminal that is connected to each chip activation pin of a plurality of logical units (83a, 83b, 83z) belonging to one channel of the NAND flash memory (80), and is connected to each of the plurality of logical units (83a, 83b, 83z) belonging to one channel of the NAND flash memory (80).

[0027] The data queue input / output section (103a, 103b, 103z) is connected to the data queue pin for data input / output to the channel (81a, 81b, 81z)) of the NAND flash memory (80) and the data queue signal bus (87a, 87b, 87z) to provide a data queue signal to the NAND flash memory (80).

[0028] The processor (105) generates a chip activation control signal to activate only one of the multiple logical units and deactivate the remaining logical units, thereby controlling the logical units of the NAND flash memory or transmitting and receiving data through the chip activation latch portions (101a, 101b, 101z).

[0029] The processor (105) transmits a chip activation control signal to the logical units of the NAND flash memory through the chip activation latch unit (101a, 101b, 101z), then transmits a predetermined command through the data queue input / output unit (103a, 103b, 103z), and determines whether the bit value of the data received in response to the command transmission does not correspond to the preset bit value, or whether there is no data received.

[0030] If the processor (105) determines that the bit value of the data received in response to the transmission of a command does not correspond to a preset bit value, or that there is no received data, the processor (105) controls the counting unit (107) to increase the counting count.

[0031] Here, the processor (105) transmits a Read ID command according to the ONFI standard to the logical unit (83a, 83b, 83z) through the data queue input / output unit (103a, 103b, 103z), and controls the counting unit (107) to increase the counting count if the bit value of the data received in response to the transmission of the Read ID command according to the ONFI standard does not correspond to the bit value according to the ONFI standard.

[0032] FIG. 4 is a timing diagram for transmitting a Read ID command to a logical unit and receiving data in a counting device (10) for the number of defective logical units of a NAND flash memory of ONFI specifications according to one embodiment of the present invention. Referring to FIG. 4, the processor (105) controls the NAND flash memory (80) through the chip activation latch unit (101a, 101b, 101z) and the data queue input / output unit (103a, 103b, 103z) with the chip activation signal (CE#, 901), the command latch activation signal (CLE, 903), the address latch activation signal (ALE, 905), the read activation signal (RE#, 907), the write activation signal (WE#, 909), and the data queue signals (DQ1 to DQ8, 911) to transmit a Read ID command to the logical unit (83a, 83b, 83z) and receive data.

[0033] Here, the chip enable signal (CE#, 901), read enable signal (RE#, 907), and write enable signal (WE#, 909) may be inverted signals that are ON when the binary value is 0 and OFF when the binary value is 1.

[0034] FIG. 3 is a timing diagram of a Read ID command according to the ONFI standard. In order to give a Read ID command to a NAND flash memory (80) according to the ONFI standard, a hexadecimal code value of 90h as a data queue value and an address value of 00h must be transmitted to the data queue signal buses (87a, 87b, 87z) of the NAND flash memory (80). When the Read ID command is transmitted, binary values ​​for the manufacturer ID (MID) and device ID can be received after a delay of a preset time.

[0035] A counting device (10) for the number of defective logical units of a NAND flash memory according to an ONFI standard according to one embodiment of the present invention transmits or receives signals according to a timing diagram as shown in FIG. 4 to give a Read ID command to the NAND flash memory (80) according to the ONFI standard. The timing diagram according to FIG. 4 corresponds to the timing diagram according to the ONFI standard of FIG. 3.

[0036] To explain the timing diagram of FIG. 4 in more detail, when the CLE signal (903) is ON (1) and the WE signal is ON (1), the processor (105) can give a command according to the ONFI standard to the logical unit (83a, 83b, 83z) through the data queue input / output section (103a, 103b, 103z).

[0037] If the binary value of the data corresponds to 90h as a command, a Read ID command is given to the logical unit (83a, 83b, 83z) according to the ONFI standard.

[0038] The processor (105) generates signals such as the timing diagram of FIG. 4 so that the binary value 10010000 of the 8-bit data (DQ1 to DQ8) can be transmitted to the logical unit (83a, 83b, 83z) through the data queue input / output unit (103a, 103b, 103z) under the condition (t2 to t3) that the CLE signal (903) is ON (1) and the WE# signal (909) is ON (0).

[0039] The binary value 10010000 transmitted to the logical unit (83a, 83b, 83z) during the time range from t2 to t4, including the time when the WE# signal (909) is ON, corresponds to 90h in hexadecimal code.

[0040] In addition, during the time range from t6 to t10, the CLE signal is OFF (0) and the ALE signal is ON (1); during the time range from t7 to t8, the WE signal is ON (0) and the RE signal is OFF (1); and during the time range from t7 to t9, including the time when the WE signal is ON, the binary value of the 8-bit data (DQ1 to DQ8), 00000000, is transmitted to the logical unit (83a, 83b, 83z) through the data queue input / output unit (103a, 103b, 103z).

[0041] The binary value 00000000 corresponds to 00h in hexadecimal code, and when a data queue signal (911) having a binary value corresponding to hexadecimal codes 90h and 00h according to the ONFI standard is sequentially transmitted to the logical units (83a, 83b, 83z), the logical units (83a, 83b, 83z) perform the operation of reading the ID of the NAND flash memory (80). That is, the operation according to the Read ID command according to the ONFI standard is performed.

[0042] Subsequently, at the time when the CLE signal is OFF (0), the ALE signal is OFF (0), the WE signal is OFF (1), and the RE signal is ON (0) in the time range from t11 to t13 after a delay for a preset time, if 8-bit data (DQ1 to DQ8) is read from the data queue input / output unit (103a, 103b, 103z) in the time range from t12 to t13, the logical unit (83a, 83b, 83z) performs the operation of reading the first byte corresponding to the ID of the NAND flash memory chip according to the ONFI standard.

[0043] Here, the operation of reading the first byte can be repeated several times.

[0044] Additionally, the processor (105) may receive binary values ​​corresponding to the second to fourth bytes in the interval t13 to t14.

[0045] The processor (105) controls the counting unit (107) to increase the counting count if the bit value of the data received in response to the transmission of a Read ID command according to the ONFI standard does not correspond to the bit value according to the ONFI standard.

[0046] As a bit-by-bit value according to the ONFI specification, the first byte may be a value corresponding to the manufacturer ID code according to the JEDEC JEP106 standard, the second byte may be an arbitrary device ID code of the manufacturer, and the bytes from the third byte onwards may be non-standard IDs unique to the NAND flash memory chip.

[0047] The manufacturer ID code, device ID code, and ID corresponding to a non-standard unique to the NAND flash memory chip may be pre-set and stored in memory (109).

[0048] The processor (105) may remove the repeating part if a pattern of binary values ​​is repeated while reading the bytes after the third byte (e.g., the 3rd to 20th bytes). For example, if the bytes after the third byte are received as binary values ​​such as EA, 2F, AC, EA, 2F, AC, EA, 2F, the processor (105) may determine whether the binary values ​​after the third byte correspond to a predetermined bit-by-bit value by setting them to EA, 2F, AC.

[0049] The processor (105) may generate a chip activation control signal that, when the sequence number according to the physical arrangement is preset for each logical unit (83a, 83b, 83z), sequentially activates only one of the logical units and deactivates the remaining logical units according to the sequence number of the preset logical units (83a, 83b, 83z), and the processor (105) may control the counting unit (107) to store the sequence number of the activated logical unit.

[0050] The counting unit (107) is controlled by the processor (105) to initialize or increase / decrease the counting count.

[0051] The counting unit (107) may count the number of defective logical units corresponding to cases where the bit value of the received data does not correspond to the bit value according to the ONFI standard or there is no received data.

[0052] The counting unit (107) may output the counting count or output the sequence number of the defective logical unit.

[0053] The memory (109) includes a computer-readable recording medium and may store an operating system and preset instructions required for the operation of the processor (105).

[0054] The processor (105) may be capable of processing instructions stored in memory (109) as it performs basic arithmetic, logic, and input / output operations.

[0055]

[0056] Since the NAND flash memory (80) according to the ONFI standard has a plurality of channels (81a, 81b, 81z), the counting device (10) for the number of defective logical units of the NAND flash memory according to the embodiment of the present invention may have a plurality of chip activation latch portions (101) corresponding to each channel of the NAND flash memory (80) and a plurality of data queue input / output portions (103).

[0057]

[0058] According to the above, in the case where physical damage or failure occurs in the NAND flash memory and a part of the logical unit is damaged, the number of defective logical units of the NAND flash memory of the ONFI standard can be counted and the defective logical unit can be identified so that data recorded in the NAND flash memory can be read from the undamaged logical unit.

[0059]

[0060] A person skilled in the art to which the present invention pertains will understand that the present invention may be implemented in other specific forms without altering its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. The scope of the present invention is defined by the claims set forth below rather than by the detailed description above, and all modifications or variations derived from the claims and their equivalents should be interpreted as being included within the scope of the present invention.

[0061] The present invention relates to a technology for counting the number of defective logical units of a NAND flash memory of the ONFI standard.

Claims

1. A chip activation latch having input / output terminals each connected to the chip activation pins of a plurality of logical units belonging to a channel of a NAND flash memory; A data queue input / output unit connected to a data queue pin for data input / output for the channel of the NAND flash memory; and A processor that generates a chip activation control signal to activate only one of a plurality of logical units and deactivate the remaining logical units, controls the logical units of a NAND flash memory through the chip activation latch, transmits a predetermined command through the data queue input / output unit, and controls a counting unit to increase the counting count if the bit value of the data received in response to the command transmission does not correspond to a preset bit value or if no data is received; A device for counting the number of defective logical units of ONFI standard NAND flash memory including 2. In Paragraph 1, The above processor is, Transmitting a Read ID command according to the ONFI standard through the above data queue input / output unit, and controlling a counting unit to increase the counting count if the bit value of the data received in response to the transmission of the Read ID command according to the ONFI standard does not correspond to the bit value according to the ONFI standard. A device for counting the number of defective logical units of ONFI standard NAND flash memory.

3. In Paragraph 1, The above processor is, Generating a chip activation control signal that, when a sequence based on physical arrangement is preset for each logical unit, sequentially activates only one of multiple logical units and deactivates the remaining logical units according to the preset sequence of logical units. A device for counting the number of defective logical units of ONFI standard NAND flash memory.

4. In Paragraph 3, The above processor is, Transmitting a Read ID command according to a predetermined ONFI standard through the above data queue input / output unit, and controlling a counting unit to store the sequence number of an activated logical unit when the bit value of the data received in response to the transmission of the Read ID command does not correspond to the bit value according to the ONFI standard or when no data is received. A device for counting the number of defective logical units of ONFI standard NAND flash memory.

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