Backside contact formation for top FET in a monolithic stacked fet
By relocating the RV connection to the side of the upper source/drain regions in an l-shaped stacked FET, the method addresses the challenges of contact congestion and shorting, enhancing device performance through increased T2T spacing and reduced resistance.
WO2026124908A1PCT designated stage Publication Date: 2026-06-18INTERNATIONAL BUSINESS MACHINE CORPORATION +1
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- INTERNATIONAL BUSINESS MACHINE CORPORATION
- Filing Date
- 2025-11-14
- Publication Date
- 2026-06-18
Smart Images
Figure EP2025083086_18062026_PF_FP_ABST
Abstract
Embodiments of the invention disclose structures and methods for making the structures. According to an embodiment, the structure may include a top transistor stacked on a bottom transistor, wherein top nanosheet stacks of the top transistor are vertically aligned to bottom nanosheet stacks of the bottom transistor, and wherein a top source / drain region of the top transistor is connected to backside interconnects by an extension region, a backside contact, and a backside via.
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