Backside contact formation for top FET in a monolithic stacked fet

By relocating the RV connection to the side of the upper source/drain regions in an l-shaped stacked FET, the method addresses the challenges of contact congestion and shorting, enhancing device performance through increased T2T spacing and reduced resistance.

WO2026124908A1 Publication Date: 2026-06-18INTERNATIONAL BUSINESS MACHINE CORPORATION +1
4 Cites 0 Cited by

Patent Information

Application Number
PCT/EP2025/083086
Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
Priority Date
2024-12-10
Filing Date
2025-11-14
Publication Date
2026-06-18

AI Technical Summary

Technical Problem

Forming backside contacts for the top source/drain regions in an l-shaped stacked FET is challenging, leading to middle-of-line congestion, high resistance, and the possibility of shorting, which degrades device performance.

Method used

The RV is moved from a congested MOL area between the upper source/drain regions to a side of the upper source drain regions, connected to an extension region that connects to the backside contact and backside interconnect, increasing T2T spacing and reducing congestion.

Benefits of technology

This solution improves device performance by reducing contact congestion and preventing shorting, resulting in superior device performance.

✦ Generated by Eureka AI based on patent content.
Patent Text Reader

Abstract

Embodiments of the invention disclose structures and methods for making the structures. According to an embodiment, the structure may include a top transistor stacked on a bottom transistor, wherein top nanosheet stacks of the top transistor are vertically aligned to bottom nanosheet stacks of the bottom transistor, and wherein a top source / drain region of the top transistor is connected to backside interconnects by an extension region, a backside contact, and a backside via.
Need to check novelty before this filing date? Find Prior Art