Circuit board and semiconductor package

Abstract

This circuit board includes: a core layer including a hole; a core via electrode disposed in the hole of the core layer; a first wiring portion disposed on an upper surface of the core layer and connected to the core via electrode; and a second wiring portion disposed on a lower surface of the core layer and connected to the core via electrode, wherein the second wiring portion includes a third portion, and the third portion includes a base portion disposed on the lower surface of the core layer and a stepped portion protruding in the vertical direction from the base portion and coupled to the hole.

Description

Circuit boards and semiconductor packages

[0001] The present embodiment relates to a circuit board and a semiconductor package.

[0002]

[0003] Recently, technologies related to electronic products such as AI and servers have been progressing toward multi-functionality and high speed. To respond to this trend, high-layer and large-area circuit board technologies are also developing rapidly to keep pace with the fast-advancing semiconductor chip manufacturing technology.

[0004] Furthermore, regarding mobile products such as smartphones and tablets, the thickness of circuit boards applied to miniaturize finished electronic products is also decreasing, and technologies related to multilayer circuit boards, which configure more circuit layers within a circuit board of the same thickness, are being actively researched. In addition, as the pitch of semiconductor chips narrows and the size of chips increases, chiplet technology for separating semiconductor chips by function is being researched. Moreover, technologies for connecting separated chiplets on circuit boards are being actively researched. Furthermore, by connecting semiconductor chips with different functions on circuit boards, technologies regarding the connection relationship between circuit boards and semiconductor chips are being actively researched, such as the circuit board connecting semiconductor chips to one another, which was previously considered only from the perspective of conventional semiconductor packaging.

[0005] A circuit board is formed by printing circuit line patterns using a conductive material, such as copper, onto an electrically insulating substrate; it is a general term for a board immediately before electronic components are mounted. To densely mount many different types of electronic components on a flat surface, the mounting positions of each component are determined, and circuit patterns connecting the components are printed on the surface of the flat plate to secure them.

[0006] A circuit board includes a core layer and a plurality of insulating layers disposed on the surface of the core layer. Wiring portions and via portions connecting different wiring portions in a vertical direction are disposed in the core layer and the plurality of insulating layers. The via portions are disposed within via holes penetrating the core layer or the insulating layer.

[0007] In the case of the core layer, the width of the via may be larger than that of other insulating layers. However, when the width of the via hole is increased for the placement of the via, deposition defects of the plating solution occur due to differences in internal current density within the via hole, making it difficult to ensure the quality of the via.

[0008]

[0009] The present invention provides a circuit board and a semiconductor package with improved reliability due to the improvement of the quality of the core via electrodes disposed in the core layer.

[0010]

[0011] A circuit board according to the present embodiment comprises: a core layer including a hole; a core via electrode disposed in the hole of the core layer; a first wiring portion disposed on the upper surface of the core layer and connected to the core via electrode; and a second wiring portion disposed on the lower surface of the core layer and connected to the core via electrode, wherein the second wiring portion includes a third portion, and the third portion includes a base portion disposed on the lower surface of the core layer and a stepped portion protruding vertically from the base portion and coupled to the hole.

[0012] The above step portion can be connected to the core via electrode and the hole.

[0013] The size of the crystal grains in the above-mentioned step portion may be larger than the size of the crystal grains in the above-mentioned core via electrode.

[0014] The second wiring section includes a fourth section disposed on the surface of the third section, and the size of the crystal grains of the fourth section may be smaller than the size of the crystal grains of the third section.

[0015] The vertical length of the core via electrode may be shorter than the vertical length of the core layer.

[0016] The first wiring section includes a first section disposed on the core layer and a second section disposed on the first section, and the size of the crystal grains of the first section may be larger than the size of the crystal grains of the second section.

[0017] It may include a polished surface disposed between the first part and the second part.

[0018] The vertical thickness of the first part above may be thinner than the vertical thickness of the second part above.

[0019] The horizontal width of the above hole may be 50 µm or more.

[0020] A semiconductor package according to the present embodiment comprises: a core layer including a hole; a first build-up structure disposed on the upper surface of the core layer; a second build-up structure disposed on the lower surface of the core layer; a semiconductor chip disposed on the first build-up structure or the second build-up structure; a core via electrode disposed in the hole of the core layer; a first wiring portion disposed on the upper surface of the core layer and connected to the core via electrode; and a second wiring portion disposed on the lower surface of the core layer and connected to the core via electrode, wherein the second wiring portion includes a third portion, and the third portion includes a base portion disposed on the lower surface of the core layer and a step portion protruding vertically from the base portion and coupled to the hole.

[0021]

[0022] In this embodiment, by forming a core via electrode by unidirectional growth of the plating area without a seed layer on the inner wall of the hole, the core via electrode can be densely formed within the hole of the core layer and the plating density can be uniform for each area, thereby improving the reliability of the circuit board through excellent electrical conductivity and signal transmission efficiency.

[0023]

[0024] FIG. 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention.

[0025] FIG. 2 is an enlarged view illustrating the combined structure of a core via electrode and a wiring portion within a core layer according to an embodiment of the present invention.

[0026] FIGS. 3 to 9 are drawings for explaining the process of forming a core via electrode according to an embodiment of the present invention.

[0027] FIG. 10 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention.

[0028]

[0029]

[0030] The present invention is susceptible to various modifications and may have various embodiments, and specific embodiments are illustrated and described in the drawings. However, this does not specify the present invention.

[0031] It should be understood that the embodiments are not intended to be limited and include all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention.

[0032] However, the technical concept of the present invention is not limited to some of the described embodiments but can be implemented in various different forms, and within the scope of the technical concept of the present invention, one or more of the components among the embodiments may be selectively combined or substituted.

[0033] In addition, terms used in the embodiments of the present invention (including technical and scientific terms) shall be interpreted in a meaning generally understood by those skilled in the art to which the present invention pertains, unless explicitly and specifically defined otherwise. Commonly used terms, such as those defined in a dictionary, shall be interpreted in consideration of their contextual meaning as described in the present invention. If a commonly used term defined in a dictionary does not match the meaning it has in the context of the description of the present invention, it shall be interpreted in accordance with the meaning it has in the context of the description of the present invention. Furthermore, even if not explicitly defined in this application, it shall not be interpreted in an ideal or overly formal sense based on the description of the present invention.

[0034] Furthermore, the terms used in the embodiments of the present invention are for describing the embodiments and are not intended to limit the present invention. In this specification, the singular form may include the plural form unless specifically stated otherwise in the text.

[0035] Terms containing ordinal numbers, such as "first," "second," etc., may be used to describe various components, but the meaning of the components is not limited by the ordinal numbers. Terms containing ordinal numbers are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the second component may be named the first component, and similarly, the first component may be named the second component. Furthermore, if the meaning of the component does not depart from the scope of the present invention even without ordinal numbers such as "first" and "second," the component may be referred to by excluding the ordinal number.

[0036] The term "and / or" includes a combination of multiple related listed items or any of the multiple related listed items. Such a term is used merely to distinguish a component from other components and is not limited by the nature, order, sequence, etc. of the component.

[0037] In this application, terms such as “comprising,” “provided,” and “having” are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not excluding in advance the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0038] When referring to directions, vertical and horizontal directions are used for convenience of explanation. Additionally, the horizontal direction may include a first horizontal direction perpendicular to the vertical direction, and a second horizontal direction perpendicular to the first horizontal direction and the vertical direction. Furthermore, if the vertical and horizontal directions follow a Cartesian coordinate system, they may correspond to the first horizontal direction (X-axis), the second horizontal direction (Y-axis), and the vertical direction (Z-axis), respectively; if they follow a cylindrical coordinate system, the first horizontal direction may refer to the azimuth (Φ) direction (or circumferential direction), and the second horizontal direction may refer to the radius (ρ) direction (or centrifugal direction) separated from a specific configuration; and if they follow a spherical coordinate system, the first horizontal direction may refer to the azimuth (Φ) direction (or circumferential direction), and the second horizontal direction may refer to the radius (r) direction (or centrifugal direction) separated from a specific configuration. In particular, the vertical direction may refer to the polar angle (θ) direction formed by the second horizontal direction and the Z-axis. For convenience of explanation, the first horizontal direction, the second horizontal direction, and the vertical direction may be used by combining the Cartesian coordinate system, the cylindrical coordinate system, and the spherical coordinate system described above. However, unless otherwise specified, the vertical direction refers to the Z-axis according to the Cartesian coordinate system, and the horizontal direction refers to any direction that can be defined on the XY plane; when referring to the first horizontal direction and the second horizontal direction perpendicular to the first horizontal direction, the first horizontal direction refers to the X-axis and the second horizontal direction refers to the Y-axis.

[0039] Furthermore, when described as being formed or placed "above or below" each component, "above" or "below" includes not only cases where two components are in direct contact with each other, but also cases where one or more other components are formed or placed between the two components. Additionally, when expressed as "above or below," it may include the meaning of a downward direction as well as an upward direction relative to a single component.

[0040] Furthermore, the meaning that Configuration A is positioned between Configuration B and Configuration C may include the meaning that Configuration A is positioned such that at least a portion of it overlaps with Configurations B and C in the horizontal and / or vertical directions. Unless otherwise noted, even if Configuration C is located between a virtual line extending vertically and / or horizontally from Configuration A and a virtual line extending vertically and / or horizontally from Configuration B, the meaning may include that Configuration C is positioned between Configuration A and Configuration B.

[0041] Furthermore, the statement that Configuration A is exposed from Configuration B should be understood as meaning that Configuration A is exposed from Configuration B, not that Configuration A is exposed from the entire product; and unless there are special circumstances, it should not be understood as meaning that the entirety of Configuration A is covered by Configuration B. In other words, when Configuration A is stated to be exposed from Configuration B, it should be understood to mean that Configuration C, in addition to Configurations A and B, covers Configuration A exposed from Configuration B.

[0042] Additionally, where it is stated that a component is 'connected,' 'combined,' 'connected,' or 'contacted' with another component, this may include not only cases where the component is directly connected, combined, or connected to the other component, but also cases where it is 'connected,' 'combined,' or 'connected' due to another component located between the component and the other component. Accordingly, if component A is to be understood only as being directly 'connected,' 'combined,' 'connected,' or 'contacted' with component B, it is described as being 'directly connected,' 'directly combined,' 'directly connected,' or 'directly contacted.'

[0043] In addition, when it is stated that configuration A is 'fixed' to configuration B, it should be understood that configuration A is indirectly fixed to configuration B through configuration C and / or configuration D, etc., unless otherwise specifically mentioned, considering the function and purpose to be solved, and in cases where configuration A is to be understood only as being 'directly fixed' to configuration B, it is stated as being 'directly fixed'.

[0044] In addition, when described as “flat” or “located on the same plane,” it should not be interpreted according to the dictionary definition, but rather understood by a person with ordinary knowledge in the relevant technical field to the extent that process deviations are taken into account.

[0045] FIG. 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention, FIG. 2 is an enlarged view illustrating the combined structure of a core via electrode and a wiring portion within a core layer according to an embodiment of the present invention, and FIG. 3 to 9 are drawings for explaining the process of forming a core via electrode according to an embodiment of the present invention.

[0046] Referring to FIGS. 1 to 9, a circuit board (10) according to an embodiment of the present invention may include a core layer (100), a first build-up structure (200), a second build-up structure (300), a plurality of circuit parts and a protective layer (290, 390).

[0047] The circuit board (10) may include a core layer (100). The core layer (100) may be a component forming the basis of the circuit board (10). Based on the vertical direction of the circuit board (10), the core layer (100) may be positioned in the center. The material of the core layer (100) may include at least one selected from the group consisting of glass, resin, plastic, and metal.

[0048] The core layer (100) may have a single-layer structure, but is not limited thereto and may include a plurality of insulating layers arranged in a vertical direction. When the core layer (100) is implemented with a plurality of insulating layers, compared to a structure in which the core layer is implemented with a single layer, via holes in each insulating layer constituting the core layer (100) can be formed using a laser in addition to mechanical drilling, thereby reducing the manufacturing cost. Furthermore, according to the structure in which a plurality of insulating layers are stacked vertically, the degree of design freedom regarding the formation of pads and via electrodes is increased, and accordingly, there is an advantage that production efficiency can be improved. Additionally, the core layer (100) may have a structure in which a plurality of reinforcing members are stacked along the vertical direction within the insulating layer. In addition, at least two of the reinforcing members may be provided with different materials.

[0049] The insulating layer constituting the core layer (100) may be a prepreg (PPG) containing glass fibers within a resin. When the core layer (100) is composed of multiple insulating layers, the glass fibers (180) within the core layer (100) may also be provided in multiple numbers and arranged along the vertical direction.

[0050] In order to suppress warpage of the circuit board (10), the vertical thickness of the core layer (100) may be greater than the vertical thickness of the first build-up structure (200) or the second build-up structure (300) to be described later. However, depending on the area of ​​the circuit board (10) and the design of the circuit, the thickness of the core layer (100) may be freely provided without being limited thereto.

[0051] The first build-up structure (200) may be disposed on one side of the core layer (100). The first build-up structure (200) may be disposed on the upper surface of the core layer (100). The second build-up structure (300) may be disposed on the other side of the core layer (100). The second build-up structure (300) may be disposed on the lower surface of the core layer (100). The first build-up structure (100) and the second build-up structure (300) may be disposed facing each other with respect to the core layer (100). The first build-up structure (200) and the second build-up structure (300) may each include a plurality of insulating layers disposed in a vertical direction. The number of insulating layers of the first build-up structure (200) and the number of insulating layers of the second build-up structure (300) may be the same. Accordingly, the occurrence of bending of the circuit board (10) based on the core layer (100) can be minimized. However, this is not limited to the number of insulating layers in the first build-up structure (200) and the number of insulating layers in the second build-up structure (300) may differ from each other.

[0052] The first build-up structure (200) may include a plurality of first insulating layers (210) arranged in a vertical direction, a plurality of wiring portions (220) each arranged in a plurality of first insulating layers (210), and a plurality of via portions (230) arranged to penetrate at least a portion of each of the plurality of first insulating layers (210) and electrically connecting the plurality of wiring portions (220) arranged in a vertical direction.

[0053] The second build-up structure (300) may include a plurality of second insulating layers (310) arranged in a vertical direction, a plurality of wiring portions (320) each arranged in the plurality of second insulating layers (310), and a plurality of via portions (330) arranged to penetrate at least a portion of each of the plurality of second insulating layers (310) and electrically connecting the plurality of wiring portions (320) arranged in a vertical direction.

[0054] The number of insulating layers constituting the first build-up structure (200) and the number of insulating layers constituting the second build-up structure (300) shown in FIG. 1 are exemplary, and the circuit board (10) may have a greater number of insulating layers stacked vertically to form the first build-up structure (200) and the second build-up structure (300), respectively.

[0055] Additionally, the number of insulating layers in the first build-up structure (200) and the number of insulating layers in the second build-up structure (300) may be the same. Accordingly, the occurrence of bending of the circuit board (10) based on the core layer (100) can be minimized. However, this is not limited to this, and the number of insulating layers in the first build-up structure (200) and the number of insulating layers in the second build-up structure (300) may be different from each other.

[0056] The insulating layer of the first build-up structure (200) and the insulating layer of the second build-up structure (300) may each be any insulating material, such as a photocurable and / or thermosetting material. As a thermosetting insulating material, an insulating material in which inorganic and / or organic fillers are dispersed within a resin, such as ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Corporation, may be used, and a prepreg (PPG) containing glass fibers within a resin may be used. Additionally, the resins mentioned above may be, for example, epoxy resin, bismaleimide triazine resin (BT resin), phenolic resin, etc., and the inorganic and / or organic fillers may be provided with materials such as silica or plastic. At least one insulating layer among the insulating layer of the first build-up structure (200) and the insulating layer of the second build-up structure (300) may be a photocurable insulating material, and if it is a photocurable insulating material, it may be a PID (Photo Imageable Dielectric).

[0057] The circuit board (10) may include a protective layer (290, 390). The protective layer (290, 390) may include a first protective layer (290) disposed on the surface of a first build-up structure (200) and a second protective layer (390) disposed on the surface of a second build-up structure (300). When a semiconductor device is disposed on the surface of the circuit board (10) using a material such as solder, the first protective layer (290) and the second protective layer (390) can perform the function of preventing short circuits between solders due to low wettability with the solder, and can prevent the problem of external contaminants penetrating into the build-up structure and reducing reliability. The first protective layer (290) and the second protective layer (390) may each utilize a photocurable insulating material. Accordingly, the first protective layer (290) and the second protective layer (390) are provided with a solder resist other than the aforementioned ABF, PPG, BT resin, and PID. However, they are not limited thereto and may be provided with various materials capable of performing low wettability with solder and thus preventing short circuits between solders as described above.

[0058] The first protective layer (290) may include a hole (292) for exposing upward a wiring portion (220) disposed on the surface of the first build-up structure (200). The second protective layer (390) may include a hole (392) for exposing downward a wiring portion (320) disposed on the surface of the second build-up structure (300) to the circuit board (10).

[0059] Below, the arrangement structure of the wiring portion of the core layer (100) and the core via electrode will be described.

[0060] A first wiring section (120) may be disposed on one side of the core layer (100). The first wiring section (120) may be disposed on the upper surface of the core layer (100). The first wiring section (120) may be electrically connected to the wiring section (220) and via section (230) of the first build-up structure (200).

[0061] A second wiring section (130) may be disposed on the other side of the core layer (100). The second wiring section (130) may be disposed on the lower side of the core layer (100). The second wiring section (130) may be electrically connected to the wiring section (320) and via section (330) of the second build-up structure (300).

[0062] The circuit board (10) may include a core via electrode (140). The core via electrode (140) may be positioned to penetrate at least a portion of the core layer (100). The core via electrode (140) may be positioned to overlap the core layer (100) in a horizontal direction. The first wiring section (120) and the third wiring section (130) may be electrically connected through the core via electrode (140). The core via electrode (140) may be provided in multiple numbers and arranged along the horizontal direction of the core layer (100).

[0063] The core layer (100) may include a hole (110) penetrating from the upper surface of the core layer (100) to the lower surface of the core layer (100). The hole (110) may be provided in multiple numbers and arranged along the horizontal direction of the core layer (100). A core via electrode (140) may be disposed within the hole (110). The core via electrode (140) may be a metal material plated within the hole (110).

[0064] The horizontal width (D1) of the hole (110) of the core via electrode (140) or the core layer (100) may be larger than the horizontal width of each of the plurality of via portions disposed in the first build-up structure (200) or the second build-up structure (300). In the embodiment, the horizontal width (D1) of the hole (110) of the core layer (100) may be 50 µm or more. When processing the hole (110) for forming the core via electrode (150) within the core layer (100) due to the vertical length of the core layer (100) itself, if the width of the hole (110) is less than 50 µm, there is a problem of reduced productivity due to the difficulty of the hole processing operation. In addition, in a structure that connects a plurality of wiring layers in the vertical direction, if the width of the hole (110) is less than 50 µm, the bonding force with the wiring layer may not be sufficient.

[0065] The vertical length of the hole (110) may be the same as the vertical length (H1) of the core layer (100). The vertical length (H2) of the core via electrode (140) may be shorter than the vertical length of the hole (110) and / or the vertical length (H1) of the core layer (100). Accordingly, one side of the core via electrode (140) may be positioned vertically stepped compared to one side of the core layer (100).

[0066] For example, the lower surface of the core via electrode (140) may be positioned so as to be stepped upward above the lower surface of the core layer (100). Accordingly, when viewed from the bottom of the core layer (100) before the formation of the second wiring portion (130), the lower surface of the hole (110) may have a groove shape in which the bottom surface is defined by the lower surface of the core via electrode (140). The upper surface of the core via electrode (140) may be positioned to form a plane with the upper surface of the core layer (100).

[0067] As a variation, the upper surface of the core via electrode (140) may be positioned so as to be stepped downward from the upper surface of the core layer (100). Accordingly, when viewed from the top of the core layer (100) before the formation of the first wiring portion (120), the upper surface of the via hole (100) may have a groove shape in which the bottom surface is defined by the upper surface of the core via electrode (140). In this case, the lower surface of the core via electrode (140) may be positioned to form a plane with the lower surface of the core layer (100).

[0068] The first wiring section (120) may include a first section (122) disposed on the core layer (100) and a second section (124) disposed on the first section (122). The vertical length of the first section (122) may be shorter than the vertical length of the second section (124). The size of the crystal grains constituting the first section (122) may be larger than the size of the crystal grains constituting the second section (124).

[0069] The second wiring section (130) may include a third section (132) disposed on the lower surface of the core layer (100) and a fourth section (134) disposed on the lower surface of the third section (133). The size of the crystal grains constituting the third section (132) may be larger than the size of the crystal grains constituting the fourth section (134). The size of the crystal grains constituting the third section (132) may be larger than the size of the crystal grains constituting the core via electrode (140).

[0070] The third part (132) may include a base portion and a stepped portion (133) that protrudes vertically from the upper surface of the base portion and is disposed in at least a portion within the hole (110). The upper surface of the stepped portion (133) may be connected to the lower surface of the core via electrode (140). The stepped portion (133) may be disposed to overlap horizontally with at least a portion of the core layer (100). The upper surface of the stepped portion (133) may be disposed vertically stepped with respect to the upper surface of the base portion. The horizontal length of the stepped portion (133) may be shorter than the horizontal length of the base portion.

[0071] Accordingly, a plurality of regions with different grain sizes may be arranged in the hole (110) of the core layer (100), and, for example, a first region with a large grain size and a second region with a small grain size arranged below the first region may be arranged within the hole (110). The first region is the arrangement region of the core via electrode (140), and the second region is the arrangement region of the third part (132).

[0072] The vertical thickness of the base of the third part (132) may be smaller than the vertical thickness of the fourth part (134).

[0073] According to the embodiment, there is no seed layer for forming a core via electrode (140) on the inner wall of the hole (110) within the core layer (100).

[0074] According to the prior art, the formation of core via electrodes within a core layer was achieved by a plating method through a seed layer placed on the inner wall of a hole within the core layer. However, during the process of forming the hole within the core layer, plating deviations occur due to glass fibers of the core layer protruding through the inner wall of the hole, and voids are generated, resulting in problems such as short circuits in electrical connections through the core via electrodes or deterioration of plating quality.

[0075] According to the embodiment, the core via electrode (140) is formed on the inner wall of the hole (110) within the core layer (100) without a seed layer, thereby resolving the aforementioned problem.

[0076] Hereinafter, the process of forming a core via electrode according to an embodiment of the present invention will be described.

[0077] Referring to FIG. 3, the process of forming a core via electrode may include a step of preparing a core layer (100). A cover (410) is disposed on one side and the other side of the core layer (100) to reinforce the rigidity of the core layer (100) required in the process of forming a hole (110) to be described later. In addition, the surface of the core layer (110) can be protected through the cover (410).

[0078] Next, referring to FIG. 4, a hole (110) can be formed in the core layer (100). The formation of the hole (110) can be achieved by a mechanical drilling method, but is not limited thereto and can be formed by various methods including a laser method. As described above, a plurality of holes can be arranged along the horizontal direction in the core layer (100). During the process of forming the hole (110), the cover (410) is also drilled together, and accordingly, a hole (412) can be processed in the area of ​​the cover (410) that overlaps vertically with the hole (110).

[0079] Next, referring to FIG. 5, a cover (410) can be removed from the surface of the core layer (100). The cover (410) can be removed by etching. Through the above process, a plurality of core layers (100) having holes (110) can each be manufactured.

[0080] Next, referring to FIG. 6, a plurality of core layers (100) with holes (110) implemented on the upper and lower surfaces of a metal layer (420) may be stacked respectively. Here, the metal layer (420) is configured to be separated from the core layer (100) after the formation of a core via electrode (140) within each core layer (100), and a first foil (430) and a second foil (440) disposed on the first foil (430) may be disposed respectively on one surface and the other surface to which the core layer (100) is joined. Here, the first foil (430) may have a first thickness in the vertical direction, as it forms a placement area for the second foil (440) on the surface of the metal layer (420) and is intended for separating the core layer (100) formed by the second foil (440) from the metal layer (420) to be described later. The second foil (440) is intended to function as a seed layer for plating the core via electrode (140) and may have a second thickness shorter than the first thickness in the vertical direction. A portion of the second foil (440) may form the first portion (122) of the first wiring portion (120) described above.

[0081] Next, as illustrated in FIG. 7, plating for forming a core via electrode (140) can be performed through a second foil (440) that is vertically superimposed with the hole (110). Plating within the hole (110) can be performed by an electrolytic copper plating method. Accordingly, a core via electrode (140) can be formed in a vertical direction from the surface of the second foil (440). That is, through the second foil (440), the core via electrode (140) can be implemented by an anisotropic plating method in a unidirectional direction.

[0082] Next, as illustrated in FIG. 8, the metal layer (420) can be removed. The metal layer (420) can be removed together with the first foil (430). Accordingly, based on a single core layer (100), a second foil (440) is disposed on one side of the core layer (100), and a core via electrode (140) can be formed in a hole (110) within the core layer (100).

[0083] In the process of forming the core via electrode (140) through the second foil (440), as the plating area increases, a portion of the core via electrode (140) may protrude from the surface of the core layer (100). Accordingly, as shown in FIG. 9, one end of the core via electrode (140) may be partially removed by etching. Accordingly, the vertical length of the core via electrode (140) may be shorter than the vertical length of the core layer (100) as described above, and the lower surface of the core via electrode (140) may be positioned so as to be stepped upward above the lower surface of the core layer (100).

[0084] Next, a first wiring section (120) and a second wiring section (130) may be formed on the upper and lower surfaces, respectively, of the core layer (100). The formation of the first wiring section (120) may be achieved by an electrolytic copper plating method through a second foil (440) for forming a core via electrode (140). To control the flatness of the first wiring section (120), the surface of the second foil (440) may be polished before the formation of the first wiring section (120), and accordingly, a polished surface (150) may be formed on the surface of the second foil (440) where the first wiring section (120) is placed. Based on FIG. 2, the polished surface (150) may be placed between the first section (122) and the second section (124). The polished surface (150) may be flat, but is not limited thereto, and may be a concave surface with a shape that is concave toward the core layer (100).

[0085] A seed layer may be disposed on the lower surface of the core layer (100) where the second wiring section (130) is formed. When the seed layer is combined, the seed layer may include a base portion disposed on the lower surface of the core layer (100) and a stepped portion protruding from the base portion and coupled to a hole (110) within the core layer (100). A portion of the seed layer is removed after the second wiring section (130) is formed, and the remaining portion may form a third portion (132) of the second wiring section (130). Accordingly, the third portion (132) may include a base portion and a stepped portion (133) protruding from the base portion and coupled to the hole (110). Subsequently, a fourth portion (134) of the second wiring section (130) may be implemented by an electrolytic copper plating method through the lower surface of the base portion of the third portion (132), which is the opposite side of the placement surface of the stepped portion (133).

[0086] A core via electrode according to the prior art is implemented by an electroplating method using a seed layer placed on the inner wall of a hole within a core layer. Accordingly, the structure is such that the core via electrode is implemented by the plating area growing in both directions from the vertical center region of the hole, which has a low current density and a high charge amount. However, due to differences in charge amount or plating density between regions within the hole, boundary areas may occur within the core via electrode, or non-uniform plating areas such as voids and burrs may occur. Consequently, the core via electrode according to the prior art has a problem in that the durability of the core via electrode is reduced and electrical conductivity is also low due to the occurrence of non-uniform areas such as boundary areas, resulting in reduced signal transmission efficiency.

[0087] According to the embodiment, as the core via electrode (140) grows in one direction, that is, in a unidirectional manner, through the second foil (440), the core via electrode (150) can be densely formed within the hole (110) of the core layer (100), and the plating density can be uniform for each region.

[0088] In addition, since the width of the core via electrode (!40) can be easily increased, there is an advantage in that the heat dissipation efficiency of the circuit board through the core layer (100) can be improved. Accordingly, the occurrence of warping of the circuit board can be minimized due to the improvement in thermal stress resulting from the increase in the thermal capacity of the core layer (100) itself.

[0089] In addition, since components such as the filling material within the core via electrode are omitted compared to conventional methods, quality defects caused by the difference in the coefficient of thermal expansion between the filling material and the core via electrode can be prevented in advance, and there is an advantage of improving production efficiency through process simplification.

[0090] FIG. 10 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention.

[0091] Referring to FIG. 10, a semiconductor package according to an embodiment of the present invention may include a first semiconductor chip (1000) disposed on a circuit board (10) and a second semiconductor chip (2000). The first semiconductor chip (1000) may be coupled to a first build-up structure (200) through a first connection part, and the second semiconductor chip (2000) may be coupled to a second build-up structure (300) through a second connection part. Here, the first connection part and the second connection part may each be a solder ball. Although all components constituting an embodiment of the present invention have been described above as being combined as one or operating as a combined unit, the present invention is not necessarily limited to such an embodiment. That is, within the scope of the purpose of the present invention, all components may be selectively combined as one or more units. Furthermore, terms such as "include," "compose," or "have" described above, unless specifically stated otherwise, mean that the relevant component may be inherent; therefore, they should be interpreted as allowing for the inclusion of additional components rather than excluding them. All terms, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the present invention pertains, unless otherwise defined. Commonly used terms, such as those defined in advance, should be interpreted in accordance with their meaning in the context of the relevant technology and, unless explicitly defined in the present invention, should not be interpreted in an ideal or overly formal sense.

[0092] The foregoing description is merely an illustrative explanation of the technical concept of the present invention, and those skilled in the art to which the present invention pertains will be able to make various modifications and variations within the scope of the essential characteristics of the present invention. Accordingly, the embodiments disclosed in the present invention are intended to explain, not limit, the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by such embodiments. The scope of protection of the present invention shall be interpreted by the claims below, and all technical concepts within an equivalent scope shall be interpreted as being included within the scope of rights of the present invention.

[0093] Meanwhile, when a circuit board having the features of the invention described above is used in IT devices or home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of the invention performs a semiconductor package function, it can safely protect the semiconductor chip from external moisture or contaminants, and can resolve issues such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. In addition, when it is responsible for signal transmission, it can resolve noise issues. Through this, the circuit board having the features of the invention described above enables the stable operation of IT devices or home appliances, thereby allowing the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability.

[0094] When a circuit board having the features of the invention described above is used in a transport device such as a vehicle, it can resolve the problem of signal distortion transmitted to the transport device, or safely protect a semiconductor chip controlling the transport device from the outside, and further improve the stability of the transport device by resolving problems such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. Accordingly, the transport device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

Claims

1. Core layer including holes; A core via electrode disposed in a hole of the core layer; A first wiring portion disposed on the upper surface of the core layer and connected to the core via electrode; and It includes a second wiring portion disposed on the lower surface of the core layer and connected to the core via electrode, The above second wiring section includes a third section, and The above third part is a circuit board comprising a base portion disposed on the lower surface of the core layer and a stepped portion protruding vertically from the base portion and coupled to the hole.

2. In Paragraph 1, The above step portion is a circuit board connected to the core via electrode and the hole.

3. In Paragraph 1, A circuit board in which the size of the crystal grains of the above-mentioned step portion is larger than the size of the crystal grains of the above-mentioned core via electrode.

4. In Paragraph 1, The second wiring section includes a fourth section disposed on the surface of the third section, and A circuit board in which the size of the crystal grains of the fourth part is smaller than the size of the crystal grains of the third part.

5. In Paragraph 1, A circuit board in which the vertical length of the core via electrode is shorter than the vertical length of the core layer.

6. In Paragraph 1, The first wiring section comprises a first section disposed on the core layer and a second section disposed on the first section. A circuit board in which the size of the crystal grains of the first part is larger than the size of the crystal grains of the second part.

7. In Paragraph 6, A circuit board comprising a polished surface disposed between the first part and the second part.

8. In Paragraph 6, A circuit board in which the vertical thickness of the first part is thinner than the vertical thickness of the second part.

9. In Paragraph 1, A circuit board in which the horizontal width of the above hole is 50 µm or more.

10. Core layer including holes; A first build-up structure disposed on the upper surface of the above-mentioned core layer; A second build-up structure disposed on the lower surface of the above-mentioned core layer; A semiconductor chip disposed in the first build-up structure or the second build-up structure; A core via electrode disposed in a hole of the core layer; A first wiring portion disposed on the upper surface of the core layer and connected to the core via electrode; and It includes a second wiring portion disposed on the lower surface of the core layer and connected to the core via electrode, The above second wiring section includes a third section, and The above third part is a semiconductor package comprising a base portion disposed on the lower surface of the core layer and a stepped portion protruding vertically from the base portion and coupled to the hole.

Images