Display panel and driving method therefor

Abstract

The present application provides a display panel and a driving method therefor. The display panel comprises: a plurality of first sub-pixel groups and a plurality of second sub-pixel groups arranged alternately; a plurality of first gate signals are used for driving the corresponding plurality of first sub-pixel groups to be enabled within first frames; a plurality of second gate signals are used for driving the corresponding plurality of second sub-pixel groups to be enabled within second frames; and the first frames and the second frames have overlapping time periods.

Description

Display panel and its driving method

[0001] This application claims priority to Chinese patent application No. 202411867338.7, filed on December 17, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, specifically to display panels and their driving methods. Background Technology

[0003] Display panels use different image refresh rates in different application scenarios. For example, in applications that display dynamic images, such as games and videos, the display panel is in high-frequency mode to ensure the smoothness of the displayed image; in applications that display static images, such as e-books, the display panel is in low-frequency mode to reduce the power consumption of the display panel.

[0004] However, when the display panel is in low-frequency mode, the leakage current is longer, which will cause screen flickering. Invention Overview

[0005] The purpose of this application is to provide a display panel and its driving method to solve the problem of existing display panels flickering in low-frequency mode.

[0006] In a first aspect, this application provides a display panel for displaying images within multiple frames, the multiple frames including a plurality of first frames and a plurality of second frames, comprising:

[0007] Multiple sub-pixel groups, including multiple first sub-pixel groups and multiple second sub-pixel groups arranged in an alternating manner;

[0008] Multiple gate lines include multiple first gate lines electrically connected to multiple corresponding first sub-pixel groups and multiple second gate lines electrically connected to multiple corresponding second sub-pixel groups. The multiple first gate lines are used to transmit multiple corresponding first gate signals, and the multiple second gate lines are used to transmit multiple corresponding second gate signals.

[0009] In this configuration, multiple first gate signals are used to drive multiple corresponding first sub-pixel groups to be turned on within the first frame, and multiple second gate signals are used to drive multiple corresponding second sub-pixel groups to be turned on within the second frame. The first frame and the second frame have an overlapping time period.

[0010] The plurality of sub-pixel groups are composed of a plurality of first sub-pixel groups and a plurality of second sub-pixel groups arranged alternately;

[0011] The multi-frame is composed of multiple first frames and multiple second frames alternately, with each of the first frames overlapping with each of the two adjacent second frames, and each of the second frames overlapping with each of the two adjacent first frames.

[0012] The plurality of sub-pixel groups further include a plurality of third sub-pixel groups, wherein at least one other is provided between each of the first sub-pixel group, the second sub-pixel group and the third sub-pixel group;

[0013] The multiple gate lines also include multiple third gate lines electrically connected to the corresponding multiple third sub-pixel groups, and the multiple third gate lines are used to transmit the corresponding multiple third gate signals;

[0014] The plurality of third gate signals are used to drive the corresponding plurality of third sub-pixel groups to be turned on in the third frame. The plurality of frames include the first frame, the second frame and the third frame arranged in sequence, and the third frame has an overlapping time period with the first frame and the second frame.

[0015] Secondly, embodiments of this application provide a display panel for displaying images within multiple frames, wherein the multiple frames include multiple first frames and multiple second frames, including:

[0016] Multiple sub-pixel groups, including multiple first sub-pixel groups and multiple second sub-pixel groups arranged in an alternating manner;

[0017] Multiple gate lines include multiple first gate lines electrically connected to multiple corresponding first sub-pixel groups and multiple second gate lines electrically connected to multiple corresponding second sub-pixel groups. The multiple first gate lines are used to transmit multiple corresponding first gate signals, and the multiple second gate lines are used to transmit multiple corresponding second gate signals.

[0018] In this configuration, multiple first gate signals are used to drive multiple corresponding first sub-pixel groups to be turned on within the first frame, and multiple second gate signals are used to drive multiple corresponding second sub-pixel groups to be turned on within the second frame. The first frame and the second frame have an overlapping time period.

[0019] Thirdly, embodiments of this application also provide a method for driving a display panel, used to drive any of the display panels described above, including:

[0020] Control multiple first gate lines to transmit corresponding multiple first gate signals to multiple first sub-pixel groups, so that the corresponding multiple first sub-pixel groups are turned on in the first frame;

[0021] Multiple second gate lines are controlled to transmit corresponding second gate signals to multiple second sub-pixel groups, so that the corresponding multiple second sub-pixel groups are turned on within the second frame, wherein the first frame and the second frame have an overlapping time period.

[0022] Beneficial effects: This application provides a display panel and its driving method, which uses multiple first gate signals to drive multiple corresponding first sub-pixel groups to turn on in the first frame, and multiple second gate signals to drive multiple corresponding second sub-pixel groups to turn on in the second frame. The first frame and the second frame have overlapping time periods, thereby avoiding the simultaneous leakage of all sub-pixel groups in each frame, which would cause a significant reduction in the overall brightness of the display panel and improve the flicker phenomenon at low frequencies. Attached Figure Description

[0023] The present application will be further described below with reference to the accompanying drawings. It should be noted that the accompanying drawings described below are merely for explaining some embodiments of the present application. Those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0024] Figures 1 and 4 are structural block diagrams of the display panel provided in the embodiments of this application.

[0025] Figure 2 is a brightness curve of the display panel provided in an embodiment of this application.

[0026] Figure 3 shows the brightness curve of a display panel in the prior art.

[0027] Figure 5 is a waveform diagram of some signals of the pixel circuit provided in the embodiment of this application.

[0028] Figure 6 shows the pixel circuit provided in an embodiment of this application. Implementation methods of this application

[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0030] In the description of this application, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified; "electrical connection" indicates that the two are conductive, without limitation to a direct or indirect connection.

[0031] In addition, it should be noted that the accompanying drawings only provide structures and steps that are closely related to this application, and omit some details that are not closely related to the application. The purpose is to simplify the drawings and make the application points clear at a glance, rather than indicating that the actual device is exactly the same as the drawings, and it is not intended to limit the actual device.

[0032] This application provides a display panel, which may include, but is not limited to, the following embodiments and combinations thereof.

[0033] In some embodiments, as shown in FIG1 and FIG2, the display panel 100 is used to display images within multiple frames, the multiple frames including multiple first frames F1 and multiple second frames F2, including: multiple sub-pixel groups, including multiple first sub-pixel groups P1 and multiple second sub-pixel groups P2 arranged in an alternating manner; multiple gate lines (GL1 to GLn), including multiple first gate lines electrically connected to the corresponding multiple first sub-pixel groups P1 and multiple second gate lines electrically connected to the corresponding multiple second sub-pixel groups P2, the multiple first gate lines being used to transmit corresponding multiple first gate signals, and the multiple second gate lines being used to transmit corresponding multiple second gate signals; wherein, the multiple first gate signals are used to drive the corresponding multiple first sub-pixel groups P1 to turn on in the first frame F1, the multiple second gate signals are used to drive the corresponding multiple second sub-pixel groups P2 to turn on in the second frame F2, and the first frame F1 and the second frame F2 have overlapping time periods.

[0034] The display panel 100 can be, but is not limited to, an organic self-emissive display panel, an inorganic self-emissive direct-view display panel, or a liquid crystal display panel. As shown in Figures 1 and 2, this example illustrates the arrangement of multiple sub-pixel arrays P, which can be arranged in n rows and m columns (n ​​and m are both positive integers). A sub-pixel group can be a corresponding row of sub-pixels P. Furthermore, the display panel 100 may also include multiple data lines (DL1 to DLm), multiple pixel circuits (not shown) corresponding to the multiple sub-pixels P, a source driver 206 electrically connected to the multiple data lines, and a gate driver 201 electrically connected to the multiple gate lines. The gate driver 201 can be a gate driving circuit located on the substrate of the display panel 100 or an independently set chip; here, only the former is illustrated as an example.

[0035] Specifically, each sub-pixel is electrically connected to a corresponding pixel circuit, and each gate line is electrically connected to multiple pixel circuits corresponding to multiple sub-pixels P (e.g., the first sub-pixel group P1 or the second sub-pixel group P2) located in the corresponding row, and outputs a corresponding gate signal (including a gate active pulse for controlling the sub-pixel P to turn on). Under normal circumstances, multiple rows of sub-pixels are turned on sequentially under the control of multiple gate signals (multiple gate active pulses). Each data line is connected to multiple pixel circuits corresponding to multiple sub-pixels P located in the corresponding column to output a corresponding data signal (including multiple data voltages corresponding to the multiple sub-pixels P). The multiple data signals corresponding to multiple columns of sub-pixels are set to transmit the corresponding multiple data voltages to the corresponding row of sub-pixels P respectively through multiple data lines when each row of sub-pixels is turned on.

[0036] As shown in Figure 3, the horizontal axis represents time t and the vertical axis represents brightness L. Since the first duration t1 of each frame of the display panel 100 at high frequency is shorter than the second duration t2 of each frame at low frequency, and the leakage rate is constant, the amount of brightness L decreases after the longer second duration t2 of leakage at low frequency is greater than the amount of brightness L decreases after the shorter first duration t1 of leakage at low frequency. Therefore, the display in multiple frames at low frequency causes flickering.

[0037] In the comparative example shown in Figure 2, only the first frame F1 of this embodiment exists. That is, in the low frequency, multiple sub-pixel groups start to emit light sequentially at the beginning of each first frame F1 and the brightness decreases at the same time, so the flickering phenomenon shown in Figure 3 exists.

[0038] As shown in Figure 2, in this embodiment, since the multiple frames include multiple first frames F1 and multiple second frames F2, the multiple gate signals do not drive multiple sub-pixel groups to turn on sequentially. Instead, they are configured to include multiple first gate signals for driving the corresponding multiple first sub-pixel groups P1 to turn on sequentially in the first frame F1, and multiple second gate signals for driving the corresponding multiple second sub-pixel groups P2 to turn on sequentially in the second frame F2. Furthermore, the first frame F1 and the second frame F2 have an overlapping time period t0, that is, at least one of the following two situations exists: "when the multiple first sub-pixel groups P1 have not yet ended their leakage (i.e., the multiple first sub-pixel groups P1 are still emitting light), the multiple second sub-pixel groups P2 have already started to turn on sequentially to emit light" and "when the multiple second sub-pixel groups P2 have not yet ended their leakage (i.e., the multiple first sub-pixel groups P1 are still emitting light), the multiple first sub-pixel groups P1 have already started to turn on sequentially to emit light". This avoids the situation where all sub-pixel groups leak at the same time in each frame (first frame F1 or second frame F2), which would cause a significant decrease in the overall brightness of the display panel 100 and improves the flickering phenomenon at low frequencies.

[0039] In some embodiments, as shown in FIG1 and FIG2, the plurality of sub-pixel groups are composed of a plurality of alternating first sub-pixel groups P1 and a plurality of second sub-pixel groups P2; the plurality of frames are composed of a plurality of alternating first frames F1 and a plurality of second frames F2, wherein each of the first frame F1 and each of the two adjacent second frames F2 has a first overlapping time period t01, and each of the second frame and each of the two adjacent first frames has a second overlapping time period t02.

[0040] Specifically, in this embodiment, the multiple sub-pixel groups are further defined as consisting of multiple alternating first sub-pixel groups P1 and multiple second sub-pixel groups P2. That is, the first sub-pixel group P1 can be either odd-numbered row sub-pixels or even-numbered row sub-pixels, and the second sub-pixel group P2 can be either odd-numbered row sub-pixels or even-numbered row sub-pixels. Correspondingly, the multiple frames are composed of multiple alternating first frames F1 and multiple second frames F2, that is, odd-numbered row sub-pixels and even-numbered row sub-pixels are turned on alternately. At the same time, each adjacent first frame F1 and second frame F2 have an overlapping time period t0, so that leakage current is not interrupted before the multiple odd-numbered row sub-pixels have finished. While still emitting light, multiple even-numbered row sub-pixels have already started to turn on sequentially to emit light. And while multiple even-numbered row sub-pixels have not yet finished leaking current (i.e., still emitting light), multiple odd-numbered row sub-pixels have already started to turn on sequentially to emit light. Thus, compared with the prior art, the time period when one of the multiple odd-numbered row sub-pixels and multiple even-numbered row sub-pixels in the entire display panel 100 has a larger leakage current (i.e., the time period when the brightness L drops more) and the time period when the other has a smaller leakage current (i.e., the time period when the brightness L drops less) are overlapped. By combining the overall brightness of the display panel 100 during this period, the flicker phenomenon at low frequencies is improved.

[0041] Furthermore, as shown in Figure 2, the duration of the first frame F1 is equal to the duration of the second frame F2, the duration of the first overlapping time period t01 between the first frame F1 and the two adjacent second frames F2 is equal, and the duration of the second overlapping time period t02 between the second frame F2 and the two adjacent first frames F1 is equal.

[0042] That is, the sum of the duration of sequential activation and leakage of multiple odd-numbered row sub-pixels (i.e., the duration of the first frame F1), and the sum of the duration of sequential activation and leakage of multiple even-numbered row sub-pixels (i.e., the duration of the second frame F2), ensure that their charging and leakage conditions are the same, avoiding any brightness difference between them. Furthermore, multiple even-numbered row sub-pixels begin to emit light sequentially at the midpoint of the preceding first frame F1, and multiple odd-numbered row sub-pixels begin to emit light sequentially at the midpoint of the preceding second frame F2, ensuring that the first... The overlapping time period t01 and the second overlapping time period t02 are essentially the same overlapping time period t0, and the first frame F1 and the second frame F2 are both divided into two overlapping time periods t0. That is, multiple frames can be approximately regarded as multiple overlapping time periods t0. In each overlapping time period t0, the brightness L of the display panel 100 is the brightness of multiple odd-numbered row sub-pixels with larger or smaller brightness at that time, and the brightness of multiple even-numbered row sub-pixels with smaller or larger brightness. Therefore, the brightness of the display panel 100 is approximately the same in each overlapping time period t0, which further improves the flicker phenomenon at low frequencies.

[0043] Of course, in other embodiments, it can be assumed that the first sub-pixel group P1 and the second sub-pixel group P2 can both include multiple rows of sub-pixels. Correspondingly, the odd-numbered rows of sub-pixels and even-numbered rows of sub-pixels in the above scheme can be understood as multiple rows of sub-pixels in the first sub-pixel group P1 and multiple rows of sub-pixels in the second sub-pixel group P2.

[0044] In some embodiments, the plurality of sub-pixel groups further include a plurality of third sub-pixel groups (not shown, but can be understood by comparing with Figure 1), wherein at least one of the first sub-pixel group P1, the second sub-pixel group P2 and the third sub-pixel group is provided between each other; the plurality of gate lines further include a plurality of third gate lines electrically connected to the corresponding plurality of third sub-pixel groups, the plurality of third gate lines being used to transmit the corresponding plurality of third gate signals; wherein the plurality of third gate signals are used to drive the corresponding plurality of third sub-pixel groups to be turned on in a third frame (not shown, but can be understood by comparing with Figure 2), the plurality of frames including the first frame F1, the second frame F2 and the third frame arranged in sequence, the third frame having an overlapping time period with the first frame F1 and the second frame F2.

[0045] Understandably, in this embodiment, multiple sub-pixel groups are divided into a first sub-pixel group P1, a second sub-pixel group P2, and a third sub-pixel group. These three groups also need to be arranged separately. For example, they can be arranged in a cycle of "first sub-pixel group P1, second sub-pixel group P2, and third sub-pixel group". The above "order" can also be adjusted. Of course, they can also not be arranged repeatedly. For example, i consecutive first sub-pixel groups P1, second sub-pixel groups P2, or third sub-pixel groups can be set, where i is a positive integer. The above i can be set so that the human eye cannot perceive the above flickering phenomenon.

[0046] In this embodiment, the duration of the overlap between the third frame and each of the first frame F1 and the second frame F2 is not limited. The duration of the two overlapping periods can be set according to the number of the first sub-pixel group P1, the second sub-pixel group P2 and the third sub-pixel group. For example, the moment when the leakage power of the first frame F1, the second frame F2 or the third frame corresponding to the one with more leakage power can be used as the start time of the next second frame F2, the third frame or the first frame F1, and vice versa.

[0047] In the case of multiple frames including the first frame F1, the second frame F2 and the third frame F3, in any three consecutive frames (i.e., three cases), the last frame has an overlapping period with the previous two frames.

[0048] Similarly, in other embodiments, the aforementioned third sub-pixel group can also be considered to include multiple consecutive rows of sub-pixels.

[0049] Furthermore, multiple sub-pixel groups can be divided into more types (e.g., k types, k is greater than 3) of sub-pixel groups depending on the situation. Similarly, in any consecutive k frames (i.e., k types), the last frame has an overlapping period with the previous (k-1) frames.

[0050] In some embodiments, as shown in FIG1 and FIG4, the display panel 100 further includes the gate driver 201 electrically connected to the plurality of sub-pixel groups, the gate driver 201 including: a plurality of cascaded first gate driving units 2011, each first gate driving unit 2011 being electrically connected to a corresponding first gate line; and a plurality of cascaded second gate driving units 2012, each second gate driving unit 2012 being electrically connected to a corresponding second gate line.

[0051] Understandably, in this embodiment, multiple first gate signals (for example, the first gate signal may include at least one of the first sub-gate signal EM-ODD, the second sub-gate signal RST-ODD, and the third sub-gate signal SCAN-ODD) are set to be output through multiple cascaded first gate driving units 2011, so as to realize that multiple gate pulses in the multiple first gate signals appear sequentially in the first frame F1, thereby driving multiple first sub-pixel groups P1 to turn on sequentially in the first frame F1; similarly, multiple second gate signals (for example, the second gate signal may include at least one of the fourth sub-gate signal EM-EVEN, the fifth sub-gate signal RST-EVEN, and the sixth sub-gate signal SCAN-EVEN) are set to be output through multiple cascaded second gate driving units 2012, so as to realize that multiple gate pulses in the multiple second gate signals appear sequentially in the second frame F2, thereby driving multiple second sub-pixel groups P2 to turn on sequentially in the second frame F2.

[0052] Specifically, referring to Figures 1, 4 to 6, the sub-pixel group includes multiple sub-pixels P, and the display panel 100 includes multiple pixel circuits 202 corresponding to the multiple sub-pixels P. Each pixel circuit 202 includes at least a first transistor T1. The first-stage first gate driving unit 2011 generates a corresponding first gate signal to turn on the corresponding first transistor T1 based on a first frame start signal (correspondingly, the first frame start signal may include at least one of a first sub-frame start signal EM-STV-ODD, a second sub-frame start signal RST-STV-ODD, and a third sub-frame start signal SCAN-STV-ODD). The first-stage second gate driving unit 2012 generates a corresponding second gate signal to turn on the corresponding first transistor T1 based on a second frame start signal (correspondingly, the second frame start signal may include at least one of a fourth sub-frame start signal EM-STV-EVEN, a fifth sub-frame start signal RST-STV-EVEN, and a sixth sub-frame start signal SCAN-STV-EVEN). The second frame start signal is obtained by shifting the first frame start signal along the time axis.

[0053] Understandably, in this embodiment, the first-stage first gate driving unit 2011 and the first-stage second gate driving unit 2012 are configured to be controlled by the first frame start signal and the second frame start signal with a phase difference. This can enable multiple gate pulses in the multiple first gate signals generated by the former to appear sequentially in the first frame F1, and multiple gate pulses in the multiple second gate signals generated by the latter to appear sequentially in the second frame F2.

[0054] In this process, the gate pulse in the second gate signal of the first stage lags behind the gate pulse of the first gate signal of the last stage to avoid simultaneously turning on the first sub-pixel group P1 and the second sub-pixel group P2. Correspondingly, the phase difference between the second frame start signal and the first frame start signal also needs to be set reasonably to meet the above requirements.

[0055] Furthermore, as shown in Figures 1, 4 to 6, the plurality of first gate driving units 2011 also generate corresponding first gate signals according to a first clock signal (not shown), and the plurality of second gate driving units 2012 also generate corresponding second gate signals according to a second clock signal (not shown); wherein, the second clock signal is obtained by shifting the first clock signal along the time axis.

[0056] Understandably, the first-level or non-first-level first gate driving unit 2011 can perform shifting or other processing on the first frame start signal or the previous stage first gate signal according to the first clock signal to generate the current stage first gate signal, or control the output of the corresponding pulse in the first clock signal according to the first frame start signal or the previous stage first gate signal to serve as the gate pulse in the first gate signal; similarly, the second clock signal has a similar effect on multiple second gate driving units 2012.

[0057] Similarly, since it is necessary to satisfy that multiple gate pulses in multiple first gate signals appear sequentially in the first frame F1, and multiple gate pulses in multiple second gate signals appear sequentially in the second frame F2, it is also possible to differentiate the phases of the first clock signal and the second clock signal.

[0058] In some embodiments, as shown in Figures 1, 4 to 6, the pixel circuit 202 further includes a second transistor T2; the first gate driving unit 2011 includes an electrically disconnected first sub-gate driving unit 301 and a second sub-gate driving unit 302, with multiple first sub-gate driving units 301 cascaded and multiple second sub-gate driving units 302 cascaded; the first gate line includes a first sub-gate line electrically connected to the first sub-gate driving unit and a second sub-gate line (for transmitting the first sub-gate signal EM-ODD) electrically connected to the second sub-gate driving unit (for transmitting the second sub-gate signal RST-ODD); the second gate driving unit 2012 includes an electrically disconnected third sub-gate driving unit 303 and a fourth sub-gate driving unit 304, with multiple third sub-gate driving units 303 cascaded. The fourth sub-gate driving units 304 are cascaded together. The second gate line includes a third sub-gate line electrically connected to the third sub-gate driving unit (for transmitting the fourth sub-gate signal EM-EVEN) and a fourth sub-gate line electrically connected to the fourth sub-gate driving unit (for transmitting the fifth sub-gate signal RST-EVEN). The first sub-gate line is electrically connected to a plurality of first transistors T1 corresponding to the corresponding first sub-pixel group P1, and the third sub-gate line is electrically connected to a plurality of first transistors T1 corresponding to the corresponding second sub-pixel group. The second sub-gate line is electrically connected to a plurality of second transistors T2 corresponding to the corresponding second sub-pixel group P2, and the fourth sub-gate line is electrically connected to a plurality of second transistors T2 corresponding to the corresponding second sub-pixel group P2.

[0059] Specifically, in this embodiment, the first gate driving unit 2011 and the second gate driving unit 2012 are further configured to include multiple sub-gate driving units for generating multiple sub-gate signals, and multiple sub-gate driving units of the same type for generating the same seed gate signal in the multi-level first gate driving unit 2011 or the multi-level second gate driving unit 2012 are cascaded, so that multiple gate pulses in the multiple seed gate signals generated appear sequentially in the first frame F1.

[0060] It should be noted that, taking multiple first sub-gate driving units 301 and multiple second sub-gate driving units 302 as examples, since at least one of the pulse width, amplitude, and phase of the pulses of the first sub-gate signal EM-ODD and the second sub-gate signal RST-ODD at the same level is different, the types of frame start signals required by the two are also different. Furthermore, similarly as discussed above, the types of clock signals required by the two can also be different.

[0061] Similarly, the frame start signal and clock signal required by the third sub-gate driving unit 303 and the fourth sub-gate driving unit 304 can also be set in the same way.

[0062] In some embodiments, as shown in FIG1, the multiple subpixels in the multiple subpixel groups are further arranged into multiple subpixel columns (e.g., multiple columns of subpixels). The display panel 100 further includes: multiple data lines electrically connected to the corresponding subpixel columns; the source driver 206 electrically connected to the multiple data lines, used to output a first sub-image signal corresponding to the multiple first subpixel groups during the time period when the first frame F1 leads the corresponding second frame F2, and also used to output a second sub-image signal corresponding to the multiple second subpixel groups during the time period when the second frame F2 leads the corresponding first frame F1.

[0063] In this embodiment, the first sub-image signal can be understood as multiple data voltages required for multiple first sub-pixel groups P1 to emit light in the first frame F1, and the second sub-image signal can be understood as multiple data voltages required for multiple second sub-pixel groups P2 to emit light in the second frame F2. That is, this embodiment describes the driving method of the source driver 206 from the perspective of data signals, avoiding the mixing of multiple data voltages of multiple first sub-pixel groups P1 and multiple data voltages of multiple second sub-pixel groups P2 during the overlapping period t0, thereby reducing the complexity of image signal processing by the source driver 206 or its front-end timing controller 203.

[0064] In some embodiments, the second sub-image signal and the preceding first sub-image signal are the same. That is, the first sub-image signal and the second sub-image signal corresponding to adjacent first frames F1 and second frames F2 are the same, so that multiple first sub-pixel groups P1 first present their corresponding first sub-images, and multiple second sub-pixel groups P2 then present their corresponding second sub-images. Since the two are arranged adjacently, even if they are the same, it is difficult for the human eye to observe them. However, this can reduce the amount of data acquired by the display panel 100 and save memory for storing data.

[0065] Referring to Figures 1, 4 to 6, this example illustrates a scenario where multiple sub-pixel groups consist only of multiple first sub-pixel groups P1 and multiple second sub-pixel groups P2. The first gate driving unit 2011 also includes a fifth sub-gate driving unit 305 for generating the third sub-gate signal SCAN-ODD, and the second gate driving unit 2012 also includes a sixth sub-gate driving unit 306 for generating the sixth sub-gate signal SCAN-EVEN. Similarly, the types of sub-gate driving units in the first gate driving unit 2011 and the second gate driving unit 2012 should be the same to provide the pixel circuit 202 with the same number of different types of sub-gate signals.

[0066] Specifically, the pixel circuit 202 includes: a data writing transistor (i.e., the fifth transistor T5), the gate of which is electrically connected to the corresponding first gate line or the corresponding second gate line, and one of the source and drain of which is electrically connected to the corresponding data line to load the data signal data; and a driving transistor (i.e., the seventh transistor T7), which is electrically connected to the other of the source and drain of the data writing transistor, and one of the source and drain of which is connected to the corresponding sub-pixel P, wherein the sub-pixel P includes a self-emissive element.

[0067] Furthermore, each of the first gate line and the second gate line includes multiple sub-gate lines (e.g., but not limited to the first to fourth sub-gate lines mentioned above). The pixel circuit 202 further includes: a first reset transistor (i.e., a second transistor T2), one of the source and drain of the first reset transistor is electrically connected to the gate of the driving transistor; one of the source and drain of the driving transistor is electrically connected to the other of the source and drain of the data writing transistor; the gate of the first reset transistor and one of the source and drain of the data writing transistor are respectively electrically connected to the two sub-gate lines of the corresponding first gate line or the corresponding second gate line.

[0068] Furthermore, the pixel circuit 202 further includes a compensation transistor (i.e., the sixth transistor T6), connected between the source and drain of the driving transistor, wherein the gate of the compensation transistor and one of the source and drain of the data writing transistor are electrically connected to the corresponding sub-gate line.

[0069] Of course, the pixel circuit 202 may also include: a second reset transistor (i.e., a third transistor T3), one of the source and drain of the second reset transistor being electrically connected to the anode of the self-emissive element; one of the source and drain of the first switching transistor (i.e., the first transistor T1) being electrically connected to the other of the source and drain of the driving transistor; one of the source and drain of the second switching transistor (i.e., the fourth transistor T4) being electrically connected to one of the source and drain of the driving transistor and the anode of the self-emissive element; the gate of the second reset transistor being electrically connected to the gate of the data writing transistor; and the gates of the first switching transistor and the second switching transistor being electrically connected to the same sub-gate line of one of the corresponding first gate line or the corresponding second gate line.

[0070] Specifically, the connection relationships of the third transistor T3 to the seventh transistor T7, the storage capacitor Cst, the first node A, the second node B, the third node C, and the fourth node Q in the pixel circuit 202, as well as the types of signals loaded, can be found in Figure 6 and the description above.

[0071] As shown in Figure 5, taking a multi-sub-pixel group consisting of only one first sub-pixel group P1 and one second sub-pixel group P2 as an example, in the first frame F1, the second sub-gate signal RST-ODD drives the second transistor T2 in the first sub-pixel group P1 to conduct, so as to transmit the reset signal Vi to the fourth node Q. After that, the third sub-gate signal SCAN-ODD drives the third transistor T3, the fifth transistor T5, and the sixth transistor T6 in the first sub-pixel group P1 to conduct, so as to transmit the reset signal Vi to the third node C and the data signal data to the first node A, so that the seventh transistor T7 conducts, and the data signal data is transmitted to the fourth node Q. Until the seventh transistor T7 is turned off, the storage capacitor Cst stores the data signal data. After that, the first sub-gate signal EM-ODD drives the first transistor T1 and the fourth transistor T4 in the first sub-pixel group P1 to conduct, and a current path is formed between the terminal of the first voltage signal VDD and the terminal of the second voltage signal VSS. The driving current generated by the seventh transistor T7 drives the sub-pixel P to emit light.

[0072] The above process can be considered to occur in the first half of the first frame F1. From the beginning of the second half of the first frame F1 (corresponding to the above overlapping period t0, during which the first transistor T1 and the fourth transistor T4 are still conducting but gradually leaking current), the second frame F2 is entered. It can also include the above processes, and the first frame F1 and the second frame F2 are carried out alternately.

[0073] This application provides a driving method for a display panel, which may include, but is not limited to, the following steps and combinations thereof.

[0074] S1, control multiple first gate lines to transmit multiple first gate signals to multiple first sub-pixel groups, so that the multiple first sub-pixel groups are turned on in the first frame;

[0075] S2, control multiple second gate lines to transmit multiple corresponding second gate signals to multiple second sub-pixel groups, so that the corresponding multiple second sub-pixel groups are turned on in the second frame, and the first frame and the second frame have an overlapping time period.

[0076] Specifically, the technical features in the above steps can be found in the relevant description of the display panel above.

[0077] It should be noted that the source driver 206, gate driver 201, pixel circuit 202, first gate driving unit 2011, second gate driving unit 2012, etc. mentioned in this application can be substantially composed of at least one transistor device, and may also include at least one of capacitors and resistors, as well as wires electrically connected between different components. For specific configuration details, please refer to the above discussion.

[0078] The display device and its driving method provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display panel, wherein, Used to display images within multiple frames, the multiple frames including multiple first frames and multiple second frames, including: Multiple sub-pixel groups, including multiple first sub-pixel groups and multiple second sub-pixel groups arranged in an alternating manner; Multiple gate lines include multiple first gate lines electrically connected to multiple corresponding first sub-pixel groups and multiple second gate lines electrically connected to multiple corresponding second sub-pixel groups. The multiple first gate lines are used to transmit multiple corresponding first gate signals, and the multiple second gate lines are used to transmit multiple corresponding second gate signals. In this configuration, multiple first gate signals are used to drive multiple corresponding first sub-pixel groups to be turned on within the first frame, and multiple second gate signals are used to drive multiple corresponding second sub-pixel groups to be turned on within the second frame. The first frame and the second frame have an overlapping time period. The plurality of sub-pixel groups are composed of a plurality of first sub-pixel groups and a plurality of second sub-pixel groups arranged alternately; The multi-frame is composed of multiple first frames and multiple second frames alternately, with each of the first frames overlapping with each of the two adjacent second frames, and each of the second frames overlapping with each of the two adjacent first frames. The plurality of sub-pixel groups further include a plurality of third sub-pixel groups, wherein at least one other is provided between each of the first sub-pixel group, the second sub-pixel group and the third sub-pixel group; The multiple gate lines also include multiple third gate lines electrically connected to the corresponding multiple third sub-pixel groups, and the multiple third gate lines are used to transmit the corresponding multiple third gate signals; The plurality of third gate signals are used to drive the corresponding plurality of third sub-pixel groups to be turned on in the third frame. The plurality of frames include the first frame, the second frame and the third frame arranged in sequence, and the third frame has an overlapping time period with the first frame and the second frame.

2. The display panel of claim 1, wherein, The duration of the first frame is equal to the duration of the second frame, the duration of the two overlapping periods of the first frame and the two adjacent second frames is equal, and the duration of the two overlapping periods of the second frame and the two adjacent first frames is equal.

3. The display panel of claim 1 or 2, wherein, It also includes a gate driver electrically connected to the plurality of said sub-pixel groups, the gate driver comprising: A plurality of cascaded first gate driving units, each of which is electrically connected to a corresponding first gate line; A plurality of cascaded second gate drive units, each of which is electrically connected to a corresponding second gate line.

4. The display panel of claim 3, wherein, The sub-pixel group includes a plurality of sub-pixels, and the display panel includes a plurality of pixel circuits corresponding to the plurality of sub-pixels, wherein the pixel circuits include at least a first transistor; The first-stage first gate driving unit generates a corresponding first gate signal according to the first frame start signal to turn on the corresponding first transistor, and the first-stage second gate driving unit generates a corresponding second gate signal according to the second frame start signal to turn on the corresponding first transistor. The second frame start signal is obtained by shifting the first frame start signal along the time axis.

5. The display panel of claim 4, wherein, The plurality of first gate driving units further generate corresponding first gate signals according to the first clock signal, and the plurality of second gate driving units further generate corresponding second gate signals according to the second clock signal; The second clock signal is obtained by shifting the first clock signal along the time axis.

6. The display panel of claim 4, wherein, The pixel circuit also includes a second transistor; The first gate driving unit includes an electrically disconnected first sub-gate driving unit and a second sub-gate driving unit. A plurality of the first sub-gate driving units are cascaded together, and a plurality of the second sub-gate driving units are cascaded together. The first gate line includes a first sub-gate line electrically connected to the first sub-gate driving unit and a second sub-gate line electrically connected to the second sub-gate driving unit. The second gate driving unit includes an electrically disconnected third sub-gate driving unit and a fourth sub-gate driving unit, a plurality of the third sub-gate driving units are cascaded, a plurality of the fourth sub-gate driving units are cascaded, and the second gate line includes a third sub-gate line electrically connected to the third sub-gate driving unit and a fourth sub-gate line electrically connected to the fourth sub-gate driving unit. Wherein, the first sub-gate line is electrically connected to a plurality of first transistors corresponding to the corresponding first sub-pixel group, and the third sub-gate line is electrically connected to a plurality of first transistors corresponding to the corresponding second sub-pixel group; The second sub-gate line is electrically connected to a plurality of second transistors corresponding to the first sub-pixel group, and the fourth sub-gate line is electrically connected to a plurality of second transistors corresponding to the second sub-pixel group.

7. A display panel, wherein, Used to display images within multiple frames, the multiple frames including multiple first frames and multiple second frames, including: Multiple sub-pixel groups, including multiple first sub-pixel groups and multiple second sub-pixel groups arranged in an alternating manner; Multiple gate lines include multiple first gate lines electrically connected to multiple corresponding first sub-pixel groups and multiple second gate lines electrically connected to multiple corresponding second sub-pixel groups. The multiple first gate lines are used to transmit multiple corresponding first gate signals, and the multiple second gate lines are used to transmit multiple corresponding second gate signals. In this configuration, multiple first gate signals are used to drive multiple corresponding first sub-pixel groups to be turned on within the first frame, and multiple second gate signals are used to drive multiple corresponding second sub-pixel groups to be turned on within the second frame. The first frame and the second frame have an overlapping time period.

8. The display panel of claim 7, wherein, The plurality of sub-pixel groups are composed of a plurality of first sub-pixel groups and a plurality of second sub-pixel groups arranged alternately; The multi-frames are composed of multiple first frames and multiple second frames alternately, with each of the first frames having an overlapping time period with each of the two adjacent second frames, and each of the second frames having an overlapping time period with each of the two adjacent first frames.

9. The display panel of claim 8, wherein, The duration of the first frame is equal to the duration of the second frame, the duration of the two overlapping periods of the first frame and the two adjacent second frames is equal, and the duration of the two overlapping periods of the second frame and the two adjacent first frames is equal.

10. The display panel of claim 7, wherein, The plurality of said sub-pixel groups further include a plurality of third sub-pixel groups, wherein at least one other is provided between each of the first sub-pixel group, the second sub-pixel group and the third sub-pixel group; The multiple gate lines also include multiple third gate lines electrically connected to the corresponding multiple third sub-pixel groups, and the multiple third gate lines are used to transmit the corresponding multiple third gate signals; The plurality of third gate signals are used to drive the corresponding plurality of third sub-pixel groups to be turned on in the third frame. The plurality of frames include the first frame, the second frame and the third frame arranged in sequence, and the third frame has an overlapping time period with the first frame and the second frame.

11. The display panel of any of claims 7 to 10, wherein, It also includes a gate driver electrically connected to the plurality of said sub-pixel groups, the gate driver comprising: A plurality of cascaded first gate driving units, each of which is electrically connected to a corresponding first gate line; A plurality of cascaded second gate drive units, each of which is electrically connected to a corresponding second gate line.

12. The display panel of claim 11, wherein, The sub-pixel group includes a plurality of sub-pixels, and the display panel includes a plurality of pixel circuits corresponding to the plurality of sub-pixels, wherein the pixel circuits include at least a first transistor; The first-stage first gate driving unit generates a corresponding first gate signal according to the first frame start signal to turn on the corresponding first transistor, and the first-stage second gate driving unit generates a corresponding second gate signal according to the second frame start signal to turn on the corresponding first transistor. The second frame start signal is obtained by shifting the first frame start signal along the time axis.

13. The display panel of claim 12, wherein, The plurality of first gate driving units further generate corresponding first gate signals according to the first clock signal, and the plurality of second gate driving units further generate corresponding second gate signals according to the second clock signal; The second clock signal is obtained by shifting the first clock signal along the time axis.

14. The display panel of claim 12, wherein, The pixel circuit also includes a second transistor; The first gate driving unit includes an electrically disconnected first sub-gate driving unit and a second sub-gate driving unit. A plurality of the first sub-gate driving units are cascaded together, and a plurality of the second sub-gate driving units are cascaded together. The first gate line includes a first sub-gate line electrically connected to the first sub-gate driving unit and a second sub-gate line electrically connected to the second sub-gate driving unit. The second gate driving unit includes an electrically disconnected third sub-gate driving unit and a fourth sub-gate driving unit, a plurality of the third sub-gate driving units are cascaded, a plurality of the fourth sub-gate driving units are cascaded, and the second gate line includes a third sub-gate line electrically connected to the third sub-gate driving unit and a fourth sub-gate line electrically connected to the fourth sub-gate driving unit. Wherein, the first sub-gate line is electrically connected to a plurality of first transistors corresponding to the corresponding first sub-pixel group, and the third sub-gate line is electrically connected to a plurality of first transistors corresponding to the corresponding second sub-pixel group; The second sub-gate line is electrically connected to a plurality of second transistors corresponding to the first sub-pixel group, and the fourth sub-gate line is electrically connected to a plurality of second transistors corresponding to the second sub-pixel group.

15. The display panel of any of claims 7 to 10, 12 to 14, wherein, The subpixels in the plurality of said subpixel groups are further arranged into a plurality of subpixel columns, and the display panel further includes: Multiple data lines, which are electrically connected to the corresponding sub-pixel columns; A source driver, electrically connected to multiple data lines, is used to output a first sub-image signal corresponding to multiple first sub-pixel groups during a period when the first frame leads the corresponding second frame, and is also used to output a second sub-image signal corresponding to multiple second sub-pixel groups during a period when the second frame leads the corresponding first frame.

16. The display panel of claim 15, wherein, The second sub-image signal is the same as the first sub-image signal preceding the second sub-image signal.

17. The display panel of any of claims 7 to 10, 12 to 14, 16, wherein, The sub-pixels in the plurality of sub-pixel groups are further arranged into plurality of sub-pixel columns. The display panel includes multiple data lines and multiple pixel circuits corresponding to the plurality of sub-pixels. The data lines are electrically connected to the corresponding sub-pixel columns. The pixel circuits include: A data writing transistor, wherein the gate of the data writing transistor is electrically connected to the corresponding first gate line or the corresponding second gate line, and one of the source and drain of the data writing transistor is electrically connected to the corresponding data line; A driving transistor is electrically connected to the other of the source and drain of the data writing transistor, and the source and drain of the driving transistor are connected to the corresponding sub-pixel, the sub-pixel including a self-emissive element.

18. The display panel of claim 17, wherein, Each of the first gate line and the second gate line includes multiple bun gate lines, and the pixel circuit further includes: A first reset transistor, wherein one of its source and drain is electrically connected to the gate of the driving transistor. One of the source and drain of the driving transistor is electrically connected to the other of the source and drain of the data writing transistor. The gate of the first reset transistor and one of the source and drain of the data write transistor are electrically connected to two of the corresponding first gate line or the corresponding second gate line.

19. The display panel of claim 18, wherein, The pixel circuit also includes: A compensation transistor is connected between the source and drain of the driving transistor, and the gate of the compensation transistor and one of the source and drain of the data writing transistor are electrically connected to the corresponding sub-gate line.

20. A driving method of a display panel, wherein, For driving the display panel as described in any one of claims 7 to 19, comprising: Control multiple first gate lines to transmit corresponding multiple first gate signals to multiple first sub-pixel groups, so that the corresponding multiple first sub-pixel groups are turned on in the first frame; Multiple second gate lines are controlled to transmit multiple corresponding second gate signals to multiple second sub-pixel groups, so that the corresponding multiple second sub-pixel groups are turned on in the second frame, and the first frame and the second frame have an overlapping period.

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