Silicon-based back-contact heterojunction solar cell, manufacturing method therefor, and cell module comprising same

Abstract

The present invention relates to the technical field of solar cells, and in particular to a silicon-based back-contact heterojunction solar cell, a manufacturing method therefor, and a cell module comprising same. In the silicon-based back-contact heterojunction solar cell, an ultrathin oxygen-doped amorphous silicon layer is added on an amorphous silicon passivation layer, thereby preventing epitaxial growth of single-crystal silicon during deposition of the amorphous silicon passivation layer from affecting the film formation quality and passivation performance of the amorphous silicon passivation layer. Additionally, an oxygen-doped amorphous silicon layer is prepared on the outermost side of a P-type amorphous silicon layer as a sacrificial layer; and because boron and oxygen tend to form a stable structure, the oxygen-doped amorphous silicon layer can effectively cover the P-type amorphous silicon layer to prevent boron out-diffusion, thereby enabling the amorphous silicon passivation layer and the P-type amorphous silicon layer to be deposited in a same PECVD system, eliminating the need for an additional PECVD system, and reducing device costs.

Description

Silicon-based back-contact heterojunction solar cells and their fabrication methods, cell modules

[0001] Cross-references to related applications

[0002] This disclosure claims priority to Chinese Patent Application No. 202411886166.8, filed on December 20, 2024, entitled "Silicon-based back-contact heterojunction solar cell and its preparation method and cell module", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure belongs to the field of solar cell technology, specifically relating to a silicon-based back-contact heterojunction solar cell, its preparation method, and cell module. Background Technology

[0004] In the current manufacturing process of silicon-based back-contact heterojunction solar cells, a plate-type PECVD equipment is required to deposit amorphous silicon passivation layers and doped semiconductor layers. However, if the amorphous silicon passivation layer and the doped semiconductor layer are deposited on the same substrate, there is a problem of cross-contamination. In particular, boron in P-type amorphous silicon can seriously affect the passivation effect on the silicon wafer surface. In addition, when depositing amorphous silicon passivation layers on the surface of monocrystalline silicon, epitaxy is easy to occur. Monocrystalline epitaxial growth can also affect the passivation effect of amorphous silicon passivation layers on the surface of monocrystalline silicon.

[0005] It should be noted that this part of the disclosure only provides background technology related to this disclosure, and does not necessarily constitute prior art or publicly known technology.

[0006] Public content

[0007] The purpose of this disclosure is to overcome the problems that existing silicon-based back-contact heterojunction solar cells have, when depositing amorphous silicon passivation layers on the surface of monocrystalline silicon, the monocrystalline silicon is prone to epitaxy, which affects the quality of amorphous silicon and the passivation effect of the single silicon wafer interface. In addition, the P-type amorphous silicon deposition system has serious boron contamination, which requires the amorphous silicon passivation layer and the P-type amorphous silicon to be deposited separately in two PECVD systems.

[0008] To achieve the above objectives, embodiments of this disclosure provide a silicon-based back-contact heterojunction solar cell, comprising:

[0009] A silicon wafer with a front and a back side;

[0010] A first semiconductor layer is disposed on the back side of the silicon wafer, the first semiconductor layer comprising a tunneling silicon oxide layer and a doped polycrystalline silicon layer sequentially formed on the silicon wafer;

[0011] The first semiconductor layer is separated by multiple second semiconductor opening regions. The second semiconductor opening regions and the surface of the first semiconductor layer surrounding the second semiconductor opening regions are covered with second semiconductor layers. The second semiconductor layer is composed of an ultrathin oxygen-doped amorphous silicon layer, an amorphous silicon passivation layer and a P-type amorphous silicon layer.

[0012] A passivation layer and an antireflection layer are sequentially disposed on the front side of a silicon wafer. The passivation layer is any one or more materials selected from aluminum oxide, silicon oxide, amorphous silicon, or microcrystalline silicon. The antireflection layer is at least one of silicon nitride, silicon oxynitride, or silicon oxide.

[0013] The thickness of the ultrathin oxygen-doped amorphous silicon layers is 0.2–1 nm, and the oxygen doping content is 3%–30%.

[0014] Optionally, a first semiconductor opening region is provided between adjacent second semiconductor opening regions, and the first semiconductor opening region separates the second semiconductor layer;

[0015] Both the first semiconductor opening region and the second semiconductor layer are covered with a transparent conductive film layer, and an isolation trench is provided between adjacent first semiconductor opening regions and second semiconductor opening regions; the isolation trench separates the transparent conductive film layer located in the first semiconductor opening region and the transparent conductive film layer located on the second semiconductor layer.

[0016] Optionally, the thickness of the tunneling silicon oxide layer is 1-2 nm, the thickness of the doped polycrystalline silicon layer is 50-150 nm, and the thickness of the amorphous silicon passivation layer is 3-10 nm; the ratio of the thickness of the amorphous silicon passivation layer to the thickness of the ultrathin oxygen-doped amorphous silicon layer is (3-50):1.

[0017] Optionally, the thickness of the antireflection layer is 70 nm to 150 nm.

[0018] Optionally, a textured surface is formed on the front side of the silicon wafer and on the surface of the silicon wafer located in the second semiconductor opening region, and the second semiconductor layer and the third semiconductor layer respectively fill the textured surface in the corresponding regions.

[0019] Optionally, the thickness of the amorphous silicon passivation layer is 3–10 nm, the thickness of the P-type amorphous silicon layer is 5–15 nm, and the boron doping concentration in the P-type amorphous silicon layer is 5e. 18 cm -3 ~4e 20 cm -3 .

[0020] Optionally, the silicon-based back-contact heterojunction solar cell further includes: a metal electrode; the metal electrode is disposed on the transparent conductive film layer of the first semiconductor opening region and the second semiconductor opening region.

[0021] Optionally, an ultrathin oxygen-doped amorphous silicon layer is formed between the passivation layer and the silicon wafer.

[0022] Secondly, embodiments of this disclosure also provide a battery assembly comprising a silicon-based back-contact heterojunction solar cell as described in the first aspect.

[0023] Thirdly, embodiments of this disclosure also provide a method for fabricating a silicon-based back-contact heterojunction solar cell, configured to fabricate a silicon-based back-contact heterojunction solar cell as described in the first aspect, the method comprising the following steps:

[0024] Provide a silicon wafer;

[0025] A tunneling silicon oxide layer and a doped polycrystalline silicon layer are sequentially formed on the back side of the silicon wafer to obtain the first semiconductor layer;

[0026] A mask layer is prepared on the surface of the first semiconductor layer;

[0027] Part of the mask layer and the corresponding portion of the first semiconductor layer are removed to form alternating second semiconductor opening regions;

[0028] The remaining mask layer, N-type doped polycrystalline layer and tunneling silicon oxide layer in the second semiconductor opening region are removed by texturing and cleaning. At the same time, a textured surface is formed on the front side of the silicon wafer and the surface of the silicon wafer located in the second semiconductor opening region. Then, part or all of the mask layer on the back side of the silicon wafer located outside the second semiconductor opening region is removed.

[0029] A passivation layer and an anti-reflection layer are sequentially formed on the front side of the silicon wafer, and an ultrathin oxygen-doped amorphous silicon layer, an amorphous silicon passivation layer, a P-type amorphous silicon layer, and an oxygen-doped amorphous silicon layer are sequentially formed on the back side of the silicon wafer.

[0030] During the fabrication of the ultrathin oxygen-doped amorphous silicon layer on the back side of the silicon wafer, silane and carbon dioxide or other gases capable of providing an oxygen source are introduced; wherein the ratio of carbon dioxide to silane is (3-30):100, and the deposition power density is 10-100 mW / cm³. 2 The gas pressure is 30–150 Pa, the thickness of the ultrathin oxygen-doped amorphous silicon layer is 0.2–1 nm, and the oxygen doping content is 3–30%. During the preparation of the oxygen-doped amorphous silicon layer, nitrous oxide or other gases that can provide oxygen, silane, and hydrogen are introduced, wherein the ratio of nitrous oxide, silane, and hydrogen is (1–10):1:(0–10), and the deposition power density is 5–50 mW / cm³. 2 The gas pressure is 30–150 Pa, the oxygen content is 20–70%, and the hydrogen content is 0–10%.

[0031] An opening is etched on the back of the silicon wafer to form a first semiconductor opening region that is spaced apart from the second semiconductor opening region, and the first semiconductor opening region exposes the doped polysilicon layer.

[0032] Remove the residual oxygen-doped amorphous silicon layer from the surface of the P-type amorphous silicon layer, and then deposit a transparent conductive film layer on the back side of the resulting silicon wafer.

[0033] An opening is made in the transparent conductive film layer between the first semiconductor opening region and the second semiconductor opening region to form an isolation trench;

[0034] Metal electrodes are formed on the transparent conductive film layer of the first semiconductor opening region and the transparent conductive film layer of the second semiconductor opening region.

[0035] The embodiments disclosed herein have at least the following beneficial effects:

[0036] The silicon-based back-contact heterojunction solar cell and its fabrication method provided in this disclosure avoid the impact of single-crystal epitaxial growth on the film quality and passivation effect of the amorphous silicon passivation layer by adding an ultrathin oxygen-doped amorphous silicon layer to the amorphous silicon passivation layer. Simultaneously, an oxygen-doped amorphous silicon layer is prepared as a sacrificial layer on the outermost layer of the P-type amorphous silicon layer. Furthermore, since boron and oxygen readily form a stable structure, the oxygen-doped amorphous silicon layer can effectively cover the P-type amorphous silicon layer, preventing boron leakage. This allows the amorphous silicon passivation layer and the P-type amorphous silicon layer to be deposited within the same PECVD system, thereby reducing the need for a separate PECVD system and lowering equipment costs. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0038] Figure 1 is a schematic diagram of the internal structure of a silicon-based back-contact heterojunction solar cell provided in an embodiment of this disclosure.

[0039] Figure 2 is a process flow diagram of a method for fabricating a silicon-based back-contact heterojunction solar cell according to an embodiment of this disclosure;

[0040] Figure 3 is a process structure diagram corresponding to steps S01 to S05 in a method for preparing a silicon-based back-contact heterojunction solar cell according to an embodiment of this disclosure.

[0041] Figure 4 is a process structure diagram corresponding to step S06 in a method for preparing a silicon-based back-contact heterojunction solar cell according to an embodiment of this disclosure;

[0042] Figure 5 is a process structure diagram corresponding to step S07 in a method for preparing a silicon-based back-contact heterojunction solar cell according to an embodiment of this disclosure;

[0043] Figure 6 is a process structure diagram corresponding to step S08 in a method for preparing a silicon-based back-contact heterojunction solar cell according to an embodiment of this disclosure;

[0044] Figure 7 is a process structure diagram corresponding to steps S08 to S10 in a method for preparing a silicon-based back-contact heterojunction solar cell according to an embodiment of this disclosure. Detailed Implementation

[0045] The technical solutions of this application will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0046] It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0047] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the term “comprising” as used in the specification of this application means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. The term “and / or” as used herein includes all or any units and all combinations of one or more associated listed items.

[0048] Firstly, as shown in Figure 1, this disclosure provides a silicon-based back-contact heterojunction solar cell, comprising: a silicon wafer 10, a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. The silicon wafer 10 has a front side and a back side. The front side refers to the light-receiving surface of the silicon wafer 10, and the back side is the opposite side of the light-receiving surface. In Figure 1, the upward-facing surface of the silicon wafer 10 is the back side, and the downward-facing surface is the front side. In this disclosure, the surface closer to the silicon wafer 10 is generally considered as the inside, and the surface farther from the silicon wafer 10 as the outside. The silicon wafer 10 is N-type or P-type, preferably N-type.

[0049] Specifically, a first semiconductor layer is disposed on the back side of the silicon wafer 10. The first semiconductor layer includes a tunneling silicon oxide layer 11 and a doped polysilicon layer 12 sequentially formed on the silicon wafer 10, i.e., the tunneling silicon oxide layer 11 is closer to the back side of the silicon wafer 10 than the doped polysilicon layer 12. Optionally, the doped polysilicon layer 12 is composed of an intrinsic polysilicon layer and a phosphorus-doped polysilicon layer, with the intrinsic polysilicon layer being closer to the back side of the silicon wafer 10 than the phosphorus-doped polysilicon layer. The doped polysilicon layer 12 is preferably N-type.

[0050] In this embodiment, multiple openings are formed on the first semiconductor layer through an etching process to obtain second semiconductor opening regions W2, i.e., the first semiconductor layer is separated by multiple second semiconductor opening regions W2. The second semiconductor layer covers the second semiconductor opening regions W2 (including the sidewalls of the second semiconductor opening regions W2) and the surface of the first semiconductor layer surrounding the second semiconductor opening regions W2. A first semiconductor opening region W1 is provided between adjacent second semiconductor opening regions W2, separating the second semiconductor layers. The second semiconductor layer consists of an ultrathin oxygen-doped amorphous silicon layer 15B, an amorphous silicon passivation layer 15, and a P-type amorphous silicon layer 16. The amorphous silicon passivation layer 14 is closer to the back side of the silicon wafer 10 than the P-type amorphous silicon layer.

[0051] Optionally, the thickness of the amorphous silicon passivation layer 14 is 3-10 nm, the thickness of the p-type amorphous silicon layer is 5-15 nm, and the boron doping concentration in the p-type amorphous silicon layer is 5e. 18 cm -3 ~4e 20 cm -3 .

[0052] To ensure the passivation effect of the amorphous silicon passivation layer 14 on the silicon wafer 10, an ultrathin oxygen-doped amorphous silicon layer 15B is provided before the amorphous silicon passivation layer 14 of the second semiconductor layer. The thickness of the ultrathin oxygen-doped amorphous silicon layer 15B is 0.2-1 nm, and the oxygen doping content is 3%-30%. Optionally, the thickness of the tunneling silicon oxide layer 11 is 1-2 nm, the thickness of the doped polycrystalline silicon layer 12 is 50-150 nm, and the ratio of the thickness of the amorphous silicon passivation layer 15 to the thickness of the ultrathin oxygen-doped amorphous silicon layer 15B is (3-50):1. This comprehensively considers the passivation effect of the silicon wafer interface and the tunneling transport effect of charge carriers, which can achieve better passivation without increasing the series resistance and affecting the flyback factor (FF).

[0053] Optionally, an ultrathin oxygen-doped amorphous silicon layer 14B is also formed between the third semiconductor layer and the silicon wafer 10 on the front side. The ultrathin oxygen-doped amorphous silicon layer 14B has the same process parameters and thickness as the ultrathin oxygen-doped amorphous silicon layer 15B. The thickness of the ultrathin oxygen-doped amorphous silicon layer 14B is 0.2–1 nm, and the oxygen doping content is 3%–30%. The ultrathin oxygen-doped amorphous silicon layer 14B effectively separates the passivation layer from the front side of the silicon wafer 10.

[0054] Optionally, the thickness of the passivation layer 14 is 3-10 nm, and the ratio of the thickness of the passivation layer 14 to the thickness of the ultrathin oxygen-doped amorphous silicon layer 14B is (3-50):1.

[0055] Optionally, a first semiconductor opening region is provided between adjacent second semiconductor opening regions, and the first semiconductor opening region separates the second semiconductor layer; both the first semiconductor opening region and the second semiconductor layer are covered with a transparent conductive film layer 18, and an isolation trench is provided between adjacent first semiconductor opening regions and second semiconductor opening regions; the isolation trench separates the transparent conductive film layer 18 located in the first semiconductor opening region and the transparent conductive film layer 18 located on the second semiconductor layer.

[0056] Optionally, the width of the first semiconductor opening region is 0.1 mm to 0.3 mm; the width of the second semiconductor opening region is 0.3 mm to 0.6 mm; and the width of the isolation trench is 30 μm to 200 μm.

[0057] Optionally, referring to Figure 1, the silicon-based back-contact heterojunction solar cell further includes an antireflection layer; the antireflection layer is disposed on the side of the passivation layer away from the silicon wafer 10. The antireflection layer 7 is mainly configured to reduce light reflection, thereby improving photoelectric conversion efficiency. The thickness of the antireflection layer is generally 80mm to 100mm; too thick a layer is not conducive to light transmission, while too thin a layer will result in poor reflection of incident light. Optionally, the antireflection layer consists of at least one of a silicon nitride antireflection layer, a silicon oxynitride layer, a silicon oxynitride antireflection layer, and a silicon oxide layer.

[0058] On the ground, a textured surface is formed on the front side of the silicon wafer 10 and on the surface of the silicon wafer 10 located in the second semiconductor opening region. The second semiconductor layer and the third semiconductor layer respectively fill the textured surface in the corresponding region. The textured surface is formed by an acid cleaning process, which can not only remove excess film material, but also help increase the bonding force between film layers.

[0059] Optionally, referring to FIG1, the silicon-based back-contact heterojunction solar cell provided in this embodiment of the present disclosure further includes: a metal electrode 19; the metal electrode 19 is disposed on the transparent conductive film layer 18 of the first semiconductor opening region and the second semiconductor opening region, wherein the metal electrode 19 of the first semiconductor opening region and the metal electrode 19 of the second semiconductor opening region correspond to different polarities.

[0060] Secondly, embodiments of this disclosure also provide a battery assembly comprising a silicon-based back-contact heterojunction solar cell as described in any of the first aspects.

[0061] Thirdly, this disclosure also provides a method for fabricating a silicon-based back-contact heterojunction solar cell, configured to fabricate a silicon-based back-contact heterojunction solar cell as described in the first aspect, as shown in FIG2. The method for fabricating a silicon-based back-contact heterojunction solar cell includes the following steps:

[0062] S01. Provide a silicon wafer 10.

[0063] Optionally, step S01 may also include other conventional operations, such as double-sided polishing of the silicon wafer 10 and optional cleaning. The silicon wafer 10 is preferably an N-type monocrystalline silicon wafer 10. The silicon wafer 101 can be a Czochralski-grown monocrystalline silicon wafer 10 or a cast monocrystalline silicon wafer 10.

[0064] S02. A tunneling silicon oxide layer 11 and a doped polycrystalline silicon layer 12 are sequentially prepared on the back side of the silicon wafer 10 to obtain the first semiconductor layer.

[0065] Optionally, the first semiconductor layer can be formed by in-situ doping deposition and annealing using tubular PECVD, LPCVD, or PVD. Preferably, tubular PECVD in-situ doping is used. In the first stage, nitrous oxide is introduced and glow discharge is activated. A tunneling silicon oxide layer 11 is formed through a chemical reaction. The reaction temperature of the first stage is 400–550°C, the reaction pressure is 100–2000 mtorr, and the time is 10–60 seconds. The thickness of the tunneling silicon oxide layer 11 is 1–2 nm. In the second stage, silane, phosphine, and hydrogen are introduced and glow discharge is activated. A phosphorus-doped polycrystalline silicon layer is formed through a chemical reaction. The reaction temperature of the second stage is 400–550°C, the reaction time is 400–1200 seconds, the reaction pressure is 1000–4000 mtorr, and the thickness of the phosphorus-doped polycrystalline silicon layer is 80–100 nm. The layer is then crystallized by annealing at 900°C.

[0066] S03. Prepare a mask layer 13 on the surface of the first semiconductor layer.

[0067] Optionally, a mask layer 13 is grown on the surface of the first semiconductor layer after cleaning. The mask layer 13 can be silicon nitride, silicon oxide, or silicon oxynitride. Preferably, silicon nitride is deposited by tubular PECVD as the mask layer 13 with a thickness of 50-200 nm, and hydrofluoric acid is used to remove the silicon nitride coated on the front side.

[0068] S04. Remove part of the mask layer 13 and the corresponding part of the first semiconductor layer to form an alternately arranged second semiconductor opening region.

[0069] Optionally, referring to Figure 3, an opening is etched on the back side of the silicon wafer 10 using laser or mask etching to form a second semiconductor opening region W2. The width of the second semiconductor opening region W2 is 0.3 to 0.6 mm, and the mask layer 13, the N-type doped polycrystalline layer, and the tunneling silicon oxide layer 11 within the second semiconductor opening region W2 are etched away.

[0070] S05. The remaining mask layer 13, N-type doped polycrystalline layer and tunneling silicon oxide layer 11 in the second semiconductor opening area are removed by texturing and cleaning. At the same time, a textured surface is formed on the front side of the silicon wafer 10 and the surface of the silicon wafer 10 located in the second semiconductor opening area. Then, all or part of the mask layer 13 on the back side of the silicon wafer 10 located outside the second semiconductor opening area is removed.

[0071] Optionally, referring to Figure 3, the mask layer 13 outside the second semiconductor opening region W2 on the back side of the silicon wafer 10 is removed by hydrofluoric acid cleaning.

[0072] S06. A passivation layer 14 and an antireflection layer 17 are sequentially formed on the front side of the silicon wafer 10; an ultrathin oxygen-doped amorphous silicon layer 15B, an amorphous silicon passivation layer 15, a P-type amorphous silicon layer 16, and an oxygen-doped amorphous silicon layer 16B are sequentially formed on the back side of the silicon wafer 10, as shown in Figure 4. During the fabrication of the ultrathin oxygen-doped amorphous silicon layer 15B, silane and carbon dioxide or other gases that can provide an oxygen source are introduced; wherein the ratio of carbon dioxide to silane is (3-30):100, and the deposition power density is 10-100 mW / cm³. 2 The air pressure is 30–150 Pa, and the oxygen content is 3–30%.

[0073] During the preparation of the oxygen-doped amorphous silicon layer 16B, nitrous oxide or other gases capable of providing an oxygen source, silane, and hydrogen are introduced, wherein the ratio of nitrous oxide, silane, and hydrogen is (1-5):1:(0-10), and the deposition power density is 5-50 mW / cm³. 2 The gas pressure is 30–150 Pa, the oxygen content is 20–70%, and the hydrogen content is 0–10%.

[0074] Optionally, the ultrathin oxygen-doped amorphous silicon layer 15B, the amorphous silicon passivation layer 15, the P-type amorphous silicon layer 16, and the oxygen-doped amorphous silicon layer 16B on the back of the silicon wafer 10 are completed in the same system without the need for breaking holes or replacing the carrier board.

[0075] Optionally, the passivation layer 14 on the front side of the silicon wafer can be any one or more materials selected from aluminum oxide, silicon oxide, amorphous silicon, or microcrystalline silicon, and the antireflection layer can be at least one of silicon nitride, silicon oxynitride, and silicon oxide.

[0076] S07. An opening is etched on the back side of the silicon wafer 10 to form a first semiconductor opening region that is spaced apart from the second semiconductor opening region. The first semiconductor opening region exposes the doped polysilicon layer 12.

[0077] Optionally, referring to Figure 5, using laser or mask etching, openings are etched on the back side of the silicon wafer 10 using an oxygen-doped amorphous silicon layer 16B as a mask layer 13 to form a first semiconductor opening region W1 spaced apart from the second semiconductor opening region W2, followed by cleaning. The width of the first semiconductor opening region W1 is 0.1 mm to 0.3 mm. Optionally, the laser is an ultraviolet or green laser with a pulse width of less than 50 ns.

[0078] S08. Remove the residual oxygen-doped amorphous silicon layer 16B from the surface of the P-type amorphous silicon layer, and then deposit a transparent conductive film layer 18 on the back side of the resulting silicon wafer 10.

[0079] Specifically, referring to Figures 6 and 7, in this embodiment, an oxygen-doped amorphous silicon layer 16B of a certain thickness is prepared on the P-type amorphous silicon layer of the second semiconductor layer. The oxygen-doped amorphous silicon layer 16B can be used as a mask layer 13 for preparing the first semiconductor opening region to protect the other film layers below and avoid etching contamination. Moreover, the oxygen-doped amorphous silicon layer is easy to remove, which is beneficial to improving process efficiency and saving production costs.

[0080] Optionally, a transparent conductive film layer 18 is deposited on the back side of the silicon wafer 10 using physical vapor deposition (PVD) or activated plasma deposition (RPD). The thickness of the transparent conductive film layer 18 is 30 nm to 120 nm. The material of the transparent conductive film layer 18 can be an indium oxide thin film doped with tin oxide, titanium oxide, zinc oxide or gallium oxide, or a zinc oxide thin film doped with aluminum oxide, gallium oxide or boron oxide.

[0081] S09. An opening is made in the transparent conductive film layer 18 between the first semiconductor opening region and the second semiconductor opening region to form an isolation trench.

[0082] Optionally, referring to Figure 7, an isolation trench is formed between the first semiconductor opening region and the second semiconductor region by means of laser or etching, and the width of the isolation trench is 30um to 200um.

[0083] S10, a metal electrode 19 is formed on the transparent conductive film layer 18 of the first semiconductor opening region and the transparent conductive film layer 18 of the second semiconductor opening region.

[0084] Optionally, referring to FIG7, a first electrode is formed on the conductive film layer 18 of the first semiconductor region, and a second electrode is formed on the conductive film layer 18 of the second semiconductor region. The silver gate electrode can be formed by screen printing and low-temperature sintering, or the electrode can be formed by electroplating. Preferably, the gate electrode is formed by electroplating.

[0085] The method for fabricating silicon-based back-contact heterojunction solar cells in this embodiment may also include other conventional steps, which can be selected according to actual needs, and will not be described in detail here.

[0086] The embodiments of this disclosure described below are exemplary and are only used to explain this disclosure, and should not be construed as limiting this disclosure.

[0087] Example 1

[0088] A silicon-based back-contact heterojunction solar cell, the structure of which is shown in Figure 1, and its fabrication method is shown in Figure 2, including:

[0089] S01. Provide a silicon wafer 10.

[0090] S02. A tunneling silicon oxide layer and a doped polycrystalline silicon layer are sequentially prepared on the back side of silicon wafer 10 to obtain the first semiconductor layer.

[0091] S03. Prepare a mask layer on the surface of the first semiconductor layer.

[0092] S04. Remove part of the mask layer and the corresponding part of the first semiconductor layer to form an alternately arranged second semiconductor opening region.

[0093] S05. The remaining mask layer, N-type doped polycrystalline layer and tunneling silicon oxide layer in the second semiconductor opening region are removed by texturing and cleaning, and a textured surface is formed on the front side of the silicon wafer 10 and on the surface of the silicon wafer 10 located in the second semiconductor opening region.

[0094] S06. A passivation layer and an antireflection layer are sequentially formed on the front side of the silicon wafer 10. An ultrathin oxygen-doped amorphous silicon layer 15B, an amorphous silicon passivation layer 15, a P-type amorphous silicon layer 16, and an oxygen-doped amorphous silicon layer 16B are fabricated on the back side of the silicon wafer 10. Silane and carbon dioxide are introduced during the fabrication of the ultrathin oxygen-doped amorphous silicon layer 15B; wherein the ratio of carbon dioxide to silane is 15:100, and the deposition power density is 30 mW / cm³. 2 The gas pressure is 100 Pa. The thickness of the ultrathin oxygen-doped amorphous silicon layer 15B is 0.5 nm, and the oxygen doping content is 15%. The thickness of the amorphous silicon passivation layer 15 is 6 nm. During the preparation of the oxygen-doped amorphous silicon layer 16B, nitrous oxide or other gases that can provide oxygen, silane, and hydrogen are introduced, wherein the ratio of nitrous oxide, silane, and hydrogen is 5:1:0, and the deposition power density is 10 mW / cm³. 2 The gas pressure is 100 Pa, the oxygen content is 65%, and the hydrogen content is 1%.

[0095] S07. An opening is etched on the back side of the silicon wafer 10 obtained in step S06 to form a first semiconductor opening region that is spaced apart from the second semiconductor opening region. The first semiconductor opening region exposes the doped polysilicon layer.

[0096] S08. Remove the residual oxygen-doped amorphous silicon layer 16B from the surface of the P-type amorphous silicon layer, and then deposit a transparent conductive film layer on the back side of the resulting silicon wafer 10.

[0097] S09. An opening is made in the transparent conductive film layer between the first semiconductor opening region and the second semiconductor opening region to form an isolation trench.

[0098] S10, forming metal electrodes on the transparent conductive film layer of the first semiconductor opening region and the transparent conductive film layer of the second semiconductor opening region.

[0099] Example 2

[0100] The method is the same as in Example 1, except that the thickness of the ultrathin oxygen-doped amorphous silicon layer 15B in step S06 is 0.2 nm, which is thinner than in Example 1 and has a relatively poorer effect in blocking epitaxial growth.

[0101] Example 3

[0102] The method is carried out in accordance with Example 1, except that the oxygen content of the ultrathin oxygen-doped amorphous silicon layer 15B in step S06 is 30%, and its conductivity is slightly worse than that in Example 1, thereby reducing the series resistance.

[0103] Example 4

[0104] The method was carried out in accordance with Example 1, except that in step S06, the ratio of carbon dioxide to silane in the ultrathin oxygen-doped amorphous silicon layer 15B was 3:100, the oxygen content was lower than that in Example 1, and the effect of blocking epitaxial growth was relatively poor.

[0105] Example 5

[0106] The method is the same as in Example 1, except that the deposition power density of the ultrathin oxygen-doped amorphous silicon layer 15B in step S06 is 10 mW / cm². 2 The power density is lower than that of Example 1, the quality of oxygen-doped amorphous silicon is poor, and the effect of blocking epitaxial growth is relatively poor.

[0107] Example 6

[0108] The method is carried out in accordance with Example 1, except that in step S06, the thickness ratio of the amorphous silicon passivation layer 15 to the thickness of the ultrathin oxygen-doped amorphous silicon layer 15B is 20:1.

[0109] Example 7

[0110] The method is carried out in accordance with Example 1, except that in step S06, the oxygen doping content of the oxygen-doped amorphous silicon layer 16B is 35% and the hydrogen doping content is 1%.

[0111] Example 8

[0112] The method is carried out in accordance with Example 1, except that in step S06, the ratio of carbon dioxide, silane and hydrogen in the oxygen-doped amorphous silicon layer 16B is 3:1:0.

[0113] Comparative Example 1

[0114] The method is carried out in accordance with Example 1, except that step S06 is not performed, that is, a first ultrathin oxygen-doped amorphous silicon layer 15B is not prepared between the first semiconductor layer and the second semiconductor layer.

[0115] Comparative Example 2

[0116] The method is carried out in accordance with Example 1, except that the thickness of the ultrathin oxygen-doped amorphous silicon layer 15B in step S06 is 1.5 nm.

[0117] Comparative Example 3

[0118] The method is carried out in accordance with Example 1, except that the oxygen doping content of the ultrathin oxygen-doped amorphous silicon layer 15B in step S06 is 40%.

[0119] Comparative Example 4

[0120] The method is carried out in accordance with Example 1, except that the ratio of carbon dioxide to silane in the ultrathin oxygen-doped amorphous silicon layer 15B in step S06 is 100:100.

[0121] Comparative Example 5

[0122] The method is carried out in accordance with Example 1, except that the thickness ratio of the ultrathin oxygen-doped amorphous silicon layer 15B to the thickness of the amorphous silicon passivation layer 15 in step S06 is 1:60.

[0123] Comparative Example 6

[0124] The method is carried out in accordance with Example 1, except that in step S06, the oxygen doping content of the oxygen-doped amorphous silicon layer 16B is 15% and the hydrogen doping content is 1%.

[0125] Comparative Example 7

[0126] The method is carried out according to Example 1, except that in step S06, the ratio of carbon dioxide, silane, and hydrogen in the oxygen-doped amorphous silicon layer 16B is 0.5:1:1.

[0127] Comparative Example 8

[0128] The method is carried out in accordance with Example 1, except that in step S06, the first ultrathin oxygen-doped amorphous silicon layer 15B and oxygen-doped amorphous silicon layer 16B are not prepared on the back side of the silicon wafer 10, and the amorphous silicon passivation layer 15 and the P-type amorphous silicon layer 16 are prepared by two separate PECVD processes.

[0129] Test case

[0130] The silicon-based back-contact heterojunction solar cells obtained in the above embodiments and comparative examples were subjected to performance tests, and the results are shown in Table 1. Minority carrier lifetime is in µs, open-circuit voltage (Voc) is in V, cell conversion efficiency (Eta) is in %, and equipment cost is based on 100% of facility example 1.

[0131] Table 1 Comparison of performance test results for each embodiment and comparative example.

[0132] The above results show that, compared to the comparative examples, the embodiments of this disclosure reduce the investment in plate-type PECVD equipment, improve the silicon wafer passivation effect, and thus reduce equipment costs and increase battery conversion efficiency. Furthermore, as shown in Embodiments 1 and 2-8, the preferred specific preparation method and specific battery structure of this disclosure maintain a good passivation effect without increasing series resistance, further improving battery efficiency.

[0133] In the description of this application, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0134] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0135] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances. In the description of this specification, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0136] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application. Industrial applicability

[0137] In summary, the embodiments of this disclosure provide a silicon-based back-contact heterojunction solar cell and its fabrication method and cell module. It can avoid the influence of single-crystal epitaxial growth on the film quality and passivation effect of the amorphous silicon passivation layer during deposition. Furthermore, it can realize the deposition of the amorphous silicon passivation layer and the P-type amorphous silicon layer in the same PECVD system, thereby reducing the number of PECVD systems and lowering equipment costs.

Claims

1. A silicon-based back contact heterojunction solar cell, characterized by, include: A silicon wafer with a front and a back side; A first semiconductor layer is disposed on the back side of the silicon wafer, the first semiconductor layer comprising a tunneling silicon oxide layer and a doped polycrystalline silicon layer sequentially formed on the silicon wafer; The first semiconductor layer is separated by multiple second semiconductor opening regions. The second semiconductor opening regions and the surface of the first semiconductor layer surrounding the second semiconductor opening regions are covered with second semiconductor layers. The second semiconductor layer is composed of an ultrathin oxygen-doped amorphous silicon layer, an amorphous silicon passivation layer and a P-type amorphous silicon layer. A passivation layer and an antireflection layer are sequentially disposed on the front side of a silicon wafer. The passivation layer is any one or more materials selected from aluminum oxide, silicon oxide, amorphous silicon, or microcrystalline silicon. The antireflection layer is at least one of silicon nitride, silicon oxynitride, or silicon oxide. The thickness of the ultrathin oxygen-doped amorphous silicon layers is 0.2–1 nm, and the oxygen doping content is 3%–30%.

2. The silicon-based back contact heterojunction solar cell of claim 1, wherein, A first semiconductor opening region is provided between adjacent second semiconductor opening regions, and the first semiconductor opening region separates the second semiconductor layer; Both the first semiconductor opening region and the second semiconductor layer are covered with a transparent conductive film layer, and an isolation trench is provided between adjacent first semiconductor opening regions and second semiconductor opening regions; the isolation trench separates the transparent conductive film layer located in the first semiconductor opening region and the transparent conductive film layer located on the second semiconductor layer.

3. The silicon-based back contact heterojunction solar cell according to claim 1 or 2, characterized in that, The thickness of the tunneling silicon oxide layer is 1-2 nm, the thickness of the doped polycrystalline silicon layer is 50-150 nm, and the thickness of the amorphous silicon passivation layer is 3-10 nm. The ratio of the thickness of the amorphous silicon passivation layer to the thickness of the ultrathin oxygen-doped amorphous silicon layer is (3-50):

1.

4. The silicon-based back contact heterojunction solar cell according to any one of claims 1 to 3, characterized in that The thickness of the antireflective layer is 70nm to 150nm.

5. The silicon-based back contact heterojunction solar cell according to any one of claims 1 to 4, characterized in that The front side of the silicon wafer and the surface of the silicon wafer located in the second semiconductor opening region are formed with a textured surface, and the second semiconductor layer and the third semiconductor layer respectively fill the textured surface in the corresponding regions.

6. The silicon-based back contact heterojunction solar cell according to any one of claims 1 to 5, wherein The thickness of the amorphous silicon passivation layer is 3-10 nm, the thickness of the P-type amorphous silicon layer is 5-15 nm, and the boron doping concentration in the P-type amorphous silicon layer is 5e 18 cm -3 -4e 20 cm -3 .

7. The silicon-based back contact heterojunction solar cell of claim 2, wherein the n-type silicon wafer is a p-type silicon wafer. Also includes: Metal electrode; the metal electrode is disposed on the transparent conductive film layer in the first semiconductor opening region and the second semiconductor opening region.

8. The silicon-based back contact heterojunction solar cell according to any one of claims 1 to 7, wherein An ultrathin oxygen-doped amorphous silicon layer is formed between the passivation layer and the silicon wafer.

9. A battery assembly characterized by, It includes silicon-based back-contact heterojunction solar cells as claimed in any one of claims 1 to 8.

10. A method for fabricating a silicon-based back-contact heterojunction solar cell, configured to fabricate a silicon-based back-contact heterojunction solar cell as described in any one of claims 1 to 8, the method comprising the following steps: Provide a silicon wafer; A tunneling silicon oxide layer and a doped polycrystalline silicon layer are sequentially formed on the back side of the silicon wafer to obtain the first semiconductor layer; A mask layer is prepared on the surface of the first semiconductor layer; Part of the mask layer and the corresponding portion of the first semiconductor layer are removed to form alternating second semiconductor opening regions; The remaining mask layer, N-type doped polycrystalline layer and tunneling silicon oxide layer in the second semiconductor opening region are removed by texturing and cleaning. At the same time, a textured surface is formed on the front side of the silicon wafer and the surface of the silicon wafer located in the second semiconductor opening region. Then, part or all of the mask layer on the back side of the silicon wafer located outside the second semiconductor opening region is removed. A passivation layer and an anti-reflection layer are sequentially formed on the front side of the silicon wafer, and an ultrathin oxygen-doped amorphous silicon layer, an amorphous silicon passivation layer, a P-type amorphous silicon layer, and an oxygen-doped amorphous silicon layer are sequentially formed on the back side of the silicon wafer. During the fabrication of the ultrathin oxygen-doped amorphous silicon layer on the back side of the silicon wafer, silane and carbon dioxide or other gases capable of providing an oxygen source are introduced; wherein the ratio of carbon dioxide to silane is (3-30):100, and the deposition power density is 10-100 mW / cm³. 2 The gas pressure is 30–150 Pa, the thickness of the ultrathin oxygen-doped amorphous silicon layer is 0.2–1 nm, and the oxygen doping content is 3–30%. During the preparation of the oxygen-doped amorphous silicon layer, nitrous oxide or other gases that can provide oxygen, silane, and hydrogen are introduced, wherein the ratio of nitrous oxide, silane, and hydrogen is (1–10):1:(0–10), and the deposition power density is 5–50 mW / cm³. 2 The gas pressure is 30–150 Pa, the oxygen content is 20–70%, and the hydrogen content is 0–10%. An opening is etched on the back side of the silicon wafer to form a first semiconductor opening region that is spaced apart from the second semiconductor opening region, and the first semiconductor opening region exposes the doped polysilicon layer. Remove the residual oxygen-doped amorphous silicon layer from the surface of the P-type amorphous silicon layer, and then deposit a transparent conductive film layer on the back side of the resulting silicon wafer. An opening is made in the transparent conductive film layer between the first semiconductor opening region and the second semiconductor opening region to form an isolation trench; Metal electrodes are formed on the transparent conductive film layer of the first semiconductor opening region and the transparent conductive film layer of the second semiconductor opening region.

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