Optoelectronic semiconductor device and method for manufacturing an optoelectronic semiconductor device

Abstract

According to embodiments, an optoelectronic semiconductor device (10) comprises a substrate (100), a first semiconductor layer (110) of a first conductivity type, an active zone (115) being configured to generate electromagnetic radiation and a second semiconductor layer (120) of a second conductivity type. The first semiconductor layer (110), the active zone (115) and the second semiconductor layer (120) form a semiconductor layer stack (118). The semiconductor layer stack (118) is arranged over a first main surface (101) of the substrate (100) and is patterned to form a mesa (102). The mesa (102) is located in a central portion (12) and is absent from an edge portion (11). The optoelectronic semiconductor device (10) further comprises an Al layer (127) which is arranged over the first main surface (101) of the substrate (100). The optoelectronic semiconductor device (10) further comprises a first separation trench (129) in the Al layer (127) which is arranged in the edge portion (11). The first separation trench (129) is filled with a filling material different from Al and extends in a first horizontal direction and from a first main surface (138) of the Al layer (127) te a second main surface (139) of the Al layer (127).

Description

[0001] OPTOELECTRONIC SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING AN OPTOELECTRONIC SEMICONDUCTOR DEVICE

[0002] A light emitting diode ( LED) chip is a light emitting device that is based on semiconductor materials . For example , an LED chip comprises a pn j unction . When electrons and holes combine with each other in a region of the pn j unction, for example , since a suitable voltage is applied, electromagnetic radiation is generated . LED chips are manufactured on a wafer basis , which have to be separated from each other in a further step .

[0003] Generally, concepts are being developed for improving these optoelectronic semiconductor devices to make them separatable without being damaged .

[0004] It is an obj ect of the present invention to provide an improved optoelectronic semiconductor device and an improved method of manufacturing an optoelectronic semiconductor device .

[0005] According to embodiments , the above obj ect is achieved by the claimed matter according to the independent claims . Further developments are defined in the dependent claims .

[0006] According to embodiments , an optoelectronic semiconductor device comprises a substrate , a first semiconductor layer of a first conductivity type , an active zone being configured to generate electromagnetic radiation and a second semiconductor layer of a second conductivity type . The first semiconductor layer, the active zone and the second semiconductor layer form a semiconductor layer stack . The semiconductor layer stack is arranged over a first main surface of the substrate and is patterned to form a mesa . The mesa is located in a central portion and is absent from an edge portion . The optoelectronic semiconductor device further comprises an Al layer which is arranged over the first main surface of the substrate. The optoelectronic semiconductor device further comprises a first separation trench in the Al layer which is arranged in the edge portion. The first separation trench is filled with a filling material different from Al and extends in a first horizontal direction and from a first main surface of the Al layer to a second main surface of the Al layer.

[0007] According to further embodiments, the optoelectronic semiconductor device may further comprise a second separation trench which extends in the first horizontal direction in the Al layer and is shifted in a second horizontal direction with respect to the first separation trench. The second separation trench is also arranged in the edge portion.

[0008] The optoelectronic semiconductor device can further comprise a third separation trench which extends in a second horizontal direction in the Al layer and is arranged in the edge portion.

[0009] The distance from the first separation trench to the mesa can be, e.g., more than 1 pm and less than 10 pm. It can be, for example, more than 3 pm.

[0010] The distance from the first separation trench to the second separation trench can be, e.g., more than 0.5 pm and less than

[0011] 5 pm. It can be, e.g., less than 2 pm or less than 1 pm.

[0012] The third separation trenches may extend along the edge of the mesa, or they may extend towards the mesa.

[0013] The semiconductor layer stack can further comprise a reflective metal layer. The optoelectronic semiconductor device may further comprise a first metallic buf fer layer which is arranged between the substrate and the Al layer . A material of the first metallic buf fer layer may be arranged in the separation trenches .

[0014] An aluminum oxide layer can be arranged over sidewalls of the separation trenches .

[0015] The separation trenches can, e . g . , have a width of more than 10 nm in a hori zontal direction . For example , the width of the separation trenches can be less than 500 nm in a hori zontal direction . For example , the width of the separation trenches can be less than 200 nm or less than 100 nm .

[0016] According to embodiments , an optoelectronic semiconductor device can comprise a first separation trench which surrounds the mesa . According to further embodiments it can comprise a second separation trench which extends parallel to the first separation trench in a hori zontal direction in the Al layer . The second separation trench is shi fted hori zontally with respect to the first separation trench and is arranged in the edge portion .

[0017] According to embodiments , a method of manufacturing an optoelectronic semiconductor device comprises forming a first semiconductor layer of a first conductivity type , forming an active zone being configured to generate electromagnetic radiation and forming a second semiconductor layer of a second conductivity type . The first semiconductor layer, the active zone and the second semiconductor layer form a semiconductor layer stack . The method further comprises forming an Al layer over the semiconductor layer stack and forming a first separation trench in an edge portion . The first separation trench extends in a first hori zontal direction in the Al layer and from a first main surface of the Al layer to a second main surface of the Al layer . The method further comprises filling the separation trench with a filling material di f ferent from Al and patterning the semiconductor layer stack to form a mesa . The mesa is arranged in the central portion and is absent from an edge portion .

[0018] According to further embodiments the method of manufacturing an optoelectronic semiconductor device can further comprise forming a first metallic buf fer layer over the Al layer .

[0019] Forming the first metallic buf fer layer can comprise filling a material of the first metallic buf fer layer into the first separation trench .

[0020] The method can further comprise forming an aluminum oxide layer onto the Al layer, before the first separation trench is filled with a filling material .

[0021] The method may further comprise arranging a material of the first metallic buf fer layer in a separation groove in a region between two device portions .

[0022] BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Fig . 1A shows a cross-sectional view of an optoelectronic semiconductor device according to embodiments .

[0024] Fig . IB shows a schematic top view of an optoelectronic semiconductor device according to embodiments .

[0025] Fig . 2A shows a schematic top view of an optoelectronic semiconductor device according to further embodiments . Fig . 2B shows a cross-sectional view of an optoelectronic semiconductor device according to further embodiments .

[0026] Fig . 20 shows a portion of a cross-sectional view of an optoelectronic semiconductor device according to further embodiments .

[0027] Fig . 3A shows a cross-sectional view of a workpiece during the process of manufacturing an optoelectronic semiconductor device according to embodiments .

[0028] Fig . 3B shows a cross-sectional view of a workpiece during the process of manufacturing an optoelectronic semiconductor device according to embodiments .

[0029] Fig . 3C shows a cross-sectional view of a workpiece during the process of manufacturing an optoelectronic semiconductor device according to further embodiments .

[0030] Fig . 4A shows a cross-sectional view of a workpiece during the process of manufacturing an optoelectronic semiconductor device according to embodiments .

[0031] Fig . 4B shows a cross-sectional view of a workpiece during the process of manufacturing an optoelectronic semiconductor device according to embodiments .

[0032] Fig . 4C shows a cross-sectional view of an optoelectronic semiconductor device during the process of manufacturing according to embodiments .

[0033] Fig . 5 summari zes a method of manufacturing an optoelectronic semiconductor device according to embodiments . DETAILED DESCRIPTION

[0034] In the following detailed description reference is made to the accompanying drawings, which form a part hereof and in which are illustrated by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology such as "top", "bottom", "front", "back", "over", "on", "above", "leading", "trailing" etc. is used with reference to the orientation of the Figures being described. Since components of embodiments of the invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized, and structural or logical changes may be made without departing from the scope defined by the claims.

[0035] The description of the embodiments is not limiting. In particular, elements of the embodiments described hereinafter may be combined with elements of different embodiments.

[0036] The terms "wafer" or "semiconductor substrate" used in the following description may include any semiconductor-based structure that has a semiconductor surface. Wafer and structure are to be understood to include doped and undoped semiconductors, epitaxial semiconductor layers, e.g., supported by a base semiconductor foundation, and other semiconductor structures. For example, a layer of a first semiconductor material may be grown on a growth substrate 113 of a second semiconductor material. According to further embodiments, the growth substrate 113 may be an insulating substrate such as a sapphire substrate. Depending on the purpose of use, the semiconductor may be based on a direct or an indirect semiconductor material. Examples of semiconductor materials particularly suitable for generation of electromagnetic radiation comprise nitride-compound semiconductors, by which, e.g. ultraviolet or blue light or longer wavelength light may be generated, such as GaN, InGaN, AIN, AlGaN, AlGalnN, phosphide-compound semiconductors, by which, e.g. green or longer wavelength light may be generated such as GaAsP, AlGalnP, GaP, AlGaP, as well as further semiconductor materials including AlGaAs, SiC, ZnSe, GaAs, ZnO, Ga2Os, diamond, hexagonal BN und combinations of these materials. Further examples of semiconductor materials may as well be silicon, silicon-germanium and germanium. The stoichiometric ratio of the compound semiconductor materials may vary. In the context of the present specification, the term "semiconductor" further encompasses organic semiconductor materials .

[0037] The term "substrate" generally refers to semiconductor substrates, conductive or insulating substrates.

[0038] The term "vertical" as used in this specification intends to describe an orientation which is arranged perpendicular to the first surface of a substrate or semiconductor body.

[0039] The terms "lateral" and "horizontal" as used in this specification intends to describe an orientation parallel to a first surface of a substrate or semiconductor body. This can be for instance the surface of a wafer or a die.

[0040] Fig. 1A shows a cross-sectional view of an optoelectronic semiconductor device 10, according to embodiments. For example, the cross-sectional view may be taken between I and I' , as is illustrated in Fig. IB. As is shown, the optoelectronic semiconductor device 10 may be implemented as a semiconductor chip. The optoelectronic semiconductor device 10 comprises a central portion 12 and an edge portion 11. The edge portion 11 can, for example, surround the central portion 12. An active zone 115 for generating or absorbing optoelectronic radiation is absent from the edge portion 11 of the optoelectronic semiconductor device 10. Accordingly, generally, optoelectronic radiation is not generated in the edge portion 11.

[0041] The optoelectronic semiconductor device 10 comprises a first semiconductor layer 110 of a first conductivity type, e.g., n- type, the active zone 115 and a second semiconductor layer 120 of a second conductivity type, e.g., p-type. The first semiconductor layer 110, the active zone 115 and the second semiconductor layer 120 form a semiconductor layer stack 118. The semiconductor layer stack 118 can contain, for example, layers of the GaN material system and is patterned to form a mesa 102. The mesa 102 is arranged in the central portion 12 and is absent from the edge portion 11.

[0042] An Al layer 127 is arranged over a first main surface 101 of the semiconductor substrate 100, e.g., in the central portion 12 and in the edge portion 11. For example, the thickness of the Al layer 127 can be more than 20 nm, e.g., more than 40 nm. The thickness of the Al layer 127 can be, for example, less than 500 nm, e.g., less than 100 nm or less than 60 nm.

[0043] According to further embodiments, the optoelectronic semiconductor device 10 comprises a first dielectric insulation layer 117, which can be arranged, e.g., over the Al layer 127. The Al layer 127 can be arranged, e.g., between the first dielectric insulation layer 117 and the first main surface 101 of the semiconductor substrate 100.

[0044] According to further embodiments, the optoelectronic semiconductor device 10 comprises a second dielectric insulation layer 119, which can be arranged, e.g., over the mesa 102. For example, the second dielectric insulation layer 119 may be arranged over a top surface of the mesa 102. Moreover, the second dielectric insulation layer 119 may cover the sidewalls of the mesa 102. The first dielectric insulation layer 117 and the second dielectric insulation layer 119 may comprise, e.g., the same material or, e.g., materials which are different from each other. The dielectric insulation layers 117, 119 may comprise, e.g., SiO or SiN.

[0045] According to further embodiments, the optoelectronic semiconductor device 10 can comprise a wavelength conversion layer, which can be arranged in the central portion 12 above the semiconductor layer stack 118.

[0046] Fig. 1A further shows a first separation trench 129 formed in the Al layer 127. The first separation trench 129 can extend in a first horizontal direction, e.g., the y-direction, and from a first main surface 138 of the Al layer 127 to a second main surface 139 of the Al layer 127. The first separation trench 129 can be filled with a filling material different from Al. For example, the first separation trench 129 can be filled with a metal, e.g., Ti, Pd, Pt, Rh, Cr or Au or with a dielectric material, e.g., AI2O3, SiCy or MgF2. The first separation trench 129 is located in a first separation trench region 125, which can extend in the first horizontal direction, e.g., the y-direction, in the Al layer 127.

[0047] For example, the first separation trench 129 can have a width w of more than 10 nm in a second horizontal direction, e.g., the x-direction. For example, the width w of the separation trench 129 can be less than 500 nm in a second horizontal direction, e.g., the x-direction. For example, the width w can be less than 200 nm or less than 100 nm. For example, the first separation trench 129 can have a distance d of more than 1 pm to the mesa 102. For example, the distance d can be less than 10 pm. For example, the distance d may correspond to a shortest distance measured between an outer edge of the mesa 102 and an adjacent outer edge of the separation trench 129.

[0048] According to implementations, the active zone 115 may, for example, comprise a pn junction, a double heterostructure, a single quantum well structure (SQW, single quantum well) or a multiple quantum well structure (MQW, multi quantum well) for generating radiation. The term "quantum well structure" does not imply any particular meaning here with regard to the dimensionality of the quantization. Therefore, it includes, among other things, quantum wells, quantum wires and quantum dots as well as any combination of these layers.

[0049] As has been discussed above, the active zone 115 is absent from the edge portion 11 and, consequently, electromagnetic radiation is not generated in the edge portion 11. Even though, it has been shown that the light extraction efficiency of the optoelectronic semiconductor device 10 may be improved when an Al layer 127 is arranged in the edge portion 11, for example, when light is scattered or reemitted at different wavelengths back onto the chip.

[0050] Fig. IB shows a schematic top view of an example of a workpiece 16 for manufacturing the optoelectronic semiconductor device 10. The workpiece 16 of Fig. IB includes two optoelectronic semiconductor devices 10, each including a mesa 102.

[0051] For example, the first dielectric insulation layer 117 may cover the edge portion 11 of the optoelectronic semiconductor device 10. Fig. IB further shows a virtual dicing path 140, which marks a path where a dicing is accomplished. Generally, when singulat- ing the workpiece 16, e.g., a wafer, into chips during a manufacturing process, dicing may be performed along the virtual dicing path 140. For example, the edge portion 11 of the optoelectronic semiconductor device 10 may be adjacent to the virtual dicing path 140. The virtual dicing path 140 may be located, for example, in the first separation trench region 125. The first separation trenches 129 act as barriers to avoid a propagation of possible dicing damage, e.g., degradation through intermetallic diffusion or chemical degradation of the Al layer 127 into further chip regions in a second horizontal direction, e.g., the x-direction, e.g., towards the mesa 102. The reflectivity of the Al layer 127 can be sacrificed in part to compensate for the lack of precision in the dicing process. Due to the relatively small width of the separation trenches 129, the high reflectivity of the Al layer 127 can be mainly maintained .

[0052] Fig. 2A shows a schematic top view of an optoelectronic semiconductor device 10 according to further embodiments. According to further embodiments, a single or a plurality of second separation trenches 229 may be located in the first separation trench region 125 in the Al layer 127. The second separation trenches 229 extend in the first horizontal direction, e.g., the y-direction and act as barriers to avoid a propagation of possible dicing damage into further chip regions in a second horizontal direction, e.g., the x-direction. The second separation trenches 229 are shifted in a second horizontal direction with respect to the first separation trench 129.

[0053] The optoelectronic semiconductor device 10 may, for example, further comprise a second separation trench region 225, which can extend in a second horizontal direction, e.g., the x-di- rection, along the edge of the mesa 102. The second separation trench region 225 may comprise a single or a plurality of third separation trenches 329 which extend in a second hori- zonal direction, e.g., the x-direction. For example, the third separation trenches 329 may extend along the edge of the mesa 102.

[0054] The virtual dicing path 140 may be located, for example, in the first or second separation trench regions 125, 225. The regions of the Al layer 127, in which reflectivity is reduced, are indicated with a hatched pattern. The reflectivity may be reduced in these regions due to intermetallic diffusion and / or chemical degradation that may be caused by the dicing process. According to further embodiments, a separation groove 300 may be arranged between adjacent semiconductor devices 10. The separation groove 300 may be located in a region outside the edge portion 11, as illustrated on the right-hand side of Fig. 2A. For example, the separation groove 300 may be filled with a material of the first separation trench 129, e.g., Ti. Due to the separation groove 300 being filled with the filling material of the first separation trench 129, for example, alignment during a dicing process may be improved. For example, the virtual dicing path 140 may be located in the separation groove 300.

[0055] The first separation trench region 125 may further comprise a single or a plurality of third separation trenches 329 which extend in the second horizontal direction towards the mesa 102. The third separation trenches 329 act as barriers to avoid a propagation of possible dicing damage into further chip regions in a first horizontal direction, e.g., the y-di- rection. The combined separation trenches 129, 229, 329 can, for example, surround the mesa 102. For example, the width of the second and third separation trenches 229, 329 as well as their structure or filling may be identical with the width and structure or filling of the first separation trenches 129.

[0056] For example, the third separation trench 329 can have a distance t of more than 1 pm to the mesa 102. For example, the distance t can be less than 10 pm. For example, the distance t may be measured between an outer edge of the mesa 102 and an adjacent outer edge of the third separation trench 329.

[0057] For example, the first separation trench 129 can be implemented as a separation trench which surrounds the mesa 102.

[0058] The first separation trench 129 can, e.g., comprise a combination of the first separation trench 129 and the third separation trench 329. In addition, more separation trenches 129, 229, 329 can be arranged, for example, parallel to the first separation trench 129.

[0059] Fig. 2B shows a cross-sectional view of an optoelectronic semiconductor device 10 shown in Fig. 2A, according to further embodiments. The cross-sectional view may be taken between II and II' as is illustrated in Fig. 2A.

[0060] The semiconductor device comprises a first separation trench 129 and one or more second separation trenches 229 in the first separation trench region 125. The first and the second separation trenches 129, 229 extend in a first horizontal direction, e.g., the y-direction. The distance s between two separation trenches 129, 229 may be, for example, more than 0.5 pm, e.g., more than 0.8 pm. The distance s between two separation trenches may be, e.g., less than 5 pm, e.g., less than 2.2 pm. For example, the distance s may be measured between two adj acent outer edges of the separation trenches 129 , 229 .

[0061] For example , even when the virtual dicing path 140 is not exactly reached by the dicing laser due to laser misalignment , the chip damage does not propagate beyond the first separation trench region 125 towards the central portion 12 .

[0062] According to all embodiments described herein, the semiconductor layer stack 118 may further comprise a reflective metal layer 122 . For example , the reflective metal layer 122 may be arranged between the second semiconductor layer 120 and the Al layer 127 .

[0063] According to all embodiments described herein, the semiconductor layer stack 118 may further comprise a reflective dielectric layer 121 . The reflective dielectric layer 121 may be arranged between the second semiconductor layer 120 and the Al layer 127 . For example , the reflective dielectric layer 121 may be arranged between the semiconductor layer 120 and the reflective metal layer 122 .

[0064] By way of example , the reflective dielectric layer 121 may be implemented as a DBR mirror . In more detail , the reflective dielectric layer 121 may comprise an alternating sequence of dielectric layers having comparably high and low refractive indices . The alternating sequence of dielectric layers may form a DBR ("distributed Bragg reflector" ) mirror .

[0065] For example , a di f ference An of the refractive index of subsequent layers forming the reflective dielectric layer 121 may be larger than 0 . 5 , e . g . , larger than 0 . 7 . The dielectric layer having the higher refractive index should have a thickness in a range of larger than 20 nm . The thickness of the dielectric layer having the higher refractive index should be less than 200 nm. For example, the thickness may be in a range of more than 30 nm. Further, the thickness may be less than 70 nm. For example, the reflective dielectric layer 121 may comprise first layers that may comprise silicon oxide or MgF2. Moreover, a second layer of the reflective dielectric layer

[0066] 121 may comprise Nb2O2or TiO2. A total thickness of the reflective dielectric layer 121 may be larger than 500 nm, e.g., larger than 800 nm. For example, the total thickness of the reflective dielectric layer 121 may be less than 1.2pm. The reflective metal layer 122 may, e.g., comprise Au, Al, Ag, Rh, or intermetallic compounds. A thickness of the reflective metal layer 122 may be determined so that the reflective metal layer 122 is "optically thick". For example, the thickness of the reflective metal layer 122 may be larger than 50 nm, e.g., larger than 80 nm. The thickness of the reflective metal layer

[0067] 122 may be less than 200 nm, e.g., less than 120 nm.

[0068] In particular, due to the combination of the reflective metal layer 122 and the reflective dielectric layer 121, the reflectivity may be increased over a wider wavelength range. For example, in wavelength regions in which the reflective metal layer 122 has a lower reflectivity, the reflective dielectric layer 121 may provide the desired reflectivity.

[0069] According to all embodiments described herein, the optoelectronic semiconductor device 10 may further comprise a solder layer 200 which may be arranged between a first main surface 101 of the substrate 100 and the Al layer 127. For example, the solder layer 200 may contain Au.

[0070] According to all embodiments described herein, the optoelectronic semiconductor device 10 may further comprise a first metallic buffer layer 201, which may be arranged between the solder layer 200 and a second main surface 139 of the Al layer 127. The first metallic buffer layer 201 may comprise a metallic material, e.g., Ti. For example, the material of the first metallic buffer layer 201 may be arranged in the separation trenches 129, 229, 329. Further, the material of the first metallic buffer layer 201 may be arranged in the in the separation groove 300.

[0071] According to all embodiments described herein, the optoelectronic semiconductor device 10 may further comprise a second metallic buffer layer 202, which may be arranged between a first main surface 101 of the substrate 100 and the solder layer 200.

[0072] Fig. 2C shows an enlarged view of an edge portion 11 of the optoelectronic semiconductor device 10 shown in Fig. 2A, according to further embodiments. According to further embodiments, the optoelectronic semiconductor device 10 may further comprise an aluminum oxide layer 150, which is arranged over sidewalls of the separation trenches 129, 229, 329 and over the second main surface 139 of the Al layer 127 and may further protect the Al layer 127 from degradation as it is unlikely to delaminate. The thickness of the aluminum oxide layer 150 may be, e.g., more than 1 nm, e.g., more than 10 nm. For example, the thickness of the aluminum oxide layer 150 may be less than 100 nm, e.g., less than 50 nm.

[0073] In the following, a method for manufacturing an optoelectronic semiconductor device 10 according to embodiments will be explained. In the following description, the formation of first separation trenches 129 will be especially referred to. As is to be clearly understood, the described process may likewise be used to form the second and third separation trenches 229, 329. As is illustrated in Fig. 3A, semiconductor layers for forming the semiconductor layer stack 118 are epitaxially grown over a growth substrate 113, e.g., a sapphire substrate. In more detail, a first semiconductor layer 110 of a first conductivity type, e.g., n-type, is epitaxially grown over the growth substrate 113, followed by one or more layers for forming the active zone 115. Thereafter, the second semiconductor layer 120 of the second conductivity type, e.g., p-type, is grown over the active zone 115.

[0074] According to further embodiments, in a next step, a reflective dielectric layer 121 or a reflective metal layer 122 may be formed over the second semiconductor layer 120. According to further embodiments, the reflective dielectric layer 121 may be formed over the second semiconductor layer 120 and, subsequently, a reflective metal layer 122 may be formed over the reflective dielectric layer 121.

[0075] A first dielectric insulation layer 117, which may comprise SiO or SiN, may be formed over the resulting workpiece 16. The first dielectric insulation layer 117 may protect the Al layer 127.

[0076] In the next step, the Al layer 127 may be formed on the resulting workpiece 16. The thickness of the Al layer 127 may be, e.g., more than20 nm, e.g., more than 40 nm. For example, the thickness of the Al layer 127 can lower than 500 nm, e.g., lower than 100 nm or lower than 60 nm.

[0077] As is illustrated in Fig. 3B, thereafter, separation trenches 129 may be etched into the Al layer 127, e.g., using a photolithographic patterning method. According to embodiments, this process may also etch separation grooves 300 in the dicing region of workpiece 16 between adjacent device portions 15.

[0078] As is illustrated in Fig. 3C, optionally, thereafter, e.g., an oxidation step may be performed. As a result, the second main surface 139 of the Al layer 127 and the aluminum sidewalls of the first separation trenches 129 may be oxidated, forming the aluminum oxide layer 150. According to further embodiments, the aluminum oxide layer 150 may be formed by depositing aluminum oxide containing material, e.g., using an ALD ("atomic layer deposition") method.

[0079] A filling material different from Al, for example, a metal, e.g., Ti or a dielectric material is deposited into the first separation trenches 129. According to further embodiments, when forming a first metallic buffer layer 201, the material of the first metallic buffer layer 201 may be filled in the separation trenches 129 and in the separation grooves 300. In a next step the solder layer 200 is deposited onto the workpiece 16. According to further embodiments, a second metallic buffer layer 202 may be deposited onto the solder layer 200.

[0080] Fig. 4A shows an example of a cross-sectional view of a resulting workpiece 16, after deposition of the metallic buffer layers 201, 202 and solder layer 200.

[0081] For example, an exposed surface of the solder layer 200 or an exposed surface of the second metallic buffer layer 202 may be an exposed surface 137 of the workpiece 16.

[0082] For example, a separation groove 300 can be located between two device portions 15. For example, when singulating a workpiece 16 into semiconductor devices 10 using laser dicing, the laser can orient itself on the separation groove 300 or on the separation trenches 129, 229, 329. The laser orienting can be facilitated by dicing along a separation groove 300. Due to the larger width of the separation groove 300, which may be filled with a metallic material, an optical alignment can be performed directly on the separation groove 300.

[0083] In a next step, the workpiece 16 illustrated in Fig. 4A is attached to a suitable substrate 100. The substrate 100 is bonded to the exposed surface 137 of the workpiece 16, as shown in Fig 4B. Thereafter, a process of removing the growth substrate 113 is performed. For example, this may be accomplished using a laser lift-off process.

[0084] Thereafter, etching processes are performed so as to pattern the semiconductor layer stack 118 to a mesa 102. Fig. 4C shows an example of a resulting optoelectronic semiconductor device 10. As is shown, semiconductor layers are absent from the edge portion 11 of the optoelectronic semiconductor device 10. The optoelectronic semiconductor device 10 comprises an Al layer 127 extending in the edge portion 11 and in the central portion 12.

[0085] A second dielectric insulation layer 119 may be formed over the mesa 102, resulting, e.g., in the optoelectronic semiconductor device 10 shown in Fig. 1A.

[0086] Thereafter, dicing of the optoelectronic semiconductor device 10 may be performed along the virtual dicing path 140, which may be located in the separation trench regions 125, 225, for example, as illustrated in Fig. 2A. According to further embodiments, the virtual dicing path 140 may be located in the separation groove 300, in between two device portions 15 of the workpiece 16, as illustrated on the right-hand side of Fig. 2A. Fig. 5 summarizes a method for manufacturing an optoelectronic semiconductor device 10 according to embodiments. The optoelectronic semiconductor device 10 comprises a central portion 12 and an edge portion 11. The method comprises forming a semiconductor layer stack 118 comprising forming (S100) a first semiconductor layer 110 of a first conductivity type, forming (S110) an active zone 115 so that it is configured to generate electromagnetic radiation and forming (S120) a second semiconductor layer 120 of a second conductivity type. The method further comprises forming (S130) an Al layer 127 over the semiconductor layer stack 118 and forming (S140) a first separation trench 129 in an edge portion 11, the first separation trench 129 extending in a first horizontal direction in the Al layer 127 and from a first main surface 138 of the Al layer 127 to a second main surface 139 of the Al layer 127. In addition, the method comprises filling (S150) the separation trench 129 with a filling material different from Al and patterning (S160) the semiconductor layer stack 118 to form a mesa 102, so that the mesa 102 is in the central portion 12 and absent from the edge portion 11.

[0087] As has been discussed, due to the feature that the Al layer 127 is arranged in the edge portion 11, as explained above, the reflectivity of the optoelectronic semiconductor device 10 and hence, the light extraction efficiency may be improved. The separation trenches 129, 229, 329 can act as barriers to avoid a propagation of possible dicing damage into further chip regions without reducing the reflective area of the optoelectronic semiconductor device 10 significantly. In more detail, the separation trenches 129, 229, 329 may prevent that intermetallic diffusion or diffusion of chemicals propagate towards the central portion 12. As described above, the separation trenches 129, 229, 329 can further be useful for laser sel f-orientation for the device separation procedure . The laser sel f-orientation can further be improved using the separation groove 300 which has a larger width than the separation trenches 129 , 229 , 329 .

[0088] While embodiments of the invention have been described above , it is obvious that further embodiments may be implemented . For example , further embodiments may comprise any subcombination of features recited in the claims or any subcombination of el- ements described in the examples given above . Accordingly, this spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein .

[0089] LIST OF REFERENCES

[0090] 10 optoelectronic semiconductor device

[0091] 11 edge portion of the semiconductor device 10

[0092] 12 central portion of the semiconductor device 10

[0093] 15 device portion

[0094] 16 workpiece

[0095] 100 substrate

[0096] 101 first main surface of the substrate 100

[0097] 102 mesa

[0098] 110 first semiconductor layer

[0099] 113 growth substrate

[0100] 115 active zone

[0101] 117 first dielectric insulation layer

[0102] 118 semiconductor layer stack

[0103] 119 second dielectric insulation layer

[0104] 120 second semiconductor layer

[0105] 121 reflective dielectric layer

[0106] 122 reflective metal layer

[0107] 125 first separation trench region

[0108] 127 Al layer

[0109] 129 first separation trench

[0110] 137 exposed surface of the workpiece 16

[0111] 138 first main surface of the Al layer 127

[0112] 139 second main surface of the Al layer 127

[0113] 140 virtual dicing path

[0114] 150 aluminum oxide layer

[0115] 200 solder layer

[0116] 201 first metallic buf fer layer

[0117] 202 second metallic buf fer layer

[0118] 225 second separation trench region

[0119] 229 second separation trench

[0120] 300 separation groove

[0121] 329 third separation trench

Claims

CLAIMS1. An optoelectronic semiconductor device (10) comprising: a substrate (100) , a first semiconductor layer (110) of a first conductivity type, an active zone (115) being configured to generate electromagnetic radiation, a second semiconductor layer (120) of a second conductivity type, wherein the first semiconductor layer (110) , the active zone (115) and the second semiconductor layer (120) form a semiconductor layer stack (118) , wherein the semiconductor layer stack (118) is arranged over a first main surface (101) of the substrate (100) and is patterned to form a mesa (102) , the mesa (102) being located in a central portion (12) and being absent from an edge portion (11) , the optoelectronic semiconductor device (10) further comprising an Al layer (127) arranged over the first main surface (101) of the substrate (100) , the optoelectronic semiconductor device (10) further comprising a first separation trench (129) in the Al layer (127) , the first separation trench (129) being filled with a filling material different from Al and extending in a first horizontal direction and from a first main surface (138) of the Al layer (127) to a second main surface (139) of the Al layer (127) , the first separation trench (129) being arranged in the edge portion (11) .

2. The optoelectronic semiconductor device (10) according to claim 1, further comprising a second separation trench (229) which extends in the first horizontal direction in theAl layer (127) , the second separation trench (229) beingarranged in the edge portion (11) and being shifted in a second horizontal direction with respect to the first separation trench (129) .

3. The optoelectronic semiconductor device (10) according to any of the preceding claims, further comprising a third separation trench (329) which extends in a second horizontal direction in the Al layer (127) and being arranged in the edge portion (11) .

4. The optoelectronic semiconductor device (10) according to any of the preceding claims wherein a distance d from the first separation trench (129) to the mesa (102) is more than 1 pm and less than 10 pm.

5. The optoelectronic semiconductor device (10) according to any of claims 2 to 4, wherein a distance s from the first separation trench (129) to the second separation trench (229) is more than 0.5 pm and less than 5 pm.

6. The optoelectronic semiconductor device (10) according to claim 3, wherein the third separation trench (329) extends along the edge of the mesa (102) .

7. The optoelectronic semiconductor device (10) according to claim 3, wherein the third separation trench (329) extends towards the mesa (102) .

8. The optoelectronic semiconductor device (10) according to any of the preceding claims, wherein the semiconductor layer stack (118) further comprises a reflective metal layer (122) .

9. The optoelectronic semiconductor device (10) according to any of the preceding claims, further comprising a first metallic buffer layer (201) which is arranged between the substrate (100) and the Al layer (127) .

10. The optoelectronic semiconductor device (10) according to claim 9, wherein a material of the first metallic buffer layer (201) is arranged in the separation trenches (129, 229, 329) .

11. The optoelectronic semiconductor device (10) according to any of the preceding claims, further comprising an aluminum oxide layer (150) arranged over sidewalls of the separation trenches (129, 229, 329) .

12. The optoelectronic semiconductor device (10) according to any of the preceding claims, wherein the separation trenches (129, 229, 329) have a width w of more than 10 nm and less than 200 nm in a horizontal direction.

13. An optoelectronic semiconductor device (10) comprising: a substrate (100) , a first semiconductor layer (110) of a first conductivity type, an active zone (115) being configured to generate electromagnetic radiation, a second semiconductor layer (120) of a second conductivity type, wherein the first semiconductor layer (110) , the active zone (115) and the second semiconductor layer (120) form a semiconductor layer stack (118) , wherein the semiconductor layer stack (118) is arranged over a first main surface (101) of the substrate (100) and is patterned to form a mesa (102) , the mesa (102) being locatedin a central portion (12) and being absent from an edge portion (11) , the optoelectronic semiconductor device (10) further comprising an Al layer (127) arranged over the first main surface (101) of the substrate (100) , the optoelectronic semiconductor device (10) further comprising a first separation trench (129) which is filled with a filling material different from Al, the first separation trench (129) extending from a first main surface (138) of the Al layer (127) to a second main surface (139) of the Al layer (127) , the first separation trench (129) being arranged in the edge portion (11) and surrounding the mesa (102) .

14. The optoelectronic semiconductor device (10) according to claim 13, further comprising a second separation trench (229) extending parallel to the first separation trench (129) in the Al layer (127) and being shifted horizontally with respect to the first separation trench (129) , the second separation trench (229) being arranged in the edge portion (11) .

15. A method of manufacturing an optoelectronic semiconductor device (10) comprising: forming (S100) a first semiconductor layer (110) of a first conductivity type (100) , forming (S110) an active zone (115) configured to generate electromagnetic radiation, forming (S120) a second semiconductor layer (120) of a second conductivity type, the first semiconductor layer (110) , the active zone (115) and the second semiconductor layer (120) forming a semiconductor layer stack (118) ; forming (S130) an Al layer (127) over the semiconductor layer stack (118) ; forming (S140) a first separation trench (129) in an edge portion (11) , the first separation trench (129) extendingin a first horizontal direction in the Al layer (127) and from a first main surface (138) of the Al layer (127) to a second main surface (139) of the Al layer (127) , and filling (S150) the separation trench (129) with a filling material different from Al, the method further comprising patterning (S160) the semiconductor layer stack (118) to form a mesa (102) , the mesa (102) being arranged in a central portion (12) and being absent from the edge portion (11) .

16. The method of manufacturing an optoelectronic semiconductor device (10) according to claim 15, further comprising forming a first metallic buffer layer (201) over the Al layer (127) .

17. The method of manufacturing an optoelectronic semiconductor device (10) according to claim 16, wherein forming the first metallic buffer layer (201) comprises filling a material of the first metallic buffer layer (201) into the first separation trench (129) .

18. The method of manufacturing an optoelectronic semiconductor device (10) according to any of claims 15 to 17, further comprising forming an aluminum oxide layer (150) onto the Al layer (127) , before the first separation trench (129) is filled with the filling material.

19. The method of manufacturing an optoelectronic semiconductor device (10) according to claim 16, 17 or 18, further comprising arranging a material of the first metallic buffer layer (201) in a separation groove (300) in a region between two device portions (15) .

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