Liquid crystal device and method for controlling liquid crystal device

Abstract

A liquid crystal device according to the present disclosure comprises: a plurality of data lines provided corresponding to columns of a plurality of pixels; a shift register unit for sequentially capturing video signals by the number of columns of the plurality of pixels; a latch unit for simultaneously outputting the plurality of captured video signals; a plurality of comparators for comparing each of the plurality of video signals with a gray-scale signal and activating a corresponding match signal when the video signal matches the gray-scale signal; a plurality of first switch elements that are provided between common wiring through which a ramp signal propagates and the plurality of data lines, that turn on at a timing when the potential of the ramp signal starts to change linearly, and turn off individually at a timing when the match signal of each of the plurality of comparators is activated; and a plurality of second switch elements that are provided between initialization wiring on a path different from the common wiring and the plurality of data lines, and initialize the potentials of the plurality of data lines.

Description

Liquid crystal device, and method for controlling liquid crystal device

[0001] The present disclosure relates to a liquid crystal device and a method for controlling a liquid crystal device, and relates to a liquid crystal device suitable for improving quality and a method for controlling a liquid crystal device.

[0002] A liquid crystal display device is required to display high-quality images. Technologies related to liquid crystal display devices are disclosed in, for example, Patent Document 1.

[0003] The liquid crystal display device disclosed in Patent Document 1 includes at least a plurality of pixels arranged in a matrix, a plurality of data lines provided corresponding to each column of the plurality of pixels, a common wiring through which a ramp signal with a linearly changing potential propagates, and a plurality of switches provided between each of the plurality of data lines and the common wiring, and supplying a voltage (analog voltage) of the ramp signal corresponding to the video signal to each of the plurality of pixels in the selected row.

[0004] Japanese Patent Application Laid-Open No. 2009-223289

[0005] In the related-art liquid crystal display device, a switch provided between the common wiring through which the ramp signal propagates and the data line connected to the pixel to which the voltage of the ramp signal corresponding to the video signal is written is turned on at the timing when the potential of the ramp signal starts to linearly change, and is turned off at the timing corresponding to the gradation level of the video signal. Therefore, at the timing when the potential of the ramp signal starts to linearly change, the voltage written in the data line in the previous horizontal scanning period propagates to the common wiring through the on-state switch, and there is a possibility that the potential of the ramp signal propagating through the common wiring fluctuates. In that case, the related-art liquid crystal display device has a problem that it cannot display high-quality images.

[0006] The present disclosure has been made in view of the above points, and an object thereof is to provide a liquid crystal device, a wavelength selection switch device, and a method for controlling a liquid crystal device capable of improving quality.

[0007] The liquid crystal device according to this disclosure comprises: a plurality of pixels; a plurality of data lines provided corresponding to each row of the plurality of pixels; a shift register unit that sequentially captures video signals for the number of rows of the plurality of pixels in synchronization with a clock signal; a latch unit that simultaneously outputs the plurality of video signals captured by the shift register unit in synchronization with a trigger signal; a plurality of comparators that compare each of the plurality of video signals output from the latch unit with a gradation signal indicating a monotonically transitioning count value and activate a matching signal when they match; a common wiring through which a ramp signal whose potential changes linearly with each horizontal ramp period propagates; a plurality of first switch elements provided between the plurality of data lines, which turn on when the potential of the ramp signal begins to change linearly, and which turn off individually when the matching signal of each of the plurality of comparators becomes active; and a plurality of second switch elements provided between the plurality of data lines and an initialization wiring on a separate path from the common wiring, which initializes the potential of the plurality of data lines.

[0008] A control method for a liquid crystal device according to this disclosure includes: a plurality of pixels; a plurality of data lines provided corresponding to each row of the plurality of pixels; a shift register unit that sequentially captures video signals for the number of rows of the plurality of pixels in synchronization with a clock signal; a latch unit that simultaneously outputs the plurality of video signals captured by the shift register unit in synchronization with a trigger signal; a plurality of comparators that compare each of the plurality of video signals output from the latch unit with a gradation signal indicating a monotonically transitioning count value and activate the respective matching signal when they match; a common wiring through which a ramp signal whose potential changes linearly with each horizontal ramp period propagates; a plurality of first switch elements provided between the plurality of data lines, which turn on when the potential of the ramp signal begins to change linearly and turn off individually when the matching signal of each of the plurality of comparators becomes active; and a separate path from the common wiring. A control method for a liquid crystal device comprising: initialization wiring and a plurality of data lines, and a plurality of second switch elements provided between them to initialize the potential of the plurality of data lines, wherein during a certain horizontal ramp period, the plurality of first switch elements are turned on at the timing when the potential of the ramp signal begins to change linearly; during a certain horizontal ramp period, the plurality of first switch elements are individually turned off at the timing when the matching signal of each of the plurality of comparators becomes active; after the current horizontal ramp period has elapsed and before the start of the next horizontal ramp period, the plurality of second switch elements are temporarily turned on; during the next horizontal ramp period, the plurality of first switch elements are turned on at the timing when the potential of the ramp signal begins to change linearly; and during the next horizontal ramp period, the plurality of first switch elements are individually turned off at the timing when the matching signal of each of the plurality of comparators becomes active.

[0009] This disclosure provides a liquid crystal device capable of improving quality, a wavelength selective switch device, and a method for controlling a liquid crystal device.

[0010] This is a view of the wavelength selective switch according to this disclosure from the x-axis direction. This is a view of the wavelength selective switch according to this disclosure from the y-axis direction. This is a diagram showing an example of a wavelength channel focused on a reflective liquid crystal element applied to the wavelength selective switch according to this disclosure. This is a diagram showing an example configuration of a liquid crystal device in the conceptual stage. This is an enlarged view of the horizontal driver and analog switch section provided in the liquid crystal device in the conceptual stage. This is a diagram showing a specific example configuration of a pixel provided in the liquid crystal device in the conceptual stage. This is a timing chart for explaining the method of driving pixels by the liquid crystal device in the conceptual stage. This is a diagram for explaining the voltage levels from black to white for the positive polarity video signal and negative polarity video signal written to the pixel. This is a timing chart showing the operation of the liquid crystal device in the image display mode in the conceptual stage. This is a diagram for explaining the problems that occur in the liquid crystal device in the conceptual stage. This is a diagram showing an example configuration of the liquid crystal device according to this disclosure. This is a diagram showing the horizontal driver, analog switch section, and initialization switch section provided in the liquid crystal device according to this disclosure in more detail. This is a diagram showing an example configuration of a switch element provided in the initialization switch section of the liquid crystal device according to this disclosure. This is a timing chart for explaining the method of driving pixels by the liquid crystal device according to this disclosure. This is a diagram for explaining the effects of the liquid crystal device according to this disclosure.

[0011] <Explanation of Wavelength Selective Switches to which Liquid Crystal Devices According to This Disclosure are Applied> Figure 1 is a diagram showing an example configuration of a Wavelength Selective Switch (WSS) array 100 according to this disclosure. Figure 1 is a view of the WSS array 100 from the x-axis direction.

[0012] In recent years, optical communication networks have been developed to meet the demands for higher speeds and larger capacities in telecommunications and data networks. Generally, optical communication networks employ Wavelength Division Multiplexing (WDM) technology, which utilizes as much of the optical spectrum as possible. In optical WDM, as in wireless WDM, data is modulated on multiple carrier waves of different wavelengths. These multiple carrier waves are called channels (wavelength channels). In optical WDM, optical waves are used instead of radio waves compared to wireless WDM, and different wavelength channels correspond to different frequencies (wavelengths) of light. Generally, in optical communication, channels within or near the wavelength range of 1 to 2 μm are used.

[0013] In many optical communication networks, optical nodes are used that correspond to branching points in the network. Each optical node uses, for example, a reconfigurable optical add-drop multiplexer (ROADM) device with reconfigurable add-drop functionality. Generally speaking, the ROADM functionality allows for the removal or addition of one or more wavelength channels at each optical node.

[0014] The WSS array 100 may be used in a ROADM system for routing arbitrary wavelength channels. In this case, the WSS array 100 may use an optical beam deflection device such as a spatial light modulator, and the optical beam deflection device may select a wavelength for deflection to a desired output port. For example, deflection of a wavelength channel to a drop port results in the channel being removed from the WDM signal. Furthermore, the WSS array 100 may use a spatial light modulator using a reflective liquid crystal element.

[0015] Here, the ROADM function uses a broadcast-and-select (BS) scheme that requires a WSS and an optical splitter at each node. However, future devices may use a route-and-select (RS) scheme with multiple WSS devices instead of an optical splitter.

[0016] The WSS array 100 according to this disclosure comprises at least two WSS devices within a single package. In the WSS array 100, at least two WSS devices share most of the optical components, while at least two WSS devices are configured to operate independently. Therefore, the WSS array 100 not only achieves miniaturization and reduces optical complexity, but can also have independent processing capabilities comparable to larger and more expensive devices. Such a WSS array 100 is suitable for use in optical communication networks, for example, as a reconfigurable optical ROADM, and is also suitable for use as a component in branch nodes using a route-and-select (RS) architecture. Furthermore, the liquid crystal device according to this disclosure is applied as a reflective liquid crystal element in the WSS array 100.

[0017] As shown in Figure 1, the WSS array 100 comprises two independent WSS devices 100a and 100b, each capable of operating as an independent WSS device. In this specification, the term “independent” refers to the function of the other WSS device 100a or 100b to process one or more WDM signals independently of the other WSS device 100a or 100b. In this specification, the term “processing” is used broadly and includes, for example, modulating, attenuating, blocking, redirecting, and switching the individual wavelength channels that constitute each WDM signal.

[0018] The WSS array 100 comprises an input unit 110, an optical system 120, and a reflective liquid crystal element 130.

[0019] The optical system 120 is configured to beam-shape each WDM signal beam. The optical system 120 is also configured to spectrally disperse (multiplex decouple) each WDM signal into wavelength channels or groups thereof that constitute them, and spectrally couple (multiplex) the dispersed wavelength channels or groups thereof into one or more WDM signals. The reflective liquid crystal element 130 optically processes the dispersed wavelength channels or groups thereof, for example, to redirect the individual wavelength channels along a predetermined path within the WSS array 100.

[0020] The WSS array 100 is configured to be line-symmetric with respect to the symmetry axis Z1 extending in the z-axis direction. This allows the WSS array 100 to enable a single optical system 120 and a single reflective liquid crystal element 130 to be shared by multiple WSS devices (WSS devices 100a and 100b in this example). In the WSS array 100, WSS devices 100a and 100b can share most of the optical components, while each WSS device 100a and 100b is configured to operate independently. Therefore, the WSS array 100 not only achieves miniaturization and reduces optical complexity, but can also have independent processing capabilities comparable to larger and more expensive devices.

[0021] The input unit 110 has input ports and output ports for transmitting one or more WDM signals to each WSS device 100a, 100b. Each input port and each output port may be, for example, an optical fiber or a planar waveguide, but in this embodiment, the case of an optical fiber will be described as an example. Therefore, below, each input port will also be referred to as an input fiber, and each output port will also be referred to as an output fiber.

[0022] Specifically, the input unit 110 includes an input fiber FI1 and n (where n is an integer of 1 or more) output fibers FO1_1 to FO1_n for the WSS device 100a, and an input fiber FI2 and n output fibers FO2_1 to FO2_n for the WSS device 100b. Here, in the input unit 110, the optical fibers FI1, FO1_1 to FO1_n that constitute the fiber stack for the WSS device 100a, and the optical fibers FI2, FO2_1 to FO2_n that constitute the fiber stack for the WSS device 100b are arranged along the y-axis.

[0023] The input unit 110 further includes collimating lenses LI1, LO1_1 to LO1_n corresponding to optical fibers FI1, FO1_1 to FO1_n for the WSS device 100a, and collimating lenses LI2, LO2_1 to LO2_n corresponding to optical fibers FI2, FO2_1 to FO2_n for the WSS device 100b. The collimating lenses LI1, LO1_1 to LO1_n and the collimating lenses LI2, LO2_1 to LO2_n constitute a microlens array. In the input unit 110, each collimating lens is positioned on the optical system 120 side of each optical fiber. Each collimating lens is an arbitrary optical element that has the ability to guide or change the direction of light rays and to focus a set of light rays.

[0024] In the input section 110, the optical fibers FI1, FO1_1 to FO1_n and the collimating lenses LI1, LO1_1 to LO1_n constitute the input section of the WSS device 100a, and the optical fibers FI2, FO2_1 to FO2_n and the collimating lenses LI2, LO2_1 to LO2_n constitute the input section of the WSS device 100b.

[0025] In the example shown in Figure 1, the WSS array 100 employs a microlens array, but other types of arrays may be used as long as they do not deviate from the purpose.

[0026] As shown in Figure 1, the optical axes of the collimating lenses LI1, LO1_1 to LO1_n are displaced with respect to the optical axes of the optical fibers FI1, FO1_1 to FO1_n. Due to this relative positional shift between the collimating lenses LI1, LO1_1 to LO1_n and the optical fibers FI1, FO1_1 to FO1_n, the input beam for the WSS device 100a is input to the optical system 120 at an angle θ1 with respect to the axis of symmetry Z1, and each output beam for the WSS device 100a is output from the optical system 120 at an angle θ1 with respect to the axis of symmetry Z1. In other words, the input beam and each output beam for the WSS device 100a are tilted in the negative y-axis direction by an angle θ1 with respect to the axis of symmetry Z1 from the input section 110 to the optical system 120.

[0027] Similarly, the optical axes of the collimating lenses LI2, LO2_1 to LO2_n are displaced with respect to the optical axes of the optical fibers FI2, FO2_1 to FO2_n. Due to this relative positional shift between the collimating lenses LI2, LO2_1 to LO2_n and the optical fibers FI2, FO2_1 to FO2_n, the input beam for the WSS device 100b is input to the optical system 120 at an angle θ2 with respect to the axis of symmetry Z1, and each output beam for the WSS device 100b is output from the optical system 120 at an angle θ2 with respect to the axis of symmetry Z1. In other words, the input beam and each output beam for the WSS device 100b are tilted in the positive y-axis direction by an angle θ2 with respect to the axis of symmetry Z1 from the input section 110 to the optical system 120.

[0028] In the WSS array 100, the first WDM signal incident from the outside is supplied to the input fiber FI1. The input fiber FI1 transmits the first WDM signal parallel to the axis of symmetry Z1. The first WDM signal transmitted from the input fiber FI1 is tilted by an angle θ1 in the negative direction of the y-axis by passing through the collimating lens LI1 and is supplied to the optical system 120. The first WDM signal supplied to the optical system 120 forms a WDM signal beam BI1 that travels along the yz plane in the optical system 120. In the optical system 120, the WDM signal beam BI1 is incident on a lens 121 that shapes the WDM signal beam BI1 in the x-axis direction. The lens 121 is, for example, a cylindrical lens whose cylindrical axis extends in the y-axis direction. Therefore, when viewed from the x-axis direction (in other words, when viewed from the yz plane), the lens 121 does not affect the shaping of the WDM signal beam BI1.

[0029] The WDM signal beam BI1 that has passed through lens 121 is incident on lens 122. Lens 122 is, for example, a cylindrical lens whose cylindrical axis extends in the x-axis direction. The function of lens 122 depends on a reflective liquid crystal element 130 positioned at the focal plane of lens 122. Furthermore, the center of lens 122 is located on the axis of symmetry Z1.

[0030] In the WSS array 100, the second WDM signal incident from the outside is supplied to the input fiber FI2. The input fiber FI2 transmits the second WDM signal parallel to the axis of symmetry Z1. The second WDM signal transmitted from the input fiber FI2 passes through the collimating lens LI2, tilting by an angle θ2 in the positive direction of the y-axis, and is supplied to the optical system 120. The second WDM signal supplied to the optical system 120 forms a WDM signal beam BI2 that travels along the yz plane in the optical system 120. In the optical system 120, the WDM signal beam BI2 is incident on a lens 121 that shapes the WDM signal beam BI2 in the x-axis direction. The lens 121 is, for example, a cylindrical lens whose cylindrical axis extends in the y-axis direction. Therefore, when viewed from the x-axis direction (in other words, when viewed from the yz plane), the lens 121 does not affect the shaping of the WDM signal beam BI2.

[0031] The WDM signal beam BI2 that has passed through lens 121 is incident on lens 122. Lens 122 is, for example, a cylindrical lens whose cylindrical axis extends in the x-axis direction. The function of lens 122 depends on a reflective liquid crystal element 130 positioned at the focal plane of lens 122. Furthermore, the center of lens 122 is located on the axis of symmetry Z1.

[0032] Here, since the reflective liquid crystal element 130 is positioned at the focal plane of the lens 122, any pair of light rays reflected by the reflective liquid crystal element 130 that are reflected from positions at the same distance in the y-axis direction with respect to the axis of symmetry Z1 will be emitted from the lens 122 as a pair of parallel light rays. Conversely, any pair of parallel light rays incident on the lens 122 from the input section 110 will be focused in the reflective liquid crystal element 130 at positions at the same distance in the y-axis direction with respect to the axis of symmetry Z1.

[0033] In the example shown in Figure 1, an arbitrary incident beam (in this example, the WDM signal beam BI1) traveling at an angle θ1 with respect to the axis of symmetry Z1 is directed by the lens 122 toward position LC1 on the reflective liquid crystal element 130. Conversely, rays starting from position LC1 on the reflective liquid crystal element 130 (in this example, the output beams BO1_1 to BO1_n) are directed by the lens 122 as parallel rays traveling at an angle θ1 with respect to the axis of symmetry Z1.

[0034] Similarly, any incident beam (in this example, the WDM signal beam BI2) traveling at an angle θ2 with respect to the axis of symmetry Z1 is directed by the lens 122 toward position LC2 on the reflective liquid crystal element 130. Conversely, rays starting from position LC2 on the reflective liquid crystal element 130 (in this example, the output beams BO2_1 to BO2_n) are directed by the lens 122 as parallel rays traveling at an angle θ2 with respect to the axis of symmetry Z1.

[0035] Figure 2 shows the WSS array 100 as viewed from the y-axis direction. Figure 3 shows an example of a wavelength channel focused on the reflective liquid crystal element 130.

[0036] Referring to Figures 2 and 3, the WDM signal beam BI1 passes through lens 122 and then through a dispersion element 124 located between lenses 122 and 123. The dispersion element 124 is, for example, a transmissive optical component such as a diffraction grating or prism, which angularly disperses the wavelength channel of the WDM signal beam BI1. The wavelength channel dispersed by the dispersion element 124 passes through lens 123. Lens 123 is, for example, a cylindrical lens, which focuses the wavelength channel dispersed by the dispersion element 124 onto position LC1 on the reflective liquid crystal element 130.

[0037] Similarly, the WDM signal beam BI2 passes through lens 122 and then through the dispersion element 124 located between lenses 122 and 123. The dispersion element 124 angularly disperses the wavelength channels of the WDM signal beam BI2. The wavelength channels dispersed by the dispersion element 124 pass through lens 123. Lens 123 focuses the wavelength channels dispersed by the dispersion element 124 onto position LC2 on the reflective liquid crystal element 130.

[0038] The reflective liquid crystal element 130 is a two-dimensional pixelated optical element, such as a pixelated spatial light modulator, which can reflect or redirect one or more of the dispersed wavelength channels so that one or more of the dispersed wavelength channels are routed to any one of the output fibers, as will be described in more detail below.

[0039] In the WSS device 100a, all light rays starting from position LC1 on the reflective liquid crystal element 130 are displaced by the lens 122 by an amount corresponding to the deflection angle from the reflective liquid crystal element 130, and directed as parallel light rays traveling at an angle θ1. Therefore, when the deflection angle is set appropriately, the output light rays reflected by the reflective liquid crystal element 130 (for example, reflected output light rays corresponding to a group of light rays, each of which may contain one or more wavelength channels of the WDM signal beam BI1) can be routed to the output fibers FO1_1 to FO1_n, respectively. Here, since the output light rays reflected by the reflective liquid crystal element 130 are displaced by the same amount by the collimating lenses LO1_1 to LO1_n, they can be recombined to the output fibers FO1_1 to FO1_n with improved efficiency.

[0040] Similarly, in the WSS device 100b, all light rays starting from position LC2 on the reflective liquid crystal element 130 are displaced by the lens 122 by an amount corresponding to the deflection angle from the reflective liquid crystal element 130, and directed as parallel light rays traveling at an angle θ2. Therefore, when the deflection angle is set appropriately, the output light rays reflected by the reflective liquid crystal element 130 (for example, reflected output light rays corresponding to a group of light rays, each of which may contain one or more wavelength channels of the WDM signal beam BI2) can be routed to the output fibers FO2_1 to FO2_n, respectively. Here, since the output light rays reflected by the reflective liquid crystal element 130 are displaced by the same amount by the collimating lenses LO2_1 to LO2_n, they can be recombined to the output fibers FO2_1 to FO2_n with improved efficiency.

[0041] Therefore, the combination of the input unit 110 and the lens 122 results in a WSS array 100 device that, after sending out a predetermined set of beams along a predetermined angle (for example, angle θ1 in the case of WSS device 100a, and angle θ2 in the case of WSS device 100b), directs these beams toward a position on the reflective liquid crystal element 130 that depends only on the input angle (for example, position LC1 in the case of WSS device 100a, and position LC2 in the case of WSS device 100b). Thus, in the WSS array 100, as will be described in more detail below with reference to Figures 2 and 3, the rays from WSS device 100a and WSS device 100b are each processed by a common optical system 120 and reflective liquid crystal element 130, while each wavelength channel is processed separately by the processing capability of the WSS array 100.

[0042] Next, the WSS array 100 will be described using Figures 2 and 3. As already explained, Figure 2 is a view of the WSS array 100 from the y-axis direction. As already explained, Figure 3 is a view of an example of a wavelength channel focused on the reflective liquid crystal element 130. In the following, we will mainly describe the WSS device 100a of the WSS devices 100a and 100b, but the same can be said for the WSS device 100b.

[0043] As shown in Figure 2, in the WSS device 100a, the WDM signal beam BI1 that has passed through the input fiber FI1 is incident on the optical system 120. In the example in Figure 2, the WDM signal beam BI1 travels along a plane perpendicular to the plane of paper (yz plane) at an angle θ1. The WDM signal beam BI1 also includes multiple wavelength channels. The multiple wavelength channels have a wavelength range from the longest wavelength λ1 to the shortest wavelength λn. The WDM signal beam BI1 may also include a large number of wavelength channels, in which case the large number of wavelength channels may be, for example, 96 wavelength channels spaced at 50 or 100 GHz intervals on a fixed grating. In other examples, the WSS device 100a can use a frequency spacing of 12.5 GHz and can be used in an adaptable grating system having, for example, 130 or more wavelength channels (i.e., 97 or more wavelength channels).

[0044] In the optical system 120, the WDM signal beam BI1 is incident on a lens 121 that shapes the WDM signal beam BI1 in the x-axis direction. The lens 121 expands the WDM signal beam BI1 so that, for example, the diameter is suitable for the WDM signal beam BI1 to achieve a desired beam size in the dispersion element 124. Note that the collimating lens provided in the input unit 110 and the lens 121 provided in the optical system 120 may function as a beam expansion telescope.

[0045] In the optical system 120, the dispersion element 124 angularly disperses the wavelength channels of the WDM signal beam BI1. The wavelength channels λ1 to λn dispersed by the dispersion element 124 are respectively focused onto the reflective liquid crystal element 130 by the lens 123. Thereby, the wavelength channels λ1 to λn are spatially dispersed in the wavelength dispersion direction (x-axis direction) on the reflective liquid crystal element 130.

[0046] In the example of FIG. 3, an example of the distribution of wavelength channels in the pixel area of the reflective liquid crystal element 130 is shown. In the example of FIG. 3, only the wavelength channels λ1 to λ3 out of the wavelength channels λ1 to λn are shown. More generally, each wavelength channel can be arranged on the two-dimensional surface of the reflective liquid crystal element 130 as a long strip or an elliptical spot. Briefly speaking, each wavelength channel is processed as a discrete wavelength signal that can be independently acted on by the reflective liquid crystal element 130. However, the reflective liquid crystal element 130 does not necessarily have to act on individual wavelength channels and may act on a group of wavelength channels. Further, as shown in FIG. 3, the wavelength channel itself or the group of wavelength channels itself does not have to have a fixed bandwidth. This is because the reflective liquid crystal element 130 can be implemented in the WSS array 100 as a dynamically fully reconfigurable spatial light modulator. Therefore, the WSS array 100 can be used in systems with a general fixed grid architecture and a highly adaptable grid architecture that can be developed generally or in the future.

[0047] As shown in Fig. 2, thereafter, the reflective liquid crystal element 130 can redirect the wavelength channels λ1 to λn selected from a plurality of wavelength channels toward the output fibers FO1_1 to FO1_n, respectively. In the example of Fig. 2, the redirection by the reflective liquid crystal element 130 is performed along a plane (yz plane) orthogonal to the paper surface. The wavelength channels redirected by being reflected in the reflective liquid crystal element 130 are incident on the lens 123. The lens 123 redirects the incident wavelength channels so as to be recombined in the dispersion element 124. For example, in the dispersion element 124, a plurality of wavelength channels are recombined to form a single beam (output beam). The output beams BO_1 to BO_n formed in the dispersion element 124 are redirected to be parallel light rays with respect to each other in the lens 122 and the collimating lens of the input unit 110, and then output to the outside as processed signals via the output fibers FO1_1 to FO1_n.

[0048] For example, consider a case where the WDM signal beam BI1 includes three wavelength channels (hereinafter referred to as wavelength channels λ1 to λ3) each having wavelengths λ1, λ2, and λ3 and channel bandwidths δλ1, δλ2, and δλ3, respectively. In this case, in the example of Fig. 1, the WDM signal beam BI1 is incident on the optical system 120 at an angle θ1. Since the light rays of the WDM signal beam BI1 advancing at an angle θ1 pass through the center of the lens 122, the inclination of the angle θ1 is maintained. The WDM signal beam BI1 passing through the lens 122 is dispersed in the dispersion element 124 into a plurality of wavelength channels including the above-described three wavelength channels along a plane (zx plane) orthogonal to the paper surface of Fig. 1. However, all of the plurality of wavelength channels passing through the dispersion element 124 maintain the inclination of the angle θ1 in a plane (yz plane) parallel to the paper surface of Fig. 1. The above-described three dispersed wavelength channels are then condensed by the lens 123 at different positions on the pixel area of the reflective liquid crystal element 130 as shown in Fig. 3.

[0049] Regarding the routing function of the device, several different routing functions may be combined. For example, considering the case where all three wavelength channels λ1 to λ3 described above are routed to a common output fiber FO_n, the wavelength channels λ1 to λ3 reflected by the reflective liquid crystal element 130 are deflected by the lens 123 and focused before reaching the dispersive element 124. Thereafter, they are recombined (multiplexed) by the dispersive element 124 to form a single output beam BO1_n. The output beam BO1_n that has passed through the dispersive element 124 is redirected by the lens 122 so that it is tilted at an angle θ1.

[0050] The output beam BO1_n, having passed through lens 122, travels along the yz plane at an angle θ1 with respect to the axis of symmetry Z1, passes through lens 121, and is then incident on collimating lens LO1_n. The collimating lens LO1_n redirects the output beam BO1_n so that it is parallel to the axis of symmetry Z1. The output beam BO1_n, having passed through collimating lens LO1_n, is emitted to the outside of the WSS array 100 via output fiber FO1_n.

[0051] Furthermore, the case is not limited to the case where multiple wavelength channels are routed to a common output fiber; multiple wavelength channels may also be routed to multiple different output fibers. For example, considering the case where the three wavelength channels λ1 to λ3 described above are routed to different output fibers FO1_1 to FO1_3, the wavelength channels λ1 to λ3 reflected by the reflective liquid crystal element 130 are deflected by the lens 123 and then their direction is changed by the dispersion element 124, thereby forming output beams BO1_1 to BO1_3 that spread out in a fan shape. The output beams BO1_1 to BO1_3 that have passed through the dispersion element 124 are then directed by the lens 122 so that they are tilted at an angle θ.

[0052] The output beams BO1_1 to BO1_3 of the parallel light rays that have passed through lens 122 all travel along the yz plane at an angle θ1 with respect to the axis of symmetry Z1, and after passing through lens 121, they are incident on collimating lenses LO1_1 to LO1_3, respectively. The collimating lenses LO1_1 to LO1_3 redirect the output beams BO1_1 to BO1_3 so that they are parallel to the axis of symmetry Z1. The output beams BO1_1 to BO1_3 that have passed through collimating lenses LO1_1 to LO1_3 are then emitted to the outside of the WSS array 100 via output fibers FO1_1 to FO1_3, respectively. In other words, in the WSS device 100a, wavelength channels λ1 to λ3 are routed from the input fiber FI1 to the output fibers FO1_1 to FO1_3 via the reflective liquid crystal element 130.

[0053] As described above, any wavelength channel of a WDM signal in WSS device 100a can be routed to one or more output fibers among multiple output fibers as needed. The same applies to any wavelength channel of a WDM signal in WSS device 100b as to WSS device 100a. That is, any wavelength channel of a WDM signal in WSS device 100b can be routed to one or more output fibers among multiple output fibers as needed. This is because, in the WSS array 100, the optical system 120 and the reflective liquid crystal element 130 are configured to be symmetrical with respect to the symmetry axis Z1, and the wavelength channels dispersed in WSS device 100a and the wavelength channels dispersed in WSS device 100b are focused at different positions on the reflective liquid crystal element 130.

[0054] Furthermore, while the examples in Figures 1 to 3 describe a case where each WSS device is provided with one input port (input fiber) and n output ports (output fibers), the explanation is not limited to this, and each WSS device may be provided with any number of input ports and any number of output ports. Also, some or all of the n output ports may be reconfigured as input ports, and one input port may be reconfigured as an output port. In addition, while the examples in Figures 1 to 3 describe a case where the WSS array 100 is composed of two WSS devices 100a and 100b, the explanation is not limited to this, and it may be composed of three or more WSS devices.

[0055] Next, we will explain the details of the reflective liquid crystal element 130 applied to the WSS array 100.

[0056] <Preliminary study on liquid crystal devices> First, the liquid crystal device 50 that the inventors have studied in advance will be described. The liquid crystal device 50 can also be used as a reflective liquid crystal element 130 of the WSS array 100.

[0057] (Configuration of liquid crystal device 50 in the conceptual stage) Figure 4 shows an example configuration of an active matrix type liquid crystal device 50 in the conceptual stage.

[0058] As shown in Figure 4, the liquid crystal device 50 comprises an image display unit 11, a timing generator 13, a polarity switching control circuit 14, a vertical shift register & level shifter 15, a horizontal driver 16, an analog switch unit 17, and AND circuits ADA1 to ADAn and ADB1 to ADBn. The horizontal driver 16, together with the analog switch unit 17, constitutes a data line driving circuit and includes a shift register circuit 161, a one-line latch circuit 162, a comparator unit 163, and a grayscale counter 164. Figure 4 also shows a ramp signal generator 40 that is connected to the liquid crystal device 50 during normal operation.

[0059] Figure 5 is an enlarged view of the horizontal driver 16 and analog switch section 17 provided on the liquid crystal device 50. The comparator section 163 comprises m comparators 163_1 to 163_m corresponding to m rows of pixels 12 (where m is an integer of 2 or more). The analog switch section 17 comprises m sets of switch elements SW1_1+, SW1_1- to SW1_m+, SW1_m- corresponding to m rows of pixels 12.

[0060] The pixel arrangement area of ​​the image display unit 11 is wired with n rows of row scan lines G1 to Gn and n rows of readout switch selection lines TG1 to TGn extending horizontally (I-axis direction), and m columns of data lines D1+, D1- to Dm+, Dm- extending vertically (J-axis direction). In addition, gate control signal lines S+, S- and gate control signal line B are wired to the pixel arrangement area of ​​the image display unit 11.

[0061] The image display unit 11 has a plurality of regularly arranged pixels 12. Here, the plurality of pixels 12 are arranged in a two-dimensional matrix at a total of n × m intersections where n rows of row scan lines G1 to Gn extending in the horizontal direction (I-axis direction) and m sets of data lines D1+, D1- to Dm+, Dm- extending in the vertical direction (J-axis direction) intersect.

[0062] The row scan line Gj (where j is any integer from 1 to n) and the read switch selection line TGj are commonly connected to each of the m pixels 12 located in the j-th row. The data lines Di+ and Di- (where i is any integer from 1 to m) are commonly connected to each of the n pixels 12 located in the i-th column. Furthermore, the gate control signal lines S+, S-, and gate control signal line B are all commonly connected to all pixels 12. However, the gate control signal lines S+, S-, and gate control signal line B may each be provided individually for each row.

[0063] The polarity switching control circuit 14 outputs a positive polarity gate control signal (hereinafter referred to as gate control signal S+) to the gate control signal line S+, a negative polarity gate control signal (hereinafter referred to as gate control signal S-) to the gate control signal line S-, and further outputs a gate control signal (hereinafter referred to as gate control signal B) to the gate control signal line B, based on the timing signal generated by the timing generator 13.

[0064] The vertical shift register & level shifter 15 outputs n-row scan pulses, one row at a time from the first row to the nth row, with a period of one horizontal scan period (HST). The AND circuits ADA1 to ADAn each control whether to output the n-row scan pulses, which are sequentially output one row at a time from the vertical shift register & level shifter 15, to the row scan lines G1 to Gn, based on the externally supplied mode switching signal MD. The AND circuits ADB1 to ADBn each control whether to output the n-row scan pulses, which are sequentially output one row at a time from the vertical shift register & level shifter 15, to the readout switch selection lines TG1 to TGn, based on the externally supplied mode switching signal MD.

[0065] For example, in the operation of writing a video signal to pixel 12 (image writing operation), an H-level mode switching signal MD is supplied from an external source. In this case, AND circuits ADA1 to ADAn each output n lines of scan pulses, which are sequentially output one line at a time from the vertical shift register and level shifter 15, to the row scan lines G1 to Gn. On the other hand, AND circuits ADB1 to ADBn each do not output n lines of scan pulses, which are sequentially output one line at a time from the vertical shift register and level shifter 15, to the read switch selection lines TG1 to TGn. Therefore, the read switch selection lines TG1 to TGn are all fixed at the L level.

[0066] In contrast, when the video signal written to the pixel 12 is read out (image readout operation), an L-level mode switching signal MD is supplied from an external source. In this case, AND circuits ADB1 to ADBn each output n lines of scan pulses, which are sequentially output one line at a time from the vertical shift register and level shifter 15, to the readout switch selection lines TG1 to TGn. On the other hand, AND circuits ADA1 to ADAn each do not output n lines of scan pulses, which are sequentially output one line at a time from the vertical shift register and level shifter 15, to the row scan lines G1 to Gn. Therefore, the row scan lines G1 to Gn are all fixed at the L level.

[0067] (Specific example of the configuration of pixel 12) Figure 6 shows a specific example of the configuration of pixel 12. Here, we will describe a pixel 12 located in the jth row and ith column of an n-row x m-column pixel 12.

[0068] As shown in Figure 6, the pixel 12 includes N-channel MOS transistors (hereinafter simply referred to as transistors) Tr1, Tr2, Tr5, Tr6, Tr9, P-channel MOS transistors (hereinafter simply referred to as transistors) Tr3, Tr4, Tr7, Tr8, holding capacitors Cs1, Cs2, and liquid crystal display elements LC.

[0069] The transistor Tr1 and the holding capacitor Cs1 constitute a sample-and-hold circuit that samples and holds the positive polarity video signal supplied via the data line Di+. Specifically, the source of transistor Tr1 is connected to one of the data line pairs, data line Di+, the drain is connected to the gate of transistor Tr3, and the gate is connected to the row scan line Gj. The holding capacitor Cs1 is provided between the gate of transistor Tr3 and the ground voltage terminal Vss.

[0070] The transistor Tr2 and the holding capacitor Cs2 constitute a sample-and-hold circuit that samples and holds the negative polarity video signal supplied via the data line Di-. Specifically, the source of transistor Tr2 is connected to the other data line Di- of the data line pair, the drain is connected to the gate of transistor Tr4, and the gate is connected to the row scan line Gj. The holding capacitor Cs2 is provided between the gate of transistor Tr3 and the ground voltage terminal Vss. The holding capacitors Cs1 and Cs2 are provided independently of each other and hold the positive and negative polarity video signals in parallel, respectively.

[0071] Transistors Tr3 and Tr7 constitute a source follower buffer (impedance conversion buffer) that outputs the voltage held in the holding capacitance Cs1. Specifically, in the source follower transistor Tr3, the drain is connected to the ground voltage line Vss and the source is connected to node Np. In transistor Tr7, which is used as a bias-controllable constant current load, the source is connected to the power supply voltage line Vdd, the drain is connected to node Np and the gate is connected to the gate control signal line B.

[0072] Transistors Tr4 and Tr8 constitute a source follower buffer that outputs the voltage held in the holding capacitance Cs2. Specifically, in the source follower transistor Tr4, the drain is connected to the ground voltage line Vss and the source is connected to node Nn. In transistor Tr8, which is used as a bias-controllable constant current load, the source is connected to the power supply voltage line Vdd, the drain is connected to node Nn and the gate is connected to the gate control signal line B.

[0073] Transistors Tr5 and Tr6 constitute a polarity switching switch. Specifically, in transistor Tr5, the source is connected to node Np, the drain is connected to the pixel drive electrode PE, and the gate is connected to one of the gate control signal lines S+ of the gate control signal line pair. In transistor Tr6, the source is connected to node Nn, the drain is connected to the pixel drive electrode PE, and the gate is connected to the other gate control signal line S- of the gate control signal line pair.

[0074] The liquid crystal display element (LC) is composed of a pixel driving electrode (reflective electrode) PE having light-reflecting properties, a common electrode CE that is spaced apart from and opposite to the pixel driving electrode and has light-transmitting properties, and liquid crystal LCM filling and encapsulating the space between them. A common voltage Vcom is applied to the common electrode CE. Transistor Tr9 is provided between the pixel driving electrode PE and the data line Di+, and is switched on and off by the readout switch selection line TGj.

[0075] The data line pairs Di+ and Di- are supplied with video signals of opposite polarities, sampled by the analog switch unit 17. When a scan pulse output from the vertical shift register & level shifter 15 is supplied to the row scan line Gj, transistors Tr1 and Tr2 turn on simultaneously. As a result, the voltages of the positive and negative video signals are stored and held in the holding capacitors Cs1 and Cs2, respectively.

[0076] Furthermore, the input resistances of the positive and negative source follower buffers are virtually infinite. Therefore, the charge accumulated in the holding capacitors Cs1 and Cs2 is retained without leakage until one vertical scan period has elapsed and a new video signal is written.

[0077] Transistors Tr5 and Tr6, which constitute the polarity switching switch, switch on and off according to the gate control signals S+ and S-, thereby alternately selecting and outputting the output voltage of the positive-side source follower buffer (voltage of the positive polarity video signal) and the output voltage of the negative-side source follower buffer (voltage of the negative polarity video signal) to the pixel drive electrode PE. As a result, the pixel drive electrode PE is supplied with a video signal voltage that periodically reverses polarity. In this way, since this liquid crystal device has a polarity reversal function in the pixels themselves, by rapidly switching the polarity of the video signal voltage supplied to the pixel drive electrode PE at each pixel, AC driving at high frequencies becomes possible regardless of the vertical scanning frequency.

[0078] (Explanation of AC driving method for pixel 12) Figure 7 is a timing chart for explaining the AC driving method of pixel 12 by the liquid crystal device 50. Here, we will explain the AC driving method for the pixel 12 located in the jth row and ith column of the n rows x m columns of pixels 12.

[0079] In Figure 7, VST represents the vertical synchronization signal which serves as the reference for vertical scanning of the video signal. B represents the gate control signals supplied to the gates of transistors Tr7 and Tr8, which are used as constant current loads for two types of source follower buffers. S+ represents the gate control signal supplied to the gate of transistor Tr5 on the positive side of the polarity switching switch. S- represents the gate control signal supplied to the gate of transistor Tr6 on the negative side of the polarity switching switch. VPE represents the voltage applied to the pixel drive electrode PE. Vcom represents the voltage applied to the common electrode CE. VLC represents the AC voltage applied to the liquid crystal LCM.

[0080] Figure 8 is a diagram illustrating the voltage levels from black to white for both the positive and negative polarity video signals written to the pixel 12. In the example in Figure 8, the positive polarity video signal represents the black level when the voltage level is minimum and the white level when the voltage level is maximum. Conversely, the negative polarity video signal represents the white level when the voltage level is minimum and the black level when the voltage level is maximum. However, the positive polarity video signal may be configured to represent the white level when the voltage level is minimum and the black level when the voltage level is maximum, and the negative polarity video signal may be configured to represent the black level when the voltage level is minimum and the white level when the voltage level is maximum. The dashed lines in the figure indicate the inversion centers of the positive and negative polarity video signals.

[0081] In pixel 12, transistor Tr9 remains in the off state because the readout switch selection line TGj is fixed at the L level. On the other hand, transistors Tr1 and Tr2 are temporarily turned on when a scan pulse is supplied to the row scan line Gj. When transistors Tr1 and Tr2 are turned on, the positive and negative polarity video signal voltages are stored and held in the holding capacitors Cs1 and Cs2, respectively.

[0082] As shown in Figure 7, the positive-side transistor Tr5 is turned on during the period when the gate control signal S+ is at the H level. At this time, by setting the gate control signal B to the L level, transistor Tr7 is turned on, and the positive-side source follower buffer becomes active. As a result, the pixel drive electrode PE is charged to the voltage level of the positive-polarity video signal. Furthermore, by setting the gate control signal B to the L level, transistor Tr8 is turned on, and the negative-polarity source follower buffer also becomes active. However, since the negative-polarity transistor Tr6 is off, the pixel drive electrode PE is not charged to the voltage level of the negative-polarity video signal. When the pixel drive electrode PE is fully charged, the gate control signal B is switched from the L level to the H level, and the gate control signal S+ is switched from the H level to the L level. As a result, the pixel drive electrode PE becomes floating, and the positive-polarity drive voltage is maintained in the liquid crystal capacitance.

[0083] On the other hand, during the period when the gate control signal S- is at the H level, the negative-side transistor Tr6 is turned on. At this time, by setting the gate control signal B to the L level, the negative-side transistor Tr8 is turned on, and the negative-side source follower buffer becomes active. As a result, the pixel drive electrode PE is charged to the voltage level of the negative polarity video signal. Furthermore, by setting the gate control signal B to the L level, the transistor Tr7 is turned on, and the positive-side source follower buffer also becomes active. However, since the positive-side transistor Tr5 is off, the pixel drive electrode PE is not charged to the voltage level of the positive polarity video signal. When the pixel drive electrode PE is fully charged, the gate control signal B is switched from the L level to the H level, and the gate control signal S- is switched from the H level to the L level. As a result, the pixel drive electrode PE becomes floating, and the negative polarity drive voltage is maintained in the liquid crystal capacitance.

[0084] By alternately repeating the operations of the positive and negative electrodes described above, a drive voltage VPE, which is converted into AC using the voltages of the positive and negative video signals, is applied to the pixel drive electrode PE.

[0085] Furthermore, since the charge held in the retention capacitors Cs1 and Cs2 is not directly transferred to the pixel drive electrode PE but is transferred via a source follower buffer, even when the positive and negative polarity video signal voltages are repeatedly charged and discharged at the pixel drive electrode PE, pixel driving can be achieved without neutralizing the charge and without attenuation of the voltage level.

[0086] Furthermore, as shown in Figure 7, the voltage level of the voltage Vcom applied to the common electrode CE is switched to the opposite level to the applied voltage VPE in synchronization with the switching of the voltage level of the voltage VPE applied to the pixel drive electrode PE. Note that the voltage Vcom applied to the common electrode CE is set to an inversion reference voltage that is approximately equal to the inversion reference voltage of the voltage VPE applied to the pixel drive electrode PE.

[0087] Here, the effective AC voltage VLC applied to the liquid crystal LCM is the difference voltage between the voltage VPE applied to the pixel drive electrode PE and the voltage Vcom applied to the common electrode CE. Therefore, an AC voltage VLC without a DC component is applied to the liquid crystal LCM. In this way, by switching the voltage Vcom applied to the common electrode CE in opposite phase to the voltage VPE applied to the pixel drive electrode PE, the amplitude of the voltage to be applied to the pixel drive electrode PE can be reduced, thereby reducing the breakdown voltage and power consumption of the transistors constituting the pixel circuit.

[0088] Even if the current flowing steadily through the source follower buffer per pixel is a minute current of 1 μA, the total current flowing steadily through all pixels of the liquid crystal device can become a significant and non-negligible current. For example, a 2-megapixel liquid crystal device for full HD can consume up to 2 A of current. Therefore, in pixel 12, transistors Tr7 and Tr8, which are used as constant current loads, are not kept on all the time, but are only turned on for a limited period of time while the positive and negative transistors Tr5 and Tr6, respectively, are on. This allows the operation of one source follower buffer to be stopped when the other source follower buffer is operating, thereby suppressing the increase in current consumption.

[0089] The AC drive frequency of a liquid crystal display element (LC) can be freely adjusted by adjusting the inversion control period of the pixel itself, regardless of the vertical scanning frequency. For example, suppose the vertical scanning frequency is 60 Hz, which is commonly used in television video signals, and the number of vertical periodic scan lines n for full HD is 1125 lines. Also, assume that polarity switching at each pixel is performed at a period of about 15 line periods. In other words, the number of lines r per polarity switching period at each pixel is 30 lines. In this case, the AC drive frequency of the liquid crystal becomes 60 Hz × 1125 / (15 × 2) = 2.25 kHz. In other words, the liquid crystal device 50 can dramatically increase the AC drive frequency of the liquid crystal. As a result, the reliability, stability, and display quality of the image displayed on the liquid crystal screen, which were problems when the AC drive frequency of the liquid crystal was low, can be greatly improved.

[0090] Next, we will explain the operation of the liquid crystal device 50 in each operating mode.

[0091] (Operation of the liquid crystal device 50 in image display mode) First, the operation of the liquid crystal device 50 in image display mode (pixel writing mode) will be explained using Figure 9. Figure 9 is a timing chart showing the operation of the liquid crystal device 50 in image display mode.

[0092] As shown in Figure 9, when the horizontal synchronization signal HST pulse signal is supplied, the shift register circuit 161 sequentially captures m rows of video signals with an N (where N is an integer of 2 or more) bit width in synchronization with the clock signal HCK. The one-line latch circuit 162 simultaneously outputs the m rows of video signals captured by the shift register circuit 161 at the timing when the trigger signal REG_S becomes temporarily active.

[0093] The grayscale counter 164 counts the number of rising edges of the clock signal CNT_CK and outputs a grayscale signal Cout indicating the count value. Here, the grayscale counter 164 outputs a grayscale signal Cout indicating the minimum count value at the start of one horizontal ramp period (the transition period of the ramp signal within one horizontal scanning period) R (when the horizontal synchronization signal HST rises) S1, increases the grayscale level of the grayscale signal Cout as the count value increases, and outputs a grayscale signal Cout indicating the maximum count value at the end of one horizontal ramp period R (the time before the next rising edge of the horizontal synchronization signal HST) E1. The count value of the grayscale counter 164 is initialized to "0", for example, when the reset signal CNT_R becomes active in response to the rising edge of the horizontal synchronization signal HST. The grayscale counter 164 is not limited to count-up operation, but may also be configured to perform count-down operation. In that case, the count value is initialized to the maximum value when the reset signal CNT_R becomes active.

[0094] The m-row comparators 163_1 to 163_m provided in the comparator unit 163 operate in synchronization with the clock signal CMP_CK. When the grayscale signal Out output from the grayscale counter 164 matches each of the m-row video signals (line data) simultaneously output from the 1-line latch circuit 162, the matching signals P1 to Pm are activated (for example, to an L level).

[0095] Of the m sets of switch elements SW1_1+, SW1_1- to SW1_m+, SW1_m- provided in the analog switch section 17, the positive polarity switch elements SW1_1+ to SW1_m+ are provided between the data lines D1+ to Dm+ and the common wiring Dcom+, respectively. The negative polarity switch elements SW1_1- to SW1_m- are provided between the data lines D1- to Dm- and the common wiring Dcom-, respectively. The m sets of switch elements SW1_1+, SW1_1- to SW1_m+, SW1_m- are switched on and off by the matching signals P1 to Pm from the comparators 163_1 to 163_m, respectively.

[0096] The common wiring Dcom+ is supplied with the reference lamp voltage Ref_R+, which is the positive polarity lamp signal output from the lamp signal generator 40. The common wiring Dcom- is supplied with the reference lamp voltage Ref_R-, which is the negative polarity lamp signal output from the lamp signal generator 40.

[0097] The reference lamp voltage Ref_R+ is a sweep signal in which the image level changes from a black level to a white level from the start to the end of each horizontal scan period. The reference lamp voltage Ref_R- is a sweep signal in which the image level changes from a black level to a white level from the start to the end of each horizontal scan period. Therefore, the reference lamp voltage Ref_R+ with respect to the common voltage Vcom and the reference lamp voltage Ref_R- with respect to the common voltage Vcom are inverse relationships with each other.

[0098] For example, the reference lamp voltage Ref_R+ linearly increases the voltage level from 0V (black level) to 4V (white level) during the horizontal lamp period R, from the start S1 to the end E1. The reference lamp voltage Ref_R- linearly decreases the voltage level from 4V (black level) to 0V (white level) during the horizontal lamp period R, from the start S1 to the end E1. Then, between the end E1 of the horizontal lamp period R and the start S2 of the next horizontal lamp period R, the reference lamp voltage Ref_R+ returns to 0V (black level), and the reference lamp voltage Ref_R- returns to 4V (black level).

[0099] The switch elements SW1_1+, SW1_1- to SW1_m+, SW1_m- are all turned on simultaneously at the start of the horizontal ramp period R (S1) when the start signal SW_Start becomes active (e.g., at level H). Subsequently, each of the switch elements SW1_1+, SW1_1- to SW1_m+, SW1_m- switches from on to off before the horizontal ramp period R has elapsed when the matching signals P1 to Pm output from comparators 163_1 to 163_m become active (e.g., at level L). After the end of the horizontal ramp period R (E1) and before the start of the next horizontal ramp period R (S2), the start signal SW_Start becomes inactive (e.g., at level L).

[0100] In the example in Figure 9, the waveform SPk represents the timing of switching the on and off of the switch elements SW1_q+ and SW1_q- (where q is an integer from 1 to m), which are provided in correspondence with the pixel row on which the video signal of grayscale level k is written. Referring to Figure 9, the switch elements SW1_q+ and SW1_q- are turned on at the rising edge of the start signal SW_Start, and then switch from on to off when the matching signal Pq becomes active before the horizontal ramp period R has elapsed. Here, the switch elements SW1_q+ and SW1_q- sample the reference ramp voltages Ref_R+ and Ref_R- (voltages P and Q in Figure 9) at the timing of switching from on to off. These sampled voltages P and Q are supplied to the data lines Dq+ and Dq-. In other words, the analog voltages P and Q, which are the DA conversion results of the video signal of grayscale level k, are supplied to the data lines Dq+ and Dq-, respectively.

[0101] In image display mode, an H-level mode switching signal MD is supplied from an external source. Therefore, the n-row scan pulses output sequentially from the vertical shift register & level shifter 15 are supplied to the row scan lines G1 to Gn, respectively. As a result, for example, transistors Tr1 and Tr2 provided in each pixel 12 of the j-th row are temporarily turned on. Consequently, the corresponding positive and negative polarity video signal voltages are stored and held in the retention capacitors Cs1 and Cs2 provided in each pixel 12 of the j-th row, respectively. On the other hand, transistor Tr9 provided in each pixel 12 remains in the off state. The AC driving method for each pixel 12 thereafter is as previously described.

[0102] As described above, the switch elements SW1_1+, SW1_1- to SW1_m+, SW1_m- are all turned on simultaneously at the start of each horizontal scanning period, but each is turned off at an arbitrary timing corresponding to the grayscale level of the image to be displayed on the corresponding pixel 12. In other words, the switch elements SW1_1+, SW1_1- to SW1_m+, SW1_m- may all be turned off at the same time, or they may be turned off at different timings. Furthermore, the order in which they are turned off is not fixed.

[0103] In this way, the liquid crystal device 50 can improve the linearity of the image by performing a D / A conversion of the video signal using a ramp signal and then writing it to the pixels 12.

[0104] (Operation of the liquid crystal device 50 in pixel inspection mode) Next, the operation of the liquid crystal device 50 in pixel inspection mode (pixel readout mode) will be described. In pixel inspection mode, an inspection device (not shown) is provided instead of the lamp signal generator 40. Alternatively, in pixel inspection mode, the lamp signal generator 40 functions as the inspection device.

[0105] In pixel inspection mode, first, inspection video signals are written to the m pixels 12 in the j-th row that are to be inspected. The operation at this time is basically the same as in pixel display mode. After that, the video signals (pixel drive voltage VPE) written to the m pixels 12 in the j-th row that are to be inspected are read out.

[0106] During the pixel readout operation, the externally supplied mode switching signal MD switches from the high level to the low level. As a result, the scan pulse for the j-th row, output from the vertical shift register & level shifter 15, is supplied to the readout switch selection line TGj. This causes the transistor Tr9 provided at each pixel 12 in the j-th row, which is the object of inspection, to be temporarily turned on. On the other hand, the transistors Tr1 and Tr2 provided at each pixel 12 remain in the off state.

[0107] For example, in the pixel 12 located in the j-th row and i-th column, the pixel drive electrode PE and the data line Di+ become conductive when transistor Tr9 is turned on. At this time, by activating transistors Tr7 and Tr8 and turning on either transistor Tr5 or Tr6, the pixel drive electrode PE becomes driven by a source follower buffer consisting of transistors Tr3 and Tr7 or transistors Tr4 and Tr8. As a result, the drive voltage VPE applied to the pixel drive electrode PE by the source follower buffer is read out to the data line Di+.

[0108] The m pixel drive voltages VPE, read from each of the m pixels 12 in the j-th row to the data lines D1+ to Dm+, are sequentially supplied to the common wiring Dcom+ by sequentially turning on the m sets of SW1_1+, SW1_1- to SW1_m+, SW1_m- provided in the analog switch unit 17. An inspection device (not shown), provided in place of the lamp signal generator 40, detects whether or not there are faults (pixel defects and characteristic degradation) in the m pixels 12 in the j-th row based on the m pixel drive voltages VPE supplied sequentially via the common wiring Dcom+.

[0109] This type of inspection is performed row by row, starting from the m pixels 12 in the first row to the m pixels 12 in the nth row.

[0110] (Challenges of the liquid crystal device 50) Liquid crystal devices are required to display high-quality images. However, in the liquid crystal device 50, the switch elements SW1_q+ and SW1_q- of the analog switch section 17, which are provided between the common wiring Dcom+ and Dcom- on which the reference lamp voltages Ref_R+ and Ref_R- propagate, and the data lines Dq+ and Dq- (where q is any integer from 1 to m) on which the reference lamp voltages Ref_R+ and Ref_R- with voltage levels corresponding to the video signal are written, turn on when the reference lamp voltages Ref_R+ and Ref_R- begin to change linearly and turn off at a timing corresponding to the gradation level of the video signal. Therefore, at the timing when the reference lamp voltages Ref_R+ and Ref_R- begin to change linearly, the voltage (charge) written to the data lines Dq+ and Dq- in the previous horizontal scanning period propagates to the common wiring Dcom+ and Dcom- via the ON-state switch elements SW1_q+ and SW1_q-, potentially causing the values ​​of the reference lamp voltages Ref_R+ and Ref_R- to fluctuate while propagating through the common wiring Dcom+ and Dcom-. As a result, the liquid crystal device 50 may not be able to display high-quality images. Furthermore, if the device waits until the fluctuations in the reference lamp voltages Ref_R+ and Ref_R- subside, the frame rate must be lowered to ensure a longer horizontal scanning period, making it difficult to achieve a high frame rate. Also, even at the same frame rate, the time of one horizontal scanning period cannot be shortened to increase the pixel count, making it difficult to increase the pixel count.

[0111] The problems that occur in the liquid crystal device 50 will be explained in detail using the timing chart in Figure 9 and Figure 10. Figure 10 is a diagram for explaining the problems that occur in the liquid crystal device 50. Figure 10 shows the waveforms of the data line D1+, the start signal SW_Start, and the reference ramp voltage Ref_R+ near the end E1 of a certain horizontal ramp period R and the start S2 of the next horizontal ramp period R.

[0112] As shown in the timing chart in Figure 9, the reference ramp voltage Ref_R+ linearly increases from 0V (black level) to 4V (white level) during the horizontal ramp period R, from the start S1 to the end E1. The reference ramp voltage Ref_R- linearly decreases from 4V (black level) to 0V (white level) during the same period. Then, at the end of the horizontal ramp period R, E1, the reference ramp voltage Ref_R+ returns to 0V (black level), and the reference ramp voltage Ref_R- returns to 4V (black level).

[0113] On the other hand, the switch elements SW1_1+, SW1_1- to SW1_m+, SW1_m- are all turned on simultaneously at the start of the horizontal ramp period R S1 when the start signal SW_Start becomes active (e.g., at level H). Subsequently, the switch elements SW1_1+, SW1_1- to SW1_m+, SW1_m- are each switched from on to off before the horizontal ramp period R has elapsed when the matching signals P1 to Pm output from comparators 163_1 to 163_m become active (e.g., at level L). After the end of the horizontal ramp period R E1, and before the start of the next horizontal ramp period R S2, the start signal SW_Start becomes inactive (e.g., at level L).

[0114] Here, at the end of the horizontal ramp period R, E1, the switch elements SW1_1+, SW1_1- to SW1_m+, SW1_m- are all in the off state. Therefore, at the end of the horizontal ramp period R, E1, the data lines D1+, D1- to Dm+, Dm- are all written with analog voltages corresponding to the grayscale level of the video signal.

[0115] For example, as shown in Figure 10, if a high white level voltage (e.g., 4V) is written to all data lines D1+ to Dm+ during a certain horizontal ramp period R, a charge equivalent to the high white level voltage (e.g., 4V) is stored in the parasitic capacitance of each data line D1+ to Dm+. The parasitic capacitance of data line Dq+ includes, for example, the wiring capacitance of data line Dq+ and the diffusion capacitance of transistor Tr1 provided in each of the n rows of pixels 12 connected to data line Dq+.

[0116] Subsequently, at the end of the horizontal ramp period R, E1, the reference ramp voltage Ref_R+ returns to a black level voltage (e.g., 0V). Then, at the start of the next horizontal ramp period R, S2, the start signal SW_Start becomes active (e.g., at the H level), causing the switch elements SW1_1+ to SW1_m+ to turn on simultaneously. At the same time, the reference ramp voltage Ref_R+ begins to increase linearly. However, at this time, the voltage written to the data lines D1+ to Dm+ in the previous horizontal scanning period propagates through the ON switch elements SW1_1+ to SW1_m+ to the common wiring Dcom+, which may cause the value of the reference ramp voltage Ref_R+ propagating through the common wiring Dcom+ to fluctuate.

[0117] In the example shown in Figure 10, the capacitance of the common wiring Dcom+ is approximately 20 pF, and when the number of pixels is FHD, the capacitance of all data lines D1+ to Dm+ becomes approximately 1000 pF. As a result, the initial value of the reference lamp voltage Ref_R+ propagating through the common wiring Dcom+ fluctuates from 0V to approximately 0.5V due to the influence of the charge on the data lines D1+ to Dm+. Consequently, the liquid crystal device 50 may not be able to display high-quality images. This problem is not limited to cases where a high white level voltage (e.g., 4V) is written to all data lines D1+ to Dm+, but can also occur when a relatively high voltage is written to some of the data lines D1+ to Dm+.

[0118] Similarly, if a low white level voltage (e.g., 0V) is written to all data lines D1- to Dm- during a certain horizontal ramp period R, a charge corresponding to the low white level voltage (e.g., 0V) is stored in the parasitic capacitance of each data line D1- to Dm-. The parasitic capacitance of data line Dq- includes, for example, the wiring capacitance of data line Dq- and the diffusion capacitance of transistors Tr2 provided in each of the n rows of pixels 12 connected to data line Dq-.

[0119] Subsequently, at the end of the horizontal ramp period R E1, the reference ramp voltage Ref_R- returns to a black level voltage (e.g., 4V). Then, at the start of the next horizontal ramp period R S2, the start signal SW_Start becomes active (e.g., H level), causing the switch elements SW1_1- to SW1_m- to turn on simultaneously. At this time, the reference ramp voltage Ref_R- also begins to increase linearly. However, at this time, the voltage written to the data lines D1- to Dm- during the previous horizontal scanning period propagates to the common wiring Dcom- via the ON switch elements SW1_1- to SW1_m-, which may cause the value of the reference ramp voltage Ref_R- propagating through the common wiring Dcom- to fluctuate. For example, the initial value of the reference ramp voltage Ref_R- propagating through the common wiring Dcom- may fluctuate from 5V to about 4.5V due to the influence of the charge on the data lines D1- to Dm-. As a result, the liquid crystal device 50 may not be able to display high-quality images. This problem is not limited to cases where a low voltage (e.g., 0V) of the white level is written to all of the data lines D1- to Dm-, but can also occur when a relatively low voltage is written to some of the data lines D1- to Dm-.

[0120] Therefore, a liquid crystal device, a wavelength selective switch device, and a control method for the liquid crystal device according to this disclosure have been found that can solve the above-mentioned problems and display high-quality images.

[0121] <Configuration of Liquid Crystal Device 1 according to this Disclosure> Figure 11 shows an example of the configuration of the liquid crystal device 1 according to this disclosure. The liquid crystal device 1 can also be used as a reflective liquid crystal element 130 of the WSS array 100.

[0122] As shown in Figure 11, the liquid crystal device 1 further includes an initialization switch unit 18 compared to the liquid crystal device 50. Figure 11 also shows a lamp signal generator 40 that is connected to the liquid crystal device 1 during normal operation. The initialization switch unit 18 is located between the analog switch unit 17 and the plurality of pixels 12. The other configurations of the liquid crystal device 1 are the same as those of the liquid crystal device 50, so their description is omitted.

[0123] Figure 12 is a diagram showing in more detail the horizontal driver 16, analog switch unit 17, and initialization switch unit 18 provided on the liquid crystal device 1.

[0124] As shown in Figure 12, the initialization switch unit 18 includes m sets of switch elements SW2_1+, SW2_1- to SW2_m+, SW2_m- corresponding to m rows of pixels 12. Of the m sets of switch elements SW2_1+, SW2_1- to SW2_m+, SW2_m-, the positive polarity switch elements SW2_1+ to SW2_m+ are provided between the data lines D1+ to Dm+ and the signal line (initialization wiring) dis+, respectively, and are switched on and off based on the control signal Rmp_dis. The negative polarity positive side switch elements SW2_1- to SW2_m- are provided between the data lines D1- to Dm- and the signal line (initialization wiring) dis-, respectively, and are switched on and off based on the control signal Rmp_dis. The signal line dis+ is set to the same voltage (e.g., 0V) as the value at which the linear increase of the reference lamp voltage Ref_R+ begins (initial value). The signal line dis- is set to the same voltage (e.g., 4V) as the value at which the linear decrease of the reference lamp voltage Ref_R- begins (initial value).

[0125] However, the signal line dis+ is not limited to being set to the same voltage as the initial value of the reference lamp voltage Ref_R+, but may also be set to a voltage close to the initial value of the reference lamp voltage Ref_R+. Similarly, the signal line dis- is not limited to being set to the same voltage as the initial value of the reference lamp voltage Ref_R-, but may also be set to a voltage close to the initial value of the reference lamp voltage Ref_R-. Therefore, for example, the signal line dis+ may be connected to the reference voltage terminal GND to which a reference voltage such as 0V is supplied, and the signal line dis- may be connected to the power supply voltage terminal VDD to which a power supply voltage such as 5V is supplied.

[0126] For example, the m-set of switch elements SW2_1+, SW2_1- to SW2_m+, SW2_m- are turned off when the control signal Rmp_dis is at a low level, and turned on when the control signal Rmp_dis is at a high level. When the control signal Rmp_dis is at a high level, the switch elements SW2_1+, SW2_1- to SW2_m+, SW2_m- are turned on, causing the positive polarity data lines D1+ to Dm+ to be initialized to the voltage of the signal line dis+ (0V), and the negative polarity positive data lines D1- to Dm- to be initialized to the voltage of the signal line dis- (4V).

[0127] Figure 13 shows an example configuration of the switch element SW2_1+, which is one of the switch elements SW2_1+, SW2_1- to SW2_m+, SW2_m-. As shown in Figure 13, the switch element SW2_1+ comprises a P-channel MOS transistor (hereinafter simply referred to as transistor) MP1, an N-channel MOS transistor (hereinafter simply referred to as transistor) MN1, and an inverter INV1. The source of transistor MP1 and the drain of transistor MN1 are connected to the signal line dis+. The drain of transistor MP1 and the source of transistor MN1 are connected to the data line D1+. The control signal Rmp_dis is supplied to the gate of transistor MN1, and the signal obtained by inverting the control signal Rmp_dis by inverter INV1 is supplied to the gate of transistor MP1. In other words, transistors MP1 and MN1 constitute a complementary switch.

[0128] Of the switch elements SW2_1+, SW2_1- to SW2_m+, SW2_m-, all switch elements except SW2_1+ have the same configuration as SW2_1+, so their explanation is omitted. However, the switch elements SW2_1+, SW2_1- to SW2_m+, SW2_m- are not limited to being composed of transistors MP1 and MN1; for example, they may be composed of transistor MP1 alone, or transistor MN1 alone.

[0129] (Operation of liquid crystal device 1 in image display mode) Figure 14 is a timing chart showing the operation of liquid crystal device 1 in image display mode (pixel writing mode). Compared to the timing chart shown in Figure 9, the timing chart in Figure 14 has an additional waveform for the control signal Rmp_dis.

[0130] As shown in Figure 14, the control signal Rmp_dis becomes temporarily active (e.g., at an H level) between the end E1 of one horizontal ramp period R and the start S2 of the next horizontal ramp period R. As a result, the m-set of switch elements SW2_1+, SW2_1- to SW2_m+, SW2_m- are turned on, so that the positive polarity data lines D1+ to Dm+ are initialized to the voltage of the signal line dis+ (0V), and the negative polarity positive data lines D1- to Dm- are initialized to the voltage of the signal line dis- (4V).

[0131] Subsequently, when the next horizontal synchronization signal HST pulse signal is supplied, the shift register circuit 161 sequentially captures m rows of N (where N is an integer greater than or equal to 2) bit wide video signals in synchronization with the clock signal HCK. The one-line latch circuit 162 simultaneously outputs the m rows of video signals captured by the shift register circuit 161 at the moment the trigger signal REG_S becomes temporarily active.

[0132] The m-row comparators 163_1 to 163_m provided in the comparator unit 163 operate in synchronization with the clock signal CMP_CK. When the grayscale signal Out output from the grayscale counter 164 matches each of the m-row video signals (line data) simultaneously output from the 1-line latch circuit 162, the matching signals P1 to Pm are activated (for example, to an L level).

[0133] The m-set of switch elements SW1_1+, SW1_1- to SW1_m+, SW1_m- provided in the analog switch section 17 are all turned on simultaneously at the start of the horizontal ramp period R S2 when the start signal SW_Start becomes active (e.g., at level H). Subsequently, each of the switch elements SW1_1+, SW1_1- to SW1_m+, SW1_m- switches from on to off before the horizontal ramp period R has elapsed when the matching signals P1 to Pm output from comparators 163_1 to 163_m become active (e.g., at level L). After the end of the horizontal ramp period R E2 and before the start of the next horizontal ramp period R, the start signal SW_Start becomes inactive (e.g., at level L).

[0134] Here, at the start of the horizontal ramp period R, S2, the data lines D1+ to Dm+ on the positive side have already been initialized to the voltage of the signal line dis+ (0V) by the initialization switch unit 18, and the data lines D1- to Dm- on the negative positive side have already been initialized to the voltage of the signal line dis- (4V). In other words, as shown in Figure 15, the initial value of the reference ramp voltage Ref_R+ propagating through the common wiring Dcom+ is approximately the same as the initial value of the data lines D1+ to Dm+ after initialization, and is also approximately the same as the initial value of the reference ramp voltage Ref_R- propagating through the common wiring Dcom-. Therefore, as shown in Figure 15, even when the switch elements SW1_1+, SW1_1- to SW1_m+, SW1_m- are turned on, the initial values ​​of the reference ramp voltages Ref_R+, Ref_R- propagating through the common wiring Dcom+, Dcom- do not change. Therefore, the liquid crystal device 1 can display high-quality images. Furthermore, since the liquid crystal device 1 does not need to wait until the fluctuations in the reference lamp voltages Ref_R+ and Ref_R- subside, the time from the end of horizontal lamp period R E1 to the start of the next horizontal lamp period R S2 can be shortened. As a result, the liquid crystal device 1 can achieve a higher frame rate and thus a higher pixel count.

[0135] As described above, the liquid crystal device 1 according to this disclosure initializes the voltages of the data lines D1+, D1- to Dm+, Dm- to a voltage corresponding to the initial value of the reference lamp voltage Ref_R+, Ref_R- using a path separate from the common wiring Dcom+, Dcom- before the start of the next horizontal ramp period. As a result, even when the switch elements SW1_1+, SW1_1- to SW1_m+, SW1_m- are turned on, the movement of charge between the data lines D1+ to Dm+ and the common wiring Dcom+, and the movement of charge between the data lines D1- to Dm- and the common wiring Dcom- are suppressed, and fluctuations in the initial value of the reference lamp voltage Ref_R+, Ref_R- propagating through the common wiring Dcom+, Dcom- are suppressed. As a result, the liquid crystal device 1 can display high-quality images. Furthermore, since the liquid crystal device 1 does not need to wait until the fluctuations in the reference lamp voltages Ref_R+ and Ref_R- subside, the time from the end of horizontal lamp period R E1 to the start of the next horizontal lamp period R S2 can be shortened. As a result, the liquid crystal device 1 can achieve a higher frame rate, thereby enabling a higher pixel count.

[0136] When the liquid crystal device 1 according to this disclosure is used as a reflective liquid crystal display element in a wavelength-selective switch, the switching time between optical signal processing and the no-signal state is shortened. As a result, the wavelength-selective switch can shorten the horizontal scanning period, which enables a higher frame rate. Furthermore, at the same frame rate, the shorter horizontal scanning period allows for higher pixel counts. Higher pixel counts lead to an increase in the number of channels in the optical switch, enabling the processing of a large amount of optical data at once. This means that, for example, when the wavelength-selective switch is used as a large-scale data switch requiring multiple ports, fewer LCOS units for the WSS are needed, thus reducing costs.

[0137] This disclosure is not limited to the embodiments described above, and may be modified as appropriate without departing from its spirit.

[0138] This application claims priority based on Japanese Patent Application No. 2024-224469, filed on 19 December 2024, and incorporates all of its disclosures herein.

[0139] This disclosure can be suitably applied to liquid crystal display devices mounted on projectors and the like, and to optical switching elements mounted on wavelength selective switching devices.

[0140] 1 Liquid crystal device 11 Image display section 12 Pixel 13 Timing generator 14 Polarity switching control circuit 15 Vertical shift register & level shifter 16 Horizontal driver 17 Analog switch section 18 Initialization switch section 30 Voltage source circuit 40 Lamp signal generator 50 Liquid crystal device 100 WSS array 100a WSS device 100b WSS device 110 Input section 120 Optical system 121 Lens 122 Lens 123 Lens 124 Dispersive element 130 Reflective liquid crystal element 161 Shift register circuit 162 1-line latch circuit 163 Comparator section 163_1 to 163_m Comparator 164 Grayscale counter ADA1 to ADAn AND circuit ADB1 to ADBn AND circuit B Gate control signal line CE Common electrodes Cs1, Cs2 Holding capacitance D1+, D1- to Dm+, Dm- Data lines Dcom+, Dcom- Common wiring FI1 Input fiber (input port) FI2 Input fiber (input port) FO1_1 to FO1_n Output fiber (output port) FO2_1 to FO2_n Output fiber (output port) G1 to Gn Row scan lines INV1 Inverter LC Liquid crystal display element LCM Liquid crystal LI1 Collimating lens LI2 Collimating lens LO1_1 to LO1_n Collimating lens LO2_1 to LO2_n Collimating lens MN1 N-channel MOS transistor MP1 P-channel MOS transistor Np, Nn Node PE Pixel driving electrode (reflection electrode) S+, S- Gate control signal lines SW1_1+, SW1_1- to SW1_m+, SW1_m- Switch elements SW2_1 to SW2_m Switch elements TG1 to TGn Switch selection lines for reading Tr1 to Tr9 Transistors Tr11 to Tr17 Transistors Tr21 to Tr25 Transistors

Claims

1. A liquid crystal device comprising: a plurality of pixels; a plurality of data lines provided corresponding to each row of the plurality of pixels; a shift register unit that sequentially captures video signals for the number of rows of the plurality of pixels in synchronization with a clock signal; a latch unit that simultaneously outputs the plurality of video signals captured by the shift register unit in synchronization with a trigger signal; a plurality of comparators that compare each of the plurality of video signals output from the latch unit with a gradation signal indicating a monotonically transitioning count value and activate the respective matching signal when they match; a plurality of first switch elements provided between a common wiring through which a ramp signal whose potential changes linearly with each horizontal ramp period propagates and the plurality of data lines, which turn on when the potential of the ramp signal begins to change linearly and turn off individually when the matching signal of each of the plurality of comparators becomes active; and a plurality of second switch elements provided between an initialization wiring on a separate path from the common wiring and the plurality of data lines, which initialize the potential of the plurality of data lines.

2. The liquid crystal device according to claim 1, wherein the plurality of second switch elements are temporarily turned on before the plurality of first switch elements are turned on.

3. The liquid crystal device according to claim 2, wherein the potential of the initialization wiring is set to a potential corresponding to the initial value of the potential of the lamp signal.

4. A control method for a liquid crystal device comprising: a plurality of pixels; a plurality of data lines provided corresponding to each row of the plurality of pixels; a shift register unit that sequentially captures video signals for the number of rows of the plurality of pixels in synchronization with a clock signal; a latch unit that simultaneously outputs the plurality of video signals captured by the shift register unit in synchronization with a trigger signal; a plurality of comparators that compare each of the plurality of video signals output from the latch unit with a gradation signal indicating a monotonically transitioning count value and activate the respective matching signal when they match; a plurality of first switch elements provided between a common wiring through which a ramp signal whose potential changes linearly with each horizontal ramp period propagates and the plurality of data lines, which turn on when the potential of the ramp signal begins to change linearly and turn off individually when the matching signal of each of the plurality of comparators becomes active; and a plurality of second switch elements provided between an initialization wiring on a separate path from the common wiring and the plurality of data lines, which initialize the potential of the plurality of data lines. A method for controlling a liquid crystal device, comprising: turning on the plurality of first switch elements at the timing when the potential of the ramp signal begins to change linearly during a certain horizontal ramp period; individually turning off the plurality of first switch elements at the timing when the matching signal of each of the plurality of comparators becomes active during a certain horizontal ramp period; temporarily turning on the plurality of second switch elements after the elapsed horizontal ramp period and before the start of the next horizontal ramp period; turning on the plurality of first switch elements at the timing when the potential of the ramp signal begins to change linearly during the next horizontal ramp period; and individually turning off the plurality of first switch elements at the timing when the matching signal of each of the plurality of comparators becomes active during the next horizontal ramp period.

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