Method for manufacturing heat-treated semiconductor wafer
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- SUMCO CORP
- Filing Date
- 2025-12-02
- Publication Date
- 2026-06-25
Smart Images

Figure JP2025042000_25062026_PF_FP_ABST
Abstract
Claims
1. A method for manufacturing a heat-treated semiconductor wafer, comprising: creating a database of relationships between one or more statistical quality parameters selected from the group consisting of flatness, LPD, lift pin mark area, and lift pin mark height, and lift operation parameters; calculating process capability parameters for multiple lift operation parameter combinations based on standard information of one or more quality parameters selected from the group consisting of flatness, LPD, lift pin mark area, and lift pin mark height, and the database; performing a pass / fail determination for the multiple lift operation parameter combinations based on the results of the calculation; selecting lift operation parameter combinations from among the lift operation parameter combinations determined to be passable in the pass / fail determination, the total lift operation time being less than or equal to a threshold, setting the selected lift operation parameter combinations in a single-wafer heat treatment furnace capable of variably setting the lift speed; and heat-treating the semiconductor wafer in the single-wafer heat treatment furnace.
2. The method for manufacturing a heat-treated semiconductor wafer according to claim 1, wherein the single-wafer heat treatment furnace is an epitaxial growth furnace, and the heat treatment is the formation of an epitaxial layer.
3. The method for manufacturing a heat-treated semiconductor wafer according to claim 1 or 2, wherein the single-wafer heat treatment furnace comprises a lift pin and a susceptor having a through hole through which the lift pin can be inserted in a semiconductor wafer mounting area, and the lift operation parameters include one or more lift operation parameters selected from the group consisting of a lift speed before contact between the lift pin and the back surface of the semiconductor wafer, a waiting time before contact between the lift pin and the back surface of the semiconductor wafer, a lift speed before contact between the susceptor and the semiconductor wafer, and a waiting time before contact between the susceptor and the semiconductor wafer.
4. A method for manufacturing a heat-treated semiconductor wafer according to claim 1 or 2, wherein, among the lift operation parameter combinations that are judged to pass in the pass / fail judgment, the lift operation parameter combination that has the shortest total lift operation time is selected.
5. The method for manufacturing a heat-treated semiconductor wafer according to claim 3, wherein, among the lift operation parameter combinations that are judged to pass in the pass / fail judgment, the lift operation parameter combination that has the shortest total lift operation time is selected.