Semiconductor structure forming a plurality of transistors

Abstract

A semiconductor structure that forms multiple transistors. The structure includes a first source layer located on a substrate and a first nanowire extending from this source layer. The nanowire extends longitudinally from a lower part in contact with the source layer to an upper part. The nanowire comprises a first and a second transistor along its length. The first transistor includes a first source terminal comprising the source layer, a first drain terminal at a drain section of the nanowire, and a first gate terminal connecting to the nanowire between the first source and drain terminals. The drain section connects to an adjacent source section of the nanowire. The second transistor includes a second source terminal comprising the source section, a second drain terminal connected to the upper part, and a second gate terminal connecting to the nanowire between the second source and drain terminals.

Description

[0001] SEMICONDUCTOR STRUCTURE FORMING A PLURALITY OF TRANSISTORS

[0002] Field

[0003] The technology pertains to the field of semiconductor devices, specifically focusing on the design and structure of semiconductor transistors. It also involves the application of nanotechnology in the fabrication of semiconductor structures, particularly in the creation of nanowire components.

[0004] Background

[0005] The field of nanotechnology has seen significant advancements in recent years, particularly in the development of nanowire-based semiconductor devices. Vertical nanowire transistors, with a nanowire length of approximately 500nm, have been widely used in amplifiers, including Power Amplifiers (PA) and Low Noise Amplifiers (LNA). These circuits often employ a cascode topology, which consists of a common source (CS) and a common gate (CG) transistor. In this configuration, the drain terminal of the CS connects to the source of the CG transistor.

[0006] However, the current design and layout of vertical nanowire transistors present several challenges. Firstly, the distance between the drain of one device and the source of the other is large due to their different heights and the presence of two separated source contacts, one at each side of the transistor fingers. This results in an increased routing distance, which can impact the efficiency and performance of the circuit.

[0007] Secondly, the layout requires the CS output to cross with the CG gate metal, which in- troduces additional parasitic capacitance. This unwanted capacitance can create signal distortion, reduce the bandwidth, and lower the cut-off frequency, thereby limiting the amplifier's performance at high frequencies.

[0008] These issues with the layout and resulting parasitics negatively impact key performance metrics, such as cut-off frequency, gain, and noise figure. These are critical for the func- tionality of amplifiers operating at high frequencies, which can achieve operating frequencies up to 300 GHz and power levels reaching 15 dBm output power. Therefore, there is a clear need for an optimized geometry that minimizes parasitic effects and is suitable for high-frequency applications. This would enhance the performance of vertical nanowire amplifiers and other similar circuit topologies. However, the development of such a solution presents significant technical challenges due to the inherent complexi- ties of nanowire-based semiconductor devices.

[0009] Summary

[0010] According to a first aspect of the disclosure, a semiconductor structure forming a plurality of transistors is provided. The semiconductor structure comprises a first source layer on a substrate, and a first nanowire extending from the first source layer, with a lower part of the first nanowire in contact with the first source layer. The first nanowire extends longitudinally with a length from the lower part to an upper part of the first nanowire. The first nanowire comprises a first transistor and a second transistor along the length. The first transistor comprises a first source terminal comprising the first source layer, a first drain terminal at a drain section of the first nanowire, and a first gate terminal connecting to the first nanowire between the first source terminal and the first drain terminal. The drain section connects to an adjacent source section of the first nanowire. The second transistor comprises a second source terminal comprising the source section, a second drain terminal connected to the upper part, and a second gate terminal connecting to the first nanowire between the second source terminal and the second drain terminal. This configuration allows for efficient use of space and materials, providing a compact and effective semiconductor structure. The parasitic capacitance is also reduced.

[0011] Optionally in some examples, the first nanowire comprises a first semiconductor material and a second semiconductor material, with the first and second transistors comprising a respective transition from the first semiconductor material to the second semiconductor material. Having a plurality of the aforementioned transitions allows for providing more than one transistor along the length of the nanowire while utilizing the benefits of bandgap engineering.

[0012] Optionally in some examples, the first gate terminal and the second gate terminal are arranged to contact the first nanowire at the respective transition. This ensures that the gate terminals are positioned at the optimal points for controlling the flow of current through the nanowire, enhancing the performance and efficiency of the transistors.

[0013] Optionally in some examples, the first drain terminal connects to the second source termi- nal at an interface between the first semiconductor material and the second semiconductor material. This configuration provides a seamless connection between the transistors, reducing resistance and improving the overall performance of the semiconductor structure.

[0014] Optionally in some examples, the lower part and the source section comprise the first semiconductor material, and the upper part and the drain section comprise the second semiconductor material.

[0015] Optionally in some examples, the nanowire comprises a stack of devices along the length, comprising the first and second transistors and at least a further gate terminal. This stacked configuration allows for the integration of multiple transistors in a compact space, increasing the functionality and performance of the semiconductor structure.

[0016] Optionally in some examples, the first gate terminal and / or the second gate terminal connects to a second nanowire or a plurality of nanowires extending from the first source layer, with the second nanowire comprising a first transistor and a second transistor, and / or the plurality of nanowires comprising a respective first transistor and a second transistor. This arrangement allows for the creation of complex and highly integrated semiconductor structures, enhancing the capabilities and performance of the device.

[0017] Optionally in some examples, the first gate terminal connects to a plurality of said nanowires along a first direction, and the second gate terminal connects to a plurality of said nanowires along a second direction, with the first direction being angled relative to the second direction. This configuration allows for the efficient routing of connections and the creation of highly integrated and compact semiconductor structures, improving the overall performance and functionality of the device. In particular, such "cross-bar" configuration reduces the parasitic capacitance between the gate terminals.

[0018] Optionally in some examples, the first gate terminal and / or the second gate terminal com- prises a first plurality of longitudinal extensions connecting to a plurality of said nanowires and being essentially parallel to each other. The first plurality of longitudinal extensions are arranged in an interleaving pattern with a second plurality of longitudinal extensions of an adjacent first gate terminal and / or second gate terminal connected to a plurality of said nanowires. This interleaving pattern allows for a more efficient and compact arrangement of the gate terminals, reducing the overall footprint of the semiconductor structure and improving its performance.

[0019] Optionally in some examples, a first conductor connects the first gate terminal to an adjacent second gate terminal connected to a plurality of said nanowires, and a second conductor connects the second gate terminal to an adjacent first gate terminal connected to a plurality of said nanowires. Such "cross coupling" capacitance is connected from the output of one transistor in the differential pair to the input of the other and vice versa. Since the gates are connected between the top and bottom devices the capacitance of the cross-coupling will track the parasitic capacitance between gate and drain of the amplifer with regards to the input signal level. This approach improves the linearity of the amplifier. Additional benefits of this approach include reduced footprint and reduced mismatch spread.

[0020] Brief Description of the Drawings

[0021] Examples are described in more detail below with reference to the appended drawings. Fig. 1 shows a schematic illustration of a semiconductor structure (100) forming a plurality of transistors, comprising a nanowire (103), the nanowire comprises a first transistor (106) and a second transistor (107) along the length (L) of the nanowire

[0022] Fig. 2 shows a schematic illustration of a semiconductor structure where the nanowire comprises a first semiconductor material (117) and a second semiconductor material (119), and a transition (118) between the first and second semiconductor materials

[0023] Fig. 3 shows a schematic illustration of a semiconductor structure where the nanowire comprises a stack of devices (106, 107, 113, 114) along the length of the nanowire, where the devices comprise the first and second transistors and at least a further gate terminal (112, 113) Fig. 4a shows a schematic illustration of a semiconductor structure where first gate terminal (106c) and / or second gate terminal (107c) of a first nanowire connects to a second nanowire (103') or a plurality of nanowires, the second nanowire comprising a respective first transistor (106) and a second transistor (107)

[0024] Fig. 4b shows a schematic top-down view of Fig. 4a, where the first and / or second gate terminal extends in a plane and connects to a plurality of nanowires, and the second drain terminal (107b) extends also in a plane and connects to the plurality of nanowires

[0025] Fig. 5 shows a schematic illustration of a semiconductor structure where the first gate terminal connects to a plurality of nanowires along a first direction (110) and the second gate terminal connects to a plurality of nanowires along a second direction (111), the first direction being angled relative the second direction Fig. 6 shows a schematic illustration of a semiconductor structure wherein a first gate terminal and / or a second gate terminal comprises a first plurality longitudinal extensions connecting to a plurality of nanowires (103), and where the first plurality longitudinal extensions are arranged in an interleaving pattern with a second plurality longitudinal extensions of an adjacent first gate terminal (106’c) and / or second gate terminal (107’c)

[0026] Fig. 7 shows a schematic illustration of a semiconductor structure where a first conductor (115) connects the first gate terminal (106c) to an adjacent second gate terminal (107’c) connected to a plurality of nanowires, and a second conductor (116) connects the second gate terminal (107c) to an adjacent first gate terminal (106’c), to form a cross-coupling. Fig. 8 shows a schematic illustration of a transistor device (200) having a corresponding cross-coupling as described in Fig. 7. The cross coupling capacitance is connected from the output of one transistor in the differential pair to the input of the other and vice versa.

[0027] Detailed Description

[0028] The detailed description set forth below provides information and examples of the dis- closed technology with sufficient detail to enable those skilled in the art to practice the disclosure.

[0029] Figure 1 shows a Semiconductor structure 100 comprising a First nanowire 103 extending longitudinally with a length (L) from a Lower part 104 to an Upper part 105. The First nanowire 103 is positioned on a Substrate 102. The First nanowire 103 comprises a First transistor 106 and a Second transistor 107 along the length (L) of the nanowire. A First source layer 101 is located on the Substrate 102 and serves as the first source terminal (106a) for the First transistor 106. The First transistor 106 includes a First source terminal (106a), a first drain terminal (106b) located at the Drain section 108 of the First nanowire 103, and a first gate terminal (106c) that connects to the First nanowire 103 between the first source terminal (106a) and the First drain terminal (106b). The first gate terminal (106c) serves as the gate for the First transistor 106. The Second transistor 107 includes a second source terminal (107a) comprising the Source section 109 of the First nanowire 103, a second drain terminal (107b) connected to the Upper part 105 of the First nanowire 103, and a second gate terminal (107c) that connects to the First nanowire 103 between the second source terminal (107a) and the Second drain terminal (107b). The second gate terminal (107c) serves as the gate for the Second transistor 107.

[0030] Figure 2 shows a schematic illustration of a semiconductor structure where the nanowire comprises a First semiconductor material 117 and a Second semiconductor material 119, and a Transition 118 between the first and second semiconductor materials. The lower part 104 and the Source section 109 comprises the first semiconductor material 117, and the upper part 105 and the Drain section 108 comprises the second semiconductor mate- rial 119. The Transition 118 forms a gradient between the First semiconductor material 117 and the Second semiconductor material 119. The First gate terminal 106c and the Second gate terminal 107c are arranged to contact the First nanowire 103 at the respective Transition 118.

[0031] Figure 3 shows a schematic illustration of a semiconductor structure where the nanowire comprises a stack of devices (106, 107, 113, 114) along the length of the nanowire, where the devices comprise the first and second transistors and at least a Further gate terminal (112, 113). The further gate terminals 112 and 113 are part of devices 113, 114, along the length of the First nanowire 103, thus forming a stacked structure with a small footprint. Respective transitions 118 between the first and second semiconductor materials 117, 118, are arranged along the nanowire 103 for the devices 106, 107, 113, 114, and forms a gradient between the First semiconductor material 117 and the Second semiconductor material 119.

[0032] Figure 4a shows a schematic illustration of a semiconductor structure 100 where a First gate terminal 106c and / or a Second gate terminal 107c of a first nanowire 103 connects to a second nanowire 103' or a plurality of nanowires. The configuration as described for the first nanowire 103 is mirrored in the second nanowire 103'. Figure 4b shows a schematic top-down view of Fig. 4a, where the first and / or second gate terminal extends in a plane and connects to a plurality of nanowires, and the second drain terminal 107b extends also in a plane and connects to the plurality of nanowires Figure 5 shows a schematic illustration of a semiconductor structure where the first gate terminal (106c) connects to a plurality of nanowires 103 along a first direction 110 and the second gate terminal (107c) connects to a plurality of nanowires 103 along a second direction 111, the first direction being angled relative to the second direction, such as perpendicular. The figure also shows an element 121 connecting to a plurality of the second gate terminal (107c) extending in parallel, and a further element 122 connecting to a plurality of the first gate terminal (106c) extending in parallel.

[0033] Figure 6 shows a schematic illustration of a semiconductor structure wherein a first gate terminal 106c and / or a second gate terminal 107c comprises a first plurality of longitudinal extensions (1061c, 1062c, 1063c; 1071c, 1072c, 1073c) connecting to a plurality of nanowires 103. The first plurality of longitudinal extensions are arranged in an interleav- ing pattern with a second plurality of longitudinal extensions (1061c, 1062c, 1063c; 1071c, 1072c, 1073c) of an adjacent first gate terminal 106'c and / or second gate terminal 107'c.

[0034] Figure 7 shows a schematic illustration of a semiconductor structure 100 where a first conductor 115 connects the First gate term inal 106c to an adjacent Second gate term inal 107'c connected to a plurality of nanowires 103. A second conductor 116 connects the Second gate terminal 107c to an adjacent First gate terminal 106'c, forming a cross-coupling.

[0035] Figure 8 shows a schematic illustration of a transistor device 200 having a corresponding cross-coupling as described in Figure 7. The cross-coupling capacitance is connected from the output of one transistor in the differential pair to the input of the other and vice versa.

[0036] 1 Semiconductor structure (100) Details

[0037] The semiconductor structure (100) includes the first source layer (101). The first source layer (101) serves as the first source terminal (106a) for the first transistor (106). The first source layer (101) may be located on a substrate (102). The first source layer (101) may be made of a semiconductor material. The semiconductor structure (100) also includes the first nanowire (103).

[0038] 1.1 First nanowire (103)

[0039] The first nanowire (103) is a component of the semiconductor structure (100). It forms the structural basis for the first transistor (106) and the second transistor (107). The first nanowire (103) includes a source section (109) and a drain section (108). The drain section (108) connects to the adjacent source section (109).

[0040] The first nanowire (103) may extend longitudinally from a lower part (104) to an upper part (105). In some instances, the first nanowire (103) may extend from the first source layer (101). The first nanowire (103) may be made of a semiconductor material. In some configurations, the first nanowire (103) includes a first semiconductor material (117) and a second semiconductor material (119). The lower part (104) and the source section (109) may comprise the first semiconductor material (117). The upper part (105) and the drain section (108) may comprise the second semiconductor material (119). A transition (118) may serve as the interface between the first and second semiconductor materials. The first gate terminal (106c) and the second gate terminal (107c) may be arranged to contact the first nanowire (103) at the respective transition (118). The first and second transistors (106, 107) may each comprise a respective transition (118) from the first semiconductor material (117) to the second semiconductor material (119). The transition (118) may form a gradient between the first and second semiconductor materials. In some configurations, the first nanowire (103) may include a stack of devices (106, 107, 113, 114) along its length. This stack of devices may form a stacked configuration with a small footprint. This stack may comprise the first and second transistors (106, 107) and at least a further gate terminal (112, 113). The further gate terminal (112, 113) may serve as the gate for additional transistors in the stack.

[0041] 1.1.1 First transistor (106)

[0042] The first nanowire (103) includes a first transistor (106). The first transistor (106) incor- porates a first source terminal (106a), which functions as the source for the transistor.

[0043] The first source terminal (106a) may be formed from the first source layer (101). The first transistor (106) also includes a first drain terminal (106b), serving as the drain. The first drain terminal (106b) may be located at the drain section (108) of the first nanowire (103). Furthermore, the first transistor (106) comprises a first gate terminal (106c), which acts as the gate. The first gate terminal (106c) may connect to the first nanowire (103) between the first source terminal (106a) and the first drain terminal (106b).

[0044] 1.1.2 Second transistor (107)

[0045] The first nanowire (103) also includes a second transistor (107). This second transistor (107) comprises a second source terminal (107a), which serves as the source. The sec- ond source terminal (107a) is formed by the source section (109) of the first nanowire (103). A second drain terminal (107b) is also part of the second transistor (107), functioning as the drain. The second drain terminal (107b) may connect to the upper part (105) of the first nanowire (103). The second transistor (107) further includes a second gate terminal (107c), which serves as the gate. The second gate terminal (107c) may connect to the first nanowire (103) between the second source terminal (107a) and the second drain terminal (107b).

[0046] 2 Operational Process

[0047] The semiconductor structure operates by utilizing the first and second transistors to control current flow. The first transistor acts as a switch, modulating the current between the first source and drain terminals based on the voltage applied to the first gate terminal. The second transistor operates similarly, controlling current flow between the second source and drain terminals based on the voltage applied to the second gate terminal. The interaction between these two transistors, along with the transition between semiconductor materials, enables complex functionalities within the semiconductor structure. The specific operation of the transistors depends on the applied voltages to the gate terminals. By varying these voltages, the current flow through the transistors can be precisely controlled, enabling the semiconductor structure to perform various logic operations or amplify sig- nals. The overall operation of the semiconductor structure can be further influenced by the configuration of the nanowires and the arrangement of the gate terminals. Different configurations can lead to variations in performance characteristics, such as switching speed and power consumption.

[0048] 2.1 Functioning of the First Transistor (106) The first transistor (106) functions as a voltage-controlled switch. When a voltage is applied to the first gate terminal (106c), it creates an electric field that modulates the conductivity of the channel region between the first source terminal (106a) and the first drain terminal (106b). This modulation controls the flow of current between the source and drain terminals. The first transistor's operation can be characterized by its threshold volt- age, which is the gate voltage required to initiate current flow between the source and drain. The transistor's on-state current, off-state current, and switching speed are also crucial performance parameters. Different biasing conditions can be applied to the first transistor to achieve various operating modes, such as saturation, linear, and cut-off regions. These modes determine the relationship between the gate voltage, drain current, and drain-source voltage.

[0049] 2.1.1 Role of the First Source Terminal (106a)

[0050] The first source terminal (106a) acts as the source of charge carriers for the first transistor (106). It provides the electrons or holes that flow through the channel region when the transistor is turned on. The first source terminal is typically connected to a voltage source that maintains a constant potential. This ensures a stable supply of charge carriers for the transistor's operation. The material and properties of the first source terminal can influence the transistor's performance, such as its contact resistance and current-carrying capacity.

[0051] 2.1.2 Role of the First Drain Terminal (106b) The first drain terminal (106b) collects the charge carriers that flow through the channel region of the first transistor (106). It serves as the output terminal for the transistor. The voltage at the first drain terminal is typically higher than the voltage at the first source terminal when the transistor is on. This voltage difference creates an electric field that drives the charge carriers towards the drain. The first drain terminal's characteristics, such as its contact resistance and capacitance, can affect the transistor's switching speed and overall performance.

[0052] 2.1.3 Role of the First Gate Terminal (106c) The first gate terminal (106c) controls the conductivity of the channel region between the first source terminal (106a) and the first drain terminal (106b). By applying a voltage to the first gate terminal, an electric field is created that modulates the flow of charge carriers through the channel. The voltage applied to the first gate terminal determines whether the first transistor is on or off. When the gate voltage is above the threshold voltage, the transistor is on, and current flows between the source and drain. When the gate voltage is below the threshold voltage, the transistor is off, and minimal current flows. The first gate terminal's capacitance and geometry can influence the transistor's switching speed and power consumption.

[0053] 2.2 Functioning of the Second Transistor (107) The second transistor (107) operates similarly to the first transistor, acting as a voltage- controlled switch. The voltage applied to the second gate terminal (107c) controls the current flow between the second source terminal (107a) and the second drain terminal (107b). The second transistor's performance is also characterized by its threshold voltage, on-state current, off-state current, and switching speed. These parameters can be influenced by the material properties of the nanowire and the dimensions of the transistor.

[0054] The second transistor can also operate in different modes, such as saturation, linear, and cut-off regions, depending on the applied voltages. The interaction between the first and second transistors, along with the transition region, enables complex functionalities within the semiconductor structure. 2.2.1 Role of the Second Source Terminal (107a)

[0055] The second source terminal (107a) serves as the source of charge carriers for the second transistor (107). It provides the electrons or holes that flow through the channel region when the transistor is turned on. The second source terminal is typically connected to a voltage source or to the drain of the first transistor, depending on the circuit configura- tion. The material and properties of the second source terminal can influence the second transistor's performance, such as its contact resistance and current-carrying capacity. 2.2.2 Role of the Second Drain Terminal (107b)

[0056] The second drain terminal (107b) of the second transistor (107) serves as the collection point for charge carriers that have traversed the channel region of the transistor. It acts as the output terminal for the second transistor, delivering the modulated current to sub- sequent components or circuits.

[0057] The voltage potential at the second drain terminal (107b) is typically maintained at a higher level compared to the second source terminal (107a) when the transistor is in an active state. This voltage difference establishes an electric field that directs the flow of charge carriers, either electrons or holes, from the source to the drain. The Second drain terminal's (107b) electrical characteristics, such as its contact resistance and capacitance, play a significant role in determining the overall performance of the second transistor. A lower contact resistance minimizes voltage drops and power dissipation, while a smaller capacitance contributes to faster switching speeds and improved frequency response. In certain configurations, the second drain terminal (107b) may be directly connected to the second source terminal (107a) of an adjacent transistor, forming a series connection. This arrangement enables cascading of multiple transistors to implement complex logic functions or amplify signals.

[0058] The second drain terminal (107b) can also be connected to other circuit elements, such as resistors, capacitors, or interconnects, depending on the specific application. These connections determine how the output signal of the second transistor is processed and utilized within the larger circuit.

[0059] The physical placement and layout of the second drain terminal (107b) are critical considerations in the design of integrated circuits. Careful placement minimizes signal interference and optimizes circuit performance. The drain terminal's geometry and dimensions are also optimized to ensure efficient current flow and heat dissipation.

[0060] 2.2.3 Role of the Second Gate Terminal (107c)

[0061] The second gate terminal (107c) of the second transistor (107) plays a crucial role in modulating the conductivity of the channel region between the second source terminal (107a) and the Second drain terminal (107b). It acts as the control terminal for the second transistor, effectively functioning as a switch.

[0062] By applying a voltage to the Second gate terminal (107c), an electric field is generated in the channel region. This electric field influences the concentration of charge carriers, either electrons or holes, in the channel, thereby controlling the flow of current between the source and drain terminals.

[0063] The voltage applied to the second gate terminal (107c) determines the operational state of the second transistor. When the gate voltage exceeds a certain threshold voltage, the transistor turns on, allowing current to flow between the source and drain. Conversely, when the gate voltage falls below the threshold voltage, the transistor turns off, effectively blocking current flow.

[0064] The Second gate terminal's (107c) capacitance and geometry significantly impact the transistor's performance characteristics. A smaller gate capacitance results in faster switching speeds and reduced power consumption. The gate terminal's geometry is carefully designed to ensure uniform control over the channel region and minimize parasitic effects.

[0065] In some configurations, the second gate terminal (107c) may be connected to the gate terminals of other transistors, enabling coordinated switching and complex logic operations. This interconnection allows for the creation of various circuit topologies, such as logic gates, amplifiers, and memory cells.

[0066] The second gate terminal (107c) can also be connected to external control signals or voltage sources, providing a means to dynamically adjust the transistor's behavior. This external control enables the implementation of adaptive circuits and systems that can respond to changing conditions or inputs.

[0067] 2.3 Transition (118) and its Role in the Operation of Transistors

[0068] The transition (118) between the first semiconductor material (117) and the second semiconductor material (119) plays a crucial role in the operation of the transistors. This transi- tion region can create a potential barrier or a change in carrier concentration, which influences the current flow through the transistors. The transition region can be engineered to optimize the performance of the transistors. For example, the transition can be designed to reduce leakage current or improve switching speed. The location and characteristics of the transition region can also affect the threshold voltage and other performance param- eters of the transistors. By carefully controlling the transition, the overall functionality of the semiconductor structure can be enhanced. 3 Description of Examples of the Disclosure

[0069] This section provides specific examples of the semiconductor structure, illustrating its various configurations and material compositions. These examples demonstrate the practical application of the invention and showcase its versatility in different scenarios. Each exam- pie highlights specific features and functionalities of the semiconductor structure, providing a deeper understanding of its operation and potential benefits. The examples also serve as a guide for those skilled in the art to implement and adapt the invention to their specific needs.

[0070] 3.1 Example of a Semiconductor Structure with Specific Material Composition This example details a semiconductor structure with a specific material composition, highlighting the use of the first semiconductor material (117) and the Second Semiconductor Material (119). The choice of materials significantly impacts the device's performance characteristics, such as electron mobility, bandgap, and thermal conductivity. This example demonstrates how different material combinations can be utilized to optimize the semiconductor structure for specific applications. The example may include details on the fabrication process, material properties, and the resulting device performance.

[0071] 3.1.1 Use of First Semiconductor Material (117)

[0072] The first semiconductor material (117) forms a crucial part of the semiconductor structure, particularly in the lower part (104) and the source section (109) of the First Nanowire (103). The specific properties of the First Semiconductor Material (117), such as its electron mobility and bandgap, influence the performance of the First Transistor (106). This material may be chosen for its compatibility with other materials in the structure, its ease of fabrication, or its specific electrical characteristics. The use of the first semiconductor material (117) contributes to the overall functionality and efficiency of the semiconductor structure.

[0073] 3.1.2 Use of Second Semiconductor Material (119)

[0074] The second semiconductor material (119) is employed in the upper part (105) and the drain section (108) of the First Nanowire (103). This material may have different properties compared to the First Semiconductor Material (117), creating a transition region that influences the device's behavior. The second semiconductor material (119) may be selected for its specific electrical properties, its ability to form a heterojunction with the First Semiconductor Material (117), or its thermal characteristics. The use of the second semi- conductor material (119) contributes to the unique functionalities of the semiconductor structure.

[0075] 3.2 Example of a Semiconductor Structure with Specific Nanowire Configuration

[0076] This example focuses on the configuration of nanowires within the semiconductor struc- ture. It explores different arrangements of nanowires, such as single nanowire and multiple nanowire configurations, and their impact on device functionality. The example may include details on the nanowire dimensions, spacing, and orientation, as well as the resulting electrical and thermal properties of the structure. This example demonstrates how the nanowire configuration can be tailored to achieve specific performance goals. 3.2.1 Single Nanowire Configuration

[0077] In a single nanowire configuration, the semiconductor structure utilizes a single first nanowire (103) to form the first transistor (106) and the Second Transistor (107). This configuration offers a compact design and can be advantageous for applications where space is limited. The single nanowire configuration may also simplify the fabrication pro- cess and reduce manufacturing costs. This example demonstrates the basic operation of the semiconductor structure using a single nanowire as the foundation for the transistors.

[0078] 3.2.2 Multiple Nanowire Configuration

[0079] A multiple nanowire configuration employs multiple first nanowire (103) arranged in parallel or other configurations. This arrangement can increase the current-carrying capacity of the semiconductor structure and improve its overall performance. The multiple nanowire configuration may also offer redundancy and fault tolerance, as the failure of a single nanowire may not significantly impact the overall device operation. This example demonstrates how multiple nanowires can be integrated into the semiconductor structure to enhance its capabilities.

[0080] 4 Potential Applications

[0081] The semiconductor structure has potential applications in various fields, capitalizing on its unique features such as stacked transistors within nanowires, enabling high-density integration and complex functionality within a small footprint.

[0082] Its adaptable design allows for tailoring to specific application requirements by selecting appropriate materials and configurations. This adaptability extends to diverse areas like microelectronics, nanotechnology, and sensor development, where the structure's compact size and functional versatility are highly advantageous.

[0083] The semiconductor structure addresses the increasing demand for miniaturization and enhanced performance in electronic devices. By integrating multiple transistors within individual nanowires, it overcomes limitations of conventional planar transistors, offering higher packing density and potentially lower power consumption.

[0084] This innovative approach improves upon prior art by enabling more complex circuit designs within limited space, paving the way for smaller, more powerful, and energy-efficient electronic devices. 4.1 Application in Microelectronics

[0085] The semiconductor structure's compact size and integrated functionality make it highly suitable for microelectronics applications. Its stacked transistor design within nanowires allows for increased component density on microchips, leading to smaller and more powerful devices. This structure offers significant advantages in addressing the limitations of traditional planar transistors, particularly in terms of scaling and performance. The ability to integrate multiple transistors within a single nanowire enables higher packing density and potentially lower power consumption, crucial for advancements in microelectronics.

[0086] The semiconductor structure's versatility extends to various microelectronic applications, including logic circuits, memory devices, and integrated sensors. Its unique architecture allows for complex circuit designs within a smaller footprint, pushing the boundaries of microchip miniaturization and performance.

[0087] 4.1.1 Use in Microprocessors

[0088] The semiconductor structure's high transistor density and potential for low power con- sumption make it well-suited for use in microprocessors. Its stacked transistor design within nanowires allows for integrating a greater number of transistors within the same chip area, leading to increased processing power and reduced energy consumption.

[0089] This structure addresses the challenges of Moore's Law, which predicts the doubling of transistors on a chip every two years. As traditional planar transistors approach their scaling limits, the semiconductor structure offers a viable path towards continued miniaturization and performance improvement in microprocessors. By enabling higher transistor density and lower power consumption, the semiconductor structure can contribute to the development of more powerful and energy-efficient microprocessors, essential for advancements in computing technology.

[0090] 4.2 Application in Nanotechnology The semiconductor structure's nanoscale dimensions and precise material composition make it a promising candidate for nanotechnology applications. Its ability to control and manipulate electrical properties at the nanoscale level opens up new possibilities for creating novel devices and materials.

[0091] The structure's unique architecture, with stacked transistors within nanowires, enables the development of highly sensitive nanoscale sensors, actuators, and other functional components. Its precise material composition and controlled transitions between different semiconductor materials allow for tailoring its properties to specific nanotechnology applications.

[0092] The semiconductor structure's potential in nanotechnology extends beyond individual devices. It can serve as a building block for more complex nanoscale systems and architectures, enabling the creation of new materials and devices with enhanced functionalities.

[0093] 4.2.1 Use in Nanoscale Devices

[0094] The semiconductor structure's nanoscale dimensions and precise material control make it ideal for integration into nanoscale devices. Its ability to operate at the nanoscale level opens up possibilities for creating highly sensitive sensors, actuators, and other functional components with enhanced performance.

[0095] The structure's unique architecture, with stacked transistors within nanowires, allows for precise control over electrical properties at the nanoscale, enabling the development of novel device functionalities. Its compact size and adaptable design make it suitable for integration into various nanoscale platforms and systems.

[0096] The semiconductor structure's potential in nanoscale devices extends to diverse applications, including biomedical sensors, nanoelectronics, and energy harvesting. Its ability to operate efficiently at the nanoscale level paves the way for advancements in various technological fields. The terminology used herein is for the purpose of describing particular aspects only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including" when used herein specify the presence of stated features, integers, actions, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, actions, steps, operations, elements, components, and / or groups thereof.

[0097] It will be understood that, although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element without departing from the scope of the present disclosure.

[0098] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe a relationship of one element to another element as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0099] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0100] It is to be understood that the present disclosure is not limited to the aspects described above and illustrated in the drawings; rather, the skilled person will recognize that many changes and modifications may be made within the scope of the present disclosure and appended claims. In the drawings and specification, there have been disclosed aspects for purposes of illustration only and not for purposes of limitation, the scope of the disclosure being set forth in the following claims.

Claims

Claims1. A semiconductor structure (100) forming a plurality of transistors, the semiconductor structure comprising a first source layer (101) on a substrate (102), a first nanowire (103) being a vertical nanowire and extending from the first source layer, whereby a lower part (104) of the first nanowire is in contact with the first source layer, wherein the first nanowire extends longitudinally with a length (L) from the lower part to an upper part (105) of the first nanowire, wherein the first nanowire comprises a first transistor (106) and a second transistor (107) along the length (L), wherein the first transistor comprises a first source terminal (106a) comprising the first source layer, a first drain terminal (106b) at a drain section (108) of the first nanowire, a first gate terminal (106c) connecting to the first nanowire between the first source terminal and the first drain terminal, wherein the drain section connects to an adjacent source section (109) of the first nanowire, wherein the second transistor comprises a second source terminal (107a) comprising the source section, a second drain terminal (107b) connected to the upper part, a second gate terminal (107c) connecting to the first nanowire between the second source terminal and the second drain terminal, and wherein the first nanowire comprises a first semiconductor material (117) and a second semiconductor material (119), wherein the first and second transistor comprises a respective transition (118) from the first semiconductor material to the second semiconductor material.

2. Semiconductor structure according to claim ?, wherein the first gate terminal and the second gate terminal are arranged to contact the first nanowire at the respective transition.

3. Semiconductor structure according to claim ? or ?, wherein the first drain terminal connects to the second source terminal at an interface between the first semiconductor material and the second semiconductor material.

4. Semiconductor structure according to any of claims ? - 4, wherein the lower part andthe source section comprises the first semiconductor material and the upper part and the drain section comprises the second semiconductor material.

5. Semiconductor structure according to any of claims 1 - 5, wherein the nanowire comprises a stack of devices (106, 107, 113, 114) along the length (L) comprising said first and second transistors and at least a further gate terminal (112, 113)6. Semiconductor structure according to any of claims 1 - 6, wherein the first gate terminal and / or the second gate terminal connects to a second nanowire (103’) or a plurality of nanowires extending from the first source layer, the second nanowire comprising a first transistor (106) and a second transistor (107), and / or the plurality of nanowires comprising a respective first transistor (106) and a second transistor (107).

7. Semiconductor structure according to any of claims 1 - 7, wherein the first gate terminal connects to a plurality of said nanowires (103) along a first direction (110) and the second gate terminal connects to a plurality of said nanowires (103) along a second direction (111), the first direction being angled relative the second direction.

8. Semiconductor structure according to any of claims 1 - 8, wherein the first gate terminal and / or the second gate terminal comprises a first plurality longitudinal extensions (1061c, 1062c, 1063c; 1071c, 1072c, 1073c) connecting to a plurality of said nanowires (103) and being essentially parallel to each other, wherein the first plurality longitudinal extensions are arranged in an interleaving pat- tern with a second plurality longitudinal extensions (1061c, 1062c, 1063c; 1071c, 1072c, 1073c) of an adjacent first gate terminal (106’c) and / or second gate terminal (107’c) connected to a plurality of said nanowires (103).

9. Semiconductor structure according to claims 8, wherein a first conductor (115) connects the first gate terminal (106c) to an adjacent second gate terminal (107’c) con- nected to a plurality of said nanowires (103), and wherein a second conductor (116) connects the second gate terminal (107c) to an adjacent first gate terminal (106’c) connected to a plurality of said nanowires (103).

Images