High safe operating area and high breakdown voltage mosfet

Abstract

Hybrid MOSFET designs in which low ON resistance RON and high transconductance Gm values can be achieved while improving the safe operating area (SOA) of the device. Embodiments accomplish these design goals by adding a sub-gate drift region substantially only under the conductive layer of the gate structure, thereby allowing the drain to be positioned in closer proximity to the source and thus reducing RON and increasing Gm. The sub-gate drift region also reduces the peak drain-side E-field by dividing the E-field into two edges. This aspect helps push out the onset of breakdown mechanisms such as band-to-band tunneling and / or impact ionizations. Another aspect is a stepped gate oxide that is thicker in the drift region, which reduces parasitic CGD and improves the breakdown voltage, BVDSS, thus enhancing device reliability. Hybrid MOSFETs are particularly useful in cascode applications such as for envelope tracking and average power tracking.

Description

Attorney Docket: P3115-PCTHIGH SAFE OPERATING AREA, HIGH BREAKDOWN VOLTAGECROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present application claims priority to U.S. Provisional Application No. 63 / 735,224, filed December 17, 2024, entitled “SAFE OPERATING AREA MOSFET”, and U.S. Provisional Application No. 63 / 809,942, filed May 21, 2025, entitled “HIGH SAFE OPERATING AREA, HIGH BREAKDOWN VOLTAGE”, the contents of both of which are incorporated herein by reference in their entirety.TECHNICAL FIELD

[0002] This invention relates to electronic integrated circuits, and more particularly to electronic integrated circuits that include metal-oxide-semiconductor field-effect transistors (MOSFETs).BACKGROUND

[0003] Virtually all modern electronic products - including laptop computers, mobile telephones, and electric cars - utilize MOSFET-based integrated circuits (ICs). A number of architectural variations exist for MOSFETs. The most common type of MOSFETs are N-type MOSFETs (NFETs), which have N+ doped source and drain regions abutting opposite sides of a channel region, which, for an enhancement-mode device, may be doped with P-type material.

[0004] FIG. l is a stylized cross-sectional view of a silicon-on-insulator (SOI) IC structure for a prior art MOSFET 100. The SOI structure includes a substrate 102, an insulating buried-oxide (BOX) layer 104, and an active layer 106 (note that the dimensions for the elements of the SOI IC structure are not to scale; some dimensions have been exaggerated for clarity or emphasis). The substrate 102 is typically a semiconductor material such as silicon (Si), but may be other materials such as glass or sapphire. The BOX layer 104 is a dielectric and is often SiO2 formed as a “top” surface of the substrate 102; for some substrates (e.g., glass or sapphire), a BOX layer 104 optionally may be omitted. Some embodiments may include a trap-rich Si layer (not shown)Attorney Docket: P3115-PCT between the BOX layer 104 and the substrate 102. A trap-rich Si layer mitigates parasitic surface conduction and improves device performance at high frequencies.

[0005] The active layer 106 may include some combination of implants and / or layers that include dopants, dielectrics, polysilicon, conductors, passivation, and other materials to form active and / or passive electronic components and / or mechanical structures. For example, the MOSFET 100 of FIG. 1 has an active layer 106 that includes an N+ source 110, a P-type body region or “P-well” 112 in which an electrically conductive channel can be formed, and an N+ drain 114, all bounded by isolation structures 118, such as a shallow trench isolation (STI) structure.

[0006] The active layer 106 may include a halo region 122 to increase a sub-surface electric field to reduce so-called punch-through, or short channel, conduction between the source 110 and the drain 114, thus increasing the channel breakdown voltage. For an N-type MOSFET, a halo region is typically doped with P or P+ material. Some embodiments may include an N-type lightly- doped drain (LDD) region 124 (“LDD” being somewhat of a misnomer, since an LDD region may be included on the source-side of a MOSFET). An LDD region 124 extends the source 110 underneath a gate structure 130 and modulates the threshold voltage VTH, transconductance Gm, and leakage current of the device.

[0007] The gate structure 130 is formed in contact with a surface of the active layer 106, positioned with respect to the P-well 112 so as to be able to control current flow through the P- well 112 between the source 110 and the drain 114. The gate structure 130 includes a conductive layer 132, such as N+ doped polysilicon, in contact with an insulating gate oxide (GOX) layer 134, the thickness of which may be varied for different applications. In the illustrated example, the gate structure 130 is surrounded by insulating spacers 136. In some applications, the insulating spacers 136 may be formed from multiple lateral dielectric layers, as illustrated.

[0008] A conductive source contact 142, a conductive gate contact 144, and a conductive drain contact 146, which may be silicides, are respectively formed in electrical contact with the source 110, the conductive layer 132 of the gate structure 130, and the drain 114. Stylized electrical terminals S, G, and D are shown coupled to the corresponding source contact 142, gate contact 144, and drain contact 146.Attorney Docket: P3115-PCT

[0009] The gate structure 130, the BOX layer 104, and the active layer 106 (which may include multiple FETs) may be collectively referred to as a “device region” or “substructure” for convenience (noting that other structures or regions may intrude into the substructure in particular IC designs). A superstructure (not shown) of various elements, regions, and structures may be fabricated on or above the substructure in order to implement particular functionality. The superstructure may include, for example, conductive interconnections from the illustrated MOSFET 100 to other components (including other FETs on the same IC die) and / or external contacts, passivation layers, and protective coatings.

[0010] One drawback of a typical thick-oxide MOSFET device, particularly in radio frequency(RF) applications such low-noise amplifiers and power amplifiers, is that it has a relatively small safe operating area (SOA). The SOA of a MOSFET is defined by a set of voltage, current, and temperature values within which the device operates reliably.

[0011] Several approaches have been used to increase the SOA of a MOSFET. For example, N-type Extended Drain MOS (NEDMOS) FETs fabricated using silicon-on-insulator (SOI) processes and Laterally-Diffused MOS (LDMOS) FETs fabricated using bulk silicon are common transistor devices capable of handling relatively high drain voltages, thus increasing the SOA.

[0012] FIG. 2 is a stylized cross-sectional view of an SOI IC structure for a prior art NEDMOS FET 200. Similar in many aspects to the MOSFET 100 of FIG. 1, several differences include (1) the addition of an N- drift region 116 disposed between the P-well 112 and the N+ drain 114 and laterally offset from the overlying drain-side edge of the conductive layer 132 of the gate structure 130, and (2) the omission of a drain-side halo region 122 and LDD region 124. In addition, part of the gate structure 130 and the N- drift region 116 may be coated with a dielectric 138 (e.g., SiO , SijN4, etc.), which in turn may be overlaid with a salicide block (SAB) layer 140, such as silicon nitride (SiN), to prevent subsequent formation of self-aligned silicides (also known as “salicides”) on those structures / regions.

[0013] One of the purposes of the N- drift region 116 is to reduce the electrical field (“E- field”) that would otherwise occur at and near the junction of the P-well 112 and an abutting drain when a sufficiently high drain voltage VDD is applied to the device. A high E-field generates “hot” ( / .t?., energetic) electrons, which may cause impact ionization which can result in avalancheAttorney Docket: P3115-PCT breakdown. In addition, hot electrons with higher energy than the GOX layer 134 can be trapped at the junction interface, which causes increased resistance in the channel of the device, thus reducing the device drain-to-source current IDS. The N- drift region 116, by having a lower doping concentration than the drain 114, reduces the electric field and impact ionization on the drain side of the gate structure 130. This increases the gate dielectric breakdown voltage, which improves the reliability of an NEDMOS FET.

[0014] One drawback of a NEDMOS FET, particularly in radio frequency (RF) applications, is that the added length of the N- drift region 116 increases the ON resistance RON and reduces the transconductance Gm of the device, both of which degrade RF performance.

[0015] Accordingly, a MOSFET design is needed in which low RON and high Gm values can be achieved while improving the SOA of the device. The present invention addresses this need.Attorney Docket: P3115-PCTSUMMARY

[0016] The present invention encompasses novel MOSFET designs in which low ON resistance RON and high transconductance Gm values can be achieved while improving the safe operating area (SOA) of the device. Embodiments accomplish these design goals by adding a subgate drift region substantially only under the conductive layer of the gate structure, thereby allowing the drain to be positioned in closer proximity to the source and thus reducing RON and increasing Gm. The sub-gate drift region with appropriate doping (e.g., N-type doping) also reduces the peak drain-side E-field by dividing the E-field into two edges: (1) a gate-to-drain edge and (2) a channel-to-drift region edge. This aspect helps push out the onset of breakdown mechanisms such as band-to-band tunneling and / or impact ionizations.

[0017] The breakdown voltage and SOA of a MOSFET device having a sub-gate drift region in accordance with the present invention is (1) less than a NEDMOS device having the same gate length LG but with a laterally-offset drift region, but (2) greater than a conventional NFET with the same conductive layer length but without any drift region. Accordingly, MOSFETs in accordance with the present invention may be termed “hybrid MOSFETs or “HB MOSFETs”. A Hybrid MOSFET includes a body region, a gate structure positioned with respect to the body region so as to be able to control current flow through the body region, a source region positioned proximate to a first side of the body region, a drain region positioned proximate to a second side of the body region, and a sub-gate drift region.

[0018] Another aspect of the invention is the use in some embodiments of a stepped gate oxide (GOX) that is thicker in the drift region, which provides a considerable reduction in parasitic gate- to-drain capacitance, CGD, a considerable improvement to the gate field plate effect, and significant improvement in the breakdown voltage, BVDSS, of the MOSFET device, thus enhancing device reliability.

[0019] The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention should be apparent from the description and drawings, and from the claims.Attorney Docket: P3115-PCTDESCRIPTION OF THE DRAWINGS

[0020] FIG. l is a stylized cross-sectional view of a silicon-on-insulator (SOI) IC structure for a prior art MOSFET.

[0021] FIG. 2 is a stylized cross-sectional view of an SOI IC structure for a prior art NEDMOS FET.

[0022] FIG. 3 A is a stylized cross-sectional view of an SOI IC structure for a first embodiment of a hybrid MOSFET in accordance with the present invention.

[0023] FIG. 3B is a stylized, simplified, and enlarged cross-sectional view of the SOI IC structure for the hybrid MOSFET of FIG. 3 A.

[0024] FIG. 4 is a stylized cross-sectional view of an SOI IC structure for a second embodiment of a hybrid MOSFET in accordance with the present invention.

[0025] FIGS. 5A-5C are graphs showing various characteristics of an N-type HB MOSFET and a conventional NFET as a function of X-dimension (“horizontal”) distance from the midpoint of the length of the conductive layer.

[0026] FIGS. 6A-6C are top plan views of three example configurations of a body-tied-to- source (BTS) structure for an HB MOSFET of the types described in this disclosure.

[0027] FIGS. 7A-7F show cross-sectional views illustrating selected stages of one method of fabricating the HB MOSFET structure shown in FIG. 3A.

[0028] FIG. 7G shows a cross-sectional view illustrating a variant of the HB MOSFET structure shown in FIG. 3 A.

[0029] FIG. 8 is a process flowchart showing another representation of an example fabrication process for a sub-gate drift region HB MOSFET that is suitable for some contemporary IC front- end-of-line (FEOL) foundries.

[0030] FIG. 9 is a graph of transducer power gain Gt as a function of power out POUT at different VDD levels for an example HB MOSFET device lacking a stepped GOX layer.Attorney Docket: P3115-PCT

[0031] FIG. 10 is a graph of CGD versus VDS for an example HB MOSFET device lacking a stepped GOX layer.

[0032] FIG. 11A is a graph showing electrostatic potential as a function of X-dimension (“horizontal”) distance from the midpoint of the length of the conductive layer of an N-type HB MOSFET.

[0033] FIG. 1 IB is a graph showing electric field as a function of X-dimension (“horizontal”) distance from the midpoint of the length of the conductive layer of an N-type HB MOSFET.

[0034] FIG. 12A is a graph of CGD versus VDS for an HB MOSFET with no stepped GOX compared to several versions of HB MOSFETs with a stepped GOX.

[0035] FIG. 12B is a graph of drain current ID versus VDS in the OFF state for an HB MOSFET with no stepped GOX compared to one version of an HB MOSFET with a stepped GOX having a step thickness of 150A.

[0036] FIG. 12C is a graph of drain current ID versus VDS in the ON state for an HB MOSFET with no stepped GOX compared to one version of an HB MOSFET with a stepped GOX having a step thickness of 150A.

[0037] FIG. 12D is a graph of ID versus VGS for an HB MOSFET with no stepped GOX compared to one version of an HB MOSFET with a stepped GOX having a step thickness of 150A.

[0038] FIGS. 13A-13D are graphs showing the effects of different stepped-GOX thicknesses on various parameters for modeled HB MOSFETs.

[0039] FIG. 14 is a top plan view of a substrate that may be, for example, a printed circuit board or chip module substrate (e.g., a thin-film tile).

[0040] Like reference numbers and designations in the various drawings indicate like elements unless the context requires otherwise.Attorney Docket: P3115-PCTDETAILED DESCRIPTION

[0041] The present invention encompasses novel MOSFET designs in which low ON resistance RON and high transconductance Gm values can be achieved while improving the safe operating area (SOA) of the device. Embodiments accomplish these design goals by adding a subgate drift region substantially only under the conductive layer of the gate structure, thereby allowing the drain to be positioned in closer proximity to the source and thus reducing RON and increasing Gm. The sub-gate drift region with appropriate doping (e.g., N-type doping) also reduces the peak drain-side E-field by dividing the E-field into two edges: (1) a gate-to-drain edge and (2) a channel-to-drift region edge. This aspect helps push out the onset of breakdown mechanisms such as band-to-band tunneling and / or impact ionizations.

[0042] Another aspect of the invention is the use in some embodiments of a stepped gate oxide (GOX) that is thicker in the drift region, which provides a considerable reduction in parasitic gate- to-drain capacitance, CGD, a considerable improvement to the gate field plate effect, and significant improvement in the breakdown voltage, BVDSS, of the MOSFET device, thus enhancing device reliability.

[0043] The breakdown voltage and SOA of a MOSFET device having a sub-gate drift region in accordance with the present invention is (1) less than a NEDMOS device 200 having the same gate length LG but with a laterally-offset drift region, but (2) greater than a conventional NFET 100 with the same conductive layer length but without any drift region. Accordingly, MOSFETs in accordance with the present invention may be termed “hybrid MOSFETs or “HB MOSFETs”.

[0044] FIG. 3 A is a stylized cross-sectional view of an SOI IC structure for a first embodiment of a hybrid MOSFET 300 in accordance with the present invention. The cross-sectional structure is similar in many aspects to the conventional MOSFET 100 of FIG. 1 and the conventional NEDMOS FET 200 of FIG. 2, and corresponding elements are labeled the same. However, significant and novel differences exist. In particular, a sub-gate drift region 302 has been fabricated substantially only under the conductive layer 132 (e.g., polysilicon) of the gate structure 130, thereby allowing the drain 114 to be positioned in closer proximity to the source, thus reducing RON and increasing Gm. In addition, optionally, a drain-side halo region 122 and / or LDD region 124 may be included in the design.Attorney Docket: P3115-PCT

[0045] FIG. 3B is a stylized, simplified, and enlarged cross-sectional view of the SOI IC structure for the hybrid MOSFET 300 of FIG. 3 A (some elements and reference numbers have been omitted to reduce clutter). Shown in FIG. 3B are the two edges along which the peak drainside E-field is divided: (1) a gate-to-drain edge (inside the oval labeled “GDE”) and (2) a channel- to-drift region edge (inside the oval labeled “CDE”). Also illustrated in FIG. 3B is a dashed line 304 that indicates that the sub-gate drift region 302 may extend slightly beyond the drain-side edge of the gate structure 130, owing primarily to mask misalignment during manufacturing and dopant diffusion, but typically such drain-side intrusion is no more than about 0.25pm, and is preferably controlled to be no more than about 0.1pm. Any extension of the sub-gate drift region 302 beyond the drain-side edge of the gate structure 130 may need to be covered by a salicide block layer.

[0046] FIG. 3B shows that the combined gate length LG of the HB MOSFET and the length LDR of the sub-gate drift region 302 is approximately the length LCL of the conductive layer 132. In various embodiments, when LCL is about 0.6pm, the sub-gate drift region 302 may have a length LDR greater than about 0.1pm, and typically in the range of about 0.1pm to about 0.3pm, with LG accounting for the difference.

[0047] FIG. 4 is a stylized cross-sectional view of an SOI IC structure for a second embodiment of a hybrid MOSFET 400 in accordance with the present invention. The cross- sectional structure is similar in most aspects to the HB MOSFET 300 of FIG. 3, and corresponding elements are labeled the same. However, the GOX layer 134s has been fabricated with a stepped structure which is thinner on the source-side of the gate structure 130 and thicker on the drain-side of the gate structure 130. A stepped GOX layer 134s can reduce the device gate capacitance CGD, which provides better RF performance. Note that the length of the thicker drain-side portion of the GOX layer 134s need not coincide with the length LDR of the sub-gate drift region 302. Further details and benefits of a stepped GOX layer 134s are described below.

[0048] By using a sub-gate drift region 302 with appropriate doping, the sharp potential drop at the drain 114 can be divided into two smaller drops resulting in marked reduction in high electric field regions and impact ionization rates. For example, FIGS. 5A-5C are graphs showing various characteristics of an N-type HB MOSFET and a conventional NFET as a function of X-dimension (“horizontal”) distance from the midpoint of the length LCL of the conductive layer 132. The HBAttorney Docket: P3115-PCTMOSFET in this example has an LG of 0.3pm and an LDR of 0.3pm, while the conventional NFET has an LG of 0.6pm (LDR is zero since the sub-gate drift region 302 is absent).

[0049] FIG. 5A shows electric field as a function of horizontal distance. Graph line 502a corresponds to the HB MOSFET while graph line 504a corresponds to the conventional NFET. As the graph indicates, the average and peak electric field for the HB MOSFET is less than for the conventional NFET.

[0050] FIG. 5B shows electrostatic potential as a function of horizontal distance. Graph line 502b corresponds to the HB MOSFET while graph line 504b corresponds to the conventional NFET. As the graph indicates, electrostatic potential drops are divided into smaller steps for the HB MOSFET, causing the peak electric field to be lower for the HB MOSFET.

[0051] FIG. 5C shows impact ionization rate as a function of horizontal distance. Graph lines 502c correspond to the HB MOSFET while graph line 504c corresponds to the conventional NFET. As the graph indicates, the rate of impact ionization is orders of magnitude less for the HB MOSFET than for the conventional NFET (keeping in mind that the Y-axis of the graph is a logarithmic scale).

[0052] In N-type HB MOSFET embodiments that may be subject to the floating body effect, such as SOI HB MOSFETs, it is very useful to include a P+ body tie formed within or near the N+ source 110 and in direct contact with the body region (P-well 112 in this example) to significantly improve the SOA and RF performance of the device. A body tie serves as a pathway for collecting holes that may be formed within the P-well 112 near the drain-side of the gate structure 130 to avoid degrading RF performance. In some embodiments, the body tie may be tied (electrically coupled) to the source 110, and thus the device will have equal potential between the body region 112 and the source 110. In some embodiments, the body tie may be separately biased in order to manipulate the body region potential independently of the source.

[0053] The use of a body tie is of a special importance - a body tie eliminates or substantially mitigates the floating body effect; mitigates turn-on of the parasitic bipolar devices inherent in a MOSFET; improves the breakdown voltage of the FET; improves electro-static discharge (ESD) protection for the FET; improves device and circuitry performance and capability, and in particularAttorney Docket: P3115-PCT improves circuit linearity, reliability, and power consumption in analog and digital circuitry, especially for such devices as radio frequency (RF) and mmWave switches, low-noise amplifiers (LNAs), and power amplifiers (PAs).

[0054] Accordingly, a body-tied-to-source configuration may be used with HB MOSFETs, particularly for RF applications. FIGS. 6A-6C are top plan views of three example configurations of a body-tied-to-source (BTS) structure for an HB MOSFET. Most of the component elements in the illustrated example have the same reference numbers as shown in FIG. 3A. Electrical contacts to the various regions are omitted to avoid clutter.

[0055] FIG. 6A includes a centrally-located P+ body contact region 602 fabricated to electrically connect to the body ( / .e., the P-well 112 in FIGS. 3 A and 4) of the device to provide a fourth terminal for the HB MOSFET.

[0056] FIG. 6B includes two end-positioned BTS structures comprising P+ body contact regions 602. The associated electrical contacts (not shown) may be coupled to the source 110 through a device superstructure (not shown). Placing the BTS structures parallel to the X- dimension edges of the device reduces current leakage by increasing the VTH at those edges. Having more than one BTS structure provides more efficient hole collection compared to the single central BTS structure shown in FIG. 6A.

[0057] The number of BTS structures may be increased in some embodiments. For example, FIG. 6C includes four P+ body contact regions 602, with two of the P+ body contact regions 602 being end-positioned as in FIG. 6B and two of the P+ body contact regions 602 being positioned at intermediate locations. As should be clear, embodiments of the inventive HB MOSFET may have any desired number of BTS structures that fit within the confines of the device layout.

[0058] The sub-gate drift region of an HB MOSFET provides low ON resistance RON and high transconductance Gm values while maintaining good breakdown voltage BVDSS and improved SOA characteristics. Accordingly, such devices are particularly useful in cascode applications such as for envelope tracking and average power tracking at relatively high voltages (e. , ranging from the low 3 V range to the high 5V range). Another advantage of the inventive IC architecture is that the sub-gate drift region virtually eliminates dynamic trapping of carriers associated with anAttorney Docket: P3115-PCT external drift region of traditional EDMOS designs. Further, the sub-gate drift region length can be optimized to improve hot carrier injection related effects by lowering the drain-side peak electric field.

[0059] While the disclosed embodiments show enhancement mode N-type HB MOSFETs, the inventive sub-gate drift region architecture may be applied to enhancement mode P-type HB MOSFETs (with P-type drift doping), depletion mode N-type HB MOSFETs, and depletion mode P-type HB MOSFETs. A number of different processes may be used to fabricate the improved HB MOSFET devices, including use of (1) SOI substrates (with or without a trap rich layer), bulk Si substrates, high-resistivity silicon substrates, or silicon-on-sapphire (SOS) substrates, (2) complex gate structures, including stepped gates and replacement metal gates (RMGs), and / or (3) engineered semiconductor material (e.g., SiGe alloys and layered mixtures).

[0060] It should be appreciated that a number of features described in this disclosure may be “mixed and matched” to create further variations without departing from the scope of the invention. For example, HB MOSFETs may be combined on a single IC with MOSFETs having conventional designs, and may be used in processes such as single-layer transfers and double-layer transfers in order to gain access to the backside of an IC for further processing and / or to form 3-D stackings of ICs. As yet another example, an N-type HB MOSFET may be combined with a P- type HB MOSFET to provide an improved hybrid complementary MOS (CMOS) device pair. Accordingly, the invention is not limited to the specific examples described and illustrated in this disclosure.

[0061] A number of different processes may be used to fabricate HB MOSFETs. For example, FIGS. 7A-7F show cross-sectional views illustrating selected stages of one method of fabricating the HB MOSFET structure shown in FIG. 3 A.

[0062] FIG. 7A shows a portion of a semiconductor active layer 106 formed on a BOX layer 104, which is in turn formed on top of a substrate 102. The active layer 106 may be masked and implanted (patterned) to form a P-type body region or well 112. Additionally, isolation structures 118 have been formed.Attorney Docket: P3115-PCT

[0063] If needed, the active layer 106 may be thinned to a suitable thickness, such as by chemical-mechanical polishing (CMP). For example, commercially available SOI wafers may have an active layer thickness of about 750A. It may be useful for some applications, particularly for RF ICs, to thin the active layer 106, for example, to about 500A.

[0064] FIG. 7B shows that an N- drift region 302 has been formed by patterning the active layer 106 and implanting a suitable N- dopant (e.g., arsenic), such as by ion implantation. In practice, the initial N- drift region 302 may be longer (in the X dimension) than the ultimate N- drift region 302, since doping the N+ drain at a later stage will dominate any N- doping in the drain region. In an alternative embodiment, the N- drift region 302 is formed after formation of the gate structure 130 by implantation of a dopant through the gate structure 130 or by highly tilted dopant implantation underneath the gate structure 130 from the drain-side of the gate structure 130. A portion of the conductive layer 132 may be protected by masking material (e.g., SiaNA during such implantation. This alternative approach assures self-alignment of the gate structure 130 with respect to the sub-gate drift region 302. In general, use of a dopant with a low diffusion characteristic is beneficial for obtaining desired values of LG and LDR.

[0065] FIG. 7C-1 shows a non-stepped gate structure 130 formed in contact with a surface of the active layer 106. The gate structure 130 includes a conductive layer 132 (e.g., poly silicon) in contact with an insulating gate oxide (GOX) layer 134, and surrounding insulating spacers 136. FIG. 7C-2 shows a first alternative gate structure 130 formed in contact with a surface of the active layer 106. The first alternative gate structure 130 includes a conductive layer 132 in contact with a drain-side single-stepped GOX layer 134s having a thickness Ts, and surrounding insulating spacers 136. FIG. 7C-3 shows a second alternative gate structure 130 formed in contact with a surface of the active layer 106. The second alternative gate structure 130 includes a conductive layer 132 in contact with a drain-side double-stepped GOX layer 134s' having a first step thickness Tsi and a second step thickness Ts2, and surrounding insulating spacers 136. As should be clear, a stepped GOX layer may have more than two steps, with the total thickness of the drain-side stepped GOX layer equaling the sum of the thicknesses of all of the steps.

[0066] The gate structure 130 in all three examples illustrated in FIG. 7C may be formed by conventional MOSFET fabrication processes such as thermal oxidation, epitaxial deposition, ionAttorney Docket: P3115-PCT implantation, photolithographic masking and etching, etc. In particular, the stepped insulating GOX layers 134s, 134s' may be fabricated using additive or subtractive process steps. For example, an additive process may include forming a thin layer of GOX over the active layer 106, then masking the GOX to expose a drain-side region over which additional oxide may be grown to form the thick regions, then removing the masking material ( .g., a photolithographic polymer). As another example, a subtractive process may include forming a thick layer of GOX over the active layer 106, then masking the GOX to protect a drain-side region of thick GOX material, then etching the unprotected GOX to a desired thinness, then removing the masking material.

[0067] FIG. 7D shows that the active layer 106 on the source and / or drain sides of the gate structure 130 may be doped (e.g., by angled ion implantation after suitable masking) with suitable dopants to form at least one halo region 122 and / or at least one LDD region 124 within the P-well material (including a portion underneath the gate structure 130). Note that formation of the halo region 122 and / or the LDD region 124 may take place after formation of the N+ source 110 and an N+ drain 114 in some embodiments.

[0068] FIG. 7E shows that an N+ source 110 and an N+ drain 114 have been formed by suitably masking and then doping with an N+ dopant. The conductive layer 132 may be doped at this time as well. Doping may be by ion implantation or diffusion. Subsequently, P+ material may be implanted in selective areas of the N+ source 1 10 to form body-tied-to-source connections (not shown, but see description of FIGS. 6A-6C above).

[0069] FIG. 7F shows that a conductive source contact 142, a conductive gate contact 144, and a conductive drain contact 146, which may be salicides, have been respectively formed in contact with the N+ source 110, the gate structure 130, and the N+ drain 114. Stylized electrical terminals S, G, and D are shown coupled to the corresponding source contact 142, gate contact 144, and drain contact 146.

[0070] In some applications, such as power amplifiers, it has been found useful to create “asymmetric” MOSFETs which exhibit a higher breakdown voltage BVDSS and reduced hot carrier injection (HCI) issues compared to symmetric MOSFETs. HCI is a phenomenon where a charge carrier (electron or hole) gains sufficient kinetic energy to overcome a potential barrier necessary to break an interface state. The charge carriers can become trapped in the gate dielectric of aAttorney Docket: P3115-PCTMOSFET and may permanently change the switching characteristics of the transistor. HCI is one of the mechanisms that adversely affects the reliability of MOSFETs. In some asymmetric MOSFETs, halo / LDD dopants may be implanted at two different angles and only from the source side of the device. For example, FIG. 7G shows a cross-sectional view illustrating a variant of the HB MOSFET structure shown in FIG. 3A. In the illustrated embodiment, only the source-side includes a halo region 122 and an LDD region 124. In some embodiments, the drain-side may include only a halo region 122 or only a LDD region 124. In some embodiments, a drain-side halo region 122 and / or LDD region 124 may be included, but with asymmetrical size and / or placement with respect to a source-side halo region 122 or LDD region 124. For example, the implantation tilt angle 0 may be about 30° for halo implants, and about 10° for LDD implants. Tilted implantation of dopants for halo and LDD regions made only from the source-side of a gate structure 130, such that the gate structure 130 “shadows” the drain-side of the gate structure 130, results in the halo implants and LDD regions on the drain side underlapping the gate structure. The resulting underlap junction on the drain side improves BVDSS and reduces HCI events due to the graded junction on the drain-side of the gate structure 130.

[0071] FIG. 8 is a process flowchart 800 showing another representation of an example fabrication process for a sub-gate drift region HB MOSFET that is suitable for some contemporary IC front-end-of-line (FEOL) foundries. Note that some conventional steps, such as planarization, passivation, details of masking and etching, and superstructure formation have been omitted as known to those of ordinary skill in the art. The illustrated process includes:• Forming shallow trench isolation (STI) regions (Step 802).• Forming a doped (e.g., P-type) or intrinsic Si well (Step 804).• Forming a doped (e.g, N-) sub-gate drift region 302 (Step 806).• Depositing or forming a gate oxide (GOX) and gate material (e.g, poly-Si), patterning to define a gate structure, and forming gate structure spacers; the GOX may be non-stepped, single-stepped, or multi-stepped (Step 808).• Implanting at least one of a source-side or drain-side halo region (Step 810).Attorney Docket: P3115-PCT• Implanting at least one of a source-side or drain-side LDD region (Step 812).• Implanting a dopant (e.g., N+) into source and drain regions (Step 814).• If including a body contact region, then implanting a dopant (e.g., P+) in the N+ source region and in contact with the doped well (Step 816).• Patterning to define contact regions (Step 818).• Depositing or forming salicide (e.g., NiSi) in the defined contact regions and annealing (Step 820).

[0072] For manufacturability purposes, it is generally desirable to have a self-aligned process for fabricating the stepped GOX layer 134s, 134s' and doping the sub-gate drift region 302 so that the source-side step-up of the stepped GOX layer 134s, 134s' is vertically aligned with the LG / LDR interface (i.e., the channel-to-drift region edge shown in FIG. 3B). Stated another way, the length Ls (in the X dimension, see FIG. 4) of the stepped portion of the GOX layer 134s, 134s' should be approximately the same as the length LDR of the sub-gate drift region 302. Misalignment may cause significant differences in device behavior. As one example of a self-aligned process, a hard mask may be used to define the drift region 302, followed by dopant implantation. The same mask may then be used to define the stepped portion of the GOX layer 134s, 134s' on which additional oxide is formed to thicken the drain-side region of that layer to create one or more steps. Re-using the same mask for drift region 302 implantation and stepped GOX layer 134s, 134s' formation ensures that the two regions are accurately aligned.

[0073] Note that not all steps that may be performed during the manufacture of a HB MOSFET device as part of an IC are shown or described in this disclosure. Such steps may vary between IC foundries and may include (but are not limited to) substrate thinning, planarization, special implantations, annealing, formation of ohmic contacts, and formation of additional temporary or permanent structures (e.g., drift regions, substrate contacts, passivation layers, salicide blocks, replacement metal gate (RMG)), etc. After formation of a basic HB MOSFET structure, back-end- of-line (BEOL) processes may be applied, such as fabrication of electrical contacts (pads), vias,Attorney Docket: P3115-PCT insulating layers (dielectrics), metallization layers, and bonding sites for die-to-package connections.

[0074] The illustrated HB MOSFETs include doped regions having different dopant concentrations. For example, an instance of an FIB MOSFET may include heavily doped (x+), intermediately doped (x), and lightly doped (x-) regions, where x is the polarity type and can be P-type (“P”) or N-type (“N”). A lightly doped region may have a dopant concentration of about 1015 / cm3, an intermediately doped region may have a dopant concentration of about 1018 / cm3, and a heavily doped region may have a dopant concentration of about 1021 / cm3. Providing other dopant concentrations for the different doped regions may also be useful. For example, the doping concentrations for the different types of doped regions may be relative and depend on a selected fabrication process. P-type dopants may include boron (B), aluminum (Al), and / or indium (In), while N-type dopants may include phosphorous (P), arsenic (As), and / or antimony (Sb).

[0075] As should be appreciated, other “recipes” that include additive and / or subtractive process steps may be used to fabricate essentially the same sub-gate drift region HB MOSFET device structures. Further, the fabrications steps may be performed in any feasible order.

[0076] The benefits of using a stepped GOX layer are severalfold due to mitigation or elimination of several potential issues with HB MOSFETs. For example, an HB MOSFET having a sub-gate drift region generally causes CGD to increase and be bias dependent. A bias-dependent CGD causes low power gain to vary with VDS in some applications, particularly envelope tracking. Too much variation in gain can limit the range of envelope tracking and impact power added efficiency (PAE).

[0077] As one example of the effects of bias-dependent CGD, FIG. 9 is a graph of transducer power gain Gt as a function of power out POUT at different VDD levels for an example HB MOSFET device lacking a stepped GOX layer. Graph line 902 corresponds to a VDD of 3.5V, and graph line 902 corresponds to a VDD of 1 ,5V. Intermediate VDD values would generate similarly shaped graph lines between the two illustrated graph lines 902, 904. For a number of applications, such gain dispersion for different values of VDD is far too high.Attorney Docket: P3115-PCT

[0078] As another example, FIG. 10 is a graph of CGD versus VDS for an example HB MOSFET device lacking a stepped GOX layer. Graph line 1002 shows that CGD varies significantly with VDS.

[0079] Following is a description of the benefits and characteristics resulting from use of stepped GOX over a sub-gate drift region.

[0080] Electric Field contours of modeled HB MOSFETS show less dense contour lines using a stepped GOX (e.g. , 150A above the conventional field GOX) compared to no step (i.e. , 0A above the conventional field GOX). This results in a potential drop that is more gradual with the increase in thickness.

[0081] For example, FIG. 11A is a graph showing electrostatic potential as a function of X- dimension (“horizontal”) distance from the midpoint of the length of the conductive layer of an N- type HB MOSFET. Solid graph line 1102 corresponds to a stepped GOX thickness of 150A while dotted graph line 1104 corresponds to a zero thickness “step” (z.e., no step at all). Intermediate step thicknesses would generate graph lines between the two illustrated graph lines 1102, 1104. The solid graph line 1102 demonstrates that the potential drop is more gradual with a non-zero step thickness.

[0082] As another example, FIG. 1 IB is a graph showing electric field as a function of X- dimension (“horizontal”) distance from the midpoint of the length of the conductive layer of an N- type HB MOSFET. Solid graph line 1202 corresponds to a stepped GOX thickness of 150A while dotted graph line 1204 corresponds to a zero thickness “step”. Intermediate step thicknesses would generate graph lines between the two illustrated graph lines 1202, 1204. The solid graph line 1202 demonstrates that the electric field is both lower and more distributed with a non-zero step thickness.

[0083] FIG. 12A is a graph of CGD versus VDS for an HB MOSFET with no stepped GOX (graph line 1202) compared to several versions of HB MOSFETs with a stepped GOX. Graph line 1204 corresponds to a step thickness of 20A, graph line 1206 corresponds to a step thickness of 75A, and graph line 1208 corresponds to a step thickness of 150A. All modeled devices have anAttorney Docket: P3115-PCTLG of 0.2pm and an LDR of 0.2pm. As is clear, the variance of CGD as a function of VDS is significantly less as step thickness increases.

[0084] FIG. 12B is a graph of drain current ID versus VDS in the OFF state for an HB MOSFET with no stepped GOX (graph line 1212) compared to one version of an HB MOSFET with a stepped GOX having a step thickness of 150A (graph line 1218). Intermediate step thicknesses would generate graph lines between the two illustrated graph lines 1212, 1218, trending towards the shape of graph line 1218 as step thickness increases. The flatter curve of graph line 1218 shows that the breakdown voltage, BVDSS, improves significantly.

[0085] HB MOSFETs with a stepped GOX do not significantly affect other parameters of a device, such as the output conductance (gDS), RON, or IDLIN (the measured drain current with the device biased in the linear region). For example, FIG. 12C is a graph of drain current ID versus VDS in the ON state for an HB MOSFET with no stepped GOX (graph line 1222) compared to one version of an HB MOSFET with a stepped GOX having a step thickness of 150A (graph line 1228). Intermediate step thicknesses would generate graph lines between the two illustrated graph lines 1222, 1228. The graph lines 1222, 1228 show very little difference in ID between the nonstepped GOX FIB MOSFET and the stepped GOX HB MOSFET as VDS increases, which indirectly shows that RON is not affected while gDS is only slightly degraded based on the flatness of the ID vs. VDS curves.

[0086] Similarly, FIG. 12D is a graph of ID versus VGS for an HB MOSFET with no stepped GOX (graph line 1232) compared to one version of an HB MOSFET with a stepped GOX having a step thickness of 150A (graph line 1238). Intermediate step thicknesses would generate graph lines between the two illustrated graph lines 1232, 1238. The graph lines 1232, 1238 show very little difference in ID between the non-stepped GOX HB MOSFET and the stepped GOX HB MOSFET as VGS increases.

[0087] FIGS. 13A-13D are graphs showing the effects of different stepped-GOX thicknesses on various parameters for modeled HB MOSFETs compared to an HB MOSFET having a nonstepped GOX (z.e., zero extra thickness). For these example graphs, the modeled HB MOSFETS have an LG of 0.2pm, an LDR of 0.2pm, and a width W of 1pm. The left-most data point at 0A corresponds to a non-stepped HB MOSFET; successive data points corresponding to stepAttorney Docket: P3115-PCT thicknesses of 20A, 75 A, and 150A. FIG. 13 A shows electric field as a function of stepped GOX thickness (in Angstroms) at VDS = 10V. FIG. 13B shows CGD as a function of stepped GOX thickness at VGS = 1.9V for 4 different VDS voltage levels (IV, 2V, 3.5V, and 5V). FIG. 13C shows BVDSS as a function of stepped GOX thickness at VGS = OV. FIG. 13D shows the device transit frequency ft and maximum oscillation frequency nax as a function of stepped GOX thickness at VDD = 3.5V and a quotient drain current density Jdq = 75pA / pm.

[0088] Note that while the examples in the disclosure have used step thicknesses of 20A, 75A, and 150A, the benefits of a stepped GOX occur within a step thickness range from about 20A to at least 200A.

[0089] As should be appreciated, using the teachings of the present invention, the field GOX (z.e., the non-stepped portion) and the gate length LG of an HB MOSFET may be reduced or optimized for gain and / or PAE while a stepped GOX over a drain-side sub-gate drift region can be selected to improve CGD, gain, and BVDSS.

[0090] Circuits and devices in accordance with the present invention may be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention may be fabricated as integrated circuits (ICs), which may be encased in IC packages and / or in modules for ease of handling, manufacture, and / or improved performance. In particular, IC embodiments of this invention are often used in modules in which one or more of such ICs are combined with other circuit components or blocks (c. ., filters, amplifiers, passive components, and possibly additional ICs) into one package. The ICs and / or modules are then typically combined with other components, often on a printed circuit board, to form part of an end-product such as a cellular telephone, laptop computer, or electronic tablet, or to form a higher-level module which may be used in a wide variety of products, such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and assemblies, such ICs typically enable a mode of communication, often wireless communication.

[0091] As one example of further integration of embodiments of the present invention with other components, FIG. 14 is a top plan view of a substrate 1400 that may be, for example, a printed circuit board or chip module substrate (e.g., a thin-film tile). In the illustrated example, the substrate 1400 includes multiple ICs 1402a-1402d having terminal pads 1404 which would beAttorney Docket: P3115-PCT interconnected by conductive vias and / or traces on and / or within the substrate 1400 or on the opposite (back) surface of the substrate 1400 (to avoid clutter, the surface conductive traces are not shown and not all terminal pads are labelled). The ICs 1402a-1402d may embody, for example, signal switches, active and / or passive fdters, amplifiers (including one or more low-noise amplifiers), and other circuitry. For example, IC 1402b may incorporate one or more instances of an HB MOSFET like the devices shown in FIG. 3 A and / or FIG. 4.

[0092] The substrate 1400 may also include one or more passive devices 1406 embedded in, formed on, and / or affixed to the substrate 1400. While shown as generic rectangles, the passive devices 1406 may be, for example, filters, capacitors, inductors, transmission lines, resistors, antennae elements, transducers (including, for example, MEMS-based transducers, such as accelerometers, gyroscopes, microphones, pressure sensors, etc batteries, e / c., interconnected by conductive traces on or in the substrate 1400 to other passive devices 1406 and / or the individual ICs 1402a-1402d.

[0093] The front or back surface of the substrate 1400 may be used as a location for the formation of other structures. For example, one or more antennae may be formed on or affixed to the front or back surface of the substrate 1400; one example of a front-surface antenna 1408 is shown, coupled to an IC die 1402b, which may include RF front-end circuitry. Thus, by including one or more antennae on the substrate 1400, a complete radio may be created.

[0094] Embodiments of the present invention are useful in a wide variety of larger radio frequency (RF) circuits and systems for performing a range of functions, including (but not limited to) impedance matching circuits, RF power amplifiers, RF low-noise amplifiers (LNAs), phase shifters, attenuators, antenna beam-steering systems, charge pump devices, RF switches, high performance envelope tracking circuits, high performance average power tracking circuits, etc. Such functions are useful in a variety of applications, such as radar systems (including phased array and automotive radar systems), radio systems (including cellular radio systems), and test equipment.

[0095] Radio system usage includes wireless RF systems (including base stations, relay stations, and hand-held transceivers) that use various technologies and protocols, including various types of orthogonal frequency-division multiplexing (“OFDM”), quadrature amplitude modulationAttorney Docket: P3115-PCT(“QAM”), Code-Division Multiple Access (“CDMA”), Time-Division Multiple Access (“TDMA”), Wide Band Code Division Multiple Access (“W-CDMA”), Global System for Mobile Communications (“GSM”), Long Term Evolution (“LTE”), 5G, 6G, and WiFi (e.g., 802.1 la, b, g, ac, ax, be) protocols, as well as other radio communication standards and protocols.

[0096] The term “MOSFET”, as used in this disclosure, includes any field effect transistor (FET) having an insulated gate whose voltage or charge level determines the conductivity of the transistor, and encompasses insulated gates having a metal or metal-like, insulator, and / or semiconductor structure. The terms “metal” or “metal-like” include at least one electrically conductive material (such as aluminum, copper, or other metal, or highly doped polysilicon, graphene, or other electrical conductor), “insulator” includes at least one insulating material (such as silicon oxide or other dielectric material), and “semiconductor” includes at least one semiconductor material.

[0097] As used in this disclosure, the term “radio frequency” (RF) refers to a rate of oscillation in the range of about 3 kHz to about 300 GHz. This term also includes the frequencies used in wireless communication systems. An RF frequency may be the frequency of an electromagnetic wave or of an alternating voltage or current in a circuit.

[0098] With respect to the figures referenced in this disclosure, the dimensions for the various elements are not to scale; some dimensions may be greatly exaggerated vertically and / or horizontally for clarity or emphasis. In addition, references to orientations and directions (e.g, “top”, “bottom”, “above”, “below”, “lateral”, “vertical”, “horizontal”, etc.) are relative to the example drawings, and not necessarily absolute orientations or directions.

[0099] Various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice. Various embodiments of the invention may be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including but not limited to standard bulk silicon, high-resistivity bulk CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, embodiments of the invention may be implemented in other transistor technologies, such asAttorney Docket: P3115-PCTBiCMOS, LDMOS, BCD, FinFET, GAAFET, and SiC-based device technologies, using 2-D, 2.5- D, and 3-D structures. However, embodiments of the invention are particularly useful when fabricated using an SOI or SOS based process, or when fabricated with processes having similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (z.e., radio frequencies up to and exceeding 300 GHz). Monolithic IC implementation is particularly useful since parasitic capacitances generally can be kept low (or at a minimum, kept uniform across all units, permitting them to be compensated) by careful design.

[0100] A number of embodiments of the invention have been described. It is to be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order independent and thus can be performed in an order different from that described. Further, some of the steps described above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, and / or parallel fashion.

[0101] It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. In particular, the scope of the invention includes any and all feasible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the claims below. (Note that the parenthetical labels for claim elements are for ease of referring to such elements, and do not in themselves indicate a particular required ordering or enumeration of elements; further, such labels may be reused in dependent claims as references to additional elements without being regarded as starting a conflicting labeling sequence).

Claims

Attorney Docket: P3115-PCTCLAIMS1. A MO SFET including;(a) a body region;(b) a gate structure positioned with respect to the body region so as to be able to control current flow through the body region;(c) a source region positioned proximate to a first side of the body region;(d) a drain region positioned proximate to a second side of the body region; and(e) a sub -gate drift region.

2. The MOSFET of claim 1, wherein the sub-gate drift region extends no more than about 0.25pm into the drain region.

3. The MOSFET of claim 1, wherein the sub-gate drift region has a length LDR is greater than about 0.1 m.

4. The MOSFET of claim 1, wherein the sub-gate drift region has a length LDR in the range of about 0.1pm to about 0.3pm.

5. The MOSFET of claim 1, wherein the MOSFET includes a halo region proximate to at least one of the first side and second side of the body region.

6. The MOSFET of claim 1, wherein the MOSFET includes a lightly-doped drain region proximate to at least one of the first side and second side of the body region.

7. The MOSFET of claim 1, wherein the gate structure includes a stepped gate oxide layer.

8. The MOSFET of claim 7, wherein the stepped gate oxide layer has a length Ls approximately equal to a length LDR of the sub -gate drift region.

9. The MOSFET of claim 7, wherein the stepped gate oxide layer has a thickness in the range of about 20A to about 200A.

10. The MOSFET of claim 7, wherein the stepped gate oxide layer has a thickness in the range of about 20A to about 150A.Attorney Docket: P3115-PCT11 . The MOSFET of claim 7, wherein the stepped gate oxide layer has a length Ls approximately equal to a length LDR of the sub-gate drift region, and a thickness in the range of about 20A to about 200A.

12. The MOSFET of claim 7, wherein the stepped gate oxide layer has a length Ls approximately equal to a length LDR of the sub-gate drift region, and a thickness in the range of about 20A to about 150A.

13. The MOSFET of claim 7, wherein the stepped gate oxide layer includes at least two steps.

14. The MOSFET of claim 1, further including at least one body tie region formed within the source region in direct contact with the body region.

15. The MOSFET of claim 1, wherein the body region is doped to have a first semiconductor characteristic, the source region is doped to have a second semiconductor characteristic, the drain region is doped to have a third semiconductor characteristic, and the sub-gate drift region is doped to have a fourth semiconductor characteristic.

16. The MOSFET of claim 15, wherein the first semiconductor characteristic is P-type, the second and third semiconductor characteristics are N+ type, and the fourth semiconductor characteristic is N- type.

17. A MOSFET including;(a) a body region;(b) a gate structure positioned with respect to the body region so as to be able to control current flow through the body region;(c) a source region positioned proximate to a first side of the body region;(d) a drain region positioned proximate to a second side of the body region;(e) a sub-gate drift region;(f) a halo region proximate to at least one of the first side and second side of the body region; and(g) a lightly-doped drain region proximate to at least one of the first side and second side of the body region.Attorney Docket: P3115-PCT18. The MOSFET of claim 17, wherein the sub-gate drift region extends no more than about 0.25pm into the drain region.

19. The MOSFET of claim 17, wherein the sub-gate drift region has a length LDR is greater than about 0.1 m.

20. The MOSFET of claim 17, wherein the sub-gate drift region has a length LDR in the range of about 0.1pm to about 0.3pm.

21. The MOSFET of claim 17, wherein the gate structure includes a stepped gate oxide layer.

22. The MOSFET of claim 21, wherein the stepped gate oxide layer has a length Ls approximately equal to a length LDR of the sub-gate drift region.

23. The MOSFET of claim 21, wherein the stepped gate oxide layer has a thickness in the range of about 20A to about 200A.

24. The MOSFET of claim 21, wherein the stepped gate oxide layer has a thickness in the range of about 20A to about 150A.

25. The MOSFET of claim 21, wherein the stepped gate oxide layer has a length Ls approximately equal to a length LDR of the sub-gate drift region, and a thickness in the range of about 20A to about 200A.

26. The MOSFET of claim 21, wherein the stepped gate oxide layer has a length Ls approximately equal to a length LDR of the sub-gate drift region, and a thickness in the range of about 20A to about 150A.

27. The MOSFET of claim 21, wherein the stepped gate oxide layer includes at least two steps.

28. The MOSFET of claim 17, further including at least one body tie region formed within the source region in direct contact with the body region.

29. The MOSFET of claim 17, wherein the body region is doped to have a first semiconductor characteristic, the source region is doped to have a second semiconductor characteristic, theAttorney Docket: P3115-PCT drain region is doped to have a third semiconductor characteristic, and the sub-gate drift region is doped to have a fourth semiconductor characteristic.

30. The MOSFET of claim 29, wherein the first semiconductor characteristic is P-type, the second and third semiconductor characteristics are N+ type, and the fourth semiconductor characteristic is N- type.

31. A method of fabricating an integrated circuit on a substrate and including:(a) fabricating a body region;(b) positioning a gate structure with respect to the body region so as to be able to control current flow through the body region;(c) fabricating a source region proximate to a first side of the body region;(d) fabricating a drain region proximate to a second side of the body region; and(e) implanting a sub-gate drift region.

32. The method of claim 31, wherein the sub-gate drift region extends no more than about 0.25pm into the drain region.

33. The method of claim 31, wherein the sub-gate drift region has a length LDR is greater than about 0.1 pm.

34. The method of claim 31, wherein the sub-gate drift region has a length LDR in the range of about 0.1 pm to about 0.3pm.

35. The method of claim 31, further including fabricating a halo region proximate to at least one of the first side and second side of the body region.

36. The method of claim 31, further including fabricating a lightly-doped drain region proximate to at least one of the first side and second side of the body region.

37. The method of claim 31, wherein the gate structure includes a stepped gate oxide layer.

38. The method of claim 37, wherein the stepped gate oxide layer has a length Ls approximately equal to a length LDR of the sub-gate drift region.Attorney Docket: P3115-PCT39. The method of claim 37, wherein the stepped gate oxide layer has a thickness in the range of about 20A to about 200A.

40. The method of claim 37, wherein the stepped gate oxide layer has a thickness in the range of about 20A to about 150A.

41. The method of claim 37, wherein the stepped gate oxide layer has a length Ls approximately equal to a length LDR of the sub-gate drift region, and a thickness in the range of about 20A to about 200A.

42. The method of claim 37, wherein the stepped gate oxide layer has a length Ls approximately equal to a length LDR of the sub-gate drift region, and a thickness in the range of about 20A to about 150A.

43. The MOSFET of claim 37, wherein the stepped gate oxide layer includes at least two steps.

44. The method of claim 31, further including fabricating at least one body tie region within the source region in direct contact with the body region.

45. The method of claim 31, wherein the body region is doped to have a first semiconductor characteristic, the source region is doped to have a second semiconductor characteristic, the drain region is doped to have a third semiconductor characteristic, and the sub-gate drift region is doped to have a fourth semiconductor characteristic.

46. The method of claim 45, wherein the first semiconductor characteristic is P-type, the second and third semiconductor characteristics are N+ type, and the fourth semiconductor characteristic is N- type.

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