Heterogeneous integration and combinatorial material processing

Abstract

The present technology is related to heterogeneous integration, thin film deposition and fabrication methods. An inventive on-wafer architecture enables facile deposition and heterogeneous integration of materials that are otherwise challenging to integrate due to thermal budget or processing constraints. The on-wafer architecture also enables growth or on- wafer processing of materials with multiple physical stimuli and high-throughput combinatorial screening of deposition / processing conditions.

Description

Attorney Docket No. MIT-26290W001Heterogeneous Integration and Combinatorial Material ProcessingCROSS-REFERENCE TO RELATED APPLICATION(S)

[0001] This application claims the priority benefit, under 35 U.S.C. 119(e), of U.S. Application No. 63 / 736,388, filed December 19, 2024, which is incorporated herein by reference in its entirety for all purposes.GOVERNMENT SUPPORT

[0002] This invention was made with government support under DMR2225968 awarded by the National Science Foundation. The government has certain rights in the invention.BACKGROUND

[0003] Heterogeneous integration (HI) combines two or more material technologies into a single chip-scale platform. In many cases, an HI process involves annealing or treatment with other physical stimuli not compatible with the standard semiconductor manufacturing process. For example, back-end-of-the-line (BEOL) integration in complementary metal-oxide- semiconductor (CMOS) processes stipulates a thermal budget (typically < 400 °C) to avoid damaging other BEOL layers on the wafer. The deposition or processing temperatures of various functional materials involved in HI are incompatible with this thermal budget requirement. The constraint presents a major barrier towards HI of many new materials into the CMOS platform. Furthermore, exploration of optimal processing conditions for a new material in HI can be a time-consuming and laborious process, especially when testing many processing parameter combinations, each involving running one or more wafers (substrates) through the integration or fabrication process followed by subsequent characterization.SUMMARY

[0004] This present technology facilitates integration of new materials that are traditionally incompatible with standard semiconductor manufacturing processes (e.g., demanding high growth temperature exceeding the CMOS thermal budget). The present technology also enables performance of high-throughput combinatorial experimentation — testing of tens to hundreds to thousands of different deposition and post-deposition processing conditions (thermal and other physical stimuli including but not limited to electric field, magnetic field, plasma processing, etc.) on a single wafer. Inventive high-throughput combinatorialAttorney Docket No. MIT-26290W001 experimentation methods utilize on-wafer (on-chip) structures, such as resistive micro-heaters, electrodes, and metal interconnects, to produce local environments applying different physical stimuli on the material being integrated with the wafer while having little to no impact on other on-wafer materials or structures. The processing parameters controlled in the local environment can be readily modified in situ during the film deposition process and varied across the wafer to facilitate combinatorial exploration of large parameter sets concurrently. These on-wafer architectures can be fabricated leveraging standard foundry manufacturing.

[0005] For example, a semiconductor device can be fabricated by applying (different) first and second physical stimuli to first and second sections, respectively, of a front side of a semiconductor substrate (e.g., a wafer, chip, or die) with first and second devices, respectively, embedded in the semiconductor substrate while depositing material on the semiconductor substrate. The first device applies the first physical stimulus in response to a first electrical signal applied to the first device through an electrical input / output layer formed on a back side of the semiconductor substrate and a first via connecting the electrical input / output layer to the first device. Similarly, the second device applies the second physical stimulus in response to a second electrical signal applied to the second device through the electrical input / output layer and a second via connecting the electrical input / output layer to the second device.

[0006] In some cases, the first and second devices are first and second heaters, respectively, that heat the first and second sections of the semiconductor substrate to different temperatures. For instance, the first temperature may be at least 350 °C.

[0007] In other case, the first device comprises at least one electrode and applying the first physical stimulus to the first section of the semiconductor substrate comprises applying a bias voltage to the first section of the semiconductor substrate.

[0008] In still other cases, the first device comprises at least one pair of electrodes and applying the first physical stimulus to the first section of the semiconductor substrate comprises applying an electric field to the first section of the semiconductor substrate.

[0009] In yet other cases, the first device comprises at least one pair of planar electrodes or a coil and applying the first physical stimulus to the first section of the semiconductor substrate comprises applying a magnetic field to the first section of the semiconductor substrate.

[0010] And in still other cases, the first device comprises at least one pair of radio-frequency electrodes and applying the first physical stimulus to the first section of the semiconductor substrate comprises applying a plasma to the first section of the semiconductor substrate.Attorney Docket No. MIT-26290W001

[0011] The first and second physical stimuli can be applied / controlled independently of each other.

[0012] These methods can be carried out with a semiconductor substrate (e.g., a wafer, chip, or die) that includes an array of micro-environment controlling units, an electrical input / output layer, and vias. The array of micro-environment controlling units is integrated with a front side of the semiconductor substrate and configured to apply (different) physical stimuli to different regions of the semiconductor substrate during deposition of material on the front side of the semiconductor substrate. The electrical input / output layer is formed on a back side of the semiconductor substrate. The vias connect the electrical input / output layer to the array of micro-environment controlling units and conduct electrical signals from the electrical input / output layer to the array of micro-environment controlling units during deposition of material on the front side of the semiconductor substrate.

[0013] The array of micro-environment controlling units can include at least one resistive micro-heater (e.g., a single-use heater) for heating a corresponding region of the semiconductor substrate (e.g., to at least 350 °C). In some cases, the array of micro-environment controlling units comprises a two-dimensional array of individually controllable resistive micro-heaters.

[0014] In other cases, the array of micro-environment controlling units comprises at least one electrode for applying a bias voltage to a corresponding region of the semiconductor substrate. The array of micro-environment controlling units can also include at least one pair of electrodes for applying an electric field to a corresponding region of the semiconductor substrate, at least one pair of planar electrodes or a coil for applying a magnetic field to a corresponding region of the semiconductor substrate, and / or at least one pair of radio-frequency electrodes for applying a plasma to a corresponding region of the semiconductor substrate.

[0015] Such a semiconductor substrate can be disposed in a vacuum deposition chamber and coupled to a controller as part of a complete system for heterogeneous integration and combinatorial material processing. The controller is operably coupled to the electrical input / output layer of the semiconductor substrate and controls the micro-environment controlling units before, during, and / or after the deposition of the material on the front side of the semiconductor substrate. If desired, the semiconductor substrate can be disposed on a rotation stage in the vacuum deposition chamber, with a cable passing through a slip ring connecting the controller to the electrical input / output layer.Attorney Docket No. MIT-26290W001

[0016] Such a semiconductor substrate can be made forming an array of micro-environment controlling units in a front side of complementary metal-oxide-semiconductor (CMOS) wafer. The array of micro-environment controlling units formed in the front side of the CMOS wafer is then bonded to redistribution layers and / or vias exposed on a front side of a handler wafer. At least a portion of a back side of the CMOS wafer is removed to expose the array of microenvironment controlling units. At least a portion of a back side of the handler wafer is removed to expose the redistribution layers and / or vias. A carrier is bonded to the back side of the handler wafer.

[0017] All combinations of the foregoing concepts and additional concepts discussed in greater detail below (provided such concepts are not mutually inconsistent) are part of the inventive subject matter disclosed herein. In particular, all combinations of claimed subject matter appearing at the end of this disclosure are part of the inventive subject matter disclosed herein. The terminology used herein that also may appear in any disclosure incorporated by reference should be accorded a meaning most consistent with the particular concepts disclosed herein.BRIEF DESCRIPTIONS OF THE DRAWINGS

[0018] The skilled artisan will understand that the drawings primarily are for illustrative purposes and are not intended to limit the scope of the inventive subject matter described herein. The drawings are not necessarily to scale; in some instances, various aspects of the inventive subject matter disclosed herein may be shown exaggerated or enlarged in the drawings to facilitate an understanding of different features. In the drawings, like reference characters generally refer to like features (e.g., functionally and / or structurally similar elements).

[0019] FIG. 1 A illustrates part of a wafer with various on-wafer architectures, also called an on-wafer lab, for applying different physical stimuli to different areas of the wafer.

[0020] FIG. IB shows the on-wafer lab of FIG. 1A in a film deposition chamber to enable physical stimuli application in situ during film deposition on the wafer.

[0021] FIG. 1C shows the on-wafer lab of FIG. 1A mounted on a rotating mount in a film deposition chamber for applying different physical stimuli to different parts of the wafer during film deposition.

[0022] FIG. 2 shows micro-environment control unit that can heat and / or apply an electric field to before, during, and / or after deposition of material.Attorney Docket No. MIT-26290W001

[0023] FIG. 3 A is a block diagram of an on-wafer lab in a deposition chamber and connected by wires through a vacuum feedthrough to external electronics that independently control the on-wafer lab’s actuators / stimulators.

[0024] FIG. 3B is a block diagram of an on-wafer lab in a deposition chamber and connected wirelessly to a wired connection between the deposition chamber and external electronics that independently control the on-wafer lab’s actuators / stimulators.

[0025] FIG. 3C is a block diagram of an on-wafer lab in a deposition chamber and connected wirelessly to external electronics that independently control the on -wafer lab’s actuators / stimul ator s .

[0026] FIG. 4A is an optical micrograph of a fabricated 2-D micro-heater pixel array.

[0027] FIG. 4B illustrates a chip containing the fabricated 2-D micro-heater pixel array mounted on a custom printed circuit board (PCB).

[0028] FIG. 5A is a perspective cutaway view of a deposition chamber that holds an on-wafer lab in the form of a ceramic-packaged micro-heater array chip. Insets show the packaged microheater array chip and the micro-heater array fabricated using CMOS-compatible processes.

[0029] FIG. 5B shows a control and measurement setup enabling independent biasing, actuation, and temperature readout of each micro-heater in the micro-heater array chip of FIG. 3A.

[0030] FIG. 6 depicts an inventive fabrication process for making an on-wafer lab.DETAILED DESCRIPTION

[0031] The present technology addresses both the complexity of process development and the barriers to material integration in semiconductor manufacturing. It leverages the precision and scalability of semiconductor microsystems technology to transform wafers from passive substrates into active, programmable testbeds. By embedding spatially addressable microstructures capable of locally modulating process conditions directly onto standard wafers, the present technology enables massively parallel and spatially localized experimentation within a foundry-compatible infrastructure. It is particularly useful for BEOL integration, as it allows high-temperature or otherwise incompatible steps to be confined to micrometer-scale regions, without violating global process constraints. The present technology enables developers to evaluate new materials and processes in a form factor and operational contextAttorney Docket No. MIT-26290W001 that are compatible with existing toolsets and workflows. In doing so, it accelerates the optimization of complex process spaces and opens a practical pathway for integrating previously inaccessible materials into advanced semiconductor platforms.

[0032] The present technology can be embodied in an on-wafer lab, which is a wafer-scale experimental platform built on standard semiconductor foundry infrastructure. Unlike other self-driving lab architectures that rely on highly customized and expensive instrumentation, an on-wafer lab leverages lithographically defined microsystems that can be readily integrated with existing CMOS process flows and toolsets. This approach avoids the need for custom- built equipment or extensive retrofitting, offering a cost-effective and scalable solution for high-throughput experimentation. An on-wafer lab transforms a wafer into a high-density array of programmable experimental units, also called micro-environment controlling units, each configured to locally modulate process parameters such as temperature, substrate bias, plasma excitation, and / or optical input. These independently addressable micro-environments enable simultaneous, spatially resolved exploration of large process parameter spaces on a single wafer. Following processing, material responses across the array of micro-environments can be characterized using high-throughput, spatially resolved techniques, converting a single wafer run into a rich combinatorial dataset. This architecture compresses weeks of serial experimentation and hundreds of wafer runs into one integrated workflow, substantially accelerating process optimization while remaining fully compatible with existing semiconductor manufacturing infrastructure.

[0033] An on-wafer lab is versatile and broadly applicable across a wide range of semiconductor processes, including thin-film deposition, plasma etching, atomic-layer etching, passivation, heat treatment, wet etching, and electroplating. Its modular, programmable architecture supports integration with diverse processing modalities, including various physical vapor deposition (PVD) and chemical vapor deposition (CVD) techniques. Beyond in situ parameter control during deposition, an on-wafer lab enables localized post-deposition treatments such as thermal annealing, plasma exposure, and electric or magnetic field activation, facilitating process steps for phase transformation, stress engineering, crystallinity control, and interface tuning. The same infrastructure can be extended to plasma etching applications, where spatially resolved biasing, plasma, or surface conditioning may enable combinatorial pattern transfer studies. Furthermore, an on-wafer lab can be coupled with characterization techniques such as electron microscopy or scanning spectroscopy to perform high-throughput, in situ imaging or mapping of material transformations. An on-wafer labAttorney Docket No. MIT-26290W001 provides a universal, wafer-scale platform for accelerating development and integration of process technologies spanning the full semiconductor fabrication stack.

[0034] An on-wafer lab can be fabricated using standard CMOS foundry processes, enabling seamless integration with existing semiconductor manufacturing infrastructure. Each pixel (programmable experimental unit or micro-environment controlling unit) can be engineered to independently modulate one or more process parameters through embedded microscale actuators and electrodes. For example, temperature control can be achieved via lithographically patterned resistive micro-heaters, with either unipolar or PIN-configured doped silicon structures serving as efficient, CMOS-compatible heating elements. Substrate biasing and electric field modulation can be implemented by routing voltage signals through backend metal interconnects or doped Si electrodes. The multi-level metallization available in modern CMOS processes enables precise spatial patterning of fields and supports sophisticated control of three-dimensional electric and magnetic field distributions at the wafer surface, where magnetic fields can be introduced through patterned current loops or microcoils embedded in the backend stack. Plasma environments can be locally generated by applying radio-frequency (RF) signals to exposed electrode structures, e.g., for on-chip chemical processing. The pixels can be controlled with either external multichannel source meters or integrated on-wafer CMOS electronics, with the potential for wireless actuation and data acquisition using inductive coupling or mm-wave communication schemes. This design flexibility allows an on- wafer lab to be tailored to diverse experimental setups while maintaining compatibility with high-volume wafer-scale tools.

[0035] In addition to streamlining process development, an on-wafer lab addresses many of the integration constraints that limit the adoption of advanced materials in semiconductor manufacturing. An on-wafer lab’s ability to apply spatially localized processing allows high- temperature steps such as epitaxial growth, crystallization anneals, or dopant activation to be confined to microscale regions, leaving the surrounding wafer at BEOL-compatible temperatures. This capability enables the backend integration of materials like ferroelectrics and magnetic oxides whose properties depend on high-temperature processing, without exceeding the global BEOL thermal budget. Beyond thermal control, an on-wafer lab may also support in situ electric field application during deposition or annealing (poling), which can influence phase formation and domain orientation in ferroelectric thin films. Furthermore, an on-wafer lab’s architecture facilitates combinatorial plasma exposure, enabling local variation of plasma power and bias across the wafer to systematically screen process windows and assessAttorney Docket No. MIT-26290W001 plasma-material interactions. This approach can help resolve plasma compatibility issues that often emerge during the integration of 2-D materials or low-k dielectrics. In addition, an on- wafer lab enables new modes of selective thin film growth, where localized heating or plasma introduction can spatially induce precursor decomposition or adsorption, effectively eliminating the need for subsequent etch patterning.An Example On-Wafer Lab

[0036] FIGS. 1A-1C illustrate an example on-wafer lab 100 and its integration with different film deposition chambers to enable in situ application of different physical stimuli during film deposition. The on-wafer lab 100 is compatible with various film deposition methods, including but not limited to magnetron sputtering, pulsed laser deposition, thermal or electron beam evaporation, molecular beam epitaxy, chemical vapor deposition, atomic layer deposition; solution processing methods such as inkjet printing; and additive manufacturing methods such as fused deposition modeling. The different physical stimuli that can be provided by the on -wafer lab 100 include but are not limited to heat, electric field, magnetic field, composition or atomic flux gradient, and plasma. For example, the composition of the material being deposited at the different sites on the wafer can be tuned by changing the adsorption of precursors with temperature at each side. Similarly, in CVD, the flux of the material being deposited can be modified by manipulating local temperature gradient to change the gas flow.

[0037] Heat can be supplied by on-chip resistive micro-heaters made of metals or doped semiconductors, electric and magnetic fields by metal or doped semiconductor electrodes, plasma similarly by on-chip electrodes, and atomic flux by varying the local temperature distribution (e.g., with one or more of the resistive micro-heaters) which impacts the gas flow profile (e.g., by controlling convective flows around a resistive micro-heater at an elevated temperature).

[0038] For physical vapor deposition and additive manufacturing methods, high substrate temperature during film deposition is often used to induce formation of a specific structural phase, controlled crystallization, grain growth, defect removal, or impurity rejection to enhance the film quality. For chemical vapor deposition and atomic layer deposition, thermal decomposition of precursors selectively takes place at the heaters. The on-wafer lab 100 can be used to realize selective area growth and patterning of the deposited material without additional etching steps.Attorney Docket No. MIT-26290W001

[0039] The local electric field can affect ferroelectric polarization (poling) and growth orientation of ferroelectric domains. On-chip electrodes can generate strong electric (e.g., > 104V / m) and magnetic fields (e.g., > 1 Tesla) that may be challenging to sustain on the macroscopic scale. Plasma can be used to perform plasma-enhanced deposition locally. The electrodes can also be used to apply local substrate bias voltages, enabling local control of this parameter in processes such as plasma-enhanced deposition and plasma etching. While FIGS. 1 A-1C show a separate structure for applying each stimulus, these structures can be combined in a single location to apply multiple stimuli concurrently to the same location, e.g., as shown in FIG. 2 and described below. These stimuli are driven by voltages applied on the on-chip electrodes.

[0040] FIG. 1A shows the on-wafer lab 100 includes a set of micro-environment controlling units (MECUs) 110-1 through 110-5 (collectively, MECUs 110) integrated with a semiconductor wafer for in situ control of local wafer environments during deposition of material(s) on the wafer. Each MECU 110 have lateral dimensions ranging from a few microns to a few millimeters (e.g., 1 pm, 5 pm, 10 pm, 25 pm, 50 pm, 100 pm, 250 pm, 500 pm, 1 mm, 2.5 mm, 5 mm, or 10 mm). In this case, the semiconductor wafer includes a silicon oxide layer 104 on a silicon substrate 102, but other wafers may include or be made of other materials, including III-V semiconductor compounds. MECU 110-1 includes a resistive micro-heater 111 formed of resistive material on the exposed portion of the wafer coupled to a pair of metal vias 121a and 121b that can be connected to a current source (not shown). Running electrical current through the resistive micro-heater 111 by way of the metal vias 121a and 121b causes Joule heating, enabling local heating of any material deposited on or near the resistive micro-heater 111. The resistive micro-heater 111 can heat the deposition site to temperatures of 350 °C to 800 °C, 900 °C, 1000 °C, or even higher for doped silicon heaters. The temperature of the resistive micro-heater 111 can be measured optically, e.g., by sensing the temperaturedependent shift in frequency of the Raman peak of silicon. These Raman measurements can be used to calibrate the resistive micro-heater’s temperature versus the resistive micro-heater’s resistance, with in situ resistance measurements enabling feedback loop control. The substrate holder can dissipate any excess heat emitted by the resistive micro-heater 111, either by incorporating or acting as a passive heat sink or with active cooling, such as a circulating cooling fluid.

[0041] MECU 110-2 includes a single electrode 112 coupled to a voltage supply 12 by way of another metal via 122 for applying a substrate bias. MECU 110-3 includes a pair of electrodesAttorney Docket No. MIT-26290W001113a and 113b connected by metal vias 123a and 123b, respectively, to another voltage supply (not shown) for applying an electric field roughly parallel to the surface of the wafer. MECU 110-4 includes coils or planar electrodes 114a and 114b connected to metal vias 124a and 124b, respectively, for applying a magnetic field roughly perpendicular to the surface of the wafer. And MECU 110-5 includes radio-frequency (RF) electrodes 115a and 115b coupled to metal vias 125a and 125b, respectively, for applying plasmas to different areas of the wafer.

[0042] The on-wafer lab 100 in FIG. 1A has five different MECUs 110. Other on-wafer labs may have thousands to millions of MECUs, e.g., arranged in a two-dimensional array on a semiconductor wafer. These MECUs may be of different types, as in the on-wafer lab 100 in FIG. 1A, or of the same type — for example, the on -wafer lab may have a two-dimensional array of micro-heaters as described below. Other on-wafer labs may have combinations of different types of MECUs, e.g., some with micro-heaters and others with RF electrodes to apply magnetic fields. The MECUs can be controlled independently or in groups, depending on the control circuitry and the experiment(s) being conducted / parameters being investigated.

[0043] Electrical connections can be made to the on-chip electrodes using packaging techniques including but not limited to wire bonding, ball grid arrays, micro-bumps, or hybrid bonding. The metal vias can be coupled to current or voltage sources on the back side of the wafer, e.g., via a detachable magnetic pin, as shown in FIG. 1C, so that the micro-hear or electrodes can be actuated to apply heat or fields locally while material is deposited on the front side of the wafer.

[0044] Other MECUs may include patterned optical antennas (not shown) that can be used to locally concentrate a light field from an external source to exert local optical excitation. For example, these optical antennas can take the form of or be similar to surface enhanced Raman spectroscopy (SERS) structures. These optical antennas can be used for non-contact optical probing (e.g., Raman spectroscopy) to monitor the film growth process in situ. Alternatively, a waveguide array can be used to apply local optical excitation, e.g., via direct or evanescent coupling of light from the waveguide to the deposition sites / MECUs. Such a waveguide array can include switches that can be actuated to route light among different MECUs for time- multiplexed optical excitation.

[0045] FIGS. IB and 1C show the on-wafer lab 100 in different vacuum deposition chambers 140 and 160, respectively. The vacuum deposition chamber 140 in FIG. IB includes a single source of material to be deposited on the active surface — the surface with the different MECUsAttorney Docket No. MIT-26290W001110 — of the on-wafer lab 100. A ribbon cable 144 that runs through a feedthrough 146 in a wall of vacuum deposition chamber 140 connects the on-wafer lab 100 to a multi-channel source meter 150, which in turn is connected to a computer 152 or other suitable controller. The feedthrough 146 provides a hermetic seal that prevents material from entering the vacuum deposition chamber 140. The ribbon cable 144 provides different electrical connections between the different electrodes of the on-wafer lab 100 and the multi-channel source meter 150. These connections allow the multi-channel source meter 150 and / or computer 152 to control each MECU 110 independently as the source 142 deposits material onto the on-wafer lab 100. Thanks to the MECUs 110, the deposition conditions vary across the active / exposed surface of the on-wafer lab 100, potentially resulting in differences in the final structure(s) formed by the deposited material.

[0046] FIG. 1C shows the on-wafer lab 100 on a rotating stage 161 in the other vacuum deposition chamber 160. Two material sources 162 in the vacuum deposition chamber 160 are used to deposit material on the active / exposed surface of the on -wafer lab 100 as the rotating stage 161 spins the on-wafer lab 100 within the vacuum deposition chamber 160. Electrical wires from the packaged on-wafer lab 100 are connected to an external microcontroller 170 and computer 172 through a hermetic feedthrough 168 on the vacuum deposition chamber 160. A slip ring connector 164 can be used to allow the on-wafer lab 100 to rotate without damaging or entangling the wires as shown in FIG. 1C. If the vacuum deposition chamber 160 has a load lock, the electrical cable can be kept in the vacuum deposition chamber 160 and clipped onto the electrical connectors linked to the on-wafer lab 100 after the on-wafer lab 100 is loaded, for instance, using a detachable magnetic pin connector 166 to facilitate the connection. This way, these parameters of the micro-environments on the active / exposed surface of the on-wafer lab 100 can be adjusted either in situ during film growth or post-deposition to optimize the material quality.

[0047] In both FIGS. IB and 1C, during process development, the heater(s) and / or electrode(s) integrated with the on-wafer lab 100 can be used to perform combinatorial testing of different deposition / processing parameter combinations (e.g., different growth temperatures or electric field strengths and / or orientations) implemented locally at each deposition site or microenvironment. By characterizing the resulting properties of the material across the deposition sites / micro-environments, a large number of growth or processing parameters can be assessed to down select the optimal parameter set through a single deposition experiment, leading to significant savings in labor, cost, time, as well as energy and material consumption. ForAttorney Docket No. MIT-26290W001 example, over 1 million MECUs at a pitch of 100 pm can fit on a single wafer, making it possible to test over 1 million different parameter combinations simultaneously.

[0048] In addition to combinatorial testing of film deposition and processing, heaters and / or electrodes can be used to grow different materials and / or different combinations of materials in different locations on the same on-wafer lab. For example, by heating different portions of the on-wafer lab to different temperatures with different heaters, or by activating plasma only on certain portions of the on-wafer lab, it may be possible to form different “pixels” made of different stacks of materials (e.g., one pixel of materials A-B-A and another pixel of materials A-B-C), where each heater or set of electrodes corresponds to a different pixel.

[0049] Each heater / pixel combination can be surrounded by a trench to limit spreading of the deposited material(s) and provide sharp pixel sidewalls. For example, in an SOI wafer with doped SOI heaters, trenches can be etched all the way to the buried oxide such that the neighboring pixels are not connected by thermally conductive silicon. This enables better control of the temperature of each deposition site. The spread of the material being deposited at each deposition site can also be limited if the precursor adsorbs preferentially on silicon.MECUs for Applying Multiple Stimuli

[0050] FIG. 2 shows an MECU 210 configured to apply multiple stimuli — in this case, heat and an electric field — to a single deposition site, either simultaneously or sequentially. The MECU 210 includes a doped silicon heater 211 with parallel doped regions 215 extending between a pair of electrical contacts 212a and 212b on opposite sides of the doped silicon heater 211. Running current between electrical contacts 212a and 212b through the doped regions 215 causes resistive heating. Another pair of electrical contacts 213a and 213b arranged parallel to the parallel doped regions 215 can be used to apply an electric field across the deposition site (here, the doped silicon heater 211). Care should be taken when designing multi-stimuli control to reduce or minimize interference between the stimuli. In this case, for example, the (conductive) doped regions 215 are patterned into two strips to avoid nullifying the electric field.Controlling an On-Wafer Lab in a Vacuum Deposition Chamber

[0051] FIGS. 3A-3C show different schemes for controlling an on-wafer lab 100 in a (sealed) vacuum deposition chamber. FIG. 3A is a block diagram showing the details of example external controllers for the on -wafer lab 100 in the vacuum deposition chamber 160 of FIG. 1C. Electrical connectors or cables 182 connect the on-wafer lab 100 to a printed circuit boardAttorney Docket No. MIT-26290W001(PCB) 180 via the feedthrough 168 in the wall of the vacuum deposition chamber 160. The PCB 180 connects in turn to the micro-controller 170, a DC voltage source 174, and a function generator 176. The micro-controller 170, DC voltage source 174, and function generator 176 can be implemented as chips that populate the PCB 180 or as discrete devices that are connected to the PCB 180. Either way, they provide electrical power and control signals to the MECUs 110 on the on-wafer lab 100 via the PCB 180 and the electrical connectors 182.

[0052] FIG. 3B illustrates a similar scheme, but with wireless control provided by a wafer holder 302 inside a vacuum deposition chamber 360 that does not feedthroughs. Electrical contacts on the wafer holder 302 electrically connects to electrical contacts the wafer holder 302, which also contains a wireless transceiver (e.g., a Bluetooth or WiFi transceiver) that is wirelessly connected to a compatible wireless transceiver 382 on or coupled to a PCB 380. The on-wafer lab 100 can also incorporate an integrated wireless transceiver 304 that is wirelessly connected to the wireless transceiver 382 as in FIG. 3C. In both cases, the wireless transceivers exchange commands, data, and other signals for carrying out combinatorial material processing with the on-wafer lab 100.An On- Wafer Lab with a 2-D Micro-Heater Array

[0053] FIGS. 4A and 4B illustrate an on-wafer lab 400 with a 2-D array of micro-heaters 410 formed in a single wafer or chip and used for in situ thermal processing during material deposition. Arrays of devices for applying other physical stimuli can be similarly implemented. The resistive micro-heaters 410 can be made of metals or doped semiconductors. When made of doped semiconductor material, each micro-heater 410 can either adopt uni -polar (e.g., assuming a P+-P-P+or N+-N-N+) doping or a PIN structure. The doping profiles of the microheaters 410 can be lithographically defined to generate on-demand temperature distributions across the micro-heaters 410 following an inverse design scheme. Refractory metals (e.g., tungsten plugs) can be used as the contacts. The micro-heaters 410 can be single-use, i.e., used only for in situ heating during film deposition, so some modifications (e.g., dopant diffusion) can be tolerated. Therefore, these micro-heaters 410 can be driven to significantly higher temperatures than their normal temperature range of usage. For example, doped Si single-use micro-heaters can be used to locally heat the wafer to over 1,000 °C with suitably optimized designs.

[0054] For deposition of a thin film with a known desired or optimal substrate temperature, the micro-heaters 410 can be connected in parallel with only two electrical leads such that every micro-heater 410 in the array reaches the same temperature. When the micro-heater array isAttorney Docket No. MIT-26290W001 used for combinatorial exploration to search for optimal substrate temperature during deposition, an active-matrix cross-bar architecture can be used to reduce the number of electrical contacts for connecting n2independently addressed micro-heaters to In (without common ground) or n + 1 (with common ground), where n is an integer greater than 0.

[0055] Each micro-heater 410 may include a uni-polar doped N+-N-N+resistor. Etched trenches can be formed in the wafer between the micro-heaters 410 to suppress thermal crosstalk. This design enables different voltages to be applied to different columns of heaters using a combination of row selectors and switches at the ends of the columns. As an alternative, each (active-matrix array) micro-heater can include a transistor and a resistive micro-heater. In this alternative, each micro-heater can be set to a different voltage / temperature.

[0056] The array of micro-heaters 410 in FIG. 4 A can be fabricated leveraging a standard Si foundry process where two different layers of BEOL metals are used to construct the vertical and horizontal metal wires (row and column lines), respectively. The BEOL dielectrics are then etched to open a window allowing the thin film material to be deposited in direct contact with each micro-heater. One advantage of this fabrication process is that the on-wafer architectures for applying multiple stimuli can be fabricated concurrently along with other CMOS devices, which adds little-to-no cost to existing wafer fabrication processes. Therefore, on-wafer architectures fabricated this way can be used in process development and in high-volume manufacturing processes.

[0057] FIG. 4A shows a top-view optical micrograph of the 2-D heater array taped out by a foundry. A chip containing the micro-heater array (the on-wafer lab 400) can then be mounted and wire bonded to a custom PCB 401 as shown in FIG. 4B. During a deposition run, the entire PCB assembly is loaded into the deposition chamber with the electrical connection provided by a ribbon cable. The temperature at each micro-heater can be controlled from outside the deposition chamber with a multi-channel source meter or through CMOS electronics integrated on the same substrate as the on-wafer lab.Chip-Level On-Wafer Labs (On-Chip Labs)

[0058] High-throughput combinatorial experimentation can be carried out at the chip level in addition to the wafer lab. Chip-scale implementations of an on-wafer lab can be made by dicing die-level chips from full wafers processed in standard CMOS foundries (e.g., as described below). These chip-level on-wafer labs, or on-chip labs, preserve the core architectural principles of on-wafer labs (such as lithographically defined, electrically addressableAttomey Docket No. MIT-26290W001 microstructures integrated into standard CMOS process stacks) while offering practical advantages for early-stage development and testing.

[0059] On-chip labs enable rapid prototyping, streamlined metrology, and compatibility with prototyping tools commonly used in academic and research settings. Moreover, chip-scale implementations are especially useful in many advanced applications. For example, modules designed for massively parallel in situ transmission electron microscopy (TEM) should conform to the stringent spatial constraints of the sample chamber, rendering full-wafer formats infeasible. In such cases, an on-chip lab provides localized process control and high-throughput experimentation within the physical limits of specialized instrumentation.

[0060] FIGS. 5A and 5B illustrate an on-chip lab 500 for high-throughput screening of in situ film growth and post-deposition annealing temperatures in a lab-scale vacuum deposition chamber 520. The on-chip lab 500 is mounted on a ceramic PCB 502 and contains a 2-D array of individually addressable doped silicon micro-heaters 510 fabricated on a silicon-on-insulator (SOI) wafer platform, mounted within a custom-designed ceramic carrier. The on-chip lab 500 and ceramic PCB 502 are certified to be high-vacuum compatible, ensuring seamless integration with standard deposition systems or vacuum / inert-atmosphere chambers.

[0061] The SOI-based micro-heaters 510 have distinct advantages over refractory metal and polysilicon heaters, including: compatibility with standard CMOS foundry processes; improved thermal stability with reduced susceptibility to resistance drift, mechanical deformation, or failure; enhanced temperature uniformity through inverse-designed doping profiles; and compatibility with Si-based electronic and photonic components without contamination or optical loss. Beyond providing localized heating, the micro-heaters 510 function as real-time temperature sensors by leveraging the temperature dependence of their electrical resistance, enabling closed-loop feedback control. Raman thermometry can be used to calibrate the temperatures of the micro-heaters 510, which can operate stably at temperatures exceeding 900 °C. The micro-heaters 510 enable high-temperature processing steps that would otherwise exceed BEOL thermal budgets, e.g., for magnetooptical garnet integration. A heat sink 522 under the ceramic PCB 502 dissipates excess heat emitted by the micro-heaters 510.

[0062] A ribbon cable connected to the on-chip lab 500 passes through a vacuum feedthrough 524 to a custom-built microcomputer 530 (FIG. 5B) located outside the processing environment (vacuum deposition chamber 520), which in turn is connected to and controls a set of function generators 532, with one function generator for each microheater 510 on the on-Attorney Docket No. MIT-26290W001 chip lab 500. A set of voltage amplifiers 534 coupled to the function generators 532 and a voltage source 536 amplifies the outputs of the function generators 532. The ribbon cable connects the voltage amplifiers 534 to respective microheaters 510 inside the vacuum deposition chamber 520. The ribbon cable also connects the microheaters 510 to respective current-voltage sensors 540, which in turn are coupled to data acquisition (DAQ) hardware 542, including analog-to-digital converters, etc. A control computer that is coupled to the DAQ hardware 542 and the microcomputer 530 provides a convenient user interface for managing operation of the micro-heaters 510 during deposition of material on the on-chip lab 500.

[0063] While the on-chip lab 500 provides spatially variable thermal control, its underlying hardware architecture is broadly extensible to other physical modalities, just like the on-chip wafer (e.g., as in FIG. 1A). Its modular multi-channel control system, vacuum-compatible construction, and foundry-processed microscale micro-environment control units provide a generic and scalable foundation for integrating localized electric, magnetic, optical, and plasma control capabilities.On-Wafer Lab Fabrication

[0064] FIG. 6 depicts a fabrication process for making an on-wafer lab or on-chip lab that can apply different stimuli to different deposition sites simultaneously during material deposition. In this fabrication process, micro-environment control units (e.g., heaters and electrodes) are made in a BEOL layer 604 of a silicon-on-insulator (SOI) platform with a buried oxide layer 602 on a silicon substrate 600, without etching trenches into the BEOL layer 604 to expose the micro-environment control units. (The same fabrication process can be implemented on a bulk Si CMOS wafer as well.) Instead, the micro-environment control units are fabricated in the BEOL layer 604 following standard CMOS foundry processes.

[0065] The resulting wafer is then hybrid-bonded (601) to a handler wafer 606 containing Cu redistribution layers (RDLs) and through silicon / glass vias (TSVs / TGVs). The handler wafer 606 acts as both a mechanical support and an electrical input / output (I / O) platform for the electrodes that control the micro-environment control units in the BEOL layer 604. The starting CMOS wafer is then removed through mechanical lapping and / or chemical etching (603), with the buried oxide layer 602 used as an etch stop.

[0066] After removal of the substrate 600 (and the buried oxide 602 when an SOI wafer is used), the doped Si micro-heaters and electrical contacts are exposed from the original wafer back side. This leaves a flat, smooth substrate surface suitable for subsequent film depositionAttorney Docket No. MIT-26290W001 and processing. Next, the handler wafer is thinned (605) to expose the TSVs or TGVs, which can be bonded (607) to a carrier 610 with a ball grid array 608 (or a micro-bump array) for subsequent film deposition and processing. Alternatively, the substrate can be bonded to a wafer or chip containing CMOS electronics to control the “pixel” array.

[0067] The fabrication method shown in FIG. 6 has several advantages over other fabrication methods. Since the electrical I / O interface is on the opposite side of the substrate on which the material integration and processing occur, shading due to electrical wires (e.g., wire bonds) is eliminated. It is also compatible with a high-density electrical I / O scheme with thousands to millions of I / O channels, enabling selective deposition on many deposition sites on a substrate or testing of many processing parameter combinations. The flat substrate surface avoids shadowing effects during deposition caused by uneven surface topology (e.g., etched trenches in BEOL layers to expose the micro-heaters). In addition, the process does not involve removal of the BEOL layers on top of the on-wafer architectures and provides considerably more design flexibility. Since the metal interconnects can run underneath the on-wafer architectures and do not occupy the substrate surface, the fill factor of the pixels (e.g., resistive micro-heaters) can also be much higher. In addition, the frontend CMOS can also be used to provide on-substrate control and distribution of electrical signals to generate diverse varying local process parameters across the entire substrate. Deviations of local parameters (e.g., due to nonuniformity) can also be corrected / compensated using the embedded CMOS control electronics. The on-substrate micro-environment control units can also act as sensors to provide real-time feedback loop control in the correction process. Alternatively, on-substrate CMOS control can also be used to reduce the number of electrical wire connections used to address an array of pixels, such that the number of wire connections can be much lower than the number of pixels.

[0068] In addition to combinatorial testing of film deposition, the on-substrate architectures can also be used to create local environments to perform combinatorial process parameter screening of other semiconductor processes, such as plasma etching, reactive ion etching, oxidation / silicidation, ashing, wet chemical etching, etc.Conclusion

[0069] While various inventive embodiments have been described and illustrated herein, those of ordinary skill in the art will readily envision a variety of other means and / or structures for performing the function and / or obtaining the results and / or one or more of the advantages described herein, and each of such variations and / or modifications is deemed to be within the scope of the inventive embodiments described herein. More generally, those skilled in the artAttorney Docket No. MIT-26290W001 will readily appreciate that all parameters, dimensions, materials, and configurations described herein are meant to be exemplary and that the actual parameters, dimensions, materials, and / or configurations will depend upon the specific application or applications for which the inventive teachings is / are used. Those skilled in the art will recognize or be able to ascertain, using no more than routine experimentation, many equivalents to the specific inventive embodiments described herein. It is, therefore, to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, inventive embodiments may be practiced otherwise than as specifically described and claimed. Inventive embodiments of the present disclosure are directed to each individual feature, system, article, material, kit, and / or method described herein. In addition, any combination of two or more such features, systems, articles, materials, kits, and / or methods, if such features, systems, articles, materials, kits, and / or methods are not mutually inconsistent, is included within the inventive scope of the present disclosure.

[0070] Also, various inventive concepts may be embodied as one or more methods, of which an example has been provided. The acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.

[0071] All definitions, as defined and used herein, should be understood to control over dictionary definitions, definitions in documents incorporated by reference, and / or ordinary meanings of the defined terms.

[0072] The indefinite articles “a” and “an,” as used herein in the specification and in the claims, unless clearly indicated to the contrary, should be understood to mean “at least one.”

[0073] The phrase “and / or,” as used herein in the specification and in the claims, should be understood to mean “either or both” of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases. Multiple elements listed with “and / or” should be construed in the same fashion, i.e., “one or more” of the elements so conjoined. Other elements may optionally be present other than the elements specifically identified by the “and / or” clause, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, a reference to “A and / or B”, when used in conjunction with open-ended language such as “comprising” can refer, in one embodiment, to A only (optionally including elements other than B); in another embodiment, to B onlyAttorney Docket No. MIT-26290W001(optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); etc.

[0074] As used herein in the specification and in the claims, “or” should be understood to have the same meaning as “and / or” as defined above. For example, when separating items in a list, “or” or “and / or” shall be interpreted as being inclusive, i.e., the inclusion of at least one, but also including more than one, of a number or list of elements, and, optionally, additional unlisted items. Only terms clearly indicated to the contrary, such as “only one of’ or “exactly one of,” or, when used in the claims, “consisting of,” will refer to the inclusion of exactly one element of a number or list of elements. In general, the term “or” as used herein shall only be interpreted as indicating exclusive alternatives (i.e. “one or the other but not both”) when preceded by terms of exclusivity, such as “either,” “one of,” “only one of,” or “exactly one of.” “Consisting essentially of,” when used in the claims, shall have its ordinary meaning as used in the field of patent law.

[0075] As used herein in the specification and in the claims, the phrase “at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements. This definition also allows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase “at least one” refers, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, “at least one of A and B” (or, equivalently, “at least one of A or B,” or, equivalently “at least one of A and / or B”) can refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another embodiment, to at least one, optionally including more than one, B, with no A present (and optionally including elements other than A); in yet another embodiment, to at least one, optionally including more than one, A, and at least one, optionally including more than one, B (and optionally including other elements); etc.

[0076] In the claims, as well as in the specification above, all transitional phrases such as “comprising,” “including,” “carrying,” “having,” “containing,” “involving,” “holding,” “composed of,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases “consisting of’ and “consisting essentially of’ shallAttorney Docket No. MIT-26290W001 be closed or semi-closed transitional phrases, respectively, as set forth in the United States Patent Office Manual of Patent Examining Procedures, Section 2111.03.

Claims

Attorney Docket No. MIT-26290W001CLAIMS1. A method of fabricating a semiconductor device, the method comprising: while depositing material on a semiconductor substrate, applying a first physical stimulus to a first section of a front side of the semiconductor substrate with a first device embedded in the semiconductor substrate and applying a second physical stimulus different than the first physical stimulus to a second section of the front side of the semiconductor substrate with a second device embedded in the semiconductor substrate, wherein applying the first physical stimulus is in response to a first electrical signal applied to the first device through an electrical input / output layer formed on a back side of the semiconductor substrate and a first via connecting the electrical input / output layer to the first device, wherein applying the second physical stimulus is in response to a second electrical signal applied to the second device through the electrical input / output layer and a second via connecting the electrical input / output layer to the second device.

2. The method of claim 1, wherein: the first device is a first heater and applying the first physical stimulus to the first section of the semiconductor substrate comprises heating the first section of the semiconductor substrate to a first temperature with the first heater, and the second device is a second heater and applying the second physical stimulus to the second section of the semiconductor substrate comprises heating the second section of the semiconductor substrate to a second temperature different than the first temperature with the second heater.

3. The method of claim 2, wherein the first temperature is at least 350 °C.

4. The method of claim 1, wherein the first device comprises at least one electrode and applying the first physical stimulus to the first section of the semiconductor substrate comprises applying a bias voltage to the first section of the semiconductor substrate.

5. The method of claim 1, wherein the first device comprises at least one pair of electrodes and applying the first physical stimulus to the first section of the semiconductor substrate comprises applying an electric field to the first section of the semiconductor substrate.Attorney Docket No. MIT-26290W0016. The method of claim 1, wherein the first device comprises at least one pair of planar electrodes or a coil and applying the first physical stimulus to the first section of the semiconductor substrate comprises applying a magnetic field to the first section of the semiconductor substrate.

7. The method of claim 1, wherein the first device comprises at least one pair of radiofrequency electrodes and applying the first physical stimulus to the first section of the semiconductor substrate comprises applying a plasma to the first section of the semiconductor substrate.

8. The method of claim 1, wherein applying the first physical stimulus is independent of applying the second physical stimulus.

9. A semiconductor substrate comprising: an array of micro-environment controlling units, integrated with a front side of the semiconductor substrate, to apply physical stimuli to different regions of the semiconductor substrate during deposition of material on the front side of the semiconductor substrate; an electrical input / output layer formed on a back side of the semiconductor substrate; and vias, connecting the electrical input / output layer to the array of micro-environment controlling units, to conduct electrical signals from the electrical input / output layer to the array of micro-environment controlling units during deposition of material on the front side of the semiconductor substrate.

10. The semiconductor substrate of claim 9, wherein the array of micro-environment controlling units comprises at least one resistive micro-heater for heating a corresponding region of the semiconductor substrate.

11. The semiconductor substrate of claim 10, wherein the at least one resistive microheater is configured to heat the corresponding region to at least 350 °C.

12. The semiconductor substrate of claim 10, wherein the at least one resistive microheater is a single-use heater.Attorney Docket No. MIT-26290W00113. The semiconductor substrate of claim 9, wherein the array of micro-environment controlling units comprises a two-dimensional array of individually controllable resistive micro-heaters.

14. The semiconductor substrate of claim 9, wherein the array of micro-environment controlling units comprises at least one electrode for applying a bias voltage to a corresponding region of the semiconductor substrate.

15. The semiconductor substrate of claim 9, wherein the array of micro-environment controlling units comprises at least one pair of electrodes for applying an electric field to a corresponding region of the semiconductor substrate.

16. The semiconductor substrate of claim 9, wherein the array of micro-environment controlling units comprises at least one pair of planar electrodes or a coil for applying a magnetic field to a corresponding region of the semiconductor substrate.

17. The semiconductor substrate of claim 9, wherein the array of micro-environment controlling units comprises at least one pair of radio-frequency electrodes for applying a plasma to a corresponding region of the semiconductor substrate.

18. A system comprising: a vacuum deposition chamber; the semiconductor substrate of claim 9 disposed in the vacuum deposition chamber; and a controller, operably coupled to the electrical input / output layer of the semiconductor substrate, to control the micro-environment controlling units before, during, and / or after the deposition of the material on the front side of the semiconductor substrate.

19. The system of claim 18, wherein the semiconductor substrate is disposed on a rotation stage and the controller is operably coupled to the electrical input / output layer via a cable passing through a slip ring.

20. A method of fabricating an apparatus for combinatorial testing of semiconductor device fabrication techniques, the method comprising: forming an array of micro-environment controlling units in a front side of complementary metal-oxide-semiconductor (CMOS) wafer;Attorney Docket No. MIT-26290W001 bonding the array of micro-environment controlling units formed in the front side of the CMOS wafer to redistribution layers and / or vias exposed on a front side of a handler wafer; removing at least a portion of a back side of the CMOS wafer to expose the array of micro-environment controlling units; removing at least a portion of a back side of the handler wafer to expose the redistribution layers and / or vias; and bonding a carrier to the back side of the handler wafer.

Images