Heterogeneous integration of programmable optical interconnect

Abstract

A device includes a substrate; a laser chiplet supported by the substrate; a comb generator chiplet supported by the substrate and in optical communication with the laser chiplet; an optical switch chiplet supported by the substrate and in optical communication with the comb generator chiplet; and a glass layer supported by the substrate and comprising one or more waveguides, at least one of the waveguides optically connecting the comb generator chiplet to the optical switch chiplet. The laser chiplet, the comb generator chiplet, the optical switch chiplet, and the glass layer lie in a common plane.

Description

[0001] Attorney Ref.: 56403-0026W01

[0002] HETEROGENEOUS INTEGRATION OF PROGRAMMABLE OPTICAL

[0003] INTERCONNECT

[0004] Claim of Priority

[0005] This application claims priority' to U.S. Patent Application No. 63 / 737,357 filed on December 20. 2024, the entire contents of which are hereby incorporated by reference.

[0006] Background

[0007] Industry demands for machine learning and generative artificial intelligence (GenAI) have guided recent development in data centers, such as increased memory' bandwidths and connectivity and reduced energy requirements. Some architectures rely on disaggregation, in which various computing components, e.g., graphics processing unit (GPU), central processing unit (CPU), application specific integrated circuit (ASIC), and memory, are separated, pooled, and interconnected with ultrahigh- bandwidth interconnections using large radix optical switching elements.

[0008] Current approaches to optical switch fabrication are typically based on large micro-electronics mechanical system (MEMS) mirror technology, which can meet performance targets. However, MEMS mirror technology' tends to be bulky7, doesn’t scale in volume or silicon photonics platforms that scale in volume, and suffers from high optical losses, thereby limiting performance scaling of Al clusters.

[0009] Traditionally, heterogeneous integration of optical chiplets has faced challenges due to high insertion losses at interfaces between chiplets and lasers, which limits performance. For example, optical chiplet interfaces are sensitive to misalignment and generally need sub-micron precision in X, Y, Z and angular axes placement to have low loss and high performance characteristics.

[0010] Summary

[0011] The disclosed devices and methods avoid the drawbacks of conventional technology by providing an optical interface between every pair of a laser source, electronic chiplet, optical chiplet, and optical waveguide (OWG) chiplets. The interface can include waveguides that directly connect one chiplet to another. The optical interface is compatible with bonding tolerances, e.g., meets sub-micron Attorney Ref.: 56403-0026W01 precision. Additionally, the devices and methods leverage sub-micron precision of advanced packaging processes like die-to-wafer, wafer-to-wafer bonding, and hybrid bonding, which can support input / output (I / O) bump pitches of less than 10 mm.

[0012] The disclosed devices feature wafer / panel scale integration of heterogeneous chiplets including III-V semiconductor light sources and amplifiers, thermo-electric coolers, optical chiplets for multi-wavelength generation, e.g., frequency comb generation, high density wavelength filtering and / or switching, data modulation and detection, electronic chiplets for programming Al fabric control plane and controlling the optical chiplets and glass substrates for low loss data transmission and metal routing. The disclosed approaches can at least partially overcome the trade-off between performance and manufacturability by leveraging high-performance glass and using an end-to-end manufacturable panel / wafer level integration process flow. Additionally, the disclosed devices can function even when individual on-chip lasers fail, providing improved reliability.

[0013] The disclosed devices provide programmable silicon photonic chiplet integration within a wafer-level / panel-level processing of semiconductor ecosystem, including semiconductor fabrication, assembly, electrical and optical interfaces, and light sources. The disclosed manufacturing capabilities further enable a new generation of semiconductor scaling by addressing one of the major challenges of scaling chiplet- based platforms to large form factors, which creates an energy-efficient, cost-effective, and distance-independent communication channel that uniformly j oins both local and remote chiplets.

[0014] The disclosed methods enable packaging manufacturing, providing programmable photonics chiplet integration. This integration can allow for energy efficient data centers. For example, the disclosed methods can be used to manufacture photonics connectors that fall under Area 3 of U.S. Department of Commerce, NIST, National Advanced Packaging Manufacturing Program (NAPMP) Advanced Packaging Research and Development (R&D) NAPMP NOFO 2.

[0015] Advantageously, the disclosed devices and techniques can provide precise alignment by co-optimizing heterogeneous optical chiplet interface design and assembly process development.

[0016] Brief Description of Drawings Attorney Ref.: 56403-0026W01

[0017] FIG. 1A depicts a schematic of an example of a disaggregated system.

[0018] FIG. IB depicts a schematic of a module from the system FIG. 1 A.

[0019] FIG. 1C depicts a cross-sectional view of an example of the module from FIG.

[0020] IB.

[0021] FIG. ID depicts a cross-sectional view of another example of the module from FIG. IB.

[0022] FIGS. 2A, 2B, 2C, 2D, and 2E depict steps in the process of manufacturing the module of FIG. IB.

[0023] FIGS. 3A and 3B depict alternate examples of processes of performing steps depicted in FIGS. 2A, 2B, 2C, 2D, and 2E.

[0024] FIG. 4 is a flowchart depicting an example of a process for manufacturing a module.

[0025] Detailed Description

[0026] With reference to FIG. 1A. a system 100 includes “all-to-all” connectivity between modules 102, processors 104, and memory module 106. In other words, each module 102 is connected to every processor 104 and memory module 106 through a respective fiber connection 108, and each processor 104 and memory' module 106 is connected to every module 102 through a respective fiber connection 108. In this arrangement, the cluster of processors 104 and memory modules 106 are disaggregated and connected via modules 102.

[0027] Each module 102 includes an optical switch and a laser source. The optical switch includes a heterogeneous integrated programmable optical interconnect. Each processor 104 and memory module 106 include a respective photonic connector 110. which can conform to one or more standard connector technologies, such as to National advanced packaging Manufacturing program (NAP MP) standards.

[0028] FIG. IB depicts a schematic of the module 102 from system 100 from a planar view. Each module 102 is a device that includes a substrate 112 and a layer 113 supported by the substrate 112 and including a heterogeneous electro-optic layer and a glass layer. Optionally, the module 102 includes a glass lid 115 overlying the layer 113. Advantageously, the entire module 102 can fit on a single substrate.

[0029] The heterogeneous electro-optic layer includes multiple laser chiplets 114, multiple comb generator chiplets 116 optically coupled to the laser chiplets 114 Attorney Ref.: 56403-0026W01 through optical waveguides 118, and optical switch chiplet 120 optically coupled to the comb generator chiplets 116 via optical waveguides 122.

[0030] The optical waveguides 122 are optically coupled to the fiber connections 108 to connect each module 102 to each processor 104 and each memory modules 106. The glass layer can include the waveguides 118 and 122. A thermo-electric chiplet 127 can be stacked on each laser chiplet 114 for thermal management of high-power density laser sources in laser chiplet 114. For example, the thermos-electric chiplet 127 can maintain a constant temperature for the laser chiplet 114 to stabilize laser radiation generation.

[0031] Each optical connection 128 couples a respective laser chiplet 114 to a different, respective comb generator chiplet 116. In this way, each laser chiplet 114 has its own respective optical interface. As will be discussed in relation to FIG. 2E, each optical connection can be formed to minimize insertion loss between the laser source on the laser chiplet and the rest of the device. Additionally, each comb generator chiplet 116 is connected to every optical switch chiplet 120 through a combination of the waveguides 118 and redistribution layers surrounding the substrate 112 beneath. Similarly, each optical switch chiplet 120 is connected to all of the output ports 108a for the fiber connections 108 for a given module 102 through a combination of the waveguides 122 and redistribution layers surrounding the substrate 112 beneath. These connections, e.g., the all-to-all connection between the comb generator chiplets 116 and optical switch chiplets 120 and the all-to-all connection between the optical switch chiplets 120 and input ports 108a, enable various types of communication within system 100, such as broadcasting. By using waveguides 118 and 122 to enable this all- to-all communication, the transmission quality of optical signals can be higher compared to MEMS mirror technology. This is because the waveguides 118 and 122 can be deposited with high precision.

[0032] In some implementations, the laser chiplets 114 can generate optical signals at the same wavelength. In this case, the frequency comb generator chiplets 116 can generate substantially similar frequency combs from similar input optical signals from the laser chiplets 114. Since there are multiple laser sources in each module 102 that can generate optical signals at the same wavelength and each laser chiplet 114 is in optical communication with each optical switch chiplet, module 102 provides beneficial redundancy that allows full capability even when a laser source in an Attorney Ref.: 56403-0026W01 individual laser chipl et 114 fails. This provides reliability for module 102, as laser chiplets including III V semiconductor laser sources can be more likely to fail compared to other components in the module 102.

[0033] FIG. 1C depicts a cross-sectional view of a module 102a, which is an example of a module 102 in system 100. In this example, a substrate 112a is a glass substrate including through glass vias (TGVs) 124, which electrically connect a redistribution layer (RDL) 125a on a first side 112x of the substrate 112a to an RDL 125b on a second side 112y of the substrate 112a opposite the first side 112x. Thus, the RDL 125b is between the substrate 112a and the heterogeneous electro-optic layer of layer 113a. The RDLs 125a and 125b can provide power to the chiplets in the heterogeneous electro-optic layer and provide electrical connection between electrical chiplets in the heterogeneous electro-optic layer.

[0034] The layer 113a includes the heterogeneous electro-optic layer, e.g., including a laser chiplet 114, a comb generator chiplet 116, and an optical switch chipl et 120, and the glass layer, e.g., including waveguides 118, 122. and 126, in a common plane. The laser chiplet 114 can generate an optical signal, which is transmitted to the comb generator chiplet 116 through an optical connection 128, e g., an optical waveguide or a micro-optical element, such as a three-dimensional (3D) printed lens or photonic wire bond. The comb generator chiplet 116 receives the optical signal from the laser chiplet 114 and generates optical signals with wavelengths different from that of the received optical signal. Waveguides 118 carry the generated optical signals with different wavelengths to the optical switch chiplet 120, which modulates the generated optical signals.

[0035] The waveguide 122 in the glass layer includes a port 119a, which can be shaped like a triangular notch and configured to redirect optical signals traveling in a horizontal direction, e.g., the X direction, through the waveguides 122 upward to glass lid 115a. The redirected optical signals 130 then encounter another port 119b in the glass lid 115a, which can be shaped like a triangular notch and configured to redirect the optical signals from an upward direction, e.g., the Z direction, to a horizontal direction, e.g., the X direction, in order to couple with the fiber connection 108. In some implementations, the ports 119a and 119b are mirror coated.

[0036] The laser chiplet 114 includes a laser source, e.g., a III-V semiconductor laser. In some implementations, the laser chiplet 114 includes an amplifier. The comb Attorney Ref.: 56403-0026W01 generator chiplet 116 can include one or more ring resonators for generating a frequency comb with laser emission from the laser chiplet 114. For example, the comb generator chiplet 116 can one of the wavelength generators of U.S. Patent Application No. 2024 / 0272364 Al, which is hereby incorporated by reference in its entirety.

[0037] At least one of the comb generator chiplet 116 and the optical switch chiplet 120 can be a silicon photonics chiplet. In some implementations, the comb generator chiplet 116 is a multi-wavelength optical source generator. In some implementations, the optical switch chiplet 120 provides high density modulation and conversion of electrical to optical data (and vice versa), wavelength selective switching, and filtering. In some limitations, the glass lid 115a includes microfluidic channels 117 for cooling the heterogeneous electro-optic layer.

[0038] FIG. ID depicts a cross-sectional view of a module 102b, which is another example of a module 102 in system 100. In this example, substrate 112b can be a glass, silicon, or a reconfigured and molded wafer. Through vias 132 extends through the substrate 112b. The through vias 132 can include through-glass vias, through- sihcon vias, and through-mold vias, depending on the surrounding material. One or more embedded chipl ets 134 are embedded in the substrate 112b.

[0039] Similarly to module 102a, module 102b includes RDLs 125a and 125b on each side of the substrate. Module 102b further includes another RDL 125c on a side of the layer 113b opposite RDL 125b. The RDL 125c is between the layer 113b and glass lid 1 15b. The glass layer in module 102b includes through vias 132, extending through the glass layer and from RDL 125b to RDL 125c. Each of substrates 112a and 112b can be a glass-based platform with through-glass vias and connected to metal RDLs to provide electrical routing layers between the various chiplets.

[0040] In some implementations, the glass lid 115b is a wafer embedded with devices, e.g., the thermo-electric chiplet 127, a control application specific integrated circuit (ASIC), microfluidic, and a fiber connection. Although the thermo-electric chiplet 127 does not directly contact the laser chiplet 114, the thermo-electric chiplet 127 is still disposed above the laser chiplet 114 and can cool the laser source during operation.

[0041] In addition to ports 119a and 119b, module 102c includes a lens receptacle 119c for out-coupling optical signals modulated by the optical switch chiplet 120 to the fiber connection 108. The lens receptacle 119c can modify the size of the out coupled optical signals to improve coupling efficiency with the fiber connection 108. Attorney Ref.: 56403-0026W01

[0042] The process of forming either of modules 102a or 102b involves wafer and / or panel scale integration of heterogeneous components of different substrate materials with various functions. With reference to FIGS. 2A-2E, 3 A, and 3B, this process can be broken dow n into multiple stages, where different steps can happen in series or in parallel. FIG. 3 A represents the process when the step depicted in FIG. 2B follow s the step depicted in FIG. 2A. FIG. 3B represents the process when the step depicted in FIG. 2C follows the step depicted in FIG. 2A. Neither process 300a nor process 300b includes the steps depicted in both FIGS. 2B and 2C.

[0043] With reference to FIG. 2A, the process includes designing and singulation of the laser chiplet 114, an electric and / or optical (E / O) chiplet 129, and the thermoelectric chiplet 127. In some implementations, forming the E / O chiplet 129 can include stacking an electronic integrated circuit (EIC) and silicon photonic chiplet to form either of the comb generator chiplet 116 or the optical switch chiplet 120. In some implementations, the EICs include control electronics for optical components and network / fabric control for memory and accelerator access. The EICs can generate high-speed electrical data streams.

[0044] With reference to FIG. 3A, the design and singulation can occur in a first stage 310a of a process 300a. For example, within the first stage 310a, processing the laser chiplet 114, singulation of the thermo-electric chiplet 127, and singulation of the comb generator chiplet 116 and optical switch chiplet 120 can occur at different times or in parallel. Generally, any combination of steps in the same stage in FIGS. 3A and 3B can be performed at different times or in parallel.

[0045] After forming the laser chiplet 114 and the thermo-electric chiplet 127, the laser chiplet 114 and the thermo-electric chiplet 127 can be three dimensionally stacked, e.g., in a die stacking process. Individual components of the comb generator chiplet 116 and optical switch chiplet 120 can also be three dimensionally stacked during first stage 310a. The first stage 310b of process 300b is generally similar to the first stage 310a.

[0046] With reference to FIG. 2B, in some implementations, the process continues with forming a glass layer 133 on the substrate 112a. The glass layer 133 includes glass substrate (GS) wafers for optical routing, optical coupling, and electrical routing between the chiplets. The glass layer 133 can provide low-loss waveguiding and optical routing layers between the various chiplets. Attorney Ref.: 56403-0026W01

[0047] The process also includes forming a glass lid 115, which functions as a thermal and optical connector (TOC) wafer / panel. For example, as a glass-based platform, the glass lid 115 can include integrated micro-fluidics for thermal cooling and micromirrors. The glass lid 115 can include lens receptacle 119c, e.g., a V groove, and other precision mechanical features for optical coupling to the fiber connection 108.

[0048] With reference to FIG. 3A, when the step depicted in FIG. 2B follows the step depicted in FIG. 2A, the second stage 320a includes forming microfluidic channels 117 in the glass lid 115. Waveguides 118, 122, and 126 and port 119b are formed in the glass layer 133. Optionally, through vias 132 are formed in the glass layer 133. RDLs 125a and 125b are formed on the substrate 112, and through vias, e.g., TGV 124 or through vias 132, are formed through the substrate 112.

[0049] Then, in a third stage 330a of process 300a, bonding between the substrate 112 and the glass layer 133 can occur to form the module in FIG. 2D. During the third stage 330a, a die-to-wafer bonding process can be used to attach the laser chiplet 114 to the thermo-electric chiplet 127, as well as attach the comb generator chiplet 116 and the optical switch chiplet 120 to the substrate 112.

[0050] In the step depicted in FIG. 2D, the alignment between the waveguides 118, 122, and 126 can be very' precise, e.g., sub-micron, relative to the chiplets, e.g., laser chiplet 114, comb generator chiplet 116, and the optical switch chiplet 120. This is because wafer-to-wafer bonding can generally be a high-precision process.

[0051] Alternatively, the step depicted in FIG. 2C can follow the step depicted in FIG. 2A. For example, in the second stage 320b of FIG. 3B, the comb generator chiplet 116, the optical switch chiplet 120, and the thermo-electric chiplet 127 are bonded to the substrate 112a, e.g., using three-dimensional heterogeneous integration (3DHI) die to wafer processing. The 3DHI die to wafer processing enables high-performance and high-density silicon stacks.

[0052] Then, in the third stage 330b, the waveguides 118, 122, and 126 undergo wafer-to-wafer bonding with the chiplets. This bonding establishes optical routing between the chiplets. This bonding yields the module of FIG. 2D.

[0053] In both processes 300a and 300b, the step depicted in FIG. 2E follows the step depicted in FIG. 2D. To reduce, e.g., minimize, impedance mismatch at the optical interface between the laser chiplet 114 and the comb generator chiplet 116, an optical connection 128, e.g.. a waveguide, can be formed through an optical routing layer Attorney Ref.: 56403-0026W01 deposition in the cavity between the laser chi let 114 and the comb generator chiplet 116. In process 300a or process 300b, this step corresponds to a fourth stage 340a or 340b, respectively. Additionally, the laser chiplet 114 couples to the comb generator chiplet 116, and the comb generator chiplet 116 couples to the optical switch chiplet 120 in the fourth stages 340a and 340b.

[0054] With reference to FIG. 1C again, following deposition of optical connection 128, the glass lid 115a can be bonded to the layer 113a. This bonding can include wafer-to-wafer or die-to-wafer bonding of the glass layer to glass lid 115. This bonding can allow thermal cooling and optical coupling out from the waveguides to the fiber connection 108. In either process 300a or process 300b, this step corresponds to a fifth stage 350a or 350b. respectively.

[0055] The fifth stages 350a and 350b include additional steps, as well. For example, the fifth stages 350a and 350b can include singulating the assembly into multiple units, e.g., to form multiple modules 102. Additionally, the fifth stages 350a and 350b can include completing off-package optical interconnects with a fiber-array-unit (FAU) connector attached. The fifth stage 350a can include completing off-package electrical interconnect with a land grid array (LGA) socket.

[0056] FIG. 4 is a flow diagram of an example process 400 for forming a device, e.g., a module 102. The process 400 can correspond to either process 300a or process 300b.

[0057] The process 400 includes mounting a silicon photonics chiplet with a photonic port on a substrate including a glass substrate layer (410). In some implementations, the silicon photonics chiplet includes a comb generator chiplet or an optical switch chiplet. For example, step 410 can correspond to FIG. 2C, where laser chiplet 114, comb generator chiplet 116, and optical switch chiplet 120 are mounted on substrate 112a.

[0058] The process includes mounting a glass layer including a waveguide on the substrate (420). For example, step 420 can correspond to FIG. 2D, where the glass layer including waveguides 118, 122 and 126 are mounted on the substrate 112a.

[0059] The order of steps in the process 400 described above is illustrative only, and the order of the steps can be reversed. For example, similarly to process 300a, step 420 can occur before step 410, as depicted in FIG. 2B, in which the glass layer including waveguides 118, 122 and 126 are mounted on the substrate 112a. In this case, step 410 Attorney Ref.: 56403-0026W01 corresponds to FIG. 2D, when the laser chiplet 114, comb generator chiplet 116, and optical switch chiplet 120 are mounted on substrate 112a.

[0060] In some implementations, the process 400 can include additional steps, or some of the steps can be divided into multiple steps. For example, the process 400 can further include mounting the laser chiplet 114 and / or additional silicon photonics chiplets on the substrate (415). In some cases, this leads to both a comb generator chiplet and an optical switch chiplet being mounted on the substrate.

[0061] In some implementations, the process 400 further includes forming an optical connection, e.g., optical connection 128, between the laser chiplet and the silicon photonics chiplet (425).

[0062] In some implementations, the process 400 further includes attaching a glass lid to the silicon photonics chiplet and the glass layer (435). The glass lid, e.g., glass lid 115, can include channels for microfluidics.

[0063] In some implementations, the substrate includes an RDL, and the silicon photonics chiplet is mounted on the RDL. In some implementations, the glass substrate layer includes one or more through glass vias electrically connecting a first RDL, e.g., RDL 125, on one side of the glass substrate layer to a second RDL, e.g., RDL 125b, on an opposite side of the glass substrate layer.

[0064] In addition to the embodiments of the attached claims and the embodiments described above, the following numbered embodiments are also innovative.

[0065] Embodiment 1 is a device including: a substrate; a laser chiplet supported by the substrate; a comb generator chiplet supported by the substrate and in optical communication with the laser chiplet; an optical switch chiplet supported by the substrate and in optical communication with the comb generator chiplet; and a glass layer supported by the substrate and including one or more waveguides, at least one of the waveguides optically connecting the comb generator chiplet to the optical switch chiplet. The laser chiplet, the comb generator chiplet, the optical switch chiplet, and the glass layer lie in a common plane.

[0066] Embodiment 2 is the device of embodiment 1, further including a glass lid overlying the glass layer.

[0067] Embodiment 3 is the device of embodiment 2, where the glass lid includes microfluidic channels for cooling the laser chiplet. Attorney Ref.: 56403-0026W01

[0068] Embodiment 4 is the device of embodiment 2, the glass lid includes one or more ports for connecting the device to one or more optical fibers.

[0069] Embodiment 5 is the device of embodiment 1, the glass layer is a first glass layer, and the substrate includes a second glass layer.

[0070] Embodiment 6 is the device of embodiment 5, where the second glass layer includes one or more through glass vias.

[0071] Embodiment 7 is the device of embodiment 6, the substrate includes a first redistribution layer (RDL) between the second glass layer and the first glass layer and a second RDL opposite the first RDL.

[0072] Embodiment 8 is the device of embodiment 7, further including a third RDL disposed on a first surface of the first glass layer. The first RDL is disposed on a second surface of the first glass layer opposite the first surface.

[0073] Embodiment 9 is the device of embodiment 1, where the laser chiplet includes a III-V semiconductor laser.

[0074] Embodiment 10 is the device of embodiment 1, where the comb generator chiplet includes one or more ring resonators for generating a frequency comb with laser emission from the laser chiplet.

[0075] Embodiment 11 is the device of embodiment 1 , where at least one of the comb generator chiplet or the optical switch chiplet is a silicon photonics chiplet.

[0076] Embodiment 12 is the device of embodiment 1, further includes a thermoelectric chiplet stacked on the laser chiplet.

[0077] Embodiment 13 is a method including: mounting a silicon photonics chiplet with a photonic port on a substrate including a glass substrate layer; and mounting a glass layer including a waveguide on the substrate. Mounting the silicon photonics chiplet and the glass layer includes aligning the waveguide with a photonics port with sufficient precision to couple an optical signal betw een the photonics port and the waveguide.

[0078] Embodiment 14 is the method of embodiment 13, where the silicon photonics chiplet is a comb generator chiplet or an optical switch chiplet.

[0079] Embodiment 15 is the method of embodiment 13, further including mounting a laser chiplet on the substrate.

[0080] Embodiment 16 is the method of embodiment 15, further including forming an optical waveguide between the laser chiplet and the silicon photonics chiplet. Attorney Ref.: 56403-0026W01

[0081] Embodiment 17 is the method of embodiment 13, further including attaching a glass lid to the silicon photonics chiplet and the glass layer, the glass lid including channels for microfluidics.

[0082] Embodiment 18 is the method of embodiment 13, further including mounting additional silicon photonics chiplets on the substrate.

[0083] Embodiment 19 is the method of embodiment 13, where the substrate includes an RDL and the silicon photonics chiplet is mounted on the RDL.

[0084] Embodiment 20 is the method of embodiment 13, where the glass substrate layer includes one or more through glass vias electrically connecting a first RDL on one side of the glass substrate layer to a second RDL on an opposite side of the glass substrate layer.

[0085] In some implementations, at least some of the chiplets in the module are replaced with a more general photonic integrated circuit configured for a particular purpose, e.g., laser radiation generation, frequency comb generation, or optical switching.

[0086] While this specification contains many specific implementation details, these should not be construed as limitations on the scope of what is being claimed, which is defined by the claims themselves, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially be claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claim may be directed to a subcombination or variation of a subcombination.

[0087] Similarly, while operations are depicted in the drawings and recited in the claims in a particular order, this by itself should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system modules and components in the embodiments Attorney Ref.: 56403-0026W01 described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products. Particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve desirable results. As one example, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results.

Claims

Attorney Ref.: 56403-0026W01What is claimed is:

1. A device, comprising: a substrate; a laser chiplet supported by the substrate; a comb generator chiplet supported by the substrate and in optical communication with the laser chiplet; an optical switch chiplet supported by the substrate and in optical communication with the comb generator chiplet; and a glass layer supported by the substrate and comprising one or more waveguides, at least one of the waveguides optically connecting the comb generator chiplet to the optical switch chiplet, wherein the laser chiplet, the comb generator chiplet, the optical switch chiplet, and the glass layer lie in a common plane.

2. The device of claim 1, further comprising a glass lid overlying the glass layer.

3. The device of claim 2, wherein the glass lid comprises microfluidic channels for cooling the laser chiplet.

4. The device of claim 2, wherein the glass lid comprises one or more ports for connecting the device to one or more optical fibers.

5. The device of claim 1, wherein the glass layer is a first glass layer, and the substrate comprises a second glass layer.

6. The device of claim 5, wherein the second glass layer comprises one or more through glass vias.

7. The device of claim 6, wherein the substrate comprises a first redistribution layer (RDL) between the second glass layer and the first glass layer and a second RDL opposite the first RDL, wherein the one or more through glass vias connect the first and second RDLs.Attorney Ref.: 56403-0026W018. The device of claim 7, further comprising a third RDL disposed on a first surface of the first glass layer, wherein the first RDL is disposed on a second surface of the first glass layer opposite the first surface.

9. The device of claim 1, wherein the laser chiplet comprises a III-V semiconductor laser.

10. The device of claim 1, wherein the comb generator chiplet comprises one or more ring resonators for generating a frequency comb with laser emission from the laser chiplet.

11. The device of claim 1, wherein at least one of the comb generator chiplet or the optical switch chiplet is a silicon photonics chiplet.

12. The device of claim 1, further comprises a thermo-electric chiplet stacked on the laser chiplet.

13. A method, comprising: mounting a silicon photonics chiplet with a photonic port on a substrate comprising a glass substrate layer; and mounting a glass layer comprising a waveguide on the substrate, wherein mounting the silicon photonics chiplet and the glass layer comprises aligning the waveguide with a photonics port with sufficient precision to couple an optical signal between the photonics port and the waveguide.

14. The method of claim 13, wherein the silicon photonics chiplet is a comb generator chiplet or an optical switch chiplet.

15. The method of claim 13, further comprising mounting a laser chiplet on the substrate.Attorney Ref.: 56403-0026W0116. The method of claim 15, further comprising forming an optical waveguide between the laser chiplet and the silicon photonics chiplet.

17. The method of claim 13, further comprising attaching a glass lid to the silicon photonics chiplet and the glass layer, the glass lid comprising channels for microfluidics.

18. The method of claim 13, further comprising mounting additional silicon photonics chiplets on the substrate.

19. The method of claim 13, wherein the substrate comprises an RDL and the silicon photonics chiplet is mounted on the RDL.

20. The method of claim 13, wherein the glass substrate layer comprises one or more through glass vias electrically connecting a first RDL on one side of the glass substrate layer to a second RDL on an opposite side of the glass substrate layer.

Images