Display substrate and preparation method therefor, and display apparatus

Abstract

Provided are a display substrate and a preparation method therefor, and a display apparatus. The display substrate comprises a plurality of sub-pixels, and at least one of the sub-pixels comprises a pixel driving circuit. The pixel driving circuit at least comprises a first transistor, a second transistor, a third transistor, and a fourth transistor. The display substrate further comprises a data signal line, a first power line, a second power line, a first power supply region, and a seventh connection electrode. The first power supply region is coupled to the first power line, and the seventh connection electrode is connected to the first power supply region by means of a twelfth via hole. The seventh connection electrode comprises a first sub-electrode, a second sub-electrode, and a third sub-electrode. The first sub-electrode and the third sub-electrode are connected by means of the second sub-electrode. The first sub-electrode and the third sub-electrode are strip-shaped and extend in a second direction. The second sub-electrode is strip-shaped and extends in a first direction. In the second direction, at least a portion of the first sub-electrode and at least a portion of the third sub-electrode are located on a same side of the second sub-electrode.

Description

Display substrate and its preparation method, display device Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and its preparation method, and a display device. Background Technology

[0002] Micro-OLEDs (Micro-Organic Light-Emitting Diodes) are microdisplays that have emerged in recent years, with silicon-based OLEDs being one type. Silicon-based OLEDs not only enable active pixel addressing but also allow for the fabrication of pixel driving circuits and other structures on silicon substrates, which helps reduce system size and achieve weight reduction. Silicon-based OLEDs offer advantages such as small size, high resolution, and high refresh rate, and are widely used in near-eye displays for virtual reality and augmented reality.

[0003] The information disclosed in this section is only for understanding the background of the inventive concept of this disclosure, and therefore may include information that does not constitute prior art. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] In one aspect, a display substrate is provided, comprising a plurality of sub-pixels arranged to form a plurality of pixel rows and a plurality of pixel columns. At least one sub-pixel includes a pixel driving circuit, wherein the pixel driving circuit includes at least a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor, the second transistor, the third transistor, and the fourth transistor each include a first electrode and a second electrode. The display substrate includes a data signal line, a first power line, and a second power line. The first electrode of the first transistor is coupled to the data signal line, the second electrode of the first transistor is coupled to the gate electrode of the third transistor, the first electrode of the second transistor is coupled to the first power line, the second electrode of the second transistor is coupled to the first electrode of the third transistor, and the first electrode of the fourth transistor is coupled to the second power line. The fourth transistor is coupled to the second electrode of the third transistor; the display substrate further includes a first power supply region and a seventh connection electrode, the first power supply region is coupled to the first power supply line, and the seventh connection electrode is connected to the first power supply region through a twelfth via; in at least one pixel row, the seventh connection electrode includes a first sub-electrode, a second sub-electrode and a third sub-electrode, the first sub-electrode and the third sub-electrode are connected through the second sub-electrode, the first sub-electrode and the third sub-electrode are strip-shaped extending along a second direction, the second sub-electrode is strip-shaped extending along a first direction, at least a portion of the first sub-electrode and at least a portion of the third sub-electrode are located on the same side of the second sub-electrode in the second direction, and the first direction and the second direction intersect.

[0006] According to some exemplary embodiments, the display substrate further includes a first connection electrode and a third connection electrode; the first transistor includes at least a first active region, the first active region includes at least a first source region and a first drain region, the first source region is connected to the first connection electrode through a first via, the first connection electrode is connected to the data signal line, and the first drain region is connected to the gate electrode of the third transistor through a third via and the third connection electrode; the display substrate plane has a first region, the first region being a region partially surrounded by the orthographic projection of the seventh connection electrode on the display substrate plane; the first region at least partially overlaps with the orthographic projection of the third connection electrode on the display substrate plane.

[0007] According to some exemplary embodiments, the third connection electrode is connected to the gate electrode of the third transistor through a tenth via, and the orthographic projection of the tenth via on the display substrate plane is in the first region.

[0008] According to some exemplary embodiments, the third transistor includes at least a third active region, the orthographic projection of the first sub-electrode on the display substrate plane does not overlap with the orthographic projection of the third active region on the display substrate plane, the orthographic projection of the second sub-electrode on the display substrate plane at least partially overlaps with the orthographic projection of the third active region on the display substrate plane, and the orthographic projection of the third sub-electrode on the display substrate plane is located within the orthographic projection of the third active region on the display substrate plane.

[0009] According to some exemplary embodiments, the first transistor further includes a first gate electrode, the display substrate includes a first scan signal line and a second scan signal line, the first gate electrode is connected to the first scan signal line, the second transistor includes at least a second gate electrode and a second active region, the second gate electrode is connected to the second scan signal line; the first scan signal line is a straight line extending along the first direction, the orthographic projection of the first scan signal line on the display substrate plane does not overlap with the orthographic projection of the second gate electrode on the display substrate plane, and the orthographic projection of the first scan signal line on the display substrate plane at least partially overlaps with the orthographic projection of the second active region on the display substrate plane; in the second direction, there is a fourth spacing between the first sub-electrode and the first scan signal line, and a third spacing between the third sub-electrode and the first scan signal line, the fourth spacing being smaller than the third spacing.

[0010] According to some exemplary embodiments, the display substrate includes a second power extension, a second power line is coupled to a first electrode of the fourth transistor through the second power extension, the second power line is a line extending along a first direction, the second power extension is a line extending along a second direction, the second power line is continuously disposed in the first direction, the second power extension is discontinuously disposed in the second direction, the second power line and the second power extension are disposed in the same layer, and the second power extension is coupled to the second power line; in the second direction, there is a second spacing between the first sub-electrode and the second power extension, and the fourth spacing is greater than the second spacing.

[0011] According to some exemplary embodiments, the display substrate further includes a second gate connection block. In the first direction, the second gate connection block is disposed on the side of the second gate electrode away from the first gate electrode and is connected to the second gate electrode. The second scan signal line is connected to the second gate connection block through a ninth via. In the first direction, the third via and the second gate connection block are disposed on both sides of the first sub-electrode, and the third via and the second gate connection block are spaced apart by the first sub-electrode.

[0012] According to some exemplary embodiments, in the first direction, there is a fifth spacing between the edge of the second gate connecting block near the first sub-electrode and the edge of the first sub-electrode near the second gate connecting block, and a sixth spacing between the edge of the third via near the first sub-electrode and the edge of the first sub-electrode near the third via; the fifth spacing is greater than the sixth spacing.

[0013] According to some exemplary embodiments, in the first direction, there is a seventh spacing between the edge of the tenth via near the first sub-electrode and the edge of the first sub-electrode near the tenth via; in the second direction, there is an eighth spacing between the edge of the tenth via near the second sub-electrode and the edge of the second sub-electrode near the tenth via; in the first direction, there is a ninth spacing between the edge of the tenth via near the third sub-electrode and the edge of the third sub-electrode near the tenth via; the seventh spacing is greater than or equal to the eighth spacing, and the seventh spacing is greater than or equal to the ninth spacing.

[0014] According to some exemplary embodiments, in the first direction, the first sub-electrode is disposed between two adjacent third transistors, separating the two adjacent third transistors; in the first direction, there is a tenth spacing between the edge of the gate electrode of the third transistor of the sub-pixel where the first sub-electrode is located and the edge of the gate electrode of the third transistor of the sub-pixel where the first sub-electrode is located and the edge of the gate electrode of the third transistor of the adjacent ... and the edge of the gate electrode of the third transistor of the first sub-pixel are located and the edge of the gate electrode of the third transistor of the adjacent sub-pixel and the edge of the gate electrode of the third transistor of the first sub-pixel and the edge of the gate electrode of the third transistor of the first sub-pixel and the edge of the gate electrode of the third transistor of the first sub-pixel and the edge of the gate electrode of the third transistor of the adjacent sub-pixel and the edge of the gate electrode of the first sub-pixel and the edge of the gate electrode of the third transistor of the first sub-pixel and the edge of the gate electrode of the third transistor of the first sub-pixel and the edge of the gate electrode of

[0015] According to some exemplary embodiments, in the first direction, the first sub-electrode is disposed between the tenth via and the third transistor of the adjacent sub-pixel, separating the third transistor of the adjacent sub-pixel from the tenth via; the seventh spacing is greater than or equal to the eleventh spacing.

[0016] According to some exemplary embodiments, the display substrate further includes a fourth connection electrode, which is connected to the second electrode of the second transistor through a fourth via; the orthographic projection of the fourth connection electrode on the display substrate plane at least partially overlaps with the orthographic projection of the gate electrode of the third transistor on the display substrate plane.

[0017] According to some exemplary embodiments, the fourth connecting electrode is L-shaped, and there is a first overhang width between the edge of the fourth connecting electrode on the display substrate plane near the first sub-electrode and the edge of the first electrode plate on the display substrate plane near the first sub-electrode; there is a second overhang width between the edge of the fourth connecting electrode on the display substrate plane near the first sub-electrode of the adjacent sub-pixel and the edge of the first electrode plate on the display substrate plane near the first sub-electrode of the adjacent sub-pixel; the first overhang width is greater than the second overhang width.

[0018] According to some exemplary embodiments, the third transistor includes at least a third active region, which includes at least a third source region and a third drain region; the fourth transistor includes at least a fourth active region, which includes at least a fourth source region and a fourth drain region; the display substrate includes a fifth connecting electrode; the third drain region is connected to the fourth drain region via the fifth connecting electrode; the orthographic projection of the fifth connecting electrode on the display substrate plane at least partially overlaps with the orthographic projection of the third active region on the display substrate plane; and the ratio of the overlapping areas of the orthographic projections in two adjacent sub-pixels is 0.9 to 1.1.

[0019] According to some exemplary embodiments, the fifth connection electrode of at least one sub-pixel includes a first sub-segment, a second sub-segment, and a third sub-segment, wherein the second sub-segment connects the first sub-segment and the third sub-segment; the first sub-segment and the third sub-segment are strip-shaped extending along the first direction; the first sub-segment is connected to the third drain region through a fifth via, and the third sub-segment is connected to the fourth drain region through a seventh via; the second sub-segment is strip-shaped extending along the second direction; the orthographic projection of the first sub-segment on the display substrate plane overlaps with the orthographic projection of the third active region on the display substrate plane, and the ratio of the overlapping areas of the orthographic projections in two adjacent sub-pixels is not 1.

[0020] According to some exemplary embodiments, in the second direction, the fifth via has a first spacing to the second power line, and the second power extension has a third extension length on one side of the second power line; the third extension length is substantially equal to the first spacing.

[0021] According to some exemplary embodiments, the orthographic projection of the third sub-segment on the display substrate plane is located in the orthographic projection of the fourth active region on the display substrate plane, and the orthographic projection of the third sub-segment on the display substrate plane at least partially overlaps with the orthographic projection of the fourth gate electrode on the display substrate plane.

[0022] According to some exemplary embodiments, the display substrate further includes a first power connection line, which is connected to the second power line through a twenty-eighth via. The first power connection line is a straight line extending along the first direction. In the same pixel row, the first power connection line is disposed between the gate electrode of the third transistor and the fourth transistor in the second direction. The orthographic projection of the first power connection line on the display substrate plane overlaps with the orthographic projection of the fifth connection electrode on the display substrate plane.

[0023] According to some exemplary embodiments, the display substrate further includes a mesh structure for transmitting a first power signal, the mesh structure being connected to the first electrode of the second transistor via vias and a twelfth connection electrode, wherein adjacent sub-pixels in a pixel column share the same twelfth connection electrode.

[0024] According to some exemplary embodiments, the second active region includes at least a second source region and a second drain region. The second source region is connected to the second connection electrode through a second via. The second connection electrode is connected to the first power line. The second drain region is connected to the first electrode of the third transistor. In at least one pixel column, the first active regions in adjacent sub-pixels are interconnected as a single structure, the second active regions in adjacent sub-pixels are interconnected as a single structure, adjacent sub-pixels share the first source region, adjacent sub-pixels share the second source region, and the first via and the second via are located on the same straight line extending along the first direction.

[0025] According to some exemplary embodiments, the display substrate further includes an anode connection electrode, which is connected to the second electrode of the fourth transistor through a via, and the third segment of the fifth connection electrode is connected to the anode connection electrode through a via; the fifth connection electrode is connected to the second electrode of the fourth transistor through a seventh via, and the fifth connection electrode is connected to the anode connection electrode through a via and a plurality of connection electrodes, wherein the orthographic projection of the via connecting the fifth connection electrode and the anode connection electrode on the display substrate plane does not overlap at least partially with the orthographic projection of the seventh via on the display substrate plane.

[0026] According to some exemplary embodiments, the display substrate further includes a thirty-fourth connection electrode, and the fifth connection electrode is connected to the thirty-fourth connection electrode through a via; in at least one insulating layer between the conductive layers containing the fifth connection electrode and the thirty-fourth connection electrode, the number of vias connecting the fifth connection electrode and the thirty-fourth connection electrode is at least two.

[0027] According to some exemplary embodiments, in at least one insulating layer between the conductive layer where the fifth connection electrode and the thirty-fourth connection electrode are located, the ratio of the distances from the via hole connecting the fifth connection electrode and the anode connection electrode to the second centerlines on the adjacent two sides is 0.9 to 1.1, and the second centerlines are straight lines located between adjacent pixel columns and extending along the second direction.

[0028] According to some exemplary embodiments, in the first direction, the distances from the orthographic projection of the anode connection electrode on the display panel plane to the second centerlines on the adjacent two sides are substantially equal; the anode connection electrode is connected to the thirty-fourth connection electrode through the sixty-second via hole, and in the first direction, the distances from the orthographic projection of the sixty-second via hole on the display panel plane to the second centerlines on the adjacent two sides are substantially equal.

[0029] According to some exemplary embodiments, the pixel driving circuit further includes a storage capacitor, and the storage capacitor at least includes a first electrode plate and a second electrode plate. The first electrode plate serves as the gate electrode of the third transistor, and the second electrode plate serves as the fourth connection electrode; the storage capacitor further includes a third electrode plate, and the third electrode plate is connected to the third connection electrode through the twenty-third via hole. The orthographic projection of the third electrode plate on the display substrate plane and the orthographic projection of the second electrode plate on the display substrate plane at least partially overlap; at least one of the twenty-third via holes has an orthographic projection on the display substrate plane in the first region.

[0030] According to some exemplary embodiments, the storage capacitor further includes a fourth electrode plate, and the fourth electrode plate is connected to the second electrode plate through a via hole. The orthographic projection of the fourth electrode plate on the display substrate plane and the orthographic projection of the third electrode plate on the display substrate plane at least partially overlap, and the shape of the fourth electrode plate is "concave" or "return" shaped.

[0031] According to some exemplary embodiments, a second region is provided on the display substrate plane, and the second region is a region surrounded or semi-surrounded by the orthographic projection of the fourth electrode plate on the display substrate plane; the orthographic projection of the third sub-electrode on the display substrate plane is in the second region.

[0032] According to some exemplary embodiments, the storage capacitor further includes a fifth electrode plate, and the fifth electrode plate is connected to the third electrode plate through a via hole. The orthographic projection of the fifth electrode plate on the display substrate plane and the orthographic projection of the fourth electrode plate on the display substrate plane at least partially overlap; the orthographic projection of the second electrode plate on the display substrate plane is located in the orthographic projection of the fifth electrode plate on the display substrate plane.

[0033] According to some exemplary embodiments, the fifth electrode plate is connected to the third electrode plate through a 33rd via and a 41st via, the 33rd via and the 41st via being located on the same straight line extending in a direction perpendicular to the plane of the display substrate; the orthographic projection of the 33rd via on the plane of the display substrate is located in the second region, and the orthographic projection of the 41st via on the plane of the display substrate is located in the second region.

[0034] According to some exemplary embodiments, the pixel driving circuit further includes a first capacitor and a second capacitor. The first capacitor includes a first sub-capacitor, a second sub-capacitor, a third sub-capacitor, a fourth sub-capacitor, and a fifth sub-capacitor connected in parallel. In a direction perpendicular to the plane of the display substrate, the second sub-capacitor is disposed on the side of the first sub-capacitor away from the display substrate, the third sub-capacitor is disposed on the side of the second sub-capacitor away from the first sub-capacitor, the fourth sub-capacitor is disposed on the side of the third sub-capacitor away from the first sub-capacitor, and the fifth sub-capacitor is disposed on the side of the fourth sub-capacitor away from the first sub-capacitor; the second capacitor is disposed on the side of the fifth sub-capacitor away from the first sub-capacitor.

[0035] According to some exemplary embodiments, the second capacitor further includes a parallel supplementary capacitor, wherein the two plates of the supplementary capacitor of the second capacitor and one plate of the first sub-capacitor are located on the same conductive layer.

[0036] According to some exemplary embodiments, in a direction perpendicular to the plane of the display substrate, the display substrate includes at least a gate conductive layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, a seventh conductive layer, and an eighth conductive layer disposed sequentially; the gate conductive layer includes at least a first electrode plate, which serves as the gate electrode of the third transistor; the first conductive layer includes at least a second electrode plate, which is connected to the second electrode of the second transistor and the first electrode of the third transistor respectively; the first sub-capacitor includes the first electrode plate and the second electrode plate; the second conductive layer includes at least the third electrode plate, which is connected to the first electrode plate; the second sub-capacitor includes the second electrode plate and the... The third electrode plate; the third conductive layer includes at least the fourth electrode plate, which is connected to the second electrode plate, and the third sub-capacitor includes the third electrode plate and the fourth electrode plate; the fourth conductive layer includes at least the fifth electrode plate, which is connected to the third electrode plate, and the fourth sub-capacitor includes the fourth electrode plate and the fifth electrode plate; the fifth conductive layer includes at least the sixth electrode plate, which is connected to the fourth electrode plate, and the fifth sub-capacitor includes the fifth electrode plate and the sixth electrode plate; the sixth conductive layer includes at least the seventh electrode plate, which is connected to the fourth electrode plate; the seventh conductive layer includes at least the eighth electrode plate, which is connected to the first power line, and the second capacitor includes the seventh electrode plate and the eighth electrode plate.

[0037] According to some exemplary embodiments, the first conductive layer further includes a ninth electrode plate, which serves as the seventh connecting electrode, and the second capacitor further includes a parallel supplementary capacitor, which includes the ninth electrode plate and the second electrode plate.

[0038] In another aspect, a display device is provided, comprising a display substrate as described above.

[0039] In another aspect, a method for fabricating a display substrate is provided, wherein the display substrate includes a plurality of sub-pixels, the plurality of sub-pixels being arranged to form a plurality of pixel rows and a plurality of pixel columns; the fabrication method includes: forming a pixel driving circuit in at least one sub-pixel, the pixel driving circuit including at least a first transistor, a second transistor, a third transistor, and a fourth transistor, the first transistor, the second transistor, the third transistor, and the fourth transistor each including a first electrode and a second electrode; the display substrate includes a data signal line, a first power line, and a second power line; the first electrode of the first transistor is coupled to the data signal line; the second electrode of the first transistor is coupled to the gate electrode of the third transistor; the first electrode of the second transistor is coupled to the first power line; the second electrode of the second transistor is coupled to the first electrode of the third transistor; and the fourth transistor... The first electrode of the transistor is coupled to the second power line, and the second electrode of the fourth transistor is coupled to the second electrode of the third transistor; the display substrate further includes a first power region and a seventh connection electrode, the first power region is coupled to the first power line, and the seventh connection electrode is connected to the first power region through a twelfth via; in at least one pixel row, the seventh connection electrode includes a first sub-electrode, a second sub-electrode, and a third sub-electrode, the first sub-electrode and the third sub-electrode are connected through the second sub-electrode, the first sub-electrode and the third sub-electrode are strip-shaped extending along the second direction, the second sub-electrode is strip-shaped extending along the first direction, at least a portion of the first sub-electrode and at least a portion of the third sub-electrode are located on the same side of the second sub-electrode in the second direction, and the first direction and the second direction intersect. Attached Figure Description

[0040] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shapes and sizes of the components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0041] Figure 1 is a schematic diagram of a silicon-based OLED display device;

[0042] Figure 2 is a schematic diagram of the planar structure of the display area in a silicon-based OLED display device;

[0043] Figure 3 is a schematic cross-sectional view of the display area in a silicon-based OLED display device;

[0044] Figure 4 is an equivalent circuit diagram of a pixel driving circuit;

[0045] Figure 5 is a driving timing diagram of the pixel driving circuit shown in Figure 4;

[0046] Figure 6 is a schematic diagram of the planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0047] Figure 7 is a schematic diagram of the P-type substrate region and the N-type substrate region in the embodiments of this disclosure;

[0048] Figure 8A is a schematic diagram of the combination of substrate and active region in an embodiment of the present disclosure; Figure 8B is a schematic diagram of the active region pattern in an embodiment of the present disclosure;

[0049] Figure 9A is a schematic diagram of the combination of the active region pattern and the gate conductive layer pattern in an embodiment of the present disclosure; Figure 9B is a schematic diagram of the gate conductive layer pattern in an embodiment of the present disclosure.

[0050] Figure 10 is a schematic diagram of the combination of the active region pattern, the gate conductive layer pattern, and the second insulating layer pattern in an embodiment of this disclosure;

[0051] Figure 11A is a schematic diagram of the combination of the active region pattern, the gate conductive layer pattern, the second insulating layer pattern, and the first conductive layer pattern in an embodiment of this disclosure;

[0052] Figure 11B is a schematic diagram of the pattern of the first conductive layer in an embodiment of this disclosure;

[0053] Figure 12 is an enlarged view of region B in Figure 11A;

[0054] Figure 13 is a schematic diagram of the combination of the first conductive layer pattern, the third insulating layer pattern, and the second conductive layer pattern in an embodiment of this disclosure;

[0055] Figure 14 is a schematic diagram of the second conductive layer pattern according to an embodiment of the present disclosure;

[0056] Figure 15 is a schematic diagram of the combination of the second conductive layer pattern, the fourth insulating layer pattern, and the third conductive layer pattern in an embodiment of this disclosure;

[0057] Figure 16 is a schematic diagram of the third conductive layer pattern according to an embodiment of this disclosure;

[0058] Figure 17 is a schematic diagram of the combination of the third conductive layer pattern, the fifth insulating layer pattern, and the fourth conductive layer pattern in an embodiment of this disclosure;

[0059] Figure 18 is a schematic diagram of the fourth conductive layer pattern according to an embodiment of this disclosure;

[0060] Figure 19 is a schematic diagram showing the fourth conductive layer pattern, the sixth insulating layer pattern, the fifth conductive layer pattern, the seventh insulating layer pattern, and the sixth conductive layer pattern in an embodiment of this disclosure.

[0061] Figure 20 is a schematic diagram of the sixth conductive layer pattern according to an embodiment of this disclosure;

[0062] Figure 21 is a schematic diagram of the formation of a combination of a sixth conductive layer pattern, an eighth insulating layer pattern, a seventh conductive layer pattern, a ninth insulating layer pattern, and an eighth conductive layer pattern according to an embodiment of the present disclosure.

[0063] Figure 22 is a schematic diagram of the pattern of the eighth conductive layer in an embodiment of this disclosure;

[0064] Figure 23 is a schematic diagram of the structure of the first capacitor and the second capacitor in an embodiment of this disclosure;

[0065] Figure 24 is a schematic diagram of a silicon-based OLED display device.

[0066] Explanation of reference numerals in the attached figures: 10A - First substrate region; 10B - First potential line region; 20A - Second substrate region; 20B - Second potential line region; 11 - First active region; 12 - Second active region; 13 - Third active region; 14 - Fourth active region; 15 - First power supply region; 16 - Second power supply region; 21 - First gate electrode; 22 - Second gate electrode; 23 - Third gate electrode; 24 - Fourth gate electrode; 31 - First scan signal line; 32 - Second scan signal line; 33 - Third scan signal line; 41 - First connecting electrode; 42 - Second connecting electrode; 43 - Third connecting electrode; 44 - Fourth connecting electrode; 45 - Fifth connecting electrode; 46 - Sixth connecting electrode; 47 - Seventh connecting electrode; 48 - Eighth connecting electrode; 49 - Ninth connecting electrode; 51 - Eleventh connecting electrode; 52 - Twelfth connecting electrode; 53 - Thirteenth connecting electrode; 54 - Fourteenth connecting electrode; 55 - Fifteenth connecting electrode; 56 - Sixteenth connecting electrode; 61 - Twenty-first connecting electrode; 62 - Twenty-second connecting electrode; 63 - Twenty-third connecting electrode; 64 - Twenty-fourth connecting electrode; 71 - Thirty-first connecting electrode; 72 - Thirty-second connecting electrode; 73 - Thirty-third connecting electrode; 74 - Thirty-fourth connecting electrode; 81 - First power line; 82 - Second power line; 83 - Data signal line; 84 - Anode connecting electrode; 91 - First power connection line; 92 - Second power connection line; 93 - Third power connection line; 94 - Fourth power connection line; 95 - Fifth power connection line; 96 - Sixth power connection line; 97 - Seventh power connection line; 98 - Eighth power connection line; 99 - Electrode connection line; 110 - First electrode plate; 120 - Second electrode plate; 130 - Third plate; 140 - Fourth plate; 150 - Fifth plate; 160 - Sixth plate;170 - Seventh electrode plate; 180 - Eighth electrode plate; 201 - First insulating layer; 202 - Second insulating layer; 203 - Third insulating layer; 204 - Fourth insulating layer; 205 - Fifth insulating layer; 206 - Sixth insulating layer; 207 - Seventh insulating layer; 208 - Eighth insulating layer; 209 - Ninth insulating layer. Detailed Implementation

[0067] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0068] The scale of the accompanying drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display device and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The accompanying drawings described in this disclosure are only structural schematic diagrams, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0069] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0070] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0071] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0072] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain terminal, drain region, or drain electrode) and the source electrode (source terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0073] In this specification, to distinguish the two terminals of a transistor other than the gate electrode, one terminal is directly described as the first terminal and the other as the second terminal. The first terminal can be the drain electrode and the second terminal can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0074] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0075] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0076] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0077] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.

[0078] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0079] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0080] Figure 1 is a schematic diagram of a silicon-based OLED display device. As shown in Figure 1, the silicon-based OLED display device may include a display area and a non-display area. The display area may include multiple scan signal lines, multiple data signal lines, and multiple sub-pixels Pxij forming multiple pixel rows and multiple pixel columns. The multiple scan signal lines are respectively arranged in the multiple pixel rows, and the multiple data signal lines are respectively arranged in the multiple pixel columns. Each sub-pixel Pxij may include at least a pixel driving circuit and a light-emitting device. The pixel driving circuit is configured to provide the current required for light emission to the connected light-emitting device. The pixel driving circuit of each sub-pixel Pxij may be connected to the scan signal line of the corresponding pixel row and the data signal line of the corresponding pixel column. The sub-pixel Pxij may refer to the sub-pixel of the i-th pixel row and the j-th pixel column. The pixel driving circuit of the sub-pixel Pxij is connected to the i-th scan signal line and the j-th data signal line, respectively. i and j can be natural numbers. The non-display area may include at least a gate driver (GD) and a source driver (SD). The gate driver is connected to multiple scan signal lines in the display area and is configured to provide the necessary timing signals to the connected pixel driving circuits to achieve progressive scan functionality. The source driver is connected to multiple data signal lines in the display area and is configured to provide the necessary data signals to the connected pixel driving circuits to achieve switching and control of the display screen.

[0081] In one exemplary embodiment, the silicon-based OLED display device can be a one-chip display architecture, integrating gate driving devices, data driving devices, clock control circuits, image processing units, and memory units onto the same chip. The one-chip architecture chip includes both digital and analog parts, belonging to mixed-signal chips.

[0082] In another exemplary embodiment, the silicon-based OLED display device may be a two-chip display architecture, in which the gate driving device and the data driving device are integrated in the display substrate, and the clock control circuit, the image processing unit, the mobile industry processor interface (MIPI), and the memory unit are integrated in one chip, which is bonded to the display substrate through a COC process.

[0083] Figure 2 is a schematic diagram of the planar structure of the display area in a silicon-based OLED display device. As shown in Figure 2, on a plane parallel to the display device, the display area may include multiple pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each of the three sub-pixels may include a pixel driving circuit and a light-emitting device. The pixel driving circuit in the sub-pixel is connected to the scan signal line and the data signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line and output a corresponding current to the display light-emitting device. The light-emitting device in the sub-pixel is connected to the pixel driving circuit of the sub-pixel and is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0084] In an exemplary embodiment, the first sub-pixel P1 may be a red (R) sub-pixel that emits red light, the second sub-pixel P2 may be a blue (B) sub-pixel that emits blue light, and the third sub-pixel P3 may be a green (G) sub-pixel that emits green light.

[0085] It should be noted that the sub-pixel Pxij shown in Figure 1 can be one of the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 shown in Figure 2.

[0086] In exemplary embodiments, the shape of a sub-pixel can be any one or more of a triangle, square, rectangle, rhombus, trapezoid, parallelogram, pentagon, hexagon, and other polygons. Three sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular pattern, etc., and this disclosure does not limit the arrangement. In other possible embodiments, a pixel unit may include four sub-pixels, and this disclosure does not limit the arrangement.

[0087] Figure 3 is a cross-sectional structural diagram of the display area in a silicon-based OLED display device, illustrating a structure that achieves full color using a white light + color filter approach. Exemplarily, Figure 3 can be a cross-sectional structural diagram taken along section line AA' in Figure 2. As shown in Figure 3, in the direction perpendicular to the display device, the silicon-based OLED display device may include: a silicon substrate 101, a driving circuit layer 102 disposed on the silicon substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the silicon substrate 101, a first encapsulation layer 104 disposed on the side of the light-emitting structure layer 103 away from the silicon substrate 101, a color filter structure layer 105 disposed on the side of the first encapsulation layer 104 away from the silicon substrate 101, a second encapsulation layer 106 disposed on the side of the color filter structure layer 105 away from the silicon substrate 101, and a cover plate layer 107 disposed on the side of the second encapsulation layer 106 away from the silicon substrate 101. In some possible implementations, the silicon-based OLED display device may include other film layers, which are not limited herein.

[0088] In an exemplary embodiment, the silicon substrate 101 can be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The driving circuit layer 102 can be fabricated on the silicon substrate 101 using silicon semiconductor processes. The driving circuit layer 102 can include multiple circuit units, each of which can include at least a pixel driving circuit. The pixel driving circuit is connected to the scan signal line and data signal line, respectively. The pixel driving circuit can include multiple transistors and storage capacitors; only one transistor is shown as an example in Figure 3. The transistor can include a gate electrode G, a source electrode S, and a drain electrode D. The gate electrode G, source electrode S, and drain electrode D can be connected to corresponding connection electrodes via tungsten-filled vias (i.e., tungsten vias, W-vias), and can be connected to other electrical structures (such as traces) via the connection electrodes.

[0089] It should be noted that, in this document, the expression "orthographic projection on the display substrate plane" means that the substrate of the display substrate includes a first surface on which a pattern, structure, or component is disposed, and the plane on which the first surface of the substrate is located can be represented as the display substrate plane. The orthographic projection of the pattern, structure, or component on the display substrate plane can be understood as the orthographic projection of the pattern, structure, or component on the plane on which the first surface of the substrate is located. The expression "orthographic projection on a silicon substrate" means that, when the substrate of the display substrate is a silicon substrate, "orthographic projection on a silicon substrate" can be used to represent "orthographic projection on the display substrate plane".

[0090] In an exemplary embodiment, the light-emitting structure layer 103 may include multiple light-emitting devices. Each light-emitting device may include at least an anode, an organic light-emitting layer, and a cathode. The anode is connected to the drain electrode D of a transistor via a connecting electrode. The organic light-emitting layer is connected to the anode, the cathode is connected to the organic light-emitting layer, and the cathode is connected to a second power line. The organic light-emitting layer emits light under the drive of the anode and cathode. In an exemplary embodiment, the organic light-emitting layer may include a light-emitting layer (EML) and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, for a light-emitting device emitting white light, the organic light-emitting layers of all sub-pixels may be a common layer connected together.

[0091] In an exemplary embodiment, the first encapsulation layer 104 and the second encapsulation layer 106 can employ thin film encapsulation (TFE) to prevent external moisture from entering the light-emitting structure layer. The color filter structure layer 105 can include at least a red filter unit, a blue filter unit, and a green filter unit. The red filter unit is located in the red sub-pixel and filters the white light emitted by the light-emitting device into red light. The blue filter unit is located in the blue sub-pixel and filters the white light emitted by the light-emitting device into blue light. The green filter unit is located in the green sub-pixel and filters the white light emitted by the light-emitting device into green light. The cover plate layer 107 can be made of glass or a flexible plastic such as colorless polyimide.

[0092] Figure 4 is an equivalent circuit diagram of a pixel driving circuit. As shown in Figure 4, the pixel driving circuit is a current-type 4T2C structure, which may include four transistors (first transistor T1, second transistor T2, third transistor T3 and fourth transistor T4) and two storage capacitors (first capacitor C1 and second capacitor C2). The pixel driving circuit is coupled to six signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, data signal line DATA, first power supply line VDD and second power supply line VSS).

[0093] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is coupled to the second terminal of a first transistor T1, the gate electrode of a third transistor T3, and the first terminal of a first capacitor C1. The second node N2 is coupled to the second terminal of a second transistor T2, the first terminal of a third transistor T3, the second terminal of a first capacitor C1, and the first terminal of a second capacitor C2. The third node N3 is coupled to the second terminal of a third transistor T3 and the second terminal of a fourth transistor T4.

[0094] In an exemplary embodiment, the first transistor T1 can be referred to as a source driver transistor or a data write transistor. The gate electrode of the first transistor T1 is coupled to the first scan signal line S1, the first electrode of the first transistor T1 is coupled to the data signal line DATA, and the second electrode of the first transistor T1 is coupled to the first node N1. In an exemplary embodiment, the first scan signal line S1 can output a write switch signal.

[0095] In an exemplary embodiment, the second transistor T2 is a compensation transistor referred to as the threshold voltage (Vth). The gate electrode of the second transistor T2 is coupled to the second scan signal line S2, the first terminal of the second transistor T2 is coupled to the first power supply line VDD, and the second terminal of the second transistor T2 is coupled to the second node N2. In an exemplary embodiment, the second scan signal line S2 can output a display switch signal.

[0096] In an exemplary embodiment, the third transistor T3 may be referred to as a driver transistor. The gate electrode of the third transistor T3 is coupled to the first node N1, the first electrode of the third transistor T3 is coupled to the second node N2, and the second electrode of the third transistor T3 is coupled to the third node N3.

[0097] In an exemplary embodiment, the fourth transistor T4 can be referred to as an auto-zero transistor. The gate electrode of the fourth transistor T4 is coupled to the third scan signal line S3, the first electrode of the fourth transistor T4 is coupled to the second power supply line VSS, and the second electrode of the fourth transistor T4 is coupled to the third node N3. In an exemplary embodiment, the third scan signal line S3 can output a reset signal.

[0098] In an exemplary embodiment, the first terminal of the first capacitor C1 is coupled to the first node N1, and the second terminal of the first capacitor C1 is coupled to the second node N2. The first terminal of the second capacitor C2 is coupled to the second node N2, and the second terminal of the second capacitor C2 is coupled to the first power line VDD.

[0099] In an exemplary embodiment, the light-emitting device EL can be an organic light-emitting diode (OLED), including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode). The first electrode of the light-emitting device EL is connected to a third node N3, and the second electrode of the light-emitting device EL is connected to a common voltage line VCOM. In an exemplary embodiment, the signal of the first power line VDD can be a continuously provided high-level signal, and the signals of the second power line VSS and the common voltage line VCOM can be continuously provided low-level signals.

[0100] In an exemplary embodiment, the first transistor T1 to the third transistor T3 can be P-type transistors, and the fourth transistor T4 can be an N-type transistor.

[0101] Figure 5 is a timing diagram of one possible pixel driving circuit shown in Figure 4. As shown in Figure 5, in an exemplary embodiment, the operation of the pixel driving circuit may include:

[0102] The first stage, A1, can be called the initialization stage. The signals on the first scan signal line S1 and the second scan signal line S2 are low-level signals, and the signal on the third scan signal line S3 is high-level, turning on the first transistor T1, the second transistor T2, and the fourth transistor T4. The first transistor T1 turns on, causing the bias voltage Vofs output from the data signal line DATA to be written into the first capacitor C1. The potential Vs of the first node N1 (i.e., the gate electrode of the third transistor T3) is equal to Vofs. The second transistor T2 turns on, causing the first power supply voltage ELVDD output from the first power supply line VDD to be written into the second node N2. The potential Vg of the second node N2 (i.e., the first electrode of the third transistor T3) is equal to ELVDD. At this time, the gate-source voltage Vgs of the third transistor T3 is equal to ELVDD - Vofs, and the storage voltage V of the first capacitor C1... cs =ELVDD-Vofs, the potential Vd = Vg + Vth at the third node N3 (i.e., the second terminal of the third transistor T3) prepares for the next stage of discharge. Where, ELVDD-V ofs >|Vth|, where Vth is the threshold voltage of the third transistor T3.

[0103] The second stage, A2, can be called the self-discharge stage. The signal on the third scan signal line S3 is high, and the fourth transistor T4 remains on. The signal on the first scan signal line S13 changes from low to high, causing the first transistor T1 to turn off first, and the first node N1 to float. Subsequently, the signal on the second scan signal line S2 changes from low to high, causing the second transistor T2 to turn off. The second node N2 forms a circuit through the on-state third transistor T3, the third node N3, and the on-state fourth transistor T4, and begins to discharge, causing the potential of the second node N2 to decrease. Because the first node N1 is floating, the voltage difference across the first capacitor C1 remains unchanged, therefore the potential of the first node N1 decreases as the potential of the second node N2 decreases. Due to the back-gate effect of the third transistor T3, the gate-source voltage Vgs of the third transistor T3 remains constant, therefore the equivalent threshold voltage |Vgs| of the third transistor T3 remains constant. th_EF The equivalent threshold voltage of the third transistor T3 gradually increases as the potential of the second node N2 decreases. th_EF |=α(ELVDD-Vs)+|Vth|, where α is the back gate coefficient. When the equivalent threshold voltage of the third transistor T3 is |V... th_EF When the gate-source voltage Vgs of the third transistor T3 is increased, the third transistor T3 is turned off, and the second node N2 stops discharging.

[0104] The third stage, A3, can be called the data writing stage and threshold compensation stage. The signal on the second scan signal line S2 is high, and the second transistor T2 remains off. The signal on the third scan signal line S3 is high, and the fourth transistor T4 remains on. The signal on the first scan signal line S1 changes from high to low, turning on the first transistor T1. The on of the first transistor T1 causes the data voltage Vdata output from the data signal line DATA to be written to the first node N1, changing the potential of the first node N1 from Vofs to Vdata. Since the second node N2 is floating, threshold compensation can be achieved in this stage.

[0105] The fourth stage, A4, can be called the light-emitting stage. The signals on the second scan signal line S2 and the third scan signal line S3 are low-level signals, while the signal on the first scan signal line S1 is high-level, turning on the second transistor T2 and turning off the first transistor T1 and the fourth transistor T4. The conduction of the second transistor T2 allows the power supply voltage output from the first power line VDD to provide a driving voltage to the first terminal of the light-emitting device EL through the conducting second transistor T2 and third transistor T3, driving the light-emitting device EL to emit light.

[0106] During the light-emitting stage, the driving current of the third transistor T3 is not affected by the threshold voltage of the third transistor T3, thus eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product, and improving the overall display effect of the display product.

[0107] Currently, silicon-based OLED displays are increasingly being applied in near-eye display fields such as Virtual Reality (VR), Augmented Reality (AR), Extended Reality (XR), and Mixed Reality (MR), allowing users to experience realistic sensations in the virtual reality world. These displays possess powerful simulation systems and enable human-computer interaction. Research shows that when screen resolution is high enough, the human retina cannot distinguish individual pixels. Resolution (Pixels Per Inch, PPI) refers to the number of pixels per unit area, also known as pixel density. A higher PPI value indicates that the display substrate can display images at a higher density, resulting in richer image details. Therefore, significantly increasing PPI has become a key research focus for manufacturers to improve display quality. Silicon-based OLEDs are fabricated using Complementary Metal Oxide Semiconductor (CMOS) integrated circuit technology. The reduced pixel size, coupled with the coupling capacitance between signal lines and circuit nodes, can lead to poor crosstalk.

[0108] Figure 6 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the pixel driving circuit structure of 12 sub-pixels in 2 pixel rows (the Mth pixel row and the (M+1)th pixel row) and 6 pixel columns (the Nth pixel column to the (N+5)th pixel column). In an exemplary embodiment, on a plane parallel to the display substrate, the display substrate may include multiple sub-pixels forming multiple pixel rows and multiple pixel columns. The multiple sub-pixels in the pixel rows may be arranged sequentially along a first direction X, and the multiple sub-pixels in the pixel columns may be arranged sequentially along a second direction Y. The multiple pixel rows and multiple pixel columns constitute an array-arranged pixel array, and the first direction X intersects the second direction Y.

[0109] In an exemplary embodiment, at least one sub-pixel may include a pixel driving circuit. The at least one pixel driving circuit may include at least a first transistor T1 as a source driving transistor, a second transistor T2 as a threshold voltage compensation transistor, a third transistor T3 as a driving transistor, and a fourth transistor T4 as a reset transistor. The first terminal of the first transistor T1 is coupled to a data signal line, and the second terminal of the first transistor T1 is coupled to the gate electrode of the third transistor T3. The first terminal of the second transistor T2 is coupled to a first power supply line, and the second terminal of the second transistor T2 is coupled to the first terminal of the third transistor T3. The first terminal of the fourth transistor T4 is coupled to a second power supply line, and the second terminal of the fourth transistor T4 is coupled to the second terminal of the third transistor T3.

[0110] In an exemplary embodiment, in at least one sub-pixel, the second transistor T2 can be disposed on one side of the first transistor T1 along the first direction X, the first transistor T1 and the second transistor T2 can be disposed on one side of the third transistor T3 along the second direction Y, and the fourth transistor T4 can be disposed on the other side of the third transistor T3 along the second direction Y. That is, the second transistor T2 and the fourth transistor T4 can be disposed on opposite sides of the third transistor T3 along the second direction Y. For example, in the Mth pixel row, the first transistor T1 and the second transistor T2 can be disposed on one side of the third transistor T3 along the second direction Y, and the fourth transistor T4 can be disposed on the opposite side of the third transistor T3 along the second direction Y. As another example, in the M+1th pixel row, the first transistor T1 and the second transistor T2 can be disposed on the opposite side of the third transistor T3 along the second direction Y, and the fourth transistor T4 can be disposed on one side of the third transistor T3 along the second direction Y.

[0111] In an exemplary embodiment, the display substrate may include at least a first center line O1 and a second center line O2. The first center line O1 may be a straight line located between adjacent pixel rows and extending along a first direction X, and the second center line O2 may be a straight line located between adjacent pixel columns and extending along a second direction Y.

[0112] In an exemplary embodiment, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 in adjacent pixel rows can be substantially mirror-symmetrical with respect to the first center line O1.

[0113] In an exemplary embodiment, the positions and shapes of the first transistor T1, the second transistor T2, and the third transistor T3 in adjacent pixel columns may be substantially the same, and the fourth transistor T4 in adjacent pixel columns may be substantially mirror-symmetrical with respect to the second center line O2.

[0114] In an exemplary embodiment, referring to Figures 8A and 8B (which will be described in more detail below), the first transistor T1 may include at least a first active region 11, which may include at least a first source region and a first drain region. The first source region is configured to be connected to a data signal line, and the first drain region is configured to be connected to the gate electrode of the third transistor T3. In at least one pixel column, the first active regions 11 in adjacent sub-pixels may be an integral structure interconnected, and adjacent sub-pixels may share the same first source region.

[0115] In an exemplary embodiment, referring to FIG6, at least one sub-pixel may further include a first connection electrode 41, which is configured to be connected to a data signal line. The first connection electrode 41 is connected to a first source region shared by adjacent sub-pixels through a first via V1, so that adjacent sub-pixels can share the same first connection electrode 41.

[0116] In an exemplary embodiment, referring to Figures 8A and 8B, the second transistor T2 may include at least a second active region 12, which may include at least a second source region and a second drain region. The second source region is configured to be connected to a first power line, and the second drain region is configured to be connected to the first terminal of the third transistor T3. In at least one pixel column, the second active regions 12 in adjacent sub-pixels may be an integral structure interconnected, and adjacent sub-pixels may share the same second source region.

[0117] In an exemplary embodiment, referring to FIG6, at least one sub-pixel may further include a second connection electrode 42, which is configured to be connected to a first power line. The second connection electrode 42 is connected to a second source region shared by adjacent sub-pixels through a second via V2, so that adjacent sub-pixels can share the same second connection electrode 42.

[0118] In an exemplary embodiment, the first via V1 and the second via V2 may be located on the same straight line extending along the first direction X.

[0119] In an exemplary embodiment, the orthographic projections of the first connecting electrode 41 and the second connecting electrode 42 on the display substrate plane at least partially overlap with the orthographic projection of the first center line O1 on the display substrate plane.

[0120] In an exemplary embodiment, the extension length of the first connecting electrode 41 in the first direction X is greater than the extension length of the second connecting electrode 42 in the first direction X.

[0121] In an exemplary embodiment, referring to Figures 8A and 8B, the third transistor T3 may include at least a third active region 13, which may include at least a third source region and a third drain region. The third source region is connected to the second drain region, as shown in Figure 6. The third drain region is connected to the fourth drain region through a fifth connecting electrode 45.

[0122] In an exemplary embodiment, referring to Figures 8A and 8B, the fourth transistor T4 may include at least a fourth active region 14, which may include at least a fourth source region and a fourth drain region. The fourth source region is configured to be connected to the second power line, and the fourth drain region is configured to be connected to the second terminal of the third transistor T3. In at least one pixel row, the fourth active regions 14 in adjacent sub-pixels may be an interconnected integral structure, and adjacent sub-pixels share the same fourth source region.

[0123] The following is an exemplary description of the fabrication process of a display device. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the plane of the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0124] In an exemplary embodiment, taking 12 sub-pixels in 2 pixel rows (the Mth pixel row and the M+1th pixel row) and 6 pixel columns (the Nth pixel column to the N+5th pixel column) as an example, the fabrication process of the display substrate may include the following steps.

[0125] (1) Forming a P-type substrate region and an N-type substrate region on a silicon substrate. In an exemplary embodiment, forming a P-type substrate region and an N-type substrate region on a silicon substrate may include: first providing a silicon substrate, and then forming a P-type substrate region and an N-type substrate region on the silicon substrate by means of coating photoresist, exposure, development, ion implantation, etc., as shown in FIG7, FIG7 is a schematic diagram of the P-type substrate region and the N-type substrate region.

[0126] In an exemplary embodiment, the P-type substrate region may include at least a first substrate region 10A and a first potential line region 10B, wherein the first substrate region 10A is configured to form a P-type transistor and the first potential line region 10B is configured to form a P-type device. The N-type substrate region may include at least a second substrate region 20A and a second potential line region 20B, wherein the second substrate region 20A is configured to form an N-type transistor and the second potential line region 20B is configured to form an N-type device.

[0127] In an exemplary embodiment, in at least one sub-pixel, the first substrate region 10A and the second substrate region 20A may be sequentially disposed along the second direction Y. For example, in a sub-pixel in the Mth pixel row, the first substrate region 10A may be disposed on one side of the second substrate region 20A along the second direction Y. Similarly, in a sub-pixel in the M+1th pixel row, the second substrate region 20A may be disposed on one side of the first substrate region 10A along the second direction Y.

[0128] In an exemplary embodiment, the first potential line region 10B may be a strip extending along the second direction Y, and may be disposed between adjacent second substrate regions 20A partially along the first direction X. For example, the first potential line region 10B may be disposed between the second substrate regions 20A in the Nth pixel column and the (N+1)th pixel column. Alternatively, the first potential line region 10B may be disposed between the second substrate regions 20A in the (N+2)th pixel column and the (N+3)th pixel column. Yet another example is that the first potential line region 10B may be disposed between the second substrate regions 20A in the (N+4)th pixel column and the (N+5)th pixel column.

[0129] In an exemplary embodiment, the second potential line region 20B can be a strip shape extending along the second direction Y, and can be disposed between partially adjacent first substrate regions 10A along the first direction X. For example, the second potential line region 20B can be disposed between the first substrate regions 10A in the Nth pixel column and the (N+1)th pixel column. Alternatively, the second potential line region 20B can be disposed between the first substrate regions 10A in the (N+2)th pixel column and the (N+3)th pixel column. Yet another example is that the second potential line region 20B can be disposed between the first substrate regions 10A in the (N+4)th pixel column and the (N+5)th pixel column.

[0130] In an exemplary embodiment, the P-type substrate region and N-type substrate region of adjacent pixel rows can be mirror-symmetrical with respect to the first center line O1. For example, the first substrate region 10A, the first potential line region 10B, the second substrate region 20A, and the second potential line region 20B in the (M-1)th pixel row and the Mth pixel row can be mirror-symmetrical with respect to the first center line O1. Similarly, the first substrate region 10A, the first potential line region 10B, the second substrate region 20A, and the second potential line region 20B in the Mth pixel row and the M+1th pixel row can be mirror-symmetrical with respect to the first center line O1. Furthermore, the first substrate region 10A, the first potential line region 10B, the second substrate region 20A, and the second potential line region 20B in the M+1th pixel row and the M+2th pixel row can be mirror-symmetrical with respect to the first center line O1.

[0131] In an exemplary embodiment, the first potential line region 10B of adjacent pixel columns can be mirror-symmetrical with respect to the second center line O2, and the second substrate region 20A of adjacent pixel columns can be mirror-symmetrical with respect to the second center line O2. For example, the first potential line region 10B in the Nth pixel column and the (N+1)th pixel column can be mirror-symmetrical with respect to the second center line O2, and the second substrate region 20A in the Nth pixel column and the (N+2)th pixel column can be mirror-symmetrical with respect to the second center line O2. Similarly, the first potential line region 10B in the (N+1)th pixel column and the (N+2)th pixel column can be mirror-symmetrical with respect to the second center line O2, and the second substrate region 20A in the (N+2)th pixel column and the (N+3)th pixel column can be mirror-symmetrical with respect to the second center line O2. For example, the first potential line region 10B in the N+3 and N+4 pixel columns can be mirror-symmetrical with respect to the second center line O2, and the second substrate region 20A in the N+3 and N+4 pixel columns can be mirror-symmetrical with respect to the second center line O2.

[0132] In an exemplary embodiment, the positions and shapes of the first substrate regions 10A of adjacent pixel columns can be substantially the same.

[0133] In an exemplary embodiment, in at least one pixel column, two first substrate regions 10A in adjacent sub-pixels can be an interconnected integral structure. For example, two first substrate regions 10A in the Mth pixel row and the M+1th pixel row can be an interconnected integral structure.

[0134] In an exemplary embodiment, in at least one pixel row, the first substrate regions 10A in adjacent sub-pixels can be interconnected as a single, integral structure. For example, multiple first substrate regions 10A in the Mth pixel row can be interconnected as a single, integral structure. Similarly, multiple first substrate regions 10A in the (M+1)th pixel row can be interconnected as a single, integral structure.

[0135] In the embodiments of this disclosure, by setting a first substrate region 10A of an integrated structure, the first transistor T1, the second transistor T2 and the third transistor T3 (a total of 6 transistors) in adjacent pixel rows and adjacent pixel columns can share the same first substrate region 10A. That is, transistors of the same type share the same type of substrate region, which can effectively reduce the layout space used by the first substrate region and reduce the area occupied by the pixel driving circuit, which is beneficial to achieving high resolution.

[0136] In an exemplary embodiment, in at least one pixel column, two second substrate regions 20A in adjacent sub-pixels can be an interconnected integral structure. For example, two second substrate regions 20A in the (M-1)th pixel row and the Mth pixel row can be an interconnected integral structure. Similarly, two second substrate regions 20A in the M+1th pixel row and the M+2th pixel row can be an interconnected integral structure.

[0137] In an exemplary embodiment, in at least one pixel row, two second substrate regions 20A in partially adjacent sub-pixels can be an interconnected integral structure. For example, two second substrate regions 20A in the (N+1)th pixel column and the (N+2)th pixel column can be an interconnected integral structure. Similarly, two second substrate regions 20A in the (N+3)th pixel column and the (N+4)th pixel column can be an interconnected integral structure.

[0138] In the embodiments of this disclosure, by setting a second substrate region 20A with an integrated structure, four fourth transistors T4 in adjacent pixel rows and adjacent pixel columns can share the same second substrate region 20A. That is, transistors of the same type share the same type of substrate region, which can effectively reduce the layout space used by the second substrate region and reduce the area occupied by the pixel driving circuit, which is beneficial to achieving high resolution.

[0139] In an exemplary embodiment, the silicon substrate may be a P-type silicon material or an N-type silicon material, and this disclosure does not limit it.

[0140] (2) An active region pattern is formed on the silicon substrate on which the aforementioned pattern is formed, as shown in Figures 8A and 8B. Figure 8A is a schematic diagram of the substrate and the active region, and Figure 8B is a schematic diagram of the active region in Figure 8A.

[0141] In an exemplary embodiment, the active area pattern of each sub-pixel in the display substrate may include at least: a first active area 11, a second active area 12, a third active area 13, and a fourth active area 14.

[0142] In an exemplary embodiment, the shape of the first active region 11 can be a strip shape extending along the second direction Y, and it can be disposed within the region where the first substrate region 10A is located. The first active region 11 can serve as the active region of the first transistor T1.

[0143] In an exemplary embodiment, the shape of the second active region 12 can be a strip shape extending along the second direction Y, and it can be disposed within the region where the first substrate region 10A is located. The second active region 12 can serve as the active region of the second transistor T2.

[0144] In an exemplary embodiment, the shape of the third active region 13 can be a strip shape extending along the second direction Y, and it can be disposed within the region where the first substrate region 10A is located. The third active region 13 can serve as the active region of the third transistor T3.

[0145] In an exemplary embodiment, the shape of the fourth active region 14 can be a strip shape extending along the first direction X, and it can be disposed within the region where the second substrate region 20A is located. The fourth active region 14 can serve as the active region of the fourth transistor T4.

[0146] In an exemplary embodiment, in at least one sub-pixel, in the first direction X, the second active region 12 may be disposed on one side of the first active region 11 along the first direction, and in the second direction Y, the second active region 12 and the fourth active region 14 may be disposed on opposite sides of the third active region 13. For example, in the Mth pixel row, the first active region 11 and the second active region 12 may be disposed on one side of the third active region 13 along the second direction Y, and the fourth active region 14 may be disposed on the opposite side of the third active region 13 along the second direction Y. As another example, in the (M+1)th pixel row, the first active region 11 and the second active region 12 may be disposed on the opposite side of the third active region 13 along the second direction Y, and the fourth active region 14 may be disposed on one side of the third active region 13 along the second direction Y.

[0147] In an exemplary embodiment, the active region pattern may further include a first power region 15 and a second power region 16.

[0148] In an exemplary embodiment, the first power region 15 may be a strip shape extending along the second direction Y, and may be located within the area where the second potential line region 20B is located. The first power region 15 is configured to be connected to the first power line subsequently formed.

[0149] In an exemplary embodiment, the second power region 16 may be a strip shape extending along the second direction Y, and may be located within the region where the first potential line region 10B is located. The second power region 16 is configured to be connected to a second power line subsequently formed.

[0150] In an exemplary embodiment, the active area patterns of adjacent pixel rows can be mirror-symmetrical with respect to the first center line O1. For example, the first active area 11 to the fourth active area 14, the first power area 15, and the second power area 16 in the (M-1)th pixel row and the Mth pixel row can be mirror-symmetrical with respect to the first center line O1. Similarly, the first active area 11 to the fourth active area 14, the first power area 15, and the second power area 16 in the Mth pixel row and the M+1th pixel row can be mirror-symmetrical with respect to the first center line O1. Furthermore, the first active area 11 to the fourth active area 14, the first power area 15, and the second power area 16 in the M+1th pixel row and the M+2th pixel row can be mirror-symmetrical with respect to the first center line O1.

[0151] In an exemplary embodiment, the fourth active region 14 and the second power region 16 of adjacent pixel columns can be mirror-symmetrical with respect to the second center line O2. For example, the fourth active region 14 and the second power region 16 in the (N+1)th and (N+2)th pixel columns can be mirror-symmetrical with respect to the second center line O2. Similarly, the fourth active region 14 and the second power region 16 in the (N+2)th and (N+3)th pixel columns can be mirror-symmetrical with respect to the second center line O2. Furthermore, the fourth active region 14 and the second power region 16 in the (N+3)th and (N+4)th pixel columns can be mirror-symmetrical with respect to the second center line O2.

[0152] In an exemplary embodiment, the orthographic projection of the first power region 15 onto the silicon substrate overlaps with a portion of the second centerline O2.

[0153] In an exemplary embodiment, the positions and shapes of the first active region 11, the second active region 12, and the third active region 13 of adjacent pixel columns can be substantially the same.

[0154] In an exemplary embodiment, the active region of each transistor may include a source region, a drain region, and a channel region located between the source region and the drain region.

[0155] In an exemplary embodiment, in at least one sub-pixel, the second active region 12 and the third active region 13 can be an integral structure that is interconnected, the second drain region 12-2 of the second active region and the third source region 13-1 of the third active region can be interconnected, and the second drain region 12-2 of the second active region can serve as the third source region 13-1 of the third active region.

[0156] In an exemplary embodiment, in at least one pixel column, the first active regions 11 in adjacent sub-pixels can be an integral structure interconnected, and the first active regions 11 of two sub-pixels can share the same first source region 11-1. For example, two sub-pixels in the Mth pixel row and the M+1th pixel row can share the same first source region 11-1. In the embodiments of this disclosure, by setting the first transistors T1 of adjacent pixel rows to be mirrored and sharing the first pole of the first transistors T1, the vertical wiring space can be effectively reduced, the number of vias can be reduced, and the area occupied by the pixel driving circuit can be reduced, which is beneficial to achieving high resolution.

[0157] In an exemplary embodiment, in at least one pixel column, the second active regions 12 in adjacent sub-pixels can be an integral structure interconnected, and the second active regions 12 of two sub-pixels can share the same second source region 12-1. For example, two sub-pixels in the Mth pixel row and the M+1th pixel row can share the same second source region 12-1. In the embodiments of this disclosure, by setting the second transistors T2 of adjacent pixel rows to be mirrored and sharing the first pole of the second transistors T2, the vertical wiring space can be effectively reduced, the number of vias can be reduced, and the area occupied by the pixel driving circuit can be reduced, which is beneficial to achieving high resolution.

[0158] In an exemplary embodiment, in at least one pixel row, the fourth active regions 14 in some adjacent sub-pixels can be an integral structure interconnected, and the fourth active regions 14 of two sub-pixels can share the same fourth source region 14-1. For example, two sub-pixels in the (N+1)th pixel column and the (N+2)th pixel column can share the same fourth source region 14-1. Similarly, two sub-pixels in the (N+3)th pixel column and the (N+4)th pixel column can share the same fourth source region 14-1. In the embodiments of this disclosure, by setting the fourth transistors T4 of some adjacent pixel columns to be mirrored and sharing the first pole of the fourth transistor T4, the lateral wiring space can be effectively reduced, the number of vias can be reduced, and the area occupied by the pixel driving circuit can be reduced, which is beneficial for achieving high resolution.

[0159] In an exemplary embodiment, since the first active regions 11 in adjacent pixel rows are mirror images and interconnected as a single structure, and the second active regions 12 in adjacent pixel rows are mirror images and interconnected as a single structure, and the second active regions 12 and the third active regions 13 in each sub-pixel are interconnected as a single structure, the first transistors T1, T2, and T3 (a total of 6 transistors) in adjacent pixel rows and adjacent pixel columns can be configured to share the same first substrate region 10A. That is, transistors of the same type share the same type of substrate region, which can effectively reduce the layout space used by the first substrate region and reduce the area occupied by the pixel driving circuit, which is beneficial to achieving high resolution.

[0160] In an exemplary embodiment, since the fourth active region 14 in adjacent pixel rows is mirrored and the fourth active region 14 in some adjacent pixel columns is mirrored and is an integral structure connected to each other, the four fourth transistors T4 in adjacent pixel rows and adjacent pixel columns can be configured to share the same second substrate region 20A. That is, transistors of the same type share the same type of substrate region, which can effectively reduce the layout space used by the second substrate region, reduce the area occupied by the pixel driving circuit, and help achieve high resolution.

[0161] In an exemplary embodiment, the first active region 11 may have a first active width B1, the second active region 12 may have a second active width B2, the third active region 13 may have a third active width B3, and the fourth active region 14 may have a fourth active width B4. The first active width B1, the second active width B2, and the third active width B3 may be dimensions in the first direction X, and the fourth active width B4 may be dimensions in the second direction Y.

[0162] In an exemplary embodiment, the third active width B3 may be greater than the first active width B1, the third active width B3 may be greater than the second active width B2, and the third active width B3 may be greater than the fourth active width B4.

[0163] In an exemplary embodiment, the first active width B1 may be greater than the second active width B2, and the first active width B1 may be greater than the fourth active width B4.

[0164] In an exemplary embodiment, the second active width B2 and the fourth active width B4 may be substantially the same.

[0165] (3) Forming a gate conductive layer pattern. In an exemplary embodiment, forming a gate conductive layer pattern may include: sequentially depositing a first insulating film and a polysilicon film on a silicon substrate on which the aforementioned pattern is formed; firstly, patterning the polysilicon film using a patterning process to form a first insulating layer covering the active region pattern and a polysilicon layer pattern disposed on the first insulating layer; and then doping the polysilicon layer to form a gate conductive layer pattern, as shown in Figures 9A and 9B, where Figure 9A is a schematic diagram of the active region and the gate conductive layer, and Figure 9B is a schematic diagram of the gate conductive layer in Figure 9A.

[0166] In an exemplary embodiment, the gate conductive layer pattern of each sub-pixel in the display substrate may include at least: a first gate electrode 21, a second gate electrode 22, a fourth gate electrode 24, and a first electrode plate 110.

[0167] In an exemplary embodiment, the first electrode plate 110 may be rectangular in shape, and the orthographic projection of the first electrode plate 110 on the silicon substrate may at least partially overlap with the orthographic projection of the third active region 13 on the silicon substrate. The first electrode plate 110 may serve as the gate electrode of the third transistor T3 on one hand, and as the lower electrode plate of the first capacitor on the other hand.

[0168] In an exemplary embodiment, a first electrode plate connecting block 110-1 may be provided on the first electrode plate 110. The shape of the first electrode plate connecting block 110-1 may be block-shaped (such as rectangular), and it may be provided on one side of the first electrode plate 110 in the opposite direction of the first direction X, and connected to the first electrode plate 110.

[0169] In an exemplary embodiment, in at least one sub-pixel, the first electrode plate 110 and the first electrode plate connecting block 110-1 can be an integral structure that is interconnected.

[0170] In an exemplary embodiment, the first gate electrode 21 can be block-shaped (such as rectangular), and the corners of the rectangular shape can be chamfered or grooved. The orthographic projection of the first gate electrode 21 on the silicon substrate at least partially overlaps with the orthographic projection of the first active region 11 on the silicon substrate. The first gate electrode 21 can serve as the gate electrode of the first transistor T1.

[0171] In an exemplary embodiment, a first gate connection block 21-1 may be provided on the first gate electrode 21. The first gate connection block 21-1 may be block-shaped (such as rectangular), and may be provided on the side of the first gate electrode 21 near the second gate electrode 22 and connected to the first gate electrode 21. The first gate connection block 21-1 is configured to be connected to the subsequently formed first scan signal line.

[0172] In an exemplary embodiment, the second gate electrode 22 may be block-shaped (e.g., rectangular), and the orthographic projection of the second gate electrode 22 on the silicon substrate at least partially overlaps with the orthographic projection of the second active region 12 on the silicon substrate. The second gate electrode 22 may serve as the gate electrode of the second transistor T2.

[0173] In an exemplary embodiment, a second gate connection block 22-1 may be provided on the second gate electrode 22. The shape of the second gate connection block 22-1 may be block-shaped (such as rectangular), and it may be located on the side of the second gate electrode 22 away from the first gate electrode 21 and connected to the second gate electrode 22. The second gate connection block 22-1 is configured to be connected to the second scan signal line subsequently formed.

[0174] In an exemplary embodiment, in at least one sub-pixel, the first gate connection block 21-1 and the second gate connection block 22-1 are arranged opposite to each other to avoid short circuits between the connection vias of the first scan signal line and the first gate connection block, the connection vias of the second scan signal line and the second gate connection block, and the subsequently formed second power connection line.

[0175] It should be noted that the “opposite setting” here can mean that in at least one sub-pixel, in the second direction Y, the first gate connecting block 21-1 is located on one side of the first gate electrode 21 along the second direction Y, and the second gate connecting block 22-1 is located on the opposite side of the second gate electrode 22 along the second direction Y. That is, in the second direction Y, the distance between the first gate connecting block 21-1 and the second gate connecting block 22-1 is relatively large.

[0176] It should also be noted that, in the exemplary embodiment, in at least one sub-pixel, in the first direction, the first gate connection block 21-1 and the second gate connection block 22-1 are respectively disposed on the same side of the first gate electrode 21 and the second gate electrode 22.

[0177] In an exemplary embodiment, the fourth gate electrode 24 may be block-shaped (e.g., rectangular), and the orthographic projection of the fourth gate electrode 24 on the silicon substrate at least partially overlaps with the orthographic projection of the fourth active region 14 on the silicon substrate. The fourth gate electrode 24 may serve as the gate electrode of the fourth transistor T4.

[0178] In an exemplary embodiment, a fourth gate connecting block 24-1 may be provided on the fourth gate electrode 24. The fourth gate connecting block 24-1 may be block-shaped (such as rectangular), and may be provided on the side of the fourth gate electrode 24 near the first electrode plate 110 and connected to the fourth gate electrode 24.

[0179] In an exemplary embodiment, the gate conductive layer patterns of adjacent pixel rows can be mirror-symmetrical with respect to the first center line O1. For example, the first gate electrode 21, the second gate electrode 22, the fourth gate electrode 24, and the first electrode plate 110 in the (M-1)th pixel row and the Mth pixel row can be mirror-symmetrical with respect to the first center line O1. Similarly, the first gate electrode 21, the second gate electrode 22, the fourth gate electrode 24, and the first electrode plate 110 in the Mth pixel row and the M+1th pixel row can be mirror-symmetrical with respect to the first center line O1. Furthermore, the first gate electrode 21, the second gate electrode 22, the fourth gate electrode 24, and the first electrode plate 110 in the M+1th pixel row and the M+2th pixel row can be mirror-symmetrical with respect to the first center line O1.

[0180] In an exemplary embodiment, the fourth gate electrode 24 of adjacent pixel columns can be mirror-symmetrical with respect to the second center line O2. For example, the fourth gate electrode 24 in the (N+1)th pixel column and the (N+2)th pixel column can be mirror-symmetrical with respect to the second center line O2. Similarly, the fourth gate electrode 24 in the (N+2)th pixel column and the (N+3)th pixel column can be mirror-symmetrical with respect to the second center line O2. Furthermore, the fourth gate electrode 24 in the (N+3)th pixel column and the (N+4)th pixel column can be mirror-symmetrical with respect to the second center line O2.

[0181] In an exemplary embodiment, the positions and shapes of the first gate electrode 21, the second gate electrode 22, and the first electrode plate 110 of adjacent pixel columns can be substantially the same.

[0182] In an exemplary embodiment, the first gate electrode 21 may have a first gate length C1, the second gate electrode 22 may have a second gate length C2, the first electrode plate 110 (third gate electrode 23) may have a third gate length C3, and the fourth gate electrode 24 may have a fourth gate length C4. The first gate length C1, the second gate length C2, and the third gate length C3 may be dimensions along the second direction Y, and the fourth gate length C4 may be dimensions along the first direction X.

[0183] In an exemplary embodiment, the third gate length C3 may be greater than the first gate length C1, the third gate length C3 may be greater than the second gate length C2, and the third gate length C3 may be greater than the fourth gate length C4.

[0184] In an exemplary embodiment, the first gate length C1 may be greater than the second gate length C2, and the first gate length C1 may be greater than the fourth gate length C4.

[0185] In an exemplary embodiment, the second gate length C2 and the fourth gate length C4 may be substantially the same.

[0186] In an exemplary embodiment, the aspect ratio of the third transistor T3 may be smaller than that of the first transistor T1, the aspect ratio of the first transistor T1 may be smaller than that of the second transistor T2, and the aspect ratios of the second transistor T2 and the fourth transistor T4 may be substantially the same. The aspect ratio may be the ratio of the active width to the gate length.

[0187] In an exemplary embodiment, after forming the gate conductive layer pattern, the process may further include forming a P-type doped (SP) region and an N-type doped (SN) region. The P-type doped region may be located in a P-type substrate region, such that P-type source and drain regions are formed on both sides of the first, second, and third gate electrodes along the second direction Y, respectively. The N-type doped region may be located in an N-type substrate region, such that N-type source and drain regions are formed on both sides of the fourth gate electrode along the first direction X, respectively.

[0188] (4) Forming a second insulating layer pattern. In an exemplary embodiment, forming a second insulating layer pattern may include: depositing a second insulating film on a silicon substrate on which the aforementioned pattern is formed, and patterning the second insulating film by a patterning process to form a second insulating layer covering the gate conductive layer pattern. The second insulating layer is provided with a plurality of vias, as shown in FIG10, FIG10 being a schematic diagram of the active region, the gate conductive layer and the second insulating layer.

[0189] In an exemplary embodiment, the plurality of vias in each sub-pixel of the display substrate may include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, and an eleventh via V11.

[0190] In an exemplary embodiment, the orthogonal projection of the first via V1 onto the silicon substrate may be located within the range of the orthogonal projection of the first source region of the first active region onto the silicon substrate. The first insulating layer and the second insulating layer within the first via V1 are etched away, exposing the surface of the first source region. The first via V1 is configured to allow the subsequently formed first connection electrode to be connected to the first source region through the via.

[0191] In an exemplary embodiment, since the first active regions of adjacent sub-pixels in a pixel column are interconnected as an integral structure, and the two sub-pixels share the first source region, adjacent sub-pixels in a pixel column can share the same first via V1, which can effectively reduce the number of vias. This not only reduces the area occupied by the pixel driving circuit, which is beneficial to achieving high resolution, but also reduces the process difficulty and improves the yield.

[0192] In an exemplary embodiment, the orthographic projection of the first via V1 onto the silicon substrate at least partially overlaps with the orthographic projection of the first centerline O1 onto the silicon substrate.

[0193] In an exemplary embodiment, the orthogonal projection of the second via V2 onto the silicon substrate may be located within the range of the orthogonal projection of the second source region of the second active region onto the silicon substrate. The first and second insulating layers within the second via V2 are etched away, exposing the surface of the second source region. The second via V2 is configured to allow a subsequently formed second connection electrode to be connected to the second source region through the via.

[0194] In an exemplary embodiment, since the second active regions of adjacent sub-pixels in a pixel column are interconnected as an integral structure, and the two sub-pixels share the second source region, adjacent sub-pixels in a pixel column can share the same second via V2, which can effectively reduce the number of vias. This not only reduces the area occupied by the pixel driving circuit, which is beneficial to achieving high resolution, but also reduces the process difficulty and improves the yield.

[0195] In an exemplary embodiment, the orthographic projection of the second via V2 onto the silicon substrate at least partially overlaps with the orthographic projection of the first centerline O1 onto the silicon substrate.

[0196] In an exemplary embodiment, in at least one pixel row, a plurality of first vias V1 and a plurality of second vias V2 may be located on the same straight line extending along the first direction X, which not only helps to improve process uniformity, but also helps to increase the wiring space for the subsequently formed first scan signal lines and second scan signal lines.

[0197] In an exemplary embodiment, the orthogonal projection of the third via V3 onto the silicon substrate may be located within the orthogonal projection range of the first drain region of the first active region onto the silicon substrate. The first and second insulating layers within the third via V3 are etched away, exposing the surface of the first drain region. The third via V3 is configured to allow a subsequently formed third connection electrode to be connected to the first drain region through the via.

[0198] In an exemplary embodiment, the orthogonal projection of the fourth via V4 onto the silicon substrate may be located within the range of the orthogonal projection of the second drain region (which is also the third source region of the third active region) onto the silicon substrate. The first and second insulating layers within the fourth via V4 are etched away, exposing the surface of the second drain region (which is also the third source region). The fourth via V4 is configured to allow the subsequently formed fourth connection electrode to be connected to the second drain region (which is also the third source region) through the via.

[0199] In an exemplary embodiment, the orthogonal projection of the fifth via V5 onto the silicon substrate may be located within the orthogonal projection of the third drain region of the third active region onto the silicon substrate. The first and second insulating layers within the fifth via V5 are etched away, exposing the surface of the third drain region. The fifth via V5 is configured to allow the subsequently formed fifth connection electrode to be connected to the third drain region through the via.

[0200] In an exemplary embodiment, the orthogonal projection of the sixth via V6 onto the silicon substrate may be located within the orthogonal projection of the fourth source region of the fourth active region onto the silicon substrate. The first and second insulating layers within the sixth via V6 are etched away, exposing the surface of the fourth source region. The sixth via V6 is configured to allow the subsequently formed eighth connection electrode to be connected to the fourth source region through the via.

[0201] In an exemplary embodiment, since the fourth active regions of some adjacent sub-pixels in a pixel row are interconnected as an integral structure, and the two sub-pixels share the fourth source region, some adjacent sub-pixels in a pixel row can share the same sixth via V6, which can effectively reduce the number of vias. This not only reduces the area occupied by the pixel driving circuit, which is beneficial to achieving high resolution, but also reduces the process difficulty and improves the yield.

[0202] In an exemplary embodiment, the orthogonal projection of the seventh via V7 onto the silicon substrate may be located within the orthogonal projection of the fourth drain region of the fourth active region onto the silicon substrate. The first and second insulating layers within the seventh via V7 are etched away, exposing the surface of the fourth drain region. The seventh via V7 is configured to allow the subsequently formed fifth connection electrode 45 to be connected to the fourth drain region through the via.

[0203] In an exemplary embodiment, the orthogonal projection of the eighth via V8 onto the silicon substrate may be located within the range of the orthogonal projection of the first gate connection block 21-1 of the first gate electrode 21 onto the silicon substrate. The second insulating layer within the eighth via V8 is etched away, exposing the surface of the first gate connection block 21-1. The eighth via V8 is configured to allow the subsequently formed first scan signal line to be connected to the first gate connection block 21-1 through the via.

[0204] In an exemplary embodiment, the orthogonal projection of the ninth via V9 onto the silicon substrate may be located within the range of the orthogonal projection of the second gate connection block 22-1 of the second gate electrode 22 onto the silicon substrate. The second insulating layer within the ninth via V9 is etched away, exposing the surface of the second gate connection block 22-1. The ninth via V9 is configured to allow the subsequently formed ninth connection electrode 49 to be connected to the second gate connection block 22-1 through the via.

[0205] In an exemplary embodiment, the orthographic projection of the tenth via V10 onto the silicon substrate may be located within the range of the orthographic projection of the first electrode connection block 110-1 of the first electrode 110 onto the silicon substrate. The second insulating layer within the tenth via V10 is etched away, exposing the surface of the first electrode connection block 110-1. The tenth via V10 is configured to allow the subsequently formed third connection electrode to be connected to the first electrode connection block 110-1 through the via.

[0206] In an exemplary embodiment, the orthogonal projection of the eleventh via V11 onto the silicon substrate may be located within the range of the orthogonal projection of the fourth gate connection block 24-1 of the fourth gate electrode 24 onto the silicon substrate. The second insulating layer within the eleventh via V11 is etched away, exposing the surface of the fourth gate connection block 24-1. The eleventh via V11 is configured to allow the subsequently formed sixth connection electrode to be connected to the fourth gate connection block 24-1 through the via.

[0207] In an exemplary embodiment, the plurality of vias on the second insulating layer may further include a twelfth via V12 and a thirteenth via V13.

[0208] In an exemplary embodiment, the orthographic projection of the twelfth via V12 onto the silicon substrate may be within the range of the orthographic projection of the first power region 15 onto the silicon substrate. The first and second insulating layers within the twelfth via V12 are etched away, exposing the surface of the first power region 15. The twelfth via V12 is configured to allow a subsequently formed seventh connection electrode to be connected to the first power region 15 through the via.

[0209] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 onto the silicon substrate may be within the range of the orthographic projection of the second power region 16 onto the silicon substrate. The first and second insulating layers within the thirteenth via V13 are etched away, exposing the surface of the second power region 16. The thirteenth via V13 is configured to allow a subsequently formed second power line to be connected to the second power region 16 through the via.

[0210] In an exemplary embodiment, one or more of the first via V1 to the thirteenth via V13 may employ a multiple via structure to reduce contact resistance and improve connection reliability.

[0211] (5) Forming a first conductive layer pattern. In an exemplary embodiment, forming a first conductive layer pattern may include: depositing a first conductive thin film on a silicon substrate on which the aforementioned pattern is formed, patterning the first conductive thin film using a patterning process, and forming the first conductive layer pattern on a second insulating layer, as shown in Figures 11A and 11B. Figure 11A is a schematic diagram of the active region, the gate conductive layer, the second insulating layer, and the first conductive layer. Figure 11B is a schematic diagram of the first conductive layer in Figure 11A. Figure 12 is an enlarged view of region B in Figure 11A. In an exemplary embodiment, the first conductive layer may be referred to as a first metal layer.

[0212] In an exemplary embodiment, the first conductive layer pattern in each sub-pixel of the display substrate may include at least: a first scan signal line 31, a first connection electrode 41, a second connection electrode 42, a third connection electrode 43, a fourth connection electrode 44, a fifth connection electrode 45, a sixth connection electrode 46, a seventh connection electrode 47, an eighth connection electrode 48, a ninth connection electrode 49, and a second power line 82.

[0213] In an exemplary embodiment, the first scan signal line 31 can be a straight line extending along the first direction X, and can be located on the side of the first electrode plate 110 away from the fourth gate electrode 24. The first scan signal line 31 can be connected to the first gate connection block 21-1 of each sub-pixel through the eighth via V8. Since the first gate connection block 21-1 is connected to the first gate electrode 21, the first scan signal line 31 is connected to the gate electrode of the first transistor T1, and the first scan signal line 31 can control the first transistor T1 to be turned on or off.

[0214] In an exemplary embodiment, the orthographic projection of the first scan signal line 31 on the display substrate plane at least partially overlaps with the orthographic projection of the second active region 12 on the display substrate plane. Meanwhile, the orthographic projection of the first scan signal line 31 on the silicon substrate does not overlap with the orthographic projection of the second gate electrode 22 on the silicon substrate. This effectively eliminates the coupling capacitance between the first scan signal line 31 and the second transistor T2, reduces the rise time and fall time of the scan signal line, thereby increasing the effective bandwidth of the signal, improving the debuggability of the scan signal, and enhancing the circuit driving capability.

[0215] In an exemplary embodiment, since the second active regions 12 in adjacent pixel rows are interconnected as a single structure, the orthographic projection of the first scan signal line 31 on the silicon substrate and the orthographic projection of the second active region 12 on the silicon substrate at least partially overlap.

[0216] In an exemplary embodiment, since the plurality of first connection electrodes 41 and the plurality of second connection electrodes 42 are located between two first scan signal lines 31 in adjacent pixel rows and are located on the same straight line extending along the first direction X, the wiring space of the first scan signal lines 31 is effectively increased. The increased wiring space can effectively increase the width of the first scan signal lines, effectively reduce the resistance of the first scan signal lines 31, effectively reduce the RC loading and IR drop of the signal lines, effectively improve the driving capability of the pixel driving circuit, and effectively improve display stability and uniformity. Furthermore, the increased wiring space allows the first scan signal lines 31 to be configured as straight lines. Compared to a concave-convex zigzag shape, a straight first scan signal line 31 can reduce its extension length, further reducing the signal line resistance.

[0217] In an exemplary embodiment, the first connection electrode 41 may be block-shaped (e.g., rectangular) and may be disposed between two first scan signal lines 31 of adjacent pixel rows. The first connection electrode 41 may be connected to the first source region through the first via V1 and may be configured to be connected to the subsequently formed eleventh connection electrode.

[0218] In an exemplary embodiment, since adjacent sub-pixels in a pixel column share the first source region and the first via V1, adjacent sub-pixels in a pixel column can share the same first connection electrode 41, which effectively reduces the number of connection electrodes, reduces the area occupied by the pixel driving circuit, and is beneficial to achieving high resolution.

[0219] In an exemplary embodiment, in at least one sub-pixel, the orthographic projection of the first connecting electrode 41 on the silicon substrate at least partially overlaps with the orthographic projection of the first center line O1 on the silicon substrate.

[0220] In an exemplary embodiment, the second connection electrode 42 may be block-shaped (e.g., rectangular) and may be disposed between two first scan signal lines 31 of adjacent pixel rows. The second connection electrode 42 may be connected to the second source region through the second via V2 and may be configured to be connected to the subsequently formed twelfth connection electrode.

[0221] In an exemplary embodiment, since adjacent sub-pixels in a pixel column share the second source region and the second via V2, adjacent sub-pixels in a pixel column can share the same second connection electrode 42, which effectively reduces the number of connection electrodes, reduces the area occupied by the pixel driving circuit, and is beneficial to achieving high resolution.

[0222] In an exemplary embodiment, in at least one sub-pixel, the orthographic projection of the second connecting electrode 42 on the silicon substrate at least partially overlaps with the orthographic projection of the first center line O1 on the silicon substrate.

[0223] In an exemplary embodiment, in at least one pixel row, a plurality of first connection electrodes 41 and a plurality of second connection electrodes 42 may be located on the same straight line extending along the first direction X, which is beneficial to improving process uniformity and also helps to increase the wiring space of the second scan signal line.

[0224] In an exemplary embodiment, the third connecting electrode 43 can be a strip extending along the second direction Y. The first end of the third connecting electrode 43 is connected to the first drain region through the third via V3, and the second end of the third connecting electrode 43 is connected to the first electrode plate connecting block 110-1 through the tenth via V10. Since the first electrode plate connecting block 110-1 is connected to the first electrode plate 110, the third connecting electrode 43 realizes the interconnection between the second electrode of the first transistor T1, the gate electrode of the third transistor T3, and the first electrode plate, forming the first node N1 of the pixel driving circuit. The first electrode plate 110 has the potential of the first node N1.

[0225] In an exemplary embodiment, the fourth connecting electrode 44 can be block-shaped (such as a rectangle or a combination of multiple rectangles), or the fourth connecting electrode 44 can be "L"-shaped. The corners of the rectangle can be chamfered or grooved. The fourth connecting electrode 44 is connected to the second drain region (which is also the third source region) through the fourth via V4 to form the second node N2 of the pixel driving circuit.

[0226] In an exemplary embodiment, the fourth connecting electrode 44 can serve as the second electrode plate 120. Since the fourth connecting electrode 44 is connected to the second drain region and the third source region through a via to form the second node N2 of the pixel driving circuit, the second electrode plate 120 has the potential of the second node N2.

[0227] In an exemplary embodiment, the orthographic projection of the fourth connection electrode 44 on the display substrate plane at least partially overlaps with the orthographic projection of the third gate electrode 23 on the display substrate plane.

[0228] In an exemplary embodiment, the orthographic projection of the second electrode 120 onto the silicon substrate at least partially overlaps with the orthographic projection of the first electrode 110 onto the silicon substrate, and the second electrode 120 can serve as the first intermediate electrode of the first capacitor. Since the first electrode 110 has a potential at the first node N1 and the second electrode 120 has a potential at the second node N2, the first electrode 110 and the second electrode 120 constitute the first sub-capacitor of the first capacitor.

[0229] In an exemplary embodiment, the fifth connecting electrode 45 can be L-shaped. The first end of the fifth connecting electrode 45 is connected to the third drain region through a fifth via V5, and the second end of the fifth connecting electrode 45 is connected to the fourth drain region through a seventh via V7. In an exemplary embodiment, the fifth connecting electrode 45 realizes the connection between the second electrode of the third transistor T2 and the second electrode of the fourth transistor T4, forming the third node N3 of the pixel driving circuit.

[0230] In an exemplary embodiment, in at least one pixel row, the fifth connecting electrodes 45 in adjacent sub-pixels have the same shape.

[0231] In an exemplary embodiment, the "L"-shaped fifth connection electrode 45 may include a first sub-segment 45-1 and a second sub-segment 45-2 connected to each other. The shape of the first sub-segment 45-1 may be a strip shape extending along the first direction X, and the shape of the second sub-segment 45-2 may be a strip shape extending along the second direction Y. The first sub-segment 45-1 is connected to the third drain region through the fifth via V5, and the second sub-segment 45-2 is connected to the fourth drain region through the seventh via V7.

[0232] In an exemplary embodiment, a third sub-segment 45-3 may also be provided on the fifth connecting electrode 45. The third sub-segment 45-3 may be provided on the side of the fifth connecting electrode 45 close to the fourth active region 14. The shape of the third sub-segment 45-3 is a strip shape extending along the first direction X and connected to the second sub-segment 45-2. The third sub-segment 45-3 is connected to the fourth drain region through the seventh via V7.

[0233] In an exemplary embodiment, in at least one sub-pixel, the first sub-segment 45-1, the second sub-segment 45-2, and the third sub-segment 45-3 of the fifth connecting electrode 45 can be an integral structure that is interconnected.

[0234] In an exemplary embodiment, the first segment 45-1 may have a first extension length L1, and the third segment 45-3 may have a second extension length L2. The ratio of the second extension length L2 to the first extension length L1 may be approximately 0.5 to 0.9. The first extension length L1 and the second extension length L2 may be dimensions along a first direction X. For example, the ratio of the second extension length L2 to the first extension length L1 may be 0.5, 0.6, 0.7, 0.73, 0.74, 0.8, or 0.9.

[0235] In an exemplary embodiment, the orthographic projection of the fifth connecting electrode 45 on the display substrate plane at least partially overlaps with the orthographic projection of the third active region 13 on the display substrate plane, and the ratio of the overlapping areas of the orthographic projections in two adjacent sub-pixels is 0.9 to 1.1. In the embodiments of this disclosure, by setting the orthographic projection areas of the fifth connecting electrode 45 on the display substrate plane and the orthographic projection areas of the third active region 13 on the display substrate plane in adjacent pixels to be substantially equal, not only can the uniformity design of the process and coupling capacitor be achieved, but also the uniformity design of the current distribution can be achieved, effectively improving the display stability and uniformity, thereby effectively improving the display effect and display quality.

[0236] In an exemplary embodiment, the orthographic projection of the first sub-segment 45-1 on the display substrate plane overlaps with the orthographic projection of the third active region on the display substrate plane, and the ratio of the overlapping areas of the orthographic projections in two adjacent sub-pixels is not 1.

[0237] In an exemplary embodiment, at least in the same pixel row, among two adjacent sub-pixels, the orthographic projection of the second sub-segment 45-2 on the display substrate plane in one sub-pixel at least partially overlaps with the orthographic projection of the third active region 13 on the display substrate plane, while the orthographic projection of the second sub-segment 45-2 on the display substrate plane in the other sub-pixel does not overlap with the orthographic projection of the third active region 13 on the display substrate plane.

[0238] In an exemplary embodiment, the orthographic projection of the third sub-segment 45-3 on the display substrate plane is located in the orthographic projection of the fourth active region 14 on the display substrate plane, and the orthographic projection of the third sub-segment 45-3 on the display substrate plane at least partially overlaps with the orthographic projection of the fourth gate electrode 14 on the display substrate plane.

[0239] In an exemplary embodiment, the sixth connecting electrode 46 may be a strip shape extending along the second direction Y. The sixth connecting electrode 46 is connected to the fourth gate connecting block 24-1 through the eleventh via V11. The sixth connecting electrode 46 is configured to be connected to the subsequently formed third scan signal line.

[0240] In an exemplary embodiment, the shape of the second power line 82 can be a straight line extending along the first direction X of the main body, and it can be disposed between two fourth gate electrodes 24 of adjacent pixel rows. The second power line 82 is connected to multiple second power regions 16 in the pixel row through multiple thirteenth vias V13, so that the second power line 82 writes the second power signal into the N-type substrate region. This not only achieves a more stable potential reference and ensures that the output circuit has consistent and reliable performance under different operating conditions, but also provides a better signal isolation effect, reduces signal crosstalk and interference, and improves the stability and reliability of the circuit.

[0241] In an exemplary embodiment, the orthographic projection of the second power line 82 onto the silicon substrate at least partially overlaps with the orthographic projection of the first center line O1 onto the silicon substrate.

[0242] In an exemplary embodiment, the first conductive layer pattern may further include a seventh connecting electrode 47 and an eighth connecting electrode 48.

[0243] In an exemplary embodiment, the seventh connecting electrode 47 may be disposed between the first electrode plates 110 adjacent to each other in the first direction X. One end of the seventh connecting electrode 47 is connected to the first power supply area 15 through the twelfth via V12, and the second end of the seventh connecting electrode 47 is configured to be connected to the first power supply connection line subsequently formed.

[0244] In an exemplary embodiment, the seventh connecting electrode 47 may include a first sub-electrode 47-1, a second sub-electrode 47-2, and a third sub-electrode 47-3. The first sub-electrode 47-1 and the third sub-electrode 47-3 are connected through the second sub-electrode 47-2. The first sub-electrode 47-1 and the third sub-electrode 47-3 are strip-shaped extending along the second direction Y. The second sub-electrode 47-2 is strip-shaped extending along the first direction X. In the second direction Y, at least a portion of the first sub-electrode 47-1 and at least a portion of the third sub-electrode 47-3 are located on the same side of the second sub-electrode 47-2. In the embodiments of this disclosure, by setting at least a portion of the first sub-electrode 47-1 and at least a portion of the first sub-electrode 47-3 on the same side as the second sub-electrode 47-2, a region semi-enclosed by the seventh connecting electrode 47 can be formed. The seventh connecting electrode 47 is connected to the first power connection line, which can provide a stable potential signal, which is beneficial for forming a better signal isolation effect in the semi-enclosed region, reducing signal crosstalk and interference, and improving the stability and reliability of the circuit. At the same time, by setting the second sub-electrode 47-2 extending along the first direction X and the first sub-electrode 47-1 and third sub-electrode 47-3 extending along the second direction Y, the facing area of ​​the seventh connecting electrode 47 and the fourth connecting electrode 44 is increased. The fourth connecting electrode 44 has the potential of the second node N2, and the in-plane capacitance of the seventh connecting electrode 47 and the fourth connecting electrode 44 can increase the capacitance value of the second capacitor, which is beneficial for improving the pixel driving capability.

[0245] In an exemplary embodiment, the orthographic projection of the seventh connecting electrode 47 on the display substrate plane semi-encloses the first region A, and the first region A at least partially overlaps with the orthographic projection of the third connecting electrode 43 on the display substrate plane. In embodiments of this disclosure, by placing the third connecting electrode 43 in the semi-enclosed region formed by the seventh connecting electrode 47, the third connecting electrode 43 has the potential of the first node N1, which helps to reduce the influence of other signals on the potential of point N1, and effectively avoids the adverse effects caused by interference noise between the second electrode plate 120, the ninth connecting electrode 49, and other signals and the potential of N1.

[0246] In an exemplary embodiment, the tenth via V10 is projected onto the first region A on the plane of the display substrate.

[0247] In an exemplary embodiment, the orthographic projection of the first sub-electrode 47-1 on the display substrate plane does not overlap with the orthographic projection of the third active region 13 on the display substrate plane, the orthographic projection of the second sub-electrode 47-2 on the display substrate plane overlaps with the orthographic projection of the third active region 13 on the display substrate plane at least partially, and the orthographic projection of the third sub-electrode 47-3 on the display substrate plane is located within the orthographic projection of the third active region on the display substrate plane.

[0248] In an exemplary embodiment, a notch may be provided at one corner of the fourth connecting electrode 44 near the first gate electrode 21, that is, the shape of the fourth connecting electrode is an "L" shape. The edge of the orthographic projection of the fourth connecting electrode 44 on the display substrate plane near the first sub-electrode 47-1 has a first over-width LK1 between the edge of the orthographic projection of the first electrode 110 on the display substrate plane near the first sub-electrode 47-1. The edge of the orthographic projection of the fourth connecting electrode 44 on the display substrate plane near the first sub-electrode 47-1 of the adjacent sub-pixel has a second over-width LK2 between the edge of the orthographic projection of the first electrode 110 on the display substrate plane near the first sub-electrode 47-1 of the adjacent sub-pixel. The first over-width LK1 is greater than the second over-width LK2.

[0249] In an exemplary embodiment, the eighth connection electrode 48 can be a straight line extending along the second direction Y, and can be disposed between two fourth gate electrodes 24 of partially adjacent pixel columns. The first end of the eighth connection electrode 48 is connected to the second power line 82, and the second end of the eighth connection electrode 48 extends towards the first scan signal line 31. The eighth connection electrode 48 is connected to the fourth source region through the sixth via V6. Because the eighth connection electrode 48 is connected to the second power line 82, the second power line 82 can write the second power signal to the first electrode of the fourth transistor T4 of each sub-pixel.

[0250] In an exemplary embodiment, the eighth connection electrode 48 can serve as a second power supply extension, and the second power line 82 is connected to the first electrode of the fourth transistor T4 via the eighth connection electrode 48, which serves as the second power supply extension.

[0251] In an exemplary embodiment, in at least one pixel column, the sixth via V6 and the twelfth via V12 are substantially located on the same straight line extending along the second direction Y, the sixth via V6 and the first sub-electrode 47-1 of the seventh connecting electrode 47 are substantially located on the same straight line extending along the second direction Y, and the distance between the sixth via V6 and the twelfth via V12 in the first direction X is less than the linewidth of the eighth connecting electrode 48.

[0252] In an exemplary embodiment, in at least one pixel column, the twelfth via V12 and the thirteenth via V13 are substantially located on the same straight line extending along the second direction Y, the twelfth via V12 and the first sub-electrode 47-1 of the seventh connecting electrode 47 are substantially located on the same straight line extending along the second direction Y, and the distance between the twelfth via V12 and the thirteenth via V13 in the first direction X is less than the linewidth of the eighth connecting electrode 48.

[0253] In an exemplary embodiment, in at least one sub-pixel, the second power line 82 and the eighth connection electrode 48 can be an integral structure that is interconnected.

[0254] In an exemplary embodiment, the two eighth connection electrodes 48 and one second power line 82 of adjacent pixel rows can be an interconnected integral structure located between the two first scan signal lines 31 of adjacent pixel rows. For example, the eighth connection electrodes 48 and the second power line 82 in the (M-1)th pixel row and the Mth pixel row can be an interconnected integral structure. Similarly, the eighth connection electrodes 48 and the second power line 82 in the (M+1)th pixel row and the (M+2)th pixel row can be an interconnected integral structure.

[0255] In an exemplary embodiment, the ninth connecting electrode 49 may be a strip shape extending along the second direction Y or an inverted "convex" shape along the second direction Y. The ninth connecting electrode 49 is connected to the second gate connecting block 22-1 through the ninth via V9. The ninth connecting electrode 49 is configured to be connected to the subsequently formed fifteenth connecting electrode.

[0256] In an exemplary embodiment, the orthographic projections of the first sub-electrode 47-1 and the first gate electrode 21 on the silicon substrate do not overlap, and the orthographic projections of the third sub-electrode 47-3 and the second gate electrode 22 on the silicon substrate do not overlap. In the second direction Y, there is a fourth spacing D4 between the first sub-electrode 47-1 and the first scan signal line 31, and a third spacing D3 between the third sub-electrode 47-3 and the first scan signal line 31. The fourth spacing D4 is smaller than the third spacing D3. In embodiments of this disclosure, by setting the first sub-electrode 47-1 and the third sub-electrode 47-3 extending along the second direction Y, a gap is formed between the ninth connecting electrode 49, the third connecting electrode 43, and the fourth connecting electrode 44, avoiding mutual interference between signals at different potentials and improving the stability of the output current.

[0257] In an exemplary embodiment, the first sub-electrode 47-1 and the eighth connecting electrode 48 have a second distance D2 in the second direction Y, and the fourth distance D4 is greater than the second distance D2.

[0258] In an exemplary embodiment, in the first direction X, the third via V3 and the second gate connecting block 22-1 are disposed on both sides of the first sub-electrode 47-1, and the orthographic projection of the third via V3 on the display substrate plane and the orthographic projection of the second gate connecting block 22-1 on the display substrate plane are separated by the orthographic projection of the first sub-electrode 47-1 on the display substrate plane.

[0259] In an exemplary embodiment, the orthographic projection of the first sub-electrode 47-1 on the silicon substrate and the orthographic projection of the second gate electrode 22 on the silicon substrate do not overlap. In the first direction X, there is a fifth spacing D5 between the edge of the second gate connection block 22-1 near the first sub-electrode 47-1 and the edge of the first sub-electrode 47-1 near the second gate connection block 22-1. There is a sixth spacing D6 between the edge of the third via V3 near the first sub-electrode 47-1 and the edge of the first sub-electrode 47-1 near the third via V3. The fifth spacing D5 is greater than the sixth spacing D6.

[0260] In an exemplary embodiment, in the first direction X, there is a seventh spacing D7 between the edge of the tenth via V10 near the first sub-electrode 47-1 and the edge of the first sub-electrode 47-1 near the tenth via V10; in the second direction Y, there is an eighth spacing D8 between the edge of the tenth via V10 near the second sub-electrode 47-2 and the edge of the second sub-electrode 47-2 near the tenth via V10; and in the first direction X, there is a ninth spacing D9 between the edge of the tenth via V10 near the third sub-electrode 47-3 and the edge of the third sub-electrode 47-3 near the tenth via V10. The seventh spacing D7 is greater than or equal to the eighth spacing D8, and the seventh spacing D7 is greater than or equal to the ninth spacing D9. In the embodiments of this disclosure, by setting the eighth spacing D8 and the ninth spacing D9 to be smaller than the seventh spacing D7, the overlap area of ​​the orthographic projection of the seventh connecting electrode 47 on the silicon substrate and the orthographic projection of the third gate electrode 23 on the silicon substrate is reduced, increasing the wiring space of the second electrode plate 120 and increasing the capacitance value of the first capacitor, which is beneficial to improving the driving capability of the circuit.

[0261] In an exemplary embodiment, in the first direction X, the first sub-electrode 47-1 is disposed between two adjacent third transistors, separating the two adjacent third transistors. There is a tenth spacing D10 between the edge of the third gate electrode 23 of the sub-pixel where the first sub-electrode 47-1 is located and the edge of the third gate electrode 23 of the sub-pixel where the first sub-electrode 47-1 is located and the edge of the third gate electrode 23 of the adjacent sub-pixel where the first sub-electrode 47-1 is located and the edge of the third gate electrode 23 of the adjacent sub-pixel where the first sub-electrode 47-1 is located and the edge of the third gate electrode 23 of the adjacent sub-pixel where the first sub-electrode 47-1 is located and the edge of the third gate electrode 23 of the adjacent sub-pixel where the first sub-electrode 47-1 is located and the edge of the third gate electrode 23 of the adjacent sub-pixel where the first sub-electrode 47-1 is located and the edge of the first sub-electrode 47-1 ...

[0262] In an exemplary embodiment, in the first direction X, the first sub-electrode 47-1 is disposed between the tenth via V10 and the third transistor of the adjacent sub-pixel, separating the third transistor of the adjacent sub-pixel from the tenth via V10, and the seventh pitch D7 is greater than or equal to the eleventh pitch D11.

[0263] In an exemplary embodiment, in the second direction Y, the fifth via V5 and the second power line 82 have a first spacing D1, and the second power extension has a third extension length L3 on one side of the second power line. The third extension length L3 is substantially equal to the first spacing D1, and the ratio of the third extension length L3 to the first spacing D1 is 0.9 to 1.1. In the embodiments of this disclosure, by setting the third extension length L3 of the second power extension to be approximately equal to the spacing between the fifth via V5 and the second power line 82, potential interference between the third nodes N3 of adjacent pixel columns is avoided, which is beneficial to improving the stability of the display.

[0264] In an exemplary embodiment, the first conductive layer pattern of adjacent pixel rows can be mirror-symmetrical with respect to the first center line O1. For example, the first scan signal line 31, the first connecting electrode 41 to the ninth connecting electrode 49, and the second power line 82 in the (M-1)th pixel row and the Mth pixel row can be mirror-symmetrical with respect to the first center line O1. Similarly, the first scan signal line 31, the first connecting electrode 41 to the ninth connecting electrode 49, and the second power line 82 in the Mth pixel row and the M+1th pixel row can be mirror-symmetrical with respect to the first center line O1. Furthermore, the first scan signal line 31, the first connecting electrode 41 to the ninth connecting electrode 49, and the second power line 82 in the M+1th pixel row and the M+2th pixel row can be mirror-symmetrical with respect to the first center line O1.

[0265] In an exemplary embodiment, the fifth connection electrode 45, sixth connection electrode 46, eighth connection electrode 48, and second power line 82 of adjacent pixel columns can be mirror-symmetrical with respect to the second center line O2. For example, the fifth connection electrode 45, sixth connection electrode 46, eighth connection electrode 48, and second power line 82 in the (N+1)th and (N+2)th pixel columns can be mirror-symmetrical with respect to the second center line O2. Similarly, the fifth connection electrode 45, sixth connection electrode 46, eighth connection electrode 48, and second power line 82 in the (N+2)th and (N+3)th pixel columns can be mirror-symmetrical with respect to the second center line O2. Furthermore, the fifth connection electrode 45, sixth connection electrode 46, eighth connection electrode 48, and second power line 82 in the (N+3)th and (N+4)th pixel columns can be mirror-symmetrical with respect to the second center line O2.

[0266] In an exemplary embodiment, the positions and shapes of the first scan signal line 31, the first connecting electrode 41 to the fourth connecting electrode 44, the seventh connecting electrode 47, and the eighth connecting electrode 48 of adjacent pixel columns can be substantially the same.

[0267] (6) Forming a third insulating layer pattern. In an exemplary embodiment, forming a third insulating layer pattern may include: depositing a third insulating film on a silicon substrate on which the aforementioned pattern is formed, and patterning the third insulating film by a patterning process to form a third insulating layer covering the pattern of the first conductive layer. The third insulating layer is provided with a plurality of vias, as shown in FIG13. FIG13 is a schematic diagram of the first conductive layer, the third insulating layer and the subsequently formed second conductive layer.

[0268] In an exemplary embodiment, the plurality of vias in each sub-pixel of the display substrate may include: a twenty-first via V21, a twenty-second via V22, a twenty-third via V23, a twenty-fourth via V24, a twenty-fifth via V25, a twenty-sixth via V26, a twenty-seventh via V27, a twenty-eighth via V28, and a twenty-ninth via V29.

[0269] In an exemplary embodiment, the orthographic projection of the 21st via V21 onto the silicon substrate may be within the range of the orthographic projection of the first connection electrode 41 onto the silicon substrate. The third insulating layer within the 21st via V21 is etched away, exposing the surface of the first connection electrode 41. The 21st via V21 is configured to allow the subsequently formed 11th connection electrode to be connected to the first connection electrode 41 through the via.

[0270] In an exemplary embodiment, the orthographic projection of the twenty-first via V21 on the silicon substrate at least partially overlaps with the orthographic projection of the first centerline O1 on the silicon substrate.

[0271] In an exemplary embodiment, the orthogonal projection of the 22nd via V22 onto the silicon substrate may be within the range of the orthogonal projection of the second connection electrode 42 onto the silicon substrate. The third insulating layer within the 22nd via V22 is etched away, exposing the surface of the second connection electrode 42. The 22nd via V22 is configured to allow the subsequently formed 12th connection electrode to be connected to the second connection electrode 42 through the via.

[0272] In an exemplary embodiment, the orthographic projection of the 22nd via V22 onto the silicon substrate at least partially overlaps with the orthographic projection of the first centerline O1 onto the silicon substrate.

[0273] In an exemplary embodiment, in at least one pixel row, a plurality of twenty-first vias V21 and a plurality of twenty-second vias V22 may be located on the same straight line extending along the first direction X.

[0274] In an exemplary embodiment, the orthogonal projection of the 23rd via V23 onto the silicon substrate may be located within the range of the orthogonal projection of the third connecting electrode 43 onto the silicon substrate. The third insulating layer within the 23rd via V23 is etched away, exposing the surface of the third connecting electrode 43. The 23rd via V23 is configured to allow the subsequently formed third electrode plate 130 to be connected to the third connecting electrode 43 through the via.

[0275] In an exemplary embodiment, the orthogonal projection of the 24th via V24 onto the silicon substrate may be within the range of the orthogonal projection of the fourth connection electrode 44 onto the silicon substrate. The third insulating layer within the 24th via V24 is etched away, exposing the surface of the fourth connection electrode 44. The 24th via V24 is configured to allow the subsequently formed fourth electrode plate to be connected to the fourth connection electrode 44 through the via.

[0276] In an exemplary embodiment, the twenty-fourth via V24 can be disposed at one end of the fourth connecting electrode 44 near the second center line O2, and its orthogonal projection on the silicon substrate can be located within the range of the orthogonal projection of the second drain region of the second active region (which is also the third source region of the third active region) on the silicon substrate.

[0277] In an exemplary embodiment, the orthogonal projection of the 25th via V25 onto the silicon substrate may be located within the range of the orthogonal projection of the fifth connection electrode 45 onto the silicon substrate. The third insulating layer within the 25th via V25 is etched away, exposing the surface of the fifth connection electrode 45. The 25th via V25 is configured to allow the subsequently formed 14th connection electrode to be connected to the fifth connection electrode 45 through the via.

[0278] In an exemplary embodiment, the orthogonal projection of the 25th via V25 onto the silicon substrate may be located within the range of the orthogonal projection of the first sub-segment 45-1 of the fifth connecting electrode 45 onto the silicon substrate.

[0279] In an exemplary embodiment, the orthogonal projection of the 26th via V26 onto the silicon substrate may be within the range of the orthogonal projection of the 6th connection electrode 46 onto the silicon substrate. The third insulating layer within the 26th via V26 is etched away, exposing the surface of the 6th connection electrode 46. The 26th via V26 is configured to allow the subsequently formed third scan signal line to be connected to the 6th connection electrode 46 through the via.

[0280] In an exemplary embodiment, the plurality of vias on the third insulating layer may further include a twenty-seventh via V27 and a twenty-eighth via V28.

[0281] In an exemplary embodiment, the orthogonal projection of the 27th via V27 onto the silicon substrate may be within the range of the orthogonal projection of the third sub-electrode 47-3 of the seventh connecting electrode 47 onto the silicon substrate. The third insulating layer within the 27th via V27 is etched away, exposing the surface of the seventh connecting electrode 47. The 27th via V27 is configured to allow the subsequently formed 12th connecting electrode to be connected to the seventh connecting electrode 47 through the via.

[0282] In an exemplary embodiment, the twenty-seventh via V27 can serve as a first power supply via. Multiple twenty-seventh vias V27 can be used to reduce contact resistance and improve connection reliability. For example, two twenty-seventh vias V27 can be located in the end region of the third sub-electrode 47-3 of the seventh connection electrode 47 near the end of the first scan signal line 31.

[0283] In an exemplary embodiment, the orthographic projection of the 28th via V28 onto the silicon substrate may be within the range of the orthographic projection of the 8th connection electrode 48 onto the silicon substrate. The third insulating layer within the 28th via V28 is etched away, exposing the surface of the 8th connection electrode 48. The 28th via V28 is configured to allow a subsequently formed second power connection line to be connected to the 8th connection electrode 48 through the via.

[0284] In an exemplary embodiment, the 28th via V28 can serve as a second power supply via. Multiple 28th vias V28 can be used to reduce contact resistance and improve connection reliability. For example, two 28th vias V28 can be located in the end region of the eighth connection electrode 48 near the second power supply line 82.

[0285] In an exemplary embodiment, the orthographic projection of the 29th via V29 onto the silicon substrate may be within the range of the orthographic projection of the 9th connection electrode 49 onto the silicon substrate. The third insulating layer within the 29th via V29 is etched away, exposing the surface of the 9th connection electrode 49. The 29th via V29 is configured to allow the subsequently formed 15th connection electrode 55 to be connected to the 9th connection electrode 49 through the via.

[0286] In an exemplary embodiment, there can be multiple vias from the 21st via V21 to the 29th via V29 to reduce contact resistance and improve connection reliability.

[0287] (7) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: depositing a second conductive film on a silicon substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process, and forming a second conductive layer pattern on a third insulating layer, as shown in Figures 13 and 14, where Figure 14 is a schematic diagram of the second conductive layer in Figure 13. In an exemplary embodiment, the second conductive layer may be referred to as a second metal (Metal2) layer.

[0288] In an exemplary embodiment, the second conductive layer pattern in each sub-pixel of the display substrate may include at least: an eleventh connecting electrode 51, a twelfth connecting electrode 52, a thirteenth connecting electrode 53, a fourteenth connecting electrode 54, a fifteenth connecting electrode 55, a first power connection line 91, a second power connection line 92, a third scan signal line 33, and a third electrode plate 130.

[0289] In an exemplary embodiment, the third electrode plate 130 can be rectangular in shape, and the corners of the rectangle can be chamfered or grooved. It can be disposed between the first scan signal line 31 and the second power line 82. The third electrode plate 130 can be connected to the third connecting electrode 43 through the twenty-third via V23.

[0290] In an exemplary embodiment, since the third electrode plate 130 is connected to the third connecting electrode 43 through the twenty-third via V23, and the third connecting electrode 43 is connected to the first drain region and the first electrode plate 110 through the via respectively, forming the first node N1 of the pixel driving circuit, the third electrode plate 130 has the potential of the first node N1.

[0291] In an exemplary embodiment, the orthographic projection of the third electrode 130 onto the silicon substrate at least partially overlaps with the orthographic projection of the second electrode 120 onto the silicon substrate, and the third electrode 130 can serve as the second intermediate electrode of the first capacitor. Since the second electrode 120 has the potential of the second node N2 and the third electrode 130 has the potential of the first node N1, the second electrode 120 and the third electrode 130 constitute the second sub-capacitor of the first capacitor.

[0292] In an exemplary embodiment, a third electrode plate connecting block 130-1 may be provided on the third electrode plate 130. The third electrode plate connecting block 130-1 may be block-shaped (such as rectangular), and may be provided on the side of the third electrode plate 130 near the first gate electrode 21 and connected to the third electrode plate 130. The third electrode plate connecting block 130-1 is connected to the third connecting electrode 43 through the twenty-third via V23.

[0293] In an exemplary embodiment, in at least one sub-pixel, the third electrode plate 130 and the third electrode plate connecting block 130-1 can be an integral structure that is interconnected.

[0294] In an exemplary embodiment, the orthographic projection of the third electrode plate 130 on the silicon substrate at least partially overlaps with the orthographic projection of the second sub-electrode 47-2 of the seventh connecting electrode on the silicon substrate, while the orthographic projection of the third electrode plate 130 on the silicon substrate does not overlap with the orthographic projection of the first sub-electrode 47-1 of the seventh connecting electrode on the silicon substrate.

[0295] In an exemplary embodiment, the orthographic projection of the third electrode connecting block 130-1 onto the silicon substrate lies within the range of the first region A formed by the orthographic projection of the seventh connecting electrode onto the silicon substrate.

[0296] In an exemplary embodiment, at least one of the twenty-third vias V23 has its orthogonal projection onto the silicon substrate located within the range of the first region A formed by the orthogonal projection of the seventh connecting electrode onto the silicon substrate.

[0297] In an exemplary embodiment, the edge of the orthographic projection of the second electrode 120 on the silicon substrate near the first sub-electrode 47-1 is closer to the first sub-electrode 47-1 than the edge of the orthographic projection of the third electrode 130 on the silicon substrate near the first sub-electrode 47-1. A third overhang width LK3 exists between the edge of the orthographic projection of the second electrode 120 on the silicon substrate near the first sub-electrode 47-1 and the edge of the orthographic projection of the third electrode 130 on the silicon substrate near the first sub-electrode 47-1. The edge of the first sub-electrode 47-1 of the adjacent sub-pixel is closer to the edge of the first sub-electrode 47-1 of the adjacent sub-pixel than the edge of the third electrode 130 on the silicon substrate. The edge of the second electrode 120 on the silicon substrate near the first sub-electrode 47-1 has a fourth over-width LK4 between the edge of the second electrode 120 on the silicon substrate near the first sub-electrode 47-1 and the edge of the third electrode 130 on the silicon substrate near the first sub-electrode 47-1. The third over-width LK3 is smaller than the fourth over-width LK4.

[0298] In an exemplary embodiment, the edge of the orthographic projection of the second electrode 120 on the silicon substrate near the first sub-electrode 47-1 is closer to the first sub-electrode 47-1 than the edge of the orthographic projection of the third electrode 130 on the silicon substrate near the first sub-electrode 47-1. There is a third over-width LK3 between the edge of the orthographic projection of the second electrode 120 on the silicon substrate near the first sub-electrode 47-1 and the edge of the orthographic projection of the third electrode 130 on the silicon substrate near the first sub-electrode 47-1. The edge of the orthographic projection of the second electrode 120 on the silicon substrate near the second power line 82 is closer to the second power line 82 than the edge of the orthographic projection of the third electrode 130 on the silicon substrate near the second power line 82. There is a fifth over-width LK5 between the edge of the orthographic projection of the second electrode 120 on the silicon substrate near the second power line 82 and the edge of the orthographic projection of the third electrode 130 on the silicon substrate near the second power line 82. The fifth over-width LK5 is greater than the third over-width LK3, and the third over-width LK3 is less than the fifth over-width LK5.

[0299] In an exemplary embodiment, the third scan signal line 33 can be a straight line extending along the first direction X, and can be located on the side of the third electrode plate 130 away from the first scan signal line 31. A third connecting block 33-1 can be provided on the third scan signal line 33. The third connecting block 33-1 can be disposed in each sub-pixel. The first end of the third connecting block 33-1 is connected to the third scan signal line 33, and the second end of the third connecting block 33-1 extends towards the second electrode plate 120 and is connected to the sixth connecting electrode 46 through the twenty-sixth via V26. Since the sixth connecting electrode 46 is connected to the fourth gate connecting block 24-1 through the via, and the fourth gate connecting block 24-1 is connected to the fourth gate electrode 24, the third scan signal line 33 is connected to the gate electrode of the fourth transistor T4 in each sub-pixel, and the third scan signal line 33 can control the conduction or disconnection of the fourth transistor T4.

[0300] In an exemplary embodiment, in the second direction Y, the third scan signal line 33 is disposed between the fourth active regions 14 of adjacent pixel rows. The third scan signal line 33 is disposed on both sides of the second power line 82, and the second power line 82 separates the two third scan signal lines 33. The orthographic projection of the third scan signal line 33 on the silicon substrate at least partially overlaps with the orthographic projection of the fourth active region 14 on the silicon substrate.

[0301] In an exemplary embodiment, the eleventh connection electrode 51 may be block-shaped (e.g., rectangular) and may be disposed between two first scan signal lines 31 of adjacent pixel rows. The eleventh connection electrode 51 may be connected to the first connection electrode 41 through the twenty-first via V21 and may be configured to be connected to the subsequently formed data signal lines.

[0302] In an exemplary embodiment, in at least one sub-pixel, the orthographic projection of the eleventh connecting electrode 51 on the silicon substrate at least partially overlaps with the orthographic projection of the first center line O1 on the silicon substrate, and adjacent sub-pixels in a pixel column can share the same eleventh connecting electrode 51.

[0303] In an exemplary embodiment, the twelfth connecting electrode 52 may be a straight line or a broken line extending along the second direction Y, and may be disposed between two third electrode plates 130 of adjacent pixel rows. The twelfth connecting electrode 52 may be connected to the second connecting electrode 42 through the twelfth via V22, and the twelfth connecting electrode 52 may be configured to be connected to the subsequently formed twentieth connecting electrode.

[0304] In an exemplary embodiment, a twelfth connecting electrode block 52-1 may be provided on the twelfth connecting electrode 52. The twelfth connecting electrode block 52-1 may be block-shaped (e.g., rectangular), and may be located on the side of the twelfth connecting electrode 52 away from the eleventh connecting electrode 51, and connected to the twelfth connecting electrode 52. The twelfth connecting electrode block 52-1 is connected to the second connecting electrode 42 through the twelfth through-hole V22.

[0305] In an exemplary embodiment, in at least one sub-pixel, the orthographic projection of the twelfth connecting electrode block 52-1 on the silicon substrate at least partially overlaps with the orthographic projection of the first center line O1 on the silicon substrate, and adjacent sub-pixels in a pixel column can share the same twelfth connecting electrode 52. In the embodiments of this disclosure, by setting adjacent sub-pixels to share the same twelfth connecting electrode 52, the layout space of the twelfth connecting electrode 52 can be effectively reduced, the occupied area of ​​the pixel driving circuit can be reduced, which is beneficial to achieving high resolution.

[0306] In an exemplary embodiment, the thirteenth connecting electrode 53 may be a strip shape extending along the second direction Y. The thirteenth connecting electrode 53 may be connected to the fourth connecting electrode 44 through the twenty-fourth through-hole V24. The thirteenth connecting electrode 53 may be configured to be connected to the subsequently formed fourth electrode plate.

[0307] In an exemplary embodiment, the orthographic projection of the thirteenth connection electrode 53 on the silicon substrate is located on the side of the orthographic projection of the second electrode plate 120 on the silicon substrate that is away from the second power line 82.

[0308] In an exemplary embodiment, the fourteenth connecting electrode 54 may be a strip shape extending along the first direction X. The fourteenth connecting electrode 54 may be connected to the fifth connecting electrode 45 through the twenty-fifth through-hole V25. The fourteenth connecting electrode 54 may be configured to be connected to the subsequently formed twenty-third connecting electrode.

[0309] In an exemplary embodiment, the fifteenth connecting electrode 55 may be a strip shape extending along the second direction Y. The fifteenth connecting electrode 55 may be connected to the ninth connecting electrode 49 through the twenty-ninth via V29. The fifteenth connecting electrode 55 may be configured to be connected to the subsequently formed twenty-second connecting electrode.

[0310] In an exemplary embodiment, the sixteenth connecting electrode 56 can be a straight line whose main body extends along the second direction Y. In the first direction X, the sixteenth connecting electrode 56 can be disposed between two third electrodes 130 of adjacent pixel columns. In the second direction Y, the sixteenth connecting electrode 56 can be disposed on the side of the third scan signal line 33 near the third electrode 130. The orthographic projection of the sixteenth connecting electrode 56 on the silicon substrate at least partially overlaps with the orthographic projection of the eighth connecting electrode 48 on the silicon substrate. The sixteenth connecting electrode 56 can be connected to the eighth connecting electrode 48 through the twenty-eighth via V28.

[0311] In an exemplary embodiment, the two sixteenth connection electrodes 56 of adjacent pixel rows can be an integral structure connected to each other and located between the two third scan signal lines 33 of adjacent pixel rows. The second power connection line 92 is not continuously arranged in the second direction Y and is spaced apart by the third scan signal line 33.

[0312] In an exemplary embodiment, the sixteenth connecting electrode 56 can serve as a second power supply connection.

[0313] In an exemplary embodiment, the shape of the first power connection line 91 can be a straight line with the main body extending along the first direction X, and it can be disposed on the side of the third electrode plate 130 near the third scan signal line 33.

[0314] In an exemplary embodiment, the orthographic projection of the first power connection line 91 on the silicon substrate at least partially overlaps with the orthographic projection of the fifth connection electrode 45 on the silicon substrate, and the orthographic projection of the third segment 45-3 of the fifth connection electrode 45 on the silicon substrate may be located within the range of the orthographic projection of the first power connection line 91 on the silicon substrate.

[0315] In an exemplary embodiment, the orthographic projection of the first power connection line 91 onto the silicon substrate overlaps with the orthographic projection of the fifth connection electrode 45 onto the silicon substrate. The first power connection line 91, having a constant potential, can effectively shield the scanning signal from affecting critical nodes of the pixel driving circuit.

[0316] In an exemplary embodiment, the eighth connecting electrode 48 located in the first conductive layer and the sixteenth connecting electrode 56 located in the second conductive layer can form a second power connection line 92. Since the sixteenth connecting electrode 56 is connected to the eighth connecting electrode 48 through a via, and the eighth connecting electrode 48 is connected to the second power line 82, the interconnection between the second power line 82 extending along the first direction X and the second power connection line 92 (the eighth connecting electrode 48 and the sixteenth connecting electrode 56) extending along the second direction Y is realized, forming a mesh-like interconnected structure for transmitting the second power signal on the display substrate. This not only effectively reduces the resistance of the second power line and the voltage drop of the second power signal, but also effectively improves the uniformity of the second power signal in the display substrate, effectively improving display uniformity, and enhancing display quality.

[0317] In an exemplary embodiment, the end of the second power connection line 92 near the third scan signal line 33 is connected to the first power connection line 91, thereby realizing the interconnection between the first power connection line 91 extending along the first direction X and the second power connection line 92 extending along the second direction Y. A second layer mesh interconnection structure for transmitting the second power signal is formed on the display substrate, which can further reduce the resistance of the second power line, further reduce the voltage drop of the second power signal, further improve the uniformity of the first power signal in the display substrate, further improve the display uniformity, and further improve the display quality and display performance.

[0318] In the embodiments of this disclosure, by placing the second power line 82 and the eighth connecting electrode 48 in the first conductive layer and the sixteenth connecting electrode 56 in the second conductive layer, the eighth connecting electrode 48 and the sixteenth connecting electrode 56 form the second power connection line 92. The two conductive layers realize a mesh-like interconnection structure for transmitting the second power signal. Furthermore, the second power connection line 92 is a double-layer structure, which can further reduce the resistance of the second power line and reduce the voltage drop of the second power signal.

[0319] In an exemplary embodiment, in at least one sub-pixel, the first power connection line 91 and the second power connection line 92 can be an integral structure that is interconnected.

[0320] In an exemplary embodiment, the two first power connection lines 91 and the multiple second power connection lines 92 of adjacent pixel rows can be an integral structure that is interconnected.

[0321] In an exemplary embodiment, two second power connection lines 92 in two adjacent pixel rows are separated by third scan signal lines 33 in the two pixel rows.

[0322] In an exemplary embodiment, the orthographic projection of the second power connection line 92 on the silicon substrate at least partially overlaps with the orthographic projection of the second center line O2 on the silicon substrate, that is, the second power connection line 92 is substantially located at the center of the adjacent pixel column, which can effectively increase the width of the second power connection line 92 and reduce the resistance of the mesh interconnection structure for transmitting the second power signal.

[0323] In an exemplary embodiment, the second conductive layer pattern of adjacent pixel rows can be mirror-symmetrical with respect to the first center line O1. For example, the eleventh to sixteenth connecting electrodes 51 to 56, the first power connection line 91, the second power connection line 92, the third scan signal line 33, and the third electrode plate 130 in the (M-1)th pixel row and the Mth pixel row can be mirror-symmetrical with respect to the first center line O1. Similarly, the eleventh to sixteenth connecting electrodes 51 to 56, the first power connection line 91, the second power connection line 92, the third scan signal line 33, and the third electrode plate 130 in the Mth pixel row and the M+1th pixel row can be mirror-symmetrical with respect to the first center line O1. Furthermore, the eleventh to sixteenth connecting electrodes 56, the first power connection line 91, the second power connection line 92, the third scan signal line 33, and the third electrode plate 130 in the M+1th pixel row and the M+2th pixel row can be mirror-symmetrical with respect to the first center line O1.

[0324] In an exemplary embodiment, the fourteenth connecting electrode 54, the sixteenth connecting electrode 56, the first power connection line 91, the second power connection line 92, and the third scan signal line 33 of adjacent pixel columns can be mirror-symmetrical with respect to the second center line O2. For example, the fourteenth connecting electrode 54, the sixteenth connecting electrode 56, the first power connection line 91, the second power connection line 92, and the third scan signal line 33 in the (N+1)th and (N+2)th pixel columns can be mirror-symmetrical with respect to the second center line O2. Similarly, the fourteenth connecting electrode 54, the sixteenth connecting electrode 56, the first power connection line 91, the second power connection line 92, and the third scan signal line 33 in the (N+2)th and (N+3)th pixel columns can be mirror-symmetrical with respect to the second center line O2. Furthermore, the fourteenth connecting electrode 54, the sixteenth connecting electrode 56, the first power connection line 91, the second power connection line 92, and the third scan signal line 33 in the (N+3)th and (N+4)th pixel columns can be mirror-symmetrical with respect to the second center line O2.

[0325] In an exemplary embodiment, the positions and shapes of the eleventh connecting electrode 51, the twelfth connecting electrode 52, the thirteenth connecting electrode 53, the fifteenth connecting electrode 55, and the third electrode plate 130 of adjacent pixel columns can be substantially the same.

[0326] (8) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming a fourth insulating layer pattern may include: depositing a fourth insulating film on a silicon substrate on which the aforementioned pattern is formed, and patterning the fourth insulating film by a patterning process to form a fourth insulating layer covering the pattern of the second conductive layer. The fourth insulating layer is provided with a plurality of vias, as shown in FIG15. FIG15 is a schematic diagram of the second conductive layer, the fourth insulating layer and the subsequently formed third conductive layer.

[0327] In an exemplary embodiment, the plurality of vias in each sub-pixel of the display substrate may include: a 31st via V31, a 32nd via V32, a 33rd via V33, a 34th via V34, a 35th via V35, and a 36th via V36.

[0328] In an exemplary embodiment, the orthographic projection of the 31st via V31 onto the silicon substrate may be within the range of the orthographic projection of the 11th connection electrode 51 onto the silicon substrate. The fourth insulating layer within the 31st via V31 is etched away, exposing the surface of the 11th connection electrode 51. The 31st via V31 is configured to allow subsequently formed data signal lines to be connected to the 11th connection electrode 51 through the via.

[0329] In an exemplary embodiment, the orthographic projection of the thirty-first via V31 on the silicon substrate at least partially overlaps with the orthographic projection of the first centerline O1 on the silicon substrate.

[0330] In an exemplary embodiment, the orthogonal projection of the 32nd via V32 onto the silicon substrate may be within the range of the orthogonal projection of the 12th connecting electrode block 52-1 onto the silicon substrate. The fourth insulating layer within the 32nd via V32 is etched away, exposing the surface of the 12th connecting electrode 52. The 32nd via V32 is configured to allow the subsequently formed 22nd connecting electrode to be connected to the 12th connecting electrode 52 through the via.

[0331] In an exemplary embodiment, the orthographic projection of the 32nd via V32 onto the silicon substrate at least partially overlaps with the orthographic projection of the first centerline O1 onto the silicon substrate.

[0332] In an exemplary embodiment, in at least one pixel row, a plurality of thirty-first vias V31 and a plurality of thirty-second vias V32 may be located on the same straight line extending along the first direction X.

[0333] In an exemplary embodiment, the orthogonal projection of the 33rd via V33 onto the silicon substrate is within the range of the orthogonal projection of the third electrode plate 130 onto the silicon substrate. The fourth insulating layer within the 33rd via V33 is etched away, exposing the surface of the third electrode plate 130. The 33rd via V33 is configured to allow the subsequently formed 24th connection electrode to be connected to the third electrode plate 130 through the via.

[0334] In an exemplary embodiment, in the first direction X, the orthographic projection of the 33rd via V33 onto the silicon substrate is located at the midpoint of the orthographic projection of the third electrode 130 onto the silicon substrate. "Midpoint" means that the distance between the orthographic projection of the 33rd via V33 and the two sides of the orthographic projection of the third electrode 130 onto the silicon substrate is substantially equal, allowing for values ​​within the range of process and measurement errors. In the second direction Y, the orthographic projection of the 33rd via V33 onto the silicon substrate is located at one end of the orthographic projection range of the third electrode 130 onto the silicon substrate, closer to the 12th connecting electrode 52. In an exemplary embodiment, the orthographic projection of the 34th via V34 onto the silicon substrate is located within the range of the orthographic projection of the 14th connecting electrode 54 onto the silicon substrate. The fourth insulating layer within the 34th via V34 is etched away, exposing the surface of the 14th connecting electrode 54. The 34th via V34 is configured to allow the subsequently formed 23rd connecting electrode to connect to the 14th connecting electrode 54 through this via.

[0335] In an exemplary embodiment, the orthographic projection of the 35th via V35 onto the silicon substrate is within the range of the orthographic projection of the 15th connection electrode 55 onto the silicon substrate. The fourth insulating layer within the 35th via V35 is etched away, exposing the surface of the 15th connection electrode 55. The 35th via V35 is configured to allow the subsequently formed 22nd connection electrode to be connected to the 15th connection electrode 55 through the via.

[0336] In an exemplary embodiment, the orthographic projection of the thirty-sixth via V36 onto the silicon substrate is within the range of the orthographic projection of the thirteenth connecting electrode 53 onto the silicon substrate. The fourth insulating layer within the thirty-sixth via V36 is etched away, exposing the surface of the thirteenth connecting electrode 53. The thirty-sixth via V36 is configured to allow the subsequently formed fourth electrode plate 140 to be connected to the thirteenth connecting electrode 53 through the via.

[0337] In an exemplary embodiment, there can be multiple vias from the thirty-first via V31 to the thirty-sixth via V36 to reduce contact resistance and improve connection reliability.

[0338] (9) Forming a third conductive layer pattern. In an exemplary embodiment, forming a third conductive layer pattern may include: depositing a third conductive film on a silicon substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process, and forming a third conductive layer pattern on a fourth insulating layer, as shown in Figures 15 and 16, where Figure 16 is a schematic diagram of the third conductive layer in Figure 15. In an exemplary embodiment, the third conductive layer may be referred to as a third metal (Metal3) layer.

[0339] In an exemplary embodiment, the third conductive layer pattern in each sub-pixel of the display substrate may include at least: a twenty-first connecting electrode 61, a twenty-second connecting electrode 62, a twenty-third connecting electrode 63, a twenty-fourth connecting electrode 64, a data signal line 83, and a fourth electrode plate 140.

[0340] In an exemplary embodiment, the fourth electrode plate 140 can be rectangular in shape, with chamfered or grooved corners. It can be positioned between the first scan signal line 31 and the second power line 82. The fourth electrode plate 140 can be connected to the thirteenth connecting electrode 53 through the thirty-sixth via V36.

[0341] Since the fourth electrode plate 140 can be connected to the thirteenth connecting electrode 53 through the thirty-sixth via V36, and the thirteenth connecting electrode 53 can be connected to the fourth connecting electrode 44 through the via, and since the fourth connecting electrode 44 is connected to the second drain region and the third source region through the via, forming the second node N2 of the pixel driving circuit, the fourth electrode plate 140 has the potential of the second node N2.

[0342] In an exemplary embodiment, the orthographic projection of the fourth electrode 140 onto the silicon substrate at least partially overlaps with the orthographic projection of the third electrode 130 onto the silicon substrate, and the fourth electrode 140 can serve as the third intermediate electrode of the first capacitor. Since the third electrode 130 has the potential of the first node N1 and the fourth electrode 140 has the potential of the second node N2, the third electrode 130 and the fourth electrode 140 together form the third sub-capacitor of the first capacitor.

[0343] In an exemplary embodiment, the fourth electrode plate 140 may be configured as an inverted "U" or "U" shape along the second direction Y. The orthogonal projection of the area surrounded or partially surrounded by the fourth electrode plate 140 on the silicon substrate forms a second region C. The second region C overlaps with the orthogonal projection of the third electrode plate on the silicon substrate. The orthogonal projection of the thirty-third via V33 on the silicon substrate is within the range of the second region C.

[0344] In an exemplary embodiment, the third sub-electrode 47-3 of the seventh connecting electrode is projected onto the silicon substrate within the second region C. In embodiments of this disclosure, by providing a U-shaped or U-shaped fourth electrode plate 140, a region surrounded or partially surrounded by the fourth electrode plate 140 can be formed, realizing the connection between the third electrode plate 130 and the fifth electrode plate 150. This also helps to increase the area of ​​the fourth electrode plate 140, increase the capacitance value of the first capacitor, and improve pixel driving capability.

[0345] In an exemplary embodiment, the data signal line 83 can be a straight line or a broken line extending along the second direction Y, and can be disposed on the side of the fourth electrode plate 140 opposite to the first direction X. A data connection block 83-1 can be disposed on the data signal line 83. The data connection block 83-1 can be a strip extending along the first direction X. The first end of the data connection block 83-1 is connected to the side of the data signal line 83 near the fourth electrode plate 140. The second end of the data connection block 83-1 extends along the first direction X and is connected to the eleventh connection electrode 51 through the thirty-first via V31. Since the eleventh connection electrode 51 is connected to the first connection electrode 41 through the via, and the first connection electrode 41 is connected to the first source region through the via, the data signal line 83 writes the data signal to the first electrode of the first transistor T1.

[0346] In an exemplary embodiment, the orthographic projection of the data connection block 83-1 on the silicon substrate at least partially overlaps with the orthographic projection of the first center line O1 on the silicon substrate. Adjacent sub-pixels in a pixel column can share the same data connection block 83-1, which effectively reduces the number of connection electrodes, reduces the area occupied by the pixel driving circuit, and is beneficial to achieving high resolution.

[0347] In an exemplary embodiment, in at least one pixel column, the data signal line 83 and the data connection block 83-1 can be an integral structure that is interconnected.

[0348] In an exemplary embodiment, since adjacent sub-pixels in a pixel column share the first source region, the first connection electrode 41, the eleventh connection electrode 51, and the data connection block 83-1, the first transistor T1 of adjacent sub-pixels in a pixel column is written with the same data signal.

[0349] In an exemplary embodiment, the orthographic projection of the data signal line 83 on the silicon substrate at least partially overlaps with the orthographic projection of the second power connection line 92 on the silicon substrate. The second power connection line 92, which has a constant potential, can shield the impact of the voltage jumps in the data signal line 83 on critical nodes of the pixel driving circuit.

[0350] In an exemplary embodiment, the twenty-first connecting electrode 61 may be block-shaped (e.g., rectangular) and may be disposed between two first scan signal lines 31 of adjacent pixel rows. The twenty-first connecting electrode 61 may be connected to the twelfth connecting electrode 52 through the thirty-second via V32. The twenty-first connecting electrode 61 is configured to be connected to the subsequently formed thirty-first connecting electrode.

[0351] In an exemplary embodiment, in at least one sub-pixel, the orthographic projection of the 21st connecting electrode 61 on the silicon substrate at least partially overlaps with the orthographic projection of the first center line O1 on the silicon substrate, and adjacent sub-pixels in a pixel column can share the same 21st connecting electrode 61.

[0352] In an exemplary embodiment, the shape of the second twelfth connecting electrode 62 can be "L" shaped, and it can be disposed on the side of the fourth electrode plate 140 away from the second power line 82. The second twelfth connecting electrode 62 is connected to the fifteenth connecting electrode 55 through the thirty-fifth via V35. The second twelfth connecting electrode 62 is configured to be connected to the second scan signal line formed subsequently.

[0353] In an exemplary embodiment, the "L"-shaped second twelfth connecting electrode 62 includes a block shape (such as a rectangle) extending along a first direction X and a block shape (such as a rectangle) extending along a second direction Y. The block shape (such as a rectangle) extending along the second direction Y in the "L"-shaped second twelfth connecting electrode 62 is connected to the fifteenth connecting electrode 55 through a thirty-fifth via V35. The block shape (such as a rectangle) extending along the first direction X in the "L"-shaped second twelfth connecting electrode 62 is configured to connect with a subsequently formed second scan signal line.

[0354] In an exemplary embodiment, the shape of the twenty-third connecting electrode 63 can be a strip shape extending along the first direction X. The orthographic projection of the twenty-third connecting electrode 63 on the silicon substrate can be disposed between the orthographic projection of the fourth electrode plate 140 on the silicon substrate and the orthographic projection of the third scan signal line 33 on the silicon substrate. The twenty-third connecting electrode 63 can be connected to the fourteenth connecting electrode 54 through the thirty-fourth via V34. The twenty-third connecting electrode 63 is configured to be connected to the subsequently formed thirty-third connecting electrode.

[0355] In an exemplary embodiment, the shape of the 24th connecting electrode 64 can be a strip shape extending along the second direction Y, and it can be disposed in the semi-enclosed area formed by the fourth electrode plate 140. The orthographic projection of the 24th connecting electrode 64 on the silicon substrate at least partially overlaps with the orthographic projection of the third electrode plate 130 on the silicon substrate.

[0356] In an exemplary embodiment, the 24th connecting electrode 64 can be connected to the third electrode plate 130 through the 33rd through-hole V33, and the 24th connecting electrode 64 is configured to be connected to the subsequently formed fifth electrode plate.

[0357] In an exemplary embodiment, the orthographic projection of the twenty-fourth connecting electrode 64 onto the silicon substrate lies within the range of the second region C formed by the orthographic projection of the "U"-shaped fourth electrode plate 140 onto the silicon substrate.

[0358] In an exemplary embodiment, the orthographic projection of the thirty-third via V33 onto the silicon substrate is located within the range of the second region C, and the orthographic projection of the forty-first via V41 onto the silicon substrate is located within the range of the second region C.

[0359] In an exemplary embodiment, the third conductive layer pattern of adjacent pixel rows can be mirror-symmetrical with respect to the first center line O1. For example, the twenty-first to twenty-fourth connecting electrodes 61 to 64, data signal lines 83, and fourth electrode plates 140 in the (M-1)th and Mth pixel rows can be mirror-symmetrical with respect to the first center line O1. Similarly, the twenty-first to twenty-fourth connecting electrodes 64, data signal lines 83, and fourth electrode plates 140 in the Mth and M+1th pixel rows can be mirror-symmetrical with respect to the first center line O1. Furthermore, the twenty-first to twenty-fourth connecting electrodes 64, data signal lines 83, and fourth electrode plates 140 in the M+1th and M+2th pixel rows can be mirror-symmetrical with respect to the first center line O1.

[0360] In an exemplary embodiment, the twenty-third connecting electrode 63 and the twenty-fourth connecting electrode 64 of adjacent pixel columns can be mirror-symmetrical with respect to the second center line O2. For example, the twenty-third connecting electrode 63 and the twenty-fourth connecting electrode 64 in the (N+1)th pixel column and the (N+2)th pixel column can be mirror-symmetrical with respect to the second center line O2. Similarly, the twenty-third connecting electrode 63 and the twenty-fourth connecting electrode 64 in the (N+2)th pixel column and the (N+3)th pixel column can be mirror-symmetrical with respect to the second center line O2. Furthermore, the twenty-third connecting electrode 63 and the twenty-fourth connecting electrode 64 in the (N+3)th pixel column and the (N+4)th pixel column can be mirror-symmetrical with respect to the second center line O2.

[0361] In an exemplary embodiment, the positions and shapes of the 21st connecting electrode 61, the 22nd connecting electrode 62, the data signal line 83, and the fourth electrode plate 140 of adjacent pixel columns can be substantially the same.

[0362] (10) Forming a fifth insulating layer pattern. In an exemplary embodiment, forming a fifth insulating layer pattern may include: depositing a fifth insulating film on a silicon substrate on which the aforementioned pattern is formed, and patterning the fifth insulating film by a patterning process to form a fifth insulating layer covering the pattern of the third conductive layer. The fifth insulating layer is provided with a plurality of vias, as shown in FIG17. FIG15 is a schematic diagram of the third conductive layer, the fifth insulating layer and the subsequently formed fourth conductive layer.

[0363] In an exemplary embodiment, the plurality of vias in each sub-pixel of the display substrate may include: a forty-first via V41, a forty-second via V42, a forty-third via V43, a forty-fourth via V44, and a forty-fifth via V45.

[0364] In an exemplary embodiment, the orthographic projection of the forty-first via V41 onto the silicon substrate may be within the range of the orthographic projection of the twenty-fourth connecting electrode 64 onto the silicon substrate. The fifth insulating layer within the forty-first via V41 is etched away, exposing the surface of the twenty-fourth connecting electrode 64. The forty-first via V41 is configured to allow the subsequently formed fifth electrode plate to be connected to the twenty-fourth connecting electrode 64 through the via.

[0365] In an exemplary embodiment, the orthographic projection of the forty-second via V42 on the silicon substrate may be within the range of the orthographic projection on the substrate of the twenty-first connecting electrode 61. The fifth edge layer of the forty-second via V42 is etched away, exposing the surface of the twenty-first connecting electrode 61. The forty-second via V42 is configured to allow the subsequently formed thirty-first connecting electrode to be connected to the twenty-first connecting electrode 61 through the via.

[0366] In an exemplary embodiment, the orthographic projection of the forty-second via V42 on the silicon substrate at least partially overlaps with the orthographic projection of the first centerline O1 on the silicon substrate.

[0367] In an exemplary embodiment, the orthogonal projection of the forty-third via V43 onto the silicon substrate is within the range of the orthogonal projection of the twenty-third connecting electrode 63 onto the silicon substrate. The fifth insulating layer within the forty-third via V43 is etched away, exposing the surface of the twenty-third connecting electrode 63. The forty-third via V43 is configured to allow the subsequently formed thirty-third connecting electrode to be connected to the twenty-third connecting electrode 63 through the via.

[0368] In an exemplary embodiment, the orthographic projection of the forty-fourth via V44 on the silicon substrate is located at one end of the orthographic projection of the fourth electrode plate 140 on the silicon substrate, close to the end of the orthographic projection of the third scan line 33 on the silicon substrate. The fifth insulating layer within the forty-fourth via V44 is etched away, exposing the surface of the fourth electrode plate 140. The forty-fourth via V44 is configured to allow the subsequently formed thirty-second connection electrode to be connected to the fourth electrode plate 140 through the via.

[0369] In an exemplary embodiment, the orthogonal projection of the forty-fifth via V45 onto the silicon substrate is within the range of the orthogonal projection of the twenty-second connecting electrode 62 onto the silicon substrate. The fifth insulating layer within the forty-fifth via V45 is etched away, exposing the twenty-second connecting electrode 62. The forty-fifth via V45 is configured to allow a subsequently formed second scan signal line to be connected to the twenty-second connecting electrode 62 through the via.

[0370] In an exemplary embodiment, there can be multiple vias from the forty-first via V41 to the forty-fifth via V45 to reduce contact resistance and improve connection reliability.

[0371] (11) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming a fourth conductive layer pattern may include: depositing a fourth conductive thin film on a silicon substrate on which the aforementioned pattern is formed, patterning the fourth conductive thin film using a patterning process, and forming a fourth conductive layer pattern on a fifth insulating layer, as shown in Figures 17 and 18, where Figure 18 is a schematic diagram of the third conductive layer in Figure 17. In an exemplary embodiment, the fourth conductive layer may be referred to as a fourth metal layer (Metal4).

[0372] In an exemplary embodiment, the fourth conductive layer pattern in each sub-pixel of the display substrate may include at least: a second scan signal line 32, a thirty-first connecting electrode 71, a thirty-second connecting electrode 72, a thirty-third connecting electrode 73, a third power connection line 93, a fourth power connection line 94, and a fifth electrode plate 150.

[0373] In an exemplary embodiment, the fifth electrode plate 150 can be rectangular in shape, with chamfered or recessed corners. The orthographic projection of the fifth electrode plate 150 onto the silicon substrate can be positioned between the orthographic projection of the first scan signal line 31 onto the silicon substrate and the orthographic projection of the second power line 82 onto the silicon substrate. The fifth electrode plate 150 can be connected to the twenty-fourth connecting electrode 64 through the forty-first via V41. The twenty-fourth connecting electrode 64 can be connected to the third electrode plate 130 through the thirty-third via V33.

[0374] For example, the 33rd via V33 and the 41st via V41 are located on the same straight line extending in a direction perpendicular to the plane of the display substrate.

[0375] In an exemplary embodiment, since the fifth electrode plate 150 is connected to the twenty-fourth connecting electrode 64 through a via, the twenty-fourth connecting electrode 64 is connected to the third electrode plate 130 through a via, the third electrode plate 130 is connected to the third connecting electrode 43 through a via V23, and the third connecting electrode 43 is connected to the first drain region and the first electrode plate 110 through vias respectively, forming the first node N1 of the pixel driving circuit, the fifth electrode plate 150 has the potential of the first node N1.

[0376] In an exemplary embodiment, the orthographic projection of the fifth electrode 150 onto the silicon substrate at least partially overlaps with the orthographic projection of the fourth electrode 140 onto the silicon substrate, and the fifth electrode 150 can serve as the fourth intermediate electrode of the first capacitor. Since the fourth electrode 140 has the potential of the second node N2 and the fifth electrode 150 has the potential of the first node N1, the fourth electrode 140 and the fifth electrode 150 constitute the fourth sub-capacitor of the first capacitor.

[0377] In an exemplary embodiment, the orthogonal projection of the second electrode 120 onto the silicon substrate is within the orthogonal projection range of the fifth electrode 150 onto the silicon substrate.

[0378] In an exemplary embodiment, the second scan signal line 32 can be a straight line extending along the first direction X, and can be located on the side of the fifth electrode plate 150 away from the second power line 82. The first scan signal line 32 can be connected to the twenty-second connecting electrode 62 through the forty-fifth via V45. Since the twenty-second connecting electrode 62 is connected to the fifteenth connecting electrode 55 through a via, the fifteenth connecting electrode 55 is connected to the ninth connecting electrode 49 through a via, the ninth connecting electrode 49 is connected to the second gate connecting block 22-1 through a via, and the second gate connecting block 22-1 is connected to the second gate electrode 22, the second scan signal line 32 is connected to the gate electrode of the second transistor T2 in each sub-pixel, and the second scan signal line 32 can control the conduction or disconnection of the second transistor T2.

[0379] In an exemplary embodiment, since the second active regions 12 in adjacent pixel rows are interconnected integral structures, the orthographic projection of the second scan signal line 32 on the silicon substrate at least partially overlaps with the orthographic projection of the second active region 12 on the silicon substrate.

[0380] In an exemplary embodiment, increasing the wiring space allows the second scan signal line 32 to be configured as a straight line. Compared to a zigzag shape, a straight second scan signal line 32 can reduce its extension length and further reduce the signal line resistance.

[0381] In an exemplary embodiment, the third power connection line 93 may be a straight line with its main body extending along the first direction X, and may be located on the side of the fifth electrode plate 150 away from the second scan signal line 32.

[0382] In an exemplary embodiment, the orthographic projection of the third power connection line 93 on the silicon substrate at least partially overlaps with the orthographic projection of the first center line O1 on the silicon substrate.

[0383] In an exemplary embodiment, the fourth power connection line 94 can be a straight line extending along the second direction Y. In the first direction X, the fourth power connection line 94 can be disposed between two fifth plates 150 of adjacent pixel columns.

[0384] In an exemplary embodiment, the end of the fourth power connection line 94 away from the second scan signal line 32 is connected to the third power connection line 93, thereby realizing the interconnection between the third power connection line 93 extending along the first direction X and the fourth power connection line 94 extending along the second direction Y. A first layer mesh interconnection structure for transmitting the first power signal is formed on the display substrate, which can further reduce the resistance of the first power line, further reduce the voltage drop of the first power signal, further improve the uniformity of the first power signal in the display substrate, further improve the display uniformity, and further improve the display quality and display performance.

[0385] In an exemplary embodiment, the orthographic projection of the fourth power connection line 94 on the silicon substrate at least partially overlaps with the orthographic projection of the data signal line 83 on the silicon substrate. The fourth power connection line 94, having a constant potential, can shield the impact of voltage jumps in the data signal line 83 on critical nodes of the pixel driving circuit.

[0386] In an exemplary embodiment, in at least one sub-pixel, the third power connection line 93 and the fourth power connection line 94 can be an integral structure that is interconnected.

[0387] In an exemplary embodiment, the two third power connection lines 93 and the multiple fourth power connection lines 94 of adjacent pixel rows can be an integral structure that is interconnected.

[0388] In an exemplary embodiment, two fourth power connection lines 94 in two adjacent pixel rows are separated by second scan signal lines 32 in the two pixel rows.

[0389] In an exemplary embodiment, the shape of the 31st connecting electrode 71 can be block-shaped (such as rectangular), and it can be disposed between two second scan signal lines 32 of adjacent pixel rows. The 31st connecting electrode 71 can be connected to the 21st connecting electrode 61 through the 42nd via V42. The 31st connecting electrode 71 is configured to be connected to the subsequently formed first power line.

[0390] In an exemplary embodiment, in at least one sub-pixel, the orthographic projection of the 31st connecting electrode 71 on the silicon substrate at least partially overlaps with the orthographic projection of the first center line O1 on the silicon substrate, and adjacent sub-pixels in a pixel column can share the same 31st connecting electrode 71.

[0391] In an exemplary embodiment, the shape of the 32nd connecting electrode 72 can be a strip shape extending along the first direction X. In the second direction Y, the 32nd connecting electrode 72 can be disposed on the side of the fifth electrode plate 150 away from the second scan signal line 32. The 32nd connecting electrode 72 can be connected to the fourth electrode plate 140 through the 44th via V44. The 32nd connecting electrode 72 is configured to be connected to the subsequently formed sixth electrode plate 160.

[0392] In an exemplary embodiment, a third second connecting electrode connecting block may be provided on the third second connecting electrode 72. The shape of the third second connecting electrode connecting block may be block-shaped (such as rectangular), and it may be disposed at both ends of the third second connecting electrode 72 and connected to the third second connecting electrode 72. The combined shape of the two third second connecting electrode connecting blocks and the third second connecting electrode 72 may be "U" shaped.

[0393] In an exemplary embodiment, the shape of the thirty-third connecting electrode 73 can be a strip shape extending along the first direction X. In the second direction Y, the thirty-third connecting electrode 73 can be disposed on the side of the thirty-second connecting electrode 72 away from the fifth electrode plate 150. The thirty-third connecting electrode 73 can be connected to the twenty-third connecting electrode 63 through the forty-third through hole V43. The thirty-third connecting electrode 73 is configured to be connected to the subsequently formed thirty-fourth connecting electrode.

[0394] In an exemplary embodiment, the fourth conductive layer pattern of adjacent pixel rows can be mirror-symmetrical with respect to the first center line O1. For example, the second scan signal line 32, the thirty-first connecting electrode 71, the thirty-second connecting electrode 72, the thirty-third connecting electrode 73, the third power connection line 93, the fourth power connection line 94, and the fifth electrode plate 150 in the (M-1)th pixel row and the Mth pixel row can be mirror-symmetrical with respect to the first center line O1. Similarly, the second scan signal line 32, the thirty-first connecting electrode 71, the thirty-second connecting electrode 72, the thirty-third connecting electrode 73, the third power connection line 93, the fourth power connection line 94, and the fifth electrode plate 150 in the Mth pixel row and the M+1th pixel row can be mirror-symmetrical with respect to the first center line O1. Furthermore, the second scan signal line 32, the thirty-first connecting electrode 71, the thirty-second connecting electrode 72, the thirty-third connecting electrode 73, the third power connection line 93, the fourth power connection line 94, and the fifth electrode plate 150 in the M+1th pixel row and the M+2th pixel row can be mirror-symmetrical with respect to the first center line O1.

[0395] In an exemplary embodiment, the third power connection line 93 and the fourth power connection line 94 of adjacent pixel columns can be mirror-symmetrical with respect to the second center line O2. For example, the third power connection line 93 and the fourth power connection line 94 in the (N+1)th pixel column and the (N+2)th pixel column can be mirror-symmetrical with respect to the second center line O2. Similarly, the third power connection line 93 and the fourth power connection line 94 in the (N+2)th pixel column and the (N+3)th pixel column can be mirror-symmetrical with respect to the second center line O2. Furthermore, the twenty-third connecting electrode 63, the third scan signal line 33, the third power connection line 93, and the fourth power connection line 94 in the (N+3)th pixel column and the (N+4)th pixel column can be mirror-symmetrical with respect to the second center line O2.

[0396] In an exemplary embodiment, the positions and shapes of the second scan signal line 32, the thirty-first connecting electrode 71, the thirty-second connecting electrode 72, the thirty-third connecting electrode 73, and the fifth electrode plate 150 of adjacent pixel columns can be substantially the same.

[0397] (12) Forming a sixth insulating layer and a fifth conductive layer pattern. In an exemplary embodiment, forming the sixth insulating layer and the fifth conductive layer pattern may include: depositing a sixth insulating film and a fifth conductive film on a silicon substrate on which the aforementioned pattern is formed; patterning the sixth insulating film using a patterning process to form a sixth insulating layer covering the fourth conductive layer; and a fifth conductive layer pattern disposed on the sixth insulating layer, as shown in FIG19. FIG19 is a schematic diagram of the fourth conductive layer, the sixth insulating layer, the fifth conductive layer, and the subsequently formed seventh insulating layer and the sixth conductive layer. In an exemplary embodiment, the fifth conductive layer may be referred to as a metal-insulator-metal (MIM) layer.

[0398] In an exemplary embodiment, the fifth conductive layer pattern in each sub-pixel may include at least a sixth electrode 160.

[0399] In an exemplary embodiment, the sixth electrode plate 160 can be rectangular in shape, and the corners of the rectangle can be chamfered or grooved. The orthographic projection of the sixth electrode plate 160 on the silicon substrate can be positioned between the orthographic projection of the first scan signal line 31 on the silicon substrate and the orthographic projection of the second power line 82 on the silicon substrate. The orthographic projection of the sixth electrode plate 160 on the silicon substrate at least partially overlaps with the orthographic projection of the fifth electrode plate 150 on the silicon substrate. The sixth electrode plate 160 is configured as the upper electrode plate of the first capacitor, and the fifth electrode plate 150 and the sixth electrode plate 160 constitute the fifth sub-capacitor of the first capacitor.

[0400] In an exemplary embodiment, the fifth conductive layer pattern of adjacent pixel rows can be mirror-symmetrical with respect to the first center line O1. For example, the sixth electrode 160 in the Mth pixel row and the M+1th pixel row can be mirror-symmetrical with respect to the first center line O1.

[0401] In an exemplary embodiment, the positions and shapes of the sixth plates 160 of adjacent pixel columns can be substantially the same.

[0402] (13) Forming a seventh insulating layer pattern. In an exemplary embodiment, forming a seventh insulating layer pattern may include: depositing a seventh insulating film on a silicon substrate on which the aforementioned pattern is formed, and patterning the seventh insulating film by a patterning process to form a seventh insulating layer covering the fifth conductive layer pattern, wherein a plurality of vias are provided on the seventh insulating layer, as shown in FIG19.

[0403] In an exemplary embodiment, the plurality of vias in each sub-pixel of the display substrate may include: via 52, via 53, via 54, and via 55.

[0404] In an exemplary embodiment, the orthogonal projection of the 52nd via V52 on the silicon substrate may be within the range of the orthogonal projection on the substrate of the 31st connection electrode 71. The 7th and 6th insulating layers of the 52nd via V52 are etched away to expose the surface of the 31st connection electrode 71. The 52nd via V52 is configured to allow the subsequently formed 31st connection electrode to be connected to the first power line through the via.

[0405] In an exemplary embodiment, the orthographic projection of the 52nd via V52 on the silicon substrate at least partially overlaps with the orthographic projection of the first centerline O1 on the silicon substrate.

[0406] In an exemplary embodiment, the orthogonal projection of the 53rd via V53 onto the silicon substrate is within the range of the orthogonal projection of the 33rd connecting electrode 73 onto the silicon substrate. The 7th and 6th insulating layers within the 53rd via V53 are etched away, exposing the surface of the 33rd connecting electrode 73. The 53rd via V53 is configured to allow the subsequently formed 34th connecting electrode to be connected to the 33rd connecting electrode 73 through the via.

[0407] In an exemplary embodiment, the orthogonal projection of the 54th via V54 onto the silicon substrate is within the range of the orthogonal projection of the 32nd connecting electrode 72 onto the silicon substrate. The 7th and 6th insulating layers within the 54th via V54 are etched away, exposing the surface of the 32nd connecting electrode 72. The 54th via V54 is configured to allow the subsequently formed 7th electrode plate to be connected to the 32nd connecting electrode 72 through the via.

[0408] In an exemplary embodiment, there can be multiple vias from the 52nd via V52 to the 54th via V54 to reduce contact resistance and improve connection reliability.

[0409] In an exemplary embodiment, the orthogonal projection of the 55th via V55 onto the silicon substrate lies within the orthogonal projection of the 6th electrode 160 onto the silicon substrate. The 7th insulating layer within the 55th via V55 is etched away, exposing the surface of the 6th electrode 160. The 55th via V55 is configured to allow a subsequently formed 7th electrode to connect to the 6th electrode 160 through this via. In an exemplary embodiment, there can be multiple 55th vias V55 to reduce contact resistance and improve connection reliability. Multiple 55th vias V55 can be sequentially arranged along the second direction Y.

[0410] In an exemplary embodiment, the plurality of vias on the seventh insulating layer and the sixth insulating layer may further include a fifty-first via V51 and a fifty-sixth via V56.

[0411] In an exemplary embodiment, the orthographic projection of the 51st via V51 onto the silicon substrate is within the range of the orthographic projection of the fourth power connection line 94 onto the silicon substrate. The seventh and sixth insulating layers of the 51st via V51 are etched away, exposing the surface of the fourth power connection line 94. The 51st via V51 is configured to allow the subsequently formed sixth power connection line to be connected to the fourth power connection line 94 through the via.

[0412] In an exemplary embodiment, there can be multiple vias V51, which can be sequentially arranged along the second direction Y to reduce contact resistance and improve connection reliability.

[0413] In an exemplary embodiment, the orthographic projection of the 56th via V56 on the silicon substrate is within the range of the orthographic projection of the third power connection line 93 on the silicon substrate. The seventh and sixth insulating layers of the 56th via V56 are etched away to expose the surface of the third power connection line 93. The 56th via V56 is configured to allow the subsequently formed fifth power connection line to be connected to the third power connection line 93 through the via.

[0414] In an exemplary embodiment, there can be multiple vias V56, which can be sequentially arranged along the first direction X to reduce contact resistance and improve connection reliability.

[0415] (14) Forming a sixth conductive layer pattern. In an exemplary embodiment, forming a sixth conductive layer pattern may include: depositing a sixth conductive thin film on a silicon substrate on which the aforementioned pattern is formed, patterning the sixth conductive thin film using a patterning process, and forming a sixth conductive layer pattern on a seventh insulating layer, as shown in Figures 19 and 20, where Figure 20 is a schematic diagram of the sixth conductive layer in Figure 19. In an exemplary embodiment, the sixth conductive layer may be referred to as the fifth metal layer (Metal5).

[0416] In an exemplary embodiment, the sixth conductive layer pattern in each sub-pixel may include at least: a first power line 81, a fifth power connection line 95, a sixth power connection line 96, a thirty-fourth connection electrode 74, and a seventh electrode plate 170.

[0417] In an exemplary embodiment, the seventh electrode plate 170 can be rectangular in shape, and the corners of the rectangle can be chamfered or grooved. The orthographic projection of the seventh electrode plate 170 on the silicon substrate can be positioned between the orthographic projection of the first scan signal line 31 on the silicon substrate and the orthographic projection of the second power line 82 on the silicon substrate. The seventh electrode plate 170 can be connected to the sixth electrode plate 160 through the fifty-fifth via V55. The seventh electrode plate 170 is configured as the lower electrode plate of the second capacitor.

[0418] In an exemplary embodiment, a seventh electrode plate connecting block 170-1 may be provided on the seventh electrode plate 170. The seventh electrode plate connecting block 170-1 may be block-shaped (e.g., rectangular), and may be disposed on the side of the seventh electrode plate 170 near the second power line 82, and connected to the seventh electrode plate 170. The seventh electrode plate connecting block 170-1 is connected to the thirty-second connecting electrode 72 through the fifty-fourth via V54. In an exemplary embodiment, there may be two seventh electrode plate connecting blocks 170-1, located on the side of the seventh electrode plate 170 near the second power line 82 and near both ends of the sixth power connection line 96. The seventh electrode plate connecting blocks 170-1 are connected to the thirty-second connecting electrode 72 through the fifty-fourth via V54.

[0419] In an exemplary embodiment, in at least one sub-pixel, the seventh electrode plate 170 and the seventh electrode plate connecting block 170-1 can be an integral structure that is interconnected.

[0420] In an exemplary embodiment, since the 32nd connecting electrode 72 is connected to the fourth electrode plate 140 through a via, and the fourth electrode plate 140 has a potential of the second node N2, the sixth electrode plate 160 (the upper electrode plate of the first capacitor) and the seventh electrode plate 170 (the lower electrode plate of the second capacitor) have the same potential of the second node N2.

[0421] In an exemplary embodiment, since the fifth electrode 150 has the potential of the first node N1 and the sixth electrode 160 has the potential of the second node N2, the fifth electrode 150 and the sixth electrode 160 constitute the fifth sub-capacitor of the first capacitor.

[0422] In an exemplary embodiment, since the first electrode 110 has the potential of the first node N1, the second electrode 120 has the potential of the second node N2, the third electrode 130 has the potential of the first node N1, the fourth electrode 140 has the potential of the second node N2, the fifth electrode 150 has the potential of the first node N1, and the sixth electrode 160 has the potential of the second node N2, the first electrode 110 with the potential of the first node N1 and the second electrode 120 with the potential of the second node N2 form the first sub-capacitor of the first capacitor, and the second electrode 120 with the potential of the second node N2 and the sixth electrode 160 with the potential of the first node N1... The third plate 130 with the potential of the first capacitor forms the second sub-capacitor of the first capacitor. The third plate 130 with the potential of the first node N1 and the fourth plate 140 with the potential of the second node N2 form the third sub-capacitor of the first capacitor. The fourth plate 140 with the potential of the second node N2 and the fifth plate 150 with the potential of the first node N1 form the fourth sub-capacitor of the first capacitor. The fifth plate 150 with the potential of the first node N1 and the sixth plate 160 with the potential of the second node N2 form the fifth sub-capacitor of the first capacitor. The first sub-capacitor, the second sub-capacitor, the third sub-capacitor, the fourth sub-capacitor and the fifth sub-capacitor are connected in parallel.

[0423] In the embodiments of this disclosure, a first sub-capacitor, a second sub-capacitor, a fourth sub-capacitor, and a fifth sub-capacitor are formed using a gate conductive layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer, respectively. These first, second, fourth, and fifth sub-capacitors, connected in parallel, form the first capacitor of the MIM capacitor structure. This maximizes the capacitance value of the first capacitor, ensuring the stability of the output current of the pixel driving circuit and the stability of the OLED brightness. In the embodiments of this disclosure, the first capacitor has a simple structure and a reasonable layout. While ensuring the capacitance value, it can effectively reduce the area occupied by the capacitor plates, which is beneficial for improving resolution.

[0424] In an exemplary embodiment, the first power line 81 can be a straight line extending along the first direction X, and can be disposed between two first substrate electrodes 21 of adjacent pixel rows. The first power line 81 is connected to the thirty-first connecting electrode 71 through the fifty-second via V52. Since the thirty-first connecting electrode 71 is connected to the shared twenty-first connecting electrode 61 through a via, the twenty-first connecting electrode 61 is connected to the shared twelfth connecting electrode 52 through a via, the twelfth connecting electrode 52 is connected to the seventh connecting electrode 47 through a via, and the seventh connecting electrode 47 is connected to the first power region 15 through a via, the first power line 81 writes the first power signal into the P-type substrate region. This not only provides better current driving capability and response speed to meet the operation requirements of the output circuit, but also reduces voltage drop and power consumption in the output circuit, improving the overall efficiency of the output circuit.

[0425] In an exemplary embodiment, since the first power line 81 is connected to the thirty-first connecting electrode 71 through the fifty-second via V52, the thirty-first connecting electrode 71 is connected to the common twenty-first connecting electrode 61 through a via, the twenty-first connecting electrode 61 is connected to the common twelfth connecting electrode 52 through a via, the twelfth connecting electrode 52 is connected to the second connecting electrode 42 through a via, and the second connecting electrode 42 is connected to the common second source region through a via, the first power line 81 writes the first power signal into the first pole of the two second transistors T2 of the adjacent sub-pixels in the pixel column.

[0426] In an exemplary embodiment, the orthographic projection of the first power line 81 onto the silicon substrate at least partially overlaps with the orthographic projection of the first center line O1 onto the silicon substrate.

[0427] In an exemplary embodiment, a first power line 81 can be set for every two pixel rows, that is, two adjacent first power lines 81 in the second direction Y can be spaced two sub-pixels apart.

[0428] In an exemplary embodiment, the first power line 81 is disposed above the data connection block 83-1 in a direction perpendicular to the silicon substrate, which can shield the impact of the switching voltage in the data connection block 83-1 on the critical nodes of the pixel driving circuit.

[0429] In an exemplary embodiment, the fifth power connection line 95 may be a straight line extending along the first direction X, and may be disposed between two fourth gate electrodes 24 of adjacent pixel rows and connected to the first power line 81.

[0430] In an exemplary embodiment, the orthographic projection of the fifth power connection line 95 on the silicon substrate at least partially overlaps with the orthographic projection of the first center line O1 on the silicon substrate.

[0431] In an exemplary embodiment, a fifth power connection line 95 can be set for every two pixel rows, that is, two adjacent fifth power connection lines 95 in the second direction Y can be spaced two sub-pixels apart.

[0432] In an exemplary embodiment, in at least one pixel column, the first power line 81 and the fifth power connection line 95 may be alternately arranged along the second direction Y.

[0433] In an exemplary embodiment, the shape of the sixth power connection line 96 can be a straight line or a broken line extending along the second direction Y of the main body. It can be disposed between two seventh plates 170 of partially adjacent pixel columns and connected to the first power line 81. Thus, the interconnection between the first power line 81 extending along the first direction X, the fifth power connection line 95 extending along the first direction X, and the sixth power connection line 96 extending along the second direction Y is realized, forming a second layer mesh interconnection structure for transmitting the first power signal on the display substrate. This can not only effectively reduce the resistance of the first power line and reduce the voltage drop of the first power signal, but also effectively improve the uniformity of the first power signal in the display substrate, effectively improve display uniformity, and improve display quality.

[0434] In an exemplary embodiment, the orthographic projection of the sixth power connection line 96 on the silicon substrate at least partially overlaps with the orthographic projection of the second center line O2 on the silicon substrate, that is, the first power connection line 91 is substantially located at the center of the adjacent pixel column, which can effectively increase the width of the sixth power connection line 96 and reduce the resistance of the first layer mesh interconnection structure.

[0435] In an exemplary embodiment, the shape of the thirty-fourth connecting electrode 74 can be block-shaped (such as rectangular), and it can be disposed between the seventh electrode plate 170 and the second power line 82. The thirty-fourth connecting electrode 74 is connected to the thirty-third connecting electrode 73 through the fifty-third through hole V53. The thirty-fourth connecting electrode 74 is configured to be connected to the subsequently formed anode connecting electrode.

[0436] In an exemplary embodiment, the fifth conductive layer pattern of adjacent pixel rows can be mirror-symmetrical with respect to the first center line O1. For example, the first power line 81, the fifth power connection line 95, the sixth power connection line 96, the thirty-fourth connection electrode 74, and the seventh electrode plate 170 in the (M-1)th pixel row and the Mth pixel row can be mirror-symmetrical with respect to the first center line O1. For example, the first power line 81, the fifth power connection line 95, the sixth power connection line 96, the thirty-fourth connection electrode 74, and the seventh electrode plate 170 in the Mth pixel row and the M+1th pixel row can be mirror-symmetrical with respect to the first center line O1. For example, the first power line 81, the fifth power connection line 95, the sixth power connection line 96, the thirty-fourth connection electrode 74, and the seventh electrode plate 170 in the M+1th pixel row and the M+2th pixel row can be mirror-symmetrical with respect to the first center line O1.

[0437] In an exemplary embodiment, the thirty-fourth connecting electrode 74 and the seventh electrode plate 170 of adjacent pixel columns can be mirror-symmetrical with respect to the second center line O2. For example, the thirty-fourth connecting electrode 74 and the seventh electrode plate 170 in the (N+1)th and (N+2)th pixel columns can be mirror-symmetrical with respect to the second center line O2. Similarly, the thirty-fourth connecting electrode 74 and the seventh electrode plate 170 in the (N+2)th and (N+3)th pixel columns can be mirror-symmetrical with respect to the second center line O2. Furthermore, the thirty-fourth connecting electrode 74 and the seventh electrode plate 170 in the (N+3)th and (N+4)th pixel columns can be mirror-symmetrical with respect to the second center line O2.

[0438] In an exemplary embodiment, the positions and shapes of the first power line 81, the fifth power connection line 95, and the sixth power connection line 96 of adjacent pixel columns can be substantially the same.

[0439] (15) Forming the eighth insulating layer and the seventh conductive layer pattern. In an exemplary embodiment, forming the eighth insulating layer and the seventh conductive layer pattern may include: sequentially depositing an eighth insulating film and a seventh conductive film on a silicon substrate on which the aforementioned pattern is formed, patterning the seventh conductive film using a patterning process to form an eighth insulating layer covering the pattern of the sixth conductive layer, and a seventh conductive layer pattern disposed on the eighth insulating layer, as shown in FIG21. FIG21 is a schematic diagram of the sixth conductive layer, the eighth insulating layer, the seventh conductive layer, and the subsequently formed ninth insulating layer and the eighth conductive layer. In an exemplary embodiment, the seventh conductive layer may be referred to as the top electrode (CTOP) layer.

[0440] In an exemplary embodiment, the seventh conductive layer pattern in each sub-pixel may include at least an eighth electrode 180.

[0441] In an exemplary embodiment, the eighth electrode plate 180 can be rectangular in shape, and the corners of the rectangle can be chamfered or grooved. It can be disposed between the second scan signal line 31 and the second power line 82. The orthographic projection of the eighth electrode plate 180 on the silicon substrate at least partially overlaps with the orthographic projection of the seventh electrode plate 170 on the silicon substrate. The eighth electrode plate 180 is configured as the upper electrode plate of the second capacitor. The seventh electrode plate 170 and the eighth electrode plate 180 constitute the second capacitor, which is also the sixth sub-capacitor of the pixel driving circuit.

[0442] In an exemplary embodiment, the orthographic projection of at least one of the first electrode plate 110, the second electrode plate 120, the third electrode plate 130, the fourth electrode plate 140, the fifth electrode plate 150, the sixth electrode plate 160, the seventh electrode plate 170, and the eighth electrode plate 180 onto the silicon substrate does not overlap with the orthographic projection of the data signal line 83 onto the silicon substrate.

[0443] In an exemplary embodiment, since the pixel driving circuit is a current-driven circuit, the data voltage range of the data signal line is very small. By ensuring that the data signal line does not overlap with the capacitor plate, the parasitic capacitance between the data signal line and the capacitor plate can be reduced. This prevents the corresponding electrodes in the pixel driving circuit from affecting the data voltage of the data signal line, improves the anti-interference capability of the data signal line, and maximizes the display quality.

[0444] In an exemplary embodiment, the seventh conductive layer pattern of adjacent pixel rows can be mirror-symmetrical with respect to the first center line O1. For example, the eighth electrode 180 in the Mth pixel row and the M+1th pixel row can be mirror-symmetrical with respect to the first center line O1.

[0445] In an exemplary embodiment, the positions and shapes of the eighth plates 180 of adjacent pixel columns can be substantially the same.

[0446] (16) Forming a ninth insulating layer pattern. In an exemplary embodiment, forming a ninth insulating layer pattern may include: depositing a ninth insulating film on a silicon substrate on which the aforementioned pattern is formed, and patterning the ninth insulating film by a patterning process to form a ninth insulating layer covering the pattern of the seventh conductive layer, wherein a plurality of vias are provided on the ninth insulating layer, as shown in FIG21.

[0447] In an exemplary embodiment, the plurality of vias in each sub-pixel may include: a sixty-first via V61, a sixty-second via V62, and a sixty-third via V63.

[0448] In an exemplary embodiment, the orthographic projection of the sixty-first via V61 on the silicon substrate is within the range of the orthographic projection of the first power line 81 on the silicon substrate. The ninth and eighth insulating layers within the sixty-first via V61 are etched away, exposing the surface of the first power line 81. The sixty-first via V61 is configured to allow the subsequently formed seventh power connection line to be connected to the thirty-first connection electrode 71 through the via.

[0449] In an exemplary embodiment, the orthographic projection of the sixty-first via V61 on the silicon substrate at least partially overlaps with the orthographic projection of the first centerline O1 on the silicon substrate.

[0450] In an exemplary embodiment, the orthogonal projection of the sixty-second via V62 onto the silicon substrate is within the range of the orthogonal projection of the thirty-fourth connection electrode 74 onto the silicon substrate. The ninth and eighth insulating layers within the sixty-second via V62 are etched away, exposing the surface of the thirty-fourth connection electrode 74. The sixty-second via V62 is configured to allow a subsequently formed anode connection electrode to be connected to the thirty-fourth connection electrode 74 through the via.

[0451] In an exemplary embodiment, the orthographic projection of the sixty-third via V63 on the silicon substrate is within the range of the orthographic projection of the seventh electrode 170 on the silicon substrate. The ninth insulating layer within the sixty-third via V63 is etched away, exposing the surface of the seventh electrode 170. The sixty-third via V63 is configured to allow the subsequently formed electrode connection lines to be connected to the seventh electrode 170 through the via.

[0452] (17) Forming an eighth conductive layer pattern. In an exemplary embodiment, forming an eighth conductive layer pattern may include: sequentially depositing an eighth conductive thin film on a silicon substrate on which the aforementioned pattern is formed, and patterning the eighth conductive thin film using a patterning process to form an eighth conductive layer pattern disposed on a ninth insulating layer, as shown in Figures 21 and 22, where Figure 22 is a schematic diagram of the eighth conductive layer in Figure 21. In an exemplary embodiment, the eighth conductive layer may be referred to as a sixth metal layer (Metal6) or a second metal interconnect (TM2) layer.

[0453] In an exemplary embodiment, the eighth conductive layer in each sub-pixel may include at least: an anode connection electrode 84, a seventh power connection line 97, an eighth power connection line 98, and an electrode plate connection line 99.

[0454] In an exemplary embodiment, the shape of the seventh power connection line 97 can be a straight line extending along the first direction X. The orthographic projection of the seventh power connection line 97 on the silicon substrate at least partially overlaps with the orthographic projection of the first power line 81 on the silicon substrate. The seventh power connection line 97 is connected to the first power line 81 through the sixty-first via V61.

[0455] In an exemplary embodiment, the orthographic projection of the seventh power connection line 97 onto the silicon substrate at least partially overlaps with the orthographic projection of the first center line O1 onto the silicon substrate.

[0456] In an exemplary embodiment, the shape of the eighth power connection line 98 can be a straight line with the main body extending along the second direction Y, and it can be disposed between two eighth plates 180 of adjacent pixel columns and connected to the seventh power connection line 97.

[0457] In an exemplary embodiment, since the seventh power connection line 97 is connected to the first power line 81 through the sixty-first via V61, the seventh power connection line 97 and the eighth power connection line 98 have the potential of the first power line. This realizes that the seventh power connection line 97 extending along the first direction X and the eighth power connection line 98 extending along the second direction Y form a third layer mesh interconnection structure on the display substrate for transmitting the first power signal. This can further reduce the resistance of the first power line, further reduce the voltage drop of the first power signal, further improve the uniformity of the first power signal in the display substrate, further improve the display uniformity, and further improve the display quality and display performance.

[0458] In an exemplary embodiment, the electrode connection line 99 can be a straight line extending along the first direction X, and can be disposed on the side of the seventh power connection line 97 near the eighth electrode plate 180. The electrode connection line 99 is connected to the eighth electrode plate 180 through the sixty-third via V63 on one hand, and to the eighth power connection line 98 on the other hand. Since the eighth power connection line 98 has the potential of the first power line, the eighth electrode plate 180 also has the potential of the first power line.

[0459] In an exemplary embodiment, in at least one sub-pixel, the seventh power connection line 97, the eighth power connection line 98, and the electrode connection line 99 can be an integral structure that is interconnected.

[0460] In an exemplary embodiment, the seventh power connection line 97, the two electrode connection lines 99, and the multiple eighth power connection lines 98 of adjacent pixel rows can be an integral structure that is interconnected.

[0461] In an exemplary embodiment, since the seventh plate 170 has the potential of the second node N2 and the eighth plate 180 has the potential of the first power line, the seventh plate 170 and the eighth plate 180 form the sixth sub-capacitor, which is also the first sub-capacitor of the second capacitor.

[0462] In an exemplary embodiment, the orthographic projection of the eighth power connection line 98 on the silicon substrate at least partially overlaps with the orthographic projection of the data signal line 83 on the silicon substrate. The eighth power connection line 98, having a constant potential, can shield the impact of voltage jumps in the data signal line 83 on critical nodes of the pixel driving circuit.

[0463] In an exemplary embodiment, in a direction perpendicular to the silicon substrate, the second power connection line 92 is disposed below the data signal line 83, and the fourth power connection line 94, the sixth power connection line 96, and the eighth power connection line 98 are disposed above the data signal line 83, which can shield the impact of the switching voltage in the data signal line 83 on the critical nodes of the pixel driving circuit from both the top and bottom directions.

[0464] In an exemplary embodiment, the seventh power connection line 97 is positioned above the data signal line 83 in a direction perpendicular to the silicon substrate, which can shield the impact of voltage transitions in the data signal line 83 on critical nodes of the pixel driving circuit.

[0465] In an exemplary embodiment, the anode connection electrode 84 can be a strip shape extending along the second direction Y. The anode connection electrode 84 can be connected to the thirty-fourth connection electrode 74 through the sixty-second via V62. The anode connection electrode 84 is configured to be connected to the subsequently formed anode. Since the thirty-fourth connection electrode 74 is connected to the thirty-third connection electrode 73 through a via, the thirty-third connection electrode 73 is connected to the twenty-third connection electrode 63 through a via, the twenty-third connection electrode 63 is connected to the fourteenth connection electrode 54 through a via, the fourteenth connection electrode 54 is connected to the fifth connection electrode 45 through a via, and the fifth connection electrode 45 is connected to the third drain region and the fourth drain region through a via, the connection between the subsequently formed anode and the second electrode of the third transistor T3 and the second electrode of the fourth transistor T4 (the third node N3 of the pixel driving circuit) can be realized, and the current output by the pixel driving circuit can be provided to the anode.

[0466] In an exemplary embodiment, the fifth connection electrode 45 is connected to the second electrode of the fourth transistor through the seventh via V7. The fifth connection electrode 45 is connected to the anode connection electrode 84 through the via and multiple connection electrodes. The orthographic projection of the multiple vias connecting the fifth connection electrode 45 and the anode connection electrode 84 on the silicon substrate does not overlap with the orthographic projection of the seventh via on the silicon substrate at least partially. With this setting, it is possible to effectively avoid the anode connection electrode and the fourth gate electrode from short-circuiting due to abnormality of the via during the production process, effectively avoid the failure of the fourth transistor T4 due to short circuit, and thus effectively avoid display defects caused by the light-emitting device being constantly on or constantly off.

[0467] In an exemplary embodiment, in at least one insulating layer between the conductive layers containing the fifth connecting electrode 45 and the thirty-fourth connecting electrode 74, the distances from the vias connecting the fifth connecting electrode 45 and the anode connecting electrode 84 to the second center lines O2 on adjacent sides are substantially equal, and the ratio of the distances from the vias connecting the fifth connecting electrode 45 and the anode connecting electrode 84 to the second center lines O2 on adjacent sides is 0.9 to 1.1. In the embodiments of this disclosure, by setting the distances from the vias connecting the fifth connecting electrode 45 and the anode connecting electrode 84 to the second center lines O2 on adjacent sides to be substantially equal, in the first direction X, it is advantageous for the anode connecting electrode to be positioned in the middle of the sub-pixel, thereby improving the display effect.

[0468] In an exemplary embodiment, the distances from the orthographic projection of the anode connection electrode onto the plane of the display panel to the second center lines on adjacent sides are substantially equal.

[0469] In an exemplary embodiment, at least two vias are provided in at least one insulating layer between the conductive layers containing the fifth connecting electrode 45 and the thirty-fourth connecting electrode 74, in order to reduce contact resistance and improve connection reliability.

[0470] In an exemplary embodiment, the eighth conductive layer pattern of adjacent pixel rows can be mirror-symmetrical with respect to the first center line O1. For example, the anode connection electrode 84, the seventh power connection line 97, the eighth power connection line 98, and the electrode connection line 99 in the (M-1)th pixel row and the Mth pixel row can be mirror-symmetrical with respect to the first center line O1. Similarly, the anode connection electrode 84, the seventh power connection line 97, the eighth power connection line 98, and the electrode connection line 99 in the Mth pixel row and the M+1th pixel row can be mirror-symmetrical with respect to the first center line O1. Furthermore, the anode connection electrode 84, the seventh power connection line 97, the eighth power connection line 98, and the electrode connection line 99 in the M+1th pixel row and the M+2th pixel row can be mirror-symmetrical with respect to the first center line O1.

[0471] In an exemplary embodiment, the anode connection electrode 84 and the eighth power connection line 98 of adjacent pixel columns can be mirror-symmetrical with respect to the second center line O2. For example, the anode connection electrode 84 and the eighth power connection line 98 in the (N+1)th and (N+2)th pixel columns can be mirror-symmetrical with respect to the second center line O2. Similarly, the anode connection electrode 84 and the eighth power connection line 98 in the (N+2)th and (N+3)th pixel columns can be mirror-symmetrical with respect to the second center line O2. Furthermore, the anode connection electrode 84 and the eighth power connection line 98 in the (N+3)th and (N+4)th pixel columns can be mirror-symmetrical with respect to the second center line O2.

[0472] In an exemplary embodiment, the positions and shapes of the seventh power connection line 97 and the electrode connection line 99 of adjacent pixel columns can be substantially the same.

[0473] In an exemplary embodiment, subsequent fabrication processes may include forming an anode, a pixel definition layer, an organic light-emitting layer, a cathode, a first encapsulation layer, a color filter structure layer, and a second encapsulation layer, etc., which will not be described in detail here.

[0474] In an exemplary embodiment, the first to eighth insulating layers can be silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON), etc., and can be a single-layer structure or a multi-layer composite structure. The first to fifth metal layers can be metallic materials, such as silver (Ag), copper (Cu), aluminum (Al), or molybdenum (Mo), etc., or can be alloy materials composed of metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), etc. The alloy material can be a single-layer structure or a multi-layer composite structure, such as a composite structure composed of Mo, Cu, and Mo layers, etc. In an exemplary embodiment, the planar shape of the via can be rectangular, circular, or elliptical, etc., and the dimensions of multiple vias can be the same or different; this disclosure does not limit this.

[0475] Figure 23 is a schematic diagram of the structure of the first capacitor and the second capacitor in an exemplary embodiment of the present disclosure. As shown in Figure 23, the first sub-capacitors of the first capacitor and the second capacitor are stacked, and the first sub-capacitor of the second capacitor is disposed on the side of the first capacitor away from the silicon substrate. The first capacitor may include a stacked first electrode 110, a second electrode 120, a third electrode 130, a fourth electrode 140, a fifth electrode 150, and a sixth electrode 160, and the first sub-capacitor of the second capacitor may include a stacked seventh electrode 170 and an eighth electrode 180.

[0476] In an exemplary embodiment, the display substrate may include at least: a silicon substrate 101 including an active region pattern, a first insulating layer 201 disposed on the silicon substrate 101, a boron conductive layer disposed on the side of the first insulating layer 201 away from the silicon substrate 101, a second insulating layer 202 disposed on the side of the boron conductive layer away from the silicon substrate 101, a first conductive layer (Metal1) disposed on the side of the second insulating layer 202 away from the silicon substrate 101, a third insulating layer 203 disposed on the side of the first conductive layer away from the silicon substrate 101, a second conductive layer (Metal2) disposed on the side of the third insulating layer 203 away from the silicon substrate 101, a fourth insulating layer 204 disposed on the side of the second conductive layer away from the silicon substrate 101, a third conductive layer (Metal3) disposed on the side of the fourth insulating layer 204 away from the silicon substrate 101, and a fifth insulating layer (Metal3) disposed on the side of the third conductive layer away from the silicon substrate 101. The fifth insulating layer 205 includes a fourth conductive layer (Metal4) disposed on the side of the fifth insulating layer 205 away from the silicon substrate 101, a sixth insulating layer 206 disposed on the side of the fourth conductive layer away from the silicon substrate 101, a fifth conductive layer (MIM) disposed on the side of the sixth insulating layer 206 away from the silicon substrate 101, a seventh insulating layer 207 disposed on the side of the fifth conductive layer away from the silicon substrate 101, a sixth conductive layer (Metal5) disposed on the side of the seventh insulating layer 207 away from the silicon substrate 101, an eighth insulating layer 208 disposed on the side of the sixth conductive layer away from the silicon substrate 101, a seventh conductive layer (CTOP) disposed on the side of the eighth insulating layer 208 away from the silicon substrate 101, a ninth insulating layer 209 disposed on the side of the seventh conductive layer away from the silicon substrate 101, and an eighth conductive layer (Metal6) disposed on the side of the ninth insulating layer 209 away from the silicon substrate 101.

[0477] In an exemplary embodiment, the gate conductive layer may include at least a first electrode 110, the first conductive layer may include at least a second electrode 120, the second conductive layer may include at least a third electrode 130, the third conductive layer may include at least a fourth electrode 140, the fourth conductive layer may include at least a fifth electrode 150, the fifth conductive layer may include at least a sixth electrode 160, the sixth conductive layer may include at least a seventh electrode 170, the seventh conductive layer may include at least an eighth electrode 180, and the eighth conductive layer may include at least a power connection line.

[0478] In an exemplary embodiment, the first conductive layer may further include a ninth electrode 190, which serves as a seventh connecting electrode 47. Since the seventh connecting electrode is connected to the first power region and the first power line 81 respectively through vias, the ninth electrode 190 has the potential of the first power line, and the second electrode 120 has the potential of the second node N2. Therefore, the in-plane capacitance of the ninth electrode 190 and the second electrode 120 forms a seventh sub-capacitor, which is also a supplementary capacitor to the second capacitor. By setting this supplementary capacitor, the capacitance value of the second capacitor can be increased. While ensuring the capacitance value, the area occupied by the capacitor plates can be effectively reduced, which is beneficial for improving resolution.

[0479] In an exemplary embodiment, the first electrode 110 can serve as the gate electrode of the third transistor T3, and thus the first electrode 110 has the potential of the first node N1. The second electrode 120 can be connected to the second electrode of the second transistor T2 and the first electrode of the third transistor T3, and thus the second electrode 120 has the potential of the second node N2. The third electrode 130 can be connected to the first electrode 110 through multiple connection electrodes, and thus the third electrode 130 has the potential of the first node N1. The fourth electrode 140 can be connected to the second electrode 120 through multiple connection electrodes, and thus the fourth electrode 140 has the potential of the second node N2. The fifth electrode 150 can be connected to the third electrode 130 through multiple connection electrodes, and thus the fifth electrode 150 has the potential of the first node N1.

[0480] The sixth electrode 160 can be connected to the seventh electrode 170 through a via, and the seventh electrode 170 can be connected to the fourth electrode 140 through multiple connecting electrodes. Therefore, the sixth electrode 160 and the seventh electrode 170 have the potential of the second node N2. The eighth electrode 180 can be connected to the first power line 81 through the eighth conductive layer (Metal 6), and therefore the eighth electrode 180 has the potential of the first power line. Thus, the first electrode plate 110 and the second electrode plate 120 form the first sub-capacitor of the first capacitor; the second electrode plate 120 and the third electrode plate 130 form the second sub-capacitor of the first capacitor; the third electrode plate 130 and the fourth electrode plate 140 form the third sub-capacitor of the first capacitor; the fourth electrode plate 140 and the fifth electrode plate 150 form the fourth sub-capacitor of the first capacitor; and the fifth electrode plate 150 and the sixth electrode plate 160 form the fifth sub-capacitor of the first capacitor. The first, second, third, fourth, and fifth sub-capacitors in parallel structure form the first capacitor of the pixel driving circuit. The seventh electrode plate 170 and the eighth electrode plate 180 form the second capacitor of the pixel driving circuit, which is also the sixth sub-capacitor. The second capacitor is located on the side of the first capacitor away from the silicon substrate.

[0481] In an exemplary embodiment, since both the first capacitor and the second capacitor are parallel plate capacitors, only one insulating layer is provided between the first electrode 110 and the second electrode 120, only one insulating layer is provided between the second electrode 120 and the third electrode 130, only one insulating layer is provided between the third electrode 130 and the fourth electrode 140, only one insulating layer is provided between the fifth electrode 150 and the sixth electrode 160, only one insulating layer is provided between the sixth electrode 160 and the seventh electrode 170, and only one insulating layer is provided between the seventh electrode 170 and the eighth electrode 180. Therefore, the capacitance of the first capacitor and the second capacitor can be effectively guaranteed. Under the premise of meeting the design requirements, the arrangement of the pixel driving circuit can be made more compact, which helps to improve the resolution of the display device.

[0482] In an exemplary embodiment, the capacitance of the first capacitor and the second capacitor can be further increased by increasing the number of conductive layers, which is not limited herein.

[0483] This exemplary embodiment provides a display substrate that, by sharing circuit nodes and optimizing signal lines, not only effectively reduces the coupling capacitance between signals and effectively avoids crosstalk caused by signal interference noise, but also effectively reduces the resistive-capacitive load and resistance voltage drop of the signal lines, effectively improves the driving capability of the pixel driving circuit, effectively improves display stability and uniformity, and effectively improves display effect and display quality.

[0484] In the embodiments of this disclosure, by setting the first transistor T1, the second transistor T2, and the third transistor T3 of adjacent pixel rows to be mirror images of the first center line, and the fourth transistor T4 of adjacent pixel columns to be mirror images of the second center line, the uniformity and symmetry of the pixel driving circuit are improved. This not only enables the design of uniform process and coupling capacitor, but also enables the design of uniform current distribution, effectively improving display stability and uniformity, and effectively enhancing display effect and display quality.

[0485] In the embodiments of this disclosure, by setting the first transistor T1 of adjacent pixel rows to be mirrored and sharing the first electrode of the first transistor T1, the second transistor T2 of adjacent pixel rows to be mirrored and sharing the first electrode of the second transistor T2, and the fourth transistor T4 of adjacent pixel columns to be mirrored and sharing the first electrode of the fourth transistor T4, the vertical wiring space can be effectively reduced, the number of vias can be reduced, and the area occupied by the pixel driving circuit can be reduced, which is beneficial to achieving high resolution.

[0486] In the embodiments of this disclosure, by setting six transistors in adjacent pixel rows and adjacent pixel columns to share the same first substrate region, and four transistors in adjacent pixel rows and adjacent pixel columns to share the same second substrate region 20A, and transistors of the same type to share the same type of substrate region, the layout space used in the substrate region can be effectively reduced, the area occupied by the pixel driving circuit can be reduced, and high resolution can be achieved.

[0487] In the embodiments of this disclosure, by setting multiple first vias and multiple second vias on the same straight line extending along the first direction X, and multiple first connecting electrodes and multiple second connecting electrodes on the same straight line extending along the first direction X, it is not only beneficial to improve process uniformity, but also helps to increase the wiring space of the first scan signal lines and the second scan signal lines. Setting the first scan signal lines and the second scan signal lines into a straight line and increasing the line width of the first scan signal lines and the second scan signal lines can effectively reduce the resistance of the scan signal lines, effectively reduce the resistive capacitive load and resistance voltage drop of the signal lines, effectively improve the driving capability of the pixel driving circuit, and effectively improve the display stability and uniformity.

[0488] In the embodiments of this disclosure, by setting the orthographic projection of the first scan signal line on the silicon substrate to not overlap with the orthographic projection of the gate electrode of the second transistor T2 on the silicon substrate, the coupling capacitance between the first scan signal line and the second scan signal line is effectively reduced, the mutual influence between the first scan signal line and the second scan signal line is weakened, the rise time and fall time of the scan signal line are reduced, thereby increasing the effective bandwidth of the signal, improving the debuggability of the scan signal, and improving the circuit driving capability.

[0489] In the embodiments of this disclosure, a first-layer mesh-like interconnection structure for transmitting the first power signal is formed by setting the third power connection line and the fourth power connection line in the fourth conductive layer; a second-layer mesh-like interconnection structure for transmitting the first power signal is formed by setting the fifth power connection line and the sixth power connection line in the sixth conductive layer; and a third-layer mesh-like interconnection structure for transmitting the first power signal is formed by setting the seventh power connection line and the eighth power connection line in the eighth conductive layer. The second-layer mesh-like interconnection structure is connected to the first-layer mesh-like interconnection structure, and the third-layer mesh-like interconnection structure is connected to the second-layer mesh-like interconnection structure. The three-layer mesh-like interconnection structure minimizes the resistance of the first power line, minimizes the voltage drop of the first power signal, maximizes the uniformity of the first power signal in the display substrate, maximizes the display uniformity, and maximizes the display quality and display performance.

[0490] In the embodiments of this disclosure, by setting the interconnection between the second power line extending along the first direction X, the first power connection line, and the second power connection line extending along the second direction Y, a mesh-like interconnection structure for transmitting the second power signal is formed on the display substrate. This not only effectively reduces the resistance of the second power line and reduces the voltage drop of the second power signal, but also effectively improves the uniformity of the second power signal in the display substrate, thereby improving display uniformity and display quality.

[0491] In the embodiments of this disclosure, by placing the second power line and the eighth connection electrode in the first conductive layer and the sixteenth connection electrode in the second conductive layer, the eighth connection electrode and the sixteenth connection electrode constitute the second power connection line of this disclosure. The mesh-like interconnection structure for transmitting the second power signal is realized by utilizing the two conductive layers, and the second power connection line is a double-layer structure of the trace. Without increasing the vias, the resistance of the second power line is further reduced, and the voltage drop of the second power signal is reduced.

[0492] In the embodiments of this disclosure, a first sub-capacitor, a second sub-capacitor, a third sub-capacitor, a fourth sub-capacitor, a fifth sub-capacitor, and a fifth sub-capacitor are formed using a gate conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer, respectively. These first, second, third, fourth, and fifth sub-capacitors, connected in parallel, form the first capacitor of the MIM capacitor structure. This maximizes the capacitance value of the first capacitor, ensuring the stability of the output current of the pixel driving circuit, guaranteeing the stability and uniformity of OLED brightness, and reducing the risk of display defects such as screen flicker. In the embodiments of this disclosure, the first capacitor has a simple structure and a reasonable layout. While ensuring the capacitance value, it can effectively reduce the area occupied by the capacitor plates, which is beneficial for improving resolution.

[0493] In the embodiments of this disclosure, by setting a first capacitor and a second capacitor in a planar capacitor structure, and stacking the first capacitor and the second capacitor, not only can the problem of capacitor area limitation be solved, but the parasitic capacitance generated by the stacked structure can also be superimposed on the capacitor itself, reducing the influence of parasitic capacitance and increasing the capacitance value. This ensures the stability and uniformity of the output current of the pixel driving circuit, and allows for a more compact arrangement of the pixel driving circuit while meeting design requirements, which helps to improve the resolution of the display device.

[0494] In the embodiments of this disclosure, by setting the data signal line to not overlap with the plates of the first capacitor and the second capacitor, the parasitic capacitance between the data signal line and each plate can be reduced, the corresponding electrodes in the pixel driving circuit can be prevented from affecting the data voltage of the data signal line, the anti-interference capability of the data signal line can be improved, and the display quality can be maximized.

[0495] In the embodiments of this disclosure, the layout of the pixel driving circuit is optimized through the above structural design, thus optimizing the layout space and reducing the area occupied by the pixel driving circuit while improving anti-interference capability. In the embodiments of this disclosure, the display substrate can meet the display requirements of 4K*4K resolution and refresh rate of 60Hz to 120Hz, with better stability and smoothness of the displayed image. It can effectively reduce dizziness in VR applications and the screen door effect in AR applications, effectively increasing immersion and improving user experience.

[0496] The fabrication process according to the embodiments of this disclosure is based on a 0.11μm integrated circuit process, which is well compatible with existing fabrication processes. The process is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0497] In exemplary embodiments, the display substrate of this disclosure can be applied to display devices with pixel driving circuits, such as Micro OLED microdisplays, OLED displays, quantum dot displays (QLED), light-emitting diode microdisplays (Micro LED or Mini LED) or quantum dot light-emitting diode microdisplays (QDLED), etc., and this disclosure does not limit them.

[0498] In exemplary embodiments, the pixel driving circuit of the display substrate disclosed herein can be applied to product types including but not limited to integrated silicon-based, glass-based, printed circuit board (PCB)-based substrate materials, amorphous silicon (a-Si), low-temperature polycrystalline silicon (LTPS), low-temperature polycrystalline oxide (LTPO), oxide semiconductor materials represented by indium gallium zinc oxide (IGZO), and devices such as thin-film transistors (TFTs), metal-oxide semiconductors (MOS), and diodes with structures such as back channel etching structure (BCE), etch stop layer structure (ESL), top gate structure, and dual gate structure.

[0499] The structure of the display device and its fabrication process in the exemplary embodiments disclosed herein are merely illustrative examples. The corresponding structure and the patterning process may be modified or increased or decreased according to actual circumstances. This disclosure does not limit the scope of the invention.

[0500] Exemplary embodiments of this disclosure also provide a method for fabricating a display substrate. In an exemplary embodiment, the display substrate includes a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns; the fabrication method may include: forming a pixel driving circuit in at least one sub-pixel, the pixel driving circuit including at least a first transistor, a second transistor, a third transistor, and a fourth transistor, wherein a first electrode of the first transistor is coupled to a data signal line, a second electrode of the first transistor is coupled to the gate electrode of the third transistor, a first electrode of the second transistor is coupled to a first power line, a second electrode of the second transistor is coupled to the first electrode of the third transistor, a first electrode of the fourth transistor is coupled to a second power line, and a second electrode of the fourth transistor is coupled to the second electrode of the third transistor; the second power line is coupled to the first electrode of the fourth transistor through a second power extension, the second power line is a line shape extending along a first direction, the second power extension is a line shape extending along a second direction, the first direction and the second direction intersect, the second power line is continuously disposed in the first direction, the second power extension is discontinuously disposed in the second direction, the second power line and the second power extension are disposed in the same layer, and the second power extension is coupled to the second power line.

[0501] This exemplary embodiment also provides a display device, including the aforementioned display substrate. As shown in FIG24, the display device provided in this embodiment can be used in virtual reality devices, augmented reality devices, extended reality devices, mixed reality devices, sights, and rangefinders, etc., and can also be used in, but not limited to, mobile phones, tablets, televisions, monitors, laptops, digital photo frames, navigators, or any product or component with display function.

[0502] While the embodiments disclosed herein are as described above, it should be noted that these embodiments are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the specific content shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the embodiments without departing from the scope of this disclosure.

Claims

A display substrate includes a plurality of sub-pixels arranged to form a plurality of pixel rows and a plurality of pixel columns, at least one sub-pixel including a pixel driving circuit, wherein The pixel driving circuit includes at least a first transistor, a second transistor, a third transistor, and a fourth transistor, the first transistor, the second transistor, the third transistor, and the fourth transistor each including a first electrode and a second electrode, the display substrate including a data signal line, a first power supply line, and a second power supply line, the first electrode of the first transistor being coupled to the data signal line, the second electrode of the first transistor being coupled to a gate electrode of the third transistor, the first electrode of the second transistor being coupled to the first power supply line, the second electrode of the second transistor being coupled to the first electrode of the third transistor, the first electrode of the fourth transistor being coupled to the second power supply line, and the second electrode of the fourth transistor being coupled to the second electrode of the third transistor; The display substrate further includes a first power supply region and a seventh connection electrode, the first power supply region being coupled to the first power supply line, and the seventh connection electrode being connected to the first power supply region through a twelfth via hole; In at least one pixel row, the seventh connection electrode includes a first sub-electrode, a second sub-electrode, and a third sub-electrode, the first sub-electrode and the third sub-electrode being connected through the second sub-electrode, the first sub-electrode and the third sub-electrode having a shape of a strip extending along a second direction, and the second sub-electrode having a shape of a strip extending along a first direction, at least a portion of the first sub-electrode and at least a portion of the third sub-electrode being located on a same side of the second sub-electrode in the second direction, the first direction and the second direction intersecting. The display substrate according to claim 1, wherein The display substrate further includes a first connection electrode and a third connection electrode; The first transistor includes at least a first active region, the first active region including at least a first source region and a first drain region, the first source region being connected to the first connection electrode through a first via hole, the first connection electrode being connected to the data signal line, and the first drain region being connected to the gate electrode of the third transistor through a third via hole and the third connection electrode; The display substrate has a first region on a display substrate plane, the first region being a region surrounded by a normal projection of the seventh connection electrode on the display substrate plane; The first region and a normal projection of the third connection electrode on the display substrate plane at least partially overlap. The display substrate according to claim 2, wherein The third connection electrode is connected to the gate electrode of the third transistor through a tenth via hole, a normal projection of the tenth via hole on the display substrate plane being in the first region. The display substrate according to any one of claims 1-3, wherein The third transistor at least includes a third active region, a positive projection of the first sub-electrode on a display substrate plane does not overlap a positive projection of the third active region on the display substrate plane, a positive projection of the second sub-electrode on the display substrate plane at least partially overlaps the positive projection of the third active region on the display substrate plane, and a positive projection of the third sub-electrode on the display substrate plane is located in the positive projection of the third active region on the display substrate plane. The display substrate according to claim 4, wherein The first transistor further includes a first gate electrode, the display substrate includes a first scan signal line and a second scan signal line, the first gate electrode is connected with the first scan signal line, and the second transistor at least includes a second gate electrode and a second active region, and the second gate electrode is connected with the second scan signal line. The first scan signal line is in a linear shape extending along the first direction, a positive projection of the first scan signal line on a display substrate plane does not overlap a positive projection of the second gate electrode on the display substrate plane, and a positive projection of the first scan signal line on the display substrate plane at least partially overlaps a positive projection of the second active region on the display substrate plane. In the second direction, a fourth distance is between the first sub-electrode and the first scan signal line, and a third distance is between the third sub-electrode and the first scan signal line, and the fourth distance is smaller than the third distance. The display substrate according to claim 5, wherein The display substrate includes a second power supply extension, the second power supply line is coupled with the first electrode of the fourth transistor through the second power supply extension, the second power supply line is in a linear shape extending along the first direction, the second power supply extension is in a linear shape extending along the second direction, the second power supply line is continuously arranged in the first direction, the second power supply extension is discontinuously arranged in the second direction, the second power supply extension and the second power supply line are arranged in the same layer, and the second power supply extension is coupled with the second power supply line. In the second direction, a second distance is between the first sub-electrode and the second power supply extension, and the fourth distance is greater than the second distance. The display substrate according to claim 6, wherein The display substrate further includes a second gate connection block, in the first direction, the second gate connection block is arranged on a side of the second gate electrode away from the first gate electrode and connected with the second gate electrode, and the second scan signal line is connected with the second gate connection block through a ninth via hole. In the first direction, the third via hole and the second gate connection block are arranged on two sides of the first sub-electrode, and the third via hole and the second gate connection block are spaced apart by the first sub-electrode. The display substrate according to claim 7, wherein In the first direction, a fifth distance is between an edge of the second gate connection block on a side close to the first sub-electrode and an edge of the first sub-electrode on a side close to the second gate connection block, and a sixth distance is between an edge of the third via hole on a side close to the first sub-electrode and an edge of the first sub-electrde on a side close to the third via hole. The fifth distance is greater than the sixth distance. The display substrate according to claim 3, wherein In the first direction, a seventh spacing is between an edge of the tenth via hole close to the first sub-electrode and an edge of the first sub-electrode close to the tenth via hole; In the second direction, an eighth spacing is between an edge of the tenth via hole close to the second sub-electrode and an edge of the second sub-electrode close to the tenth via hole; In the first direction, a ninth spacing is between an edge of the tenth via hole close to the third sub-electrode and an edge of the third sub-electrode close to the tenth via hole; The seventh spacing is greater than or equal to the eighth spacing, and the seventh spacing is greater than or equal to the ninth spacing. The display substrate according to claim 9, wherein In the first direction, the first sub-electrode is arranged between two adjacent third transistors to separate the two adjacent third transistors; In the first direction, a tenth spacing is between an edge of the first sub-electrode close to a gate electrode of a third transistor of a sub-pixel where the first sub-electrode is located and an edge of the gate electrode of the third transistor of the sub-pixel close to the first sub-electrode, and an eleventh spacing is between an edge of the first sub-electrode close to a gate electrode of a second third transistor of a second sub-pixel and an edge of the gate electrode of the second third transistor of the second sub-pixel close to the first sub-electrode, and the tenth spacing is greater than the eleventh spacing. The display substrate according to claim 10, wherein In the first direction, the first sub-electrode is arranged between the tenth via hole and a third transistor of a second sub-pixel to separate the third transistor of the second sub-pixel and the tenth via hole; The seventh spacing is greater than or equal to the eleventh spacing. The display substrate according to claim 2, wherein The display substrate further comprises a fourth connection electrode connected to the second electrode of the second transistor through a fourth via hole; A projection of the fourth connection electrode on the display substrate plane at least partially overlaps a projection of the gate electrode of the third transistor on the display substrate plane. The display substrate according to claim 12, wherein The fourth connection electrode has an "L" shape, a first excess width is between an edge of the projection of the fourth connection electrode on the display substrate plane close to the first sub-electrode and an edge of the projection of the first electrode plate on the display substrate plane close to the first sub-electrode, and a second excess width is between an edge of the projection of the fourth connection electrode on the display substrate plane and an edge of the projection of the first electrode plate on the display substrate plane close to the second sub-pixel; The first excess width is greater than the second excess width. The display substrate according to claim 6, wherein The third transistor comprises at least a third active region comprising at least a third source region and a third drain region, the fourth transistor comprises at least a fourth active region comprising at least a fourth source region and a fourth drain region, and the display substrate comprises a fifth connection electrode, and the third drain region is connected to the fourth drain region through the fifth connection electrode. The fifth connection electrode has a projection on the display substrate plane that at least partially overlaps with a projection of the third active region on the display substrate plane, and in adjacent two sub-pixels, a ratio of overlapping areas of the projections is 0.9 to 1.

1. The display substrate according to claim 14, wherein The fifth connection electrode of at least one sub-pixel includes a first sub-section, a second sub-section and a third sub-section, and the second sub-section connects the first sub-section and the third sub-section; The first sub-section and the third sub-section are in a strip shape extending along the first direction, the first sub-section is connected with the third drain region through a fifth via, the third sub-section is connected with the fourth drain region through a seventh via, and the second sub-section is in a strip shape extending along the second direction; The first sub-section has a projection on the display substrate plane that partially overlaps with a projection of the third active region on the display substrate plane, and in adjacent sub-pixels, a ratio of overlapping areas of the projections is not 1. The display substrate according to claim 15, wherein In the second direction, the fifth via to the second power supply line has a first interval, and the second power supply extension has a third extension length on one side of the second power supply line; The third extension length is substantially equal to the first interval. The display substrate according to claim 15, wherein The third sub-section has a projection on the display substrate plane that is located in a projection of the fourth active region on the display substrate plane, and the projection of the third sub-section on the display substrate plane at least partially overlaps with a projection of the fourth gate electrode on the display substrate plane. The display substrate according to claim 14, wherein The display substrate further includes a first power supply connection line connected with the second power supply line through a twenty-eighth via, the first power supply connection line is in a straight line shape extending along the first direction, and in the same pixel row, the first power supply connection line is arranged between the gate electrode of the third transistor and the fourth transistor in the second direction, The first power supply connection line has a projection on the display substrate plane that partially overlaps with a projection of the fifth connection electrode on the display substrate plane. The display substrate according to claim 5, wherein The display substrate further includes a mesh structure for transmitting a first power supply signal, the mesh structure is connected with the first electrode of the second transistor through a via and a twelfth connection electrode, and adjacent sub-pixels in one pixel column share the same twelfth connection electrode. The display substrate according to claim 2, wherein The second active region includes at least a second source region and a second drain region, the second source region is connected with the second connection electrode through a second via, the second connection electrode is connected with the first power supply line, and the second drain region is connected with the first electrode of the third transistor; In at least one pixel column, the first active regions in adjacent sub-pixels are an integrated structure connected with each other, the second active regions in adjacent sub-pixels are an integrated structure connected with each other, the first source regions in adjacent sub-pixels are shared, the second source regions in adjacent sub-pixels are shared, and the first via and the second via are located on the same straight line extending along the first direction. The display substrate according to claim 14, wherein The display substrate further comprises an anode connecting electrode connected with the second electrode of the fourth transistor through a via, and the third sub segment of the fifth connecting electrode is connected with the anode connecting electrode through a via. The fifth connecting electrode is connected with the second electrode of the fourth transistor through a seventh via, and the fifth connecting electrode is connected with the anode connecting electrode through a via and a plurality of connecting electrodes, and the orthographic projection of the via connecting the fifth connecting electrode and the anode connecting electrode on the display substrate plane at least partially does not overlap with the orthographic projection of the seventh via on the display substrate plane. The display substrate according to claim 21, wherein The display substrate further comprises a thirty-fourth connecting electrode, and the fifth connecting electrode is connected with the thirty-fourth connecting electrode through a via. In at least one insulating layer between the conductive layers where the fifth connecting electrode and the thirty-fourth connecting electrode are located, the number of the vias connecting the fifth connecting electrode and the thirty-fourth connecting electrode is at least two. The display substrate according to claim 22, wherein In at least one insulating layer between the conductive layers where the fifth connecting electrode and thirty-fourth connecting electrode are located, the ratio of the distance from the via connecting the fifth connecting electrode and the anode connecting electrode to the second center line on the adjacent two sides is 0.9-1.1, and the second center line is a straight line located between the adjacent pixel columns and extending along the second direction. The display substrate according to claim 23, wherein In the first direction, the orthographic projection of the anode connecting electrode on the display panel plane to the second center line on the adjacent two sides is substantially equal; The anode connecting electrode is connected with the thirty-fourth connecting electrode through a sixty-second via, and in the first direction, the orthographic projection of the sixty-second via on the display panel plane to the second center line on the adjacent two sides is substantially equal. The display substrate according to claim 12, wherein, The pixel driving circuit further comprises a storage capacitor, and the storage capacitor at least comprises a first plate and a second plate, the first plate serving as the gate electrode of the third transistor, and the second plate serving as the fourth connecting electrode. The storage capacitor further comprises a third plate, and the third plate is connected with the third connecting electrode through a twenty-third via, and the orthographic projection of the third plate on the display substrate plane and the orthographic projection of the second plate on the display substrate plane at least partially overlap. At least one of the twenty-third vias has an orthographic projection on the display substrate plane in the first area. The display substrate according to claim 25, wherein The storage capacitor further comprises a fourth plate, and the fourth plate is connected with the second plate through a via, and the orthographic projection of the fourth plate on the display substrate plane and the orthographic projection of the third plate on the display substrate plane at least partially overlap, and the shape of the fourth plate is "concave” or "back” shape. The display substrate according to claim 26, wherein The display substrate plane has a second area, and the second area is formed by the orthographic projection of the fourth plate on the display substrate plane being surrounded or half-enclosed; The orthographic projection of the third sub-electrode on the display substrate plane is in the second area. The display substrate according to claim 26, wherein The storage capacitor further comprises a fifth plate, and the fifth plate is connected with the third plate through a via, and the orthographic projection of the fifth plate on the display substrate plane and the orthographic projection of the fourth plate on the display substrate plane at least partially overlap. The orthographic projection of the second electrode plate on the display substrate plane is located in the orthographic projection of the fifth electrode plate on the display substrate plane. The display substrate according to claim 28, wherein, The fifth electrode plate is connected with the third electrode plate through a thirty-third via hole and a forty-first via hole, and the thirty-third via hole and the forty-first via hole are located on the same straight line extending in a direction perpendicular to the display substrate plane. The orthographic projection of the thirty-third via hole on the display substrate plane is located in the second region, and the orthographic projection of the forty-first via hole on the display substrate plane is located in the second region. The display substrate according to any one of claims 1-24, wherein The pixel driving circuit further comprises a first capacitor and a second capacitor, the first capacitor comprises a first sub-capacitor, a second sub-capacitor, a third sub-capacitor, a fourth sub-capacitor and a fifth sub-capacitor in a parallel structure, In a direction perpendicular to the display substrate plane, the second sub-capacitor is arranged on a side of the first sub-capacitor away from the display substrate, the third sub-capacitor is arranged on a side of the second sub-capacitor away from the first sub-capacitor, the fourth sub-capacitor is arranged on a side of the third sub-capacitor away from the first sub-capacitor, and the fifth sub-capacitor is arranged on a side of the fourth sub-capacitor away from the first sub-capacitor. The second capacitor is arranged on a side of the fifth sub-capacitor away from the first sub-capacitor. The display substrate according to claim 30, wherein The second capacitor further comprises a supplementary capacitor in parallel, and two electrode plates of the supplementary capacitor of the second capacitor are located in the same conductive layer as one electrode plate of the first sub-capacitor. The display substrate according to claim 30, wherein In a direction perpendicular to the display substrate plane, the display substrate comprises at least a gate conductive layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, a seventh conductive layer and an eighth conductive layer arranged in sequence; The gate conductive layer comprises at least the first electrode plate, and the first electrode plate serves as a gate electrode of the third transistor; The first conductive layer comprises at least the second electrode plate, and the second electrode plate is connected with a second electrode of the second transistor and a first electrode of the third transistor respectively, and the first sub-capacitor comprises the first electrode plate and the second electrode plate; The second conductive layer comprises at least the third electrode plate, and the third electrode plate is connected with the first electrode plate, and the second sub-capacitor comprises the second electrode plate and the third electrode plate; The third conductive layer comprises at least the fourth electrode plate, and the fourth electrode plate is connected with the second electrode plate, and the third sub-capacitor comprises the third electrode plate and the fourth electrode plate; The fourth conductive layer comprises at least the fifth electrode plate, and the fifth electrode plate is connected with the third electrode plate, and the fourth sub-capacitor comprises the fourth electrode plate and the fifth electrode plate; The fifth conductive layer comprises at least a sixth electrode plate, and the sixth electrode plate is connected with the fourth electrode plate, and the fifth sub-capacitor comprises the fifth electrode plate and the sixth electrode plate; The sixth conductive layer comprises at least a seventh electrode plate, and the seventh electrode plate is connected with the fourth electrode plate. The seventh conductive layer includes at least an eighth plate, the eighth plate is connected with the first power line, and the second capacitor includes the seventh plate and the eighth plate. The display substrate according to claim 32, wherein The first conductive layer further includes a ninth plate, the ninth plate serves as the seventh connection electrode, and the second capacitor further includes a supplementary capacitor in parallel, and the supplementary capacitor includes the ninth plate and the second plate. A display device, wherein, The display substrate includes any one of 1 to 33. A method for manufacturing a display substrate, wherein The display substrate includes a plurality of sub-pixels arranged to form a plurality of pixel rows and a plurality of pixel columns; the preparation method includes forming a pixel driving circuit in at least one sub-pixel, The pixel driving circuit includes at least a first transistor, a second transistor, a third transistor and a fourth transistor, the first transistor, the second transistor, the third transistor and the fourth transistor each include a first electrode and a second electrode, the display substrate includes a data signal line, a first power line and a second power line, the first electrode of the first transistor is coupled with the data signal line, the second electrode of the first transistor is coupled with the gate electrode of the third transistor, the first electrode of the second transistor is coupled with the first power line, the second electrode of the second transistor is coupled with the first electrode of the third transistor, the first electrode of the fourth transistor is coupled with the second power line, and the second electrode of the fourth transistor is coupled with the second electrode of the third transistor; The display substrate further includes a first power area and a seventh connection electrode, the first power area is coupled with the first power line, and the seventh connection electrode is connected with the first power area through a twelfth via hole; In at least one pixel row, the seventh connection electrode includes a first sub-electrode, a second sub-electrode and a third sub-electrode, the first sub-electrode and the third sub-electrode are connected through the second sub-electrode, the shapes of the first sub-electrode and the third sub-electrode are strip shapes extending along the second direction, the shape of the second sub-electrode is a strip shape extending along the first direction, at least a part of the first sub-electrode and at least a part of the third sub-electrode are located on the same side of the second sub-electrode in the second direction, and the first direction and the second direction intersect.

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