A data processing structure, semiconductor structure and memory

Abstract

This disclosure provides a data processing structure, a semiconductor structure, and a memory. The data processing structure includes a data sampling module, which comprises a logic module and a control module, with the control module located around the logic module. The logic module includes a first well region, and the control module includes a second well region, with a gap between the first and second well regions to separate the control module and the logic module. The control module generates an enable control signal, and the logic module receives a first data signal, a clock signal, and the enable control signal. When the enable control signal is active, the clock signal is used to sample the first data signal, and a second data signal is output. This complete separation of the control module and the logic module mitigates interference from the control module to the logic module, improves the data sampling performance of the logic module, and reduces substrate noise.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a data processing structure, semiconductor structure, and memory. Background Technology

[0002] Currently, with the continuous improvement of circuit integration, the device size and spacing of integrated circuits are further compressed, placing higher demands on device functionality. Memory contains functional modules that perform logical data processing. At high operating speeds, interference can exist between different parts of the data processing structure, reducing memory performance. Summary of the Invention

[0003] This disclosure provides a data processing structure, a semiconductor structure, and a memory that can reduce noise interference problems and improve the performance of the data processing structure.

[0004] In a first aspect, embodiments of this disclosure provide a data processing structure, the data processing structure including a data sampling module, and the data sampling module including a logic module and a control module, the control module being located around the logic module; the logic module including a first well region, the control module including a second well region, and a gap existing between the first well region and the second well region, so that the control module and the logic module are separately configured; wherein,

[0005] The control module is used to generate an enable control signal;

[0006] The logic module is used to receive a first data signal, a clock signal, and an enable control signal; when the enable control signal is valid, it uses the clock signal to sample and process the first data signal and outputs a second data signal.

[0007] In some embodiments, the first well region is connected to a first power source, the second well region is connected to a second power source, and the potential of the first power source is higher than the potential of the second power source.

[0008] In some embodiments, the data processing structure further includes a data buffer module, which is used to output the first data signal or receive the second data signal;

[0009] The data buffer module and the data sampling module are adjacent to each other, and the data sampling module and the data buffer module are arranged along a first direction.

[0010] In some embodiments, in a first direction, the projection of the control module overlaps with the projection of the logic module.

[0011] In some embodiments, in the first direction, the control module and the logic module are both located on the same side of the data buffer module, and the control module is in contact with the data buffer module, with the distance between the logic module and the data buffer module being a first value; in the second direction, the distance between the control module and the logic module is a second value, such that there is a continuous region between the control module, the logic module, and the data buffer module; wherein, the second direction is perpendicular to the first direction.

[0012] In some embodiments, the data processing structure further includes multiple capacitor modules; wherein,

[0013] Multiple capacitor modules are located in a continuous area between the control module, the logic module, and the data buffer module; wherein the data sampling module and the data buffer module share multiple capacitor modules to implement power supply noise reduction function.

[0014] In some embodiments, the power supply terminal of the capacitor module is connected to the power signal terminal through a metal layer and a contact structure, and the ground terminal of the capacitor module is connected to the ground signal terminal through a metal layer and a contact structure.

[0015] The power signal terminal supplies power to the data sampling module and the data buffer module.

[0016] In some embodiments, each capacitor module includes a plurality of capacitor structures arranged in parallel, the first end of each capacitor structure being connected to the power supply terminal of its respective capacitor module, and the second end of each capacitor structure being connected to the ground terminal of its respective capacitor module.

[0017] In some embodiments, the capacitor structure is a columnar capacitor structure.

[0018] In some embodiments, the continuous region has a first opening and a second opening in a second direction, and the first opening and the second opening are symmetrically distributed along the logic module;

[0019] When there are multiple data processing structures, the multiple data processing structures are arranged sequentially along the second direction; wherein, the first opening of the continuous region in the data sampling module is connected to the second opening of the continuous region in the adjacent data sampling module, so that the continuous regions of all data sampling modules are connected.

[0020] In some embodiments, the control module includes a first control module and a second control module; in a second direction, the first control module and the second control module are symmetrically located on both sides of the logic module.

[0021] In the first direction, the lengths of the first control module and the second control module are both third values, the length of the logic module is a fourth value, and the sum of the fourth value and the first value is greater than the third value.

[0022] In some embodiments, in a second direction, a first control module in one data processing structure is adjacent to a second control module in another data processing structure; in a plurality of capacitor modules, one of the capacitor modules provides power supply noise reduction functionality for both the first control module and the adjacent second control module.

[0023] In some embodiments, the data sampling module is at least a parallel-to-serial conversion module, and the first well region and the second well region are deep N-wells.

[0024] In a second aspect, embodiments of this disclosure provide a semiconductor structure including a plurality of data processing structures as described in the first aspect.

[0025] Thirdly, embodiments of this disclosure provide a memory comprising the semiconductor structure described in the second aspect.

[0026] This disclosure provides a data processing structure, a semiconductor structure, and a memory. The data processing structure includes a data sampling module, which comprises a logic module and a control module, with the control module located around the logic module. The logic module includes a first well region, and the control module includes a second well region, with a gap between the first and second well regions to separate the control module and the logic module. The control module generates an enable control signal, and the logic module receives a first data signal, a clock signal, and the enable control signal. When the enable control signal is active, the clock signal is used to sample the first data signal, and a second data signal is output. This complete separation of the control module and the logic module mitigates interference from the control module to the logic module, improves the data sampling performance of the logic module, and reduces substrate noise. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of a data processing structure.

[0028] Figure 2 This is a schematic diagram of the layout of a data sampling module;

[0029] Figure 3 A schematic diagram of a data processing structure provided in an embodiment of this disclosure. Figure 1 ;

[0030] Figure 4 A schematic diagram of a data processing structure provided in an embodiment of this disclosure. Figure 2 ;

[0031] Figure 5A A schematic diagram of a data processing structure provided in an embodiment of this disclosure. Figure 3 ;

[0032] Figure 5B A schematic diagram of a data processing structure provided in an embodiment of this disclosure. Figure 4 ;

[0033] Figure 6 Schematic diagram five of a data processing structure provided in an embodiment of this disclosure;

[0034] Figure 7A A schematic diagram of a data processing structure provided in an embodiment of this disclosure. Figure 6 ;

[0035] Figure 7B Schematic diagram seven of a data processing structure provided in an embodiment of this disclosure;

[0036] Figure 8 A schematic diagram of a data processing structure provided in an embodiment of this disclosure. Figure 8 ;

[0037] Figure 9 A schematic diagram of a data processing structure provided in an embodiment of this disclosure. Figure 9 ;

[0038] Figure 10 A schematic diagram of a data processing structure provided in an embodiment of this disclosure. Figure 10 ;

[0039] Figure 11 A schematic diagram of a semiconductor structure provided in an embodiment of this disclosure;

[0040] Figure 12 This is a schematic diagram of the structure of a memory provided in an embodiment of the present disclosure. Detailed Implementation

[0041] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are merely for explaining the relevant applications and not for limiting the applications. It should also be noted that, for ease of description, only the parts related to the relevant applications are shown in the accompanying drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to limit this disclosure. In the following description, references to "some embodiments" describe a subset of all possible embodiments; however, it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict. It should be noted that the terms "first, second, third" involved in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0042] The following are explanations of some terms used in the embodiments of this disclosure:

[0043] P2S (Parallel to Serializer): Parallel-to-serial conversion;

[0044] FIFO (First Input First Output): Data is entered and exited first; it is a type of data buffer.

[0045] DNW (Deep N-Well): Deep N-well;

[0046] DRAM (Dynamic Random Access Memory): Dynamic random access memory;

[0047] DDR (Double Data Rate SDRAM): Memory with double data rates;

[0048] LPDDR (Low Power DDR): Low power DDR.

[0049] Integrated circuit layout design is the foundation of integrated circuit physical implementation, and its quality directly affects the power consumption and performance of the underlying circuit. This disclosure relates to a data processing structure for a memory, which functions by sampling and processing data signals using a clock signal. This data processing structure may be used to implement functions such as parallel-to-serial conversion and serial-to-parallel conversion.

[0050] Taking a data processing structure (or serializer P2S) that implements parallel-to-serial conversion as an example, see [link to documentation]. Figure 1 It illustrates a layout diagram of a data processing structure. For example... Figure 1 As shown, the data processing structure includes a data sampling module and a data buffer module. The data buffer module can consist of multiple FIFO data buffers, used to output multiple parallel data signals. The data sampling module samples the data signals output by the data buffer module and selects the output, thereby converting the parallel data signals into serial data signals. See also... Figure 2 This illustrates a layout diagram of a data sampling module. (For example...) Figure 2 As shown, the data sampling module includes a logic module and a control module. The control module outputs an enable signal to the logic module, and the logic module performs the specific data sampling processing. Figure 2 In this system, there are two control modules, both located below the logic module and symmetrically positioned on the left and right sides of the logic module. For Figure 2 In the control module shown, the logic module and the control module share the same well potential. Additionally, as... Figure 1 As shown, in order to reduce power supply interference, multiple capacitor modules are independently set around the data buffer module and the data sampling module to achieve the function of power supply noise reduction coupling.

[0051] However, since the logic module and the control module share the same well potential, the logic module may be subject to potential interference from the control module, introducing additional noise during the signal parallel-to-serial conversion process, resulting in a deterioration in the serialization effect. In addition, the current layout design also leads to a larger circuit area, increasing the chip cost.

[0052] This disclosure provides a data processing structure including a data sampling module, which comprises a logic module and a control module, with the control module located around the logic module. The logic module includes a first well region, and the control module includes a second well region, with a gap between the first and second well regions to separate the control module and the logic module. The control module generates an enable control signal; the logic module receives a first data signal, a clock signal, and the enable control signal. When the enable control signal is valid, the clock signal is used to sample the first data signal, and a second data signal is output. This complete separation of the control module and the logic module mitigates interference from the control module to the logic module, improves the data sampling performance of the logic module, and reduces substrate noise.

[0053] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0054] In one embodiment of this disclosure, see Figure 3 It illustrates a schematic diagram of a data processing structure 10 provided in an embodiment of this disclosure. Figure 1 .like Figure 3 As shown, the data processing structure includes a data sampling module 11, which includes a logic module 111 and a control module 112. The control module 112 is located around the logic module 111. The logic module 111 includes a first well region, and the control module 112 includes a second well region. There is a gap between the first well region and the second well region, so that the control module 112 and the logic module 111 are separately configured.

[0055] The control module 112 is used to generate an enable control signal;

[0056] The logic module 111 is used to receive a first data signal, a clock signal and the enable control signal; when the enable control signal is valid, it uses the clock signal to sample and process the first data signal and outputs a second data signal.

[0057] It should be noted that the data processing structure 10 provided in this embodiment is mainly used to implement data signal sampling processing and can be applied to various types of electronic devices, such as DRAM, DDR, LPDDR, etc. Specifically, the data processing structure 10 can be used to implement signal parallel-to-serial conversion, signal serial-to-parallel conversion, etc.

[0058] For example, when the data processing structure 10 is used to implement the signal parallel-to-serial conversion function, the first data signal is a parallel signal and the second data signal is a serial signal. When the data processing structure 10 is used to implement the signal serial-to-parallel conversion function, the first data signal is a serial signal and the second data signal is a parallel signal; or, the data sampling module 11 can also implement the signal sampling function in other scenarios, that is, the serial-to-parallel type of the first data signal and the second data signal can also be the same.

[0059] It should be understood that the control module 112 can control the operating state of the logic module 111, that is, the logic module 111 needs to operate according to the enable control signal output by the control module 112. For example... Figure 3 As shown, there are two control modules 112, which are arranged on the left and right sides of the logic module 111. In this way, the control module 112 on the left controls the logic module 111 on the left side, and the control module 112 on the right controls the logic module 111 on the right side. This not only reduces the winding length but also improves the control effect.

[0060] This disclosure does not limit the specific number of control modules 112. See also Figure 4 It illustrates a schematic diagram of a data processing structure 10 provided in an embodiment of this disclosure. Figure 2 .like Figure 4 As shown, the number of control modules 112 can also be one, in which case the control module 112 can be located on either side of the logic module 111. In other words, Figure 3 or Figure 4 These are all feasible embodiments of the present disclosure, but do not constitute a limitation of the present disclosure. The number of control modules 112 may be more or less.

[0061] In this embodiment of the disclosure, for the data sampling module 11, since the first well region in the logic module 111 and the second well region in the control module 112 are completely separated, the control module 112 and the logic module 111 are completely independent, and there is no direct contact between the two.

[0062] For comparison, please refer to... Figure 2 The logic module and control module are adjacent and share the same well potential. Substrate noise generated by the control module will affect the performance of the logic module. In the embodiments of this disclosure, such as Figure 3 or Figure 4 As shown, the well regions of the control module 112 and the logic module 111 are independent of each other and are spaced apart, that is, the well potentials of the control module 112 and the logic module 111 are separated, which can reduce the substrate noise generated by the control module 112, improve the interference of the control module 112 to the logic module 111, and improve the performance of the data sampling module 11.

[0063] For example, the data sampling module 11 is at least a parallel-to-serial module P2S, and both the first well region and the second well region can be deep N-wells (DNW).

[0064] It should be noted that in memory, if all N-type switches (e.g., NMOS) are formed on a P-type doped substrate, noise can crosstalk to noise-sensitive circuit modules through the substrate. By using deep N-wells as the well regions, the deep N-wells can isolate critical modules (e.g., data sampling module 11) from noise sources, effectively forming a protective shield and significantly reducing noise interference experienced by internal devices. In other words, deep N-wells can isolate logic module 111 (or control module 112) from other noise sources, minimizing the impact of noise.

[0065] In other embodiments, the first and second well regions may also employ conventional P-wells or N-wells.

[0066] In some embodiments, the first well region is connected to a first power supply VDD, the second well region is connected to a second power supply Vbp, and the potential of the first power supply VDD is higher than the potential of the second power supply Vbp.

[0067] It should be noted that, please refer to Figure 2 The control module and the logic module share the same well potential VDD. In this embodiment, please refer to... Figure 3 or Figure 4 The well potentials of the control module 112 and the logic module 111 have been separated. The control module 112 only needs to output the control signal of the logic module 111, and the required drive power is low. Therefore, a second power supply with a slightly lower voltage, Vbp, can be selected as the well potential of the control module 112, which can save the energy consumption of the control module 12.

[0068] In some embodiments, such as Figure 5A or Figure 5B As shown, the data processing structure 10 further includes a data buffer module 12, which is used to output the first data signal or receive the second data signal; the data buffer module 12 and the data sampling module 11 are adjacent to each other, and the data sampling module 11 and the data buffer module 12 are arranged along a first direction.

[0069] It should be noted that, Figure 5A The example is illustrated using two control modules (i.e., the first control module and the second control module). Figure 5B The example shown is based on a single control module; other cases can be understood by referring to this example.

[0070] Here, the data buffer module 12 includes multiple FiFo data buffers. Here, the FiFo data buffers can buffer data in a first-in-first-out order, that is, the data received first is also output first. The FiFo data buffer is the buffer link of the system, and its functions include: (1) buffering continuous data streams to prevent data loss during data entry and storage operations; (2) centralizing data for data entry and storage, which can avoid frequent bus operations and reduce the burden on the central processing unit; (3) allowing the system to perform grouped data transmission and improve the data transmission speed.

[0071] For example, if the data sampling module 11 is used to implement parallel-to-serial conversion of signals, then the first data signal is a parallel signal and the second data signal is a serial signal; correspondingly, the data buffer module 12 is used to provide the parallel first data signal. Alternatively, if the data sampling module 11 implements serial-to-parallel conversion of signals, then the first data signal is a serial signal and the second data signal is a parallel signal; correspondingly, the data buffer module 12 is used to receive the parallel second data signal.

[0072] In some embodiments, such as Figure 3 or Figure 4 As shown, in the first direction, the projection of the control module 112 overlaps with the projection of the logic module 111.

[0073] Thus, compared to Figure 2 The structure shown in this disclosure provides a data processing structure 10 with a higher density in the second direction, which can reduce the layout area and lower production costs.

[0074] In some embodiments, such as Figure 5A Alternatively, as shown in 5B, in the first direction, the control module 112 and the logic module 111 are both located on the same side of the data buffer module 12, and the control module 112 is in contact with the data buffer module 12, with the distance between the logic module 111 and the data buffer module 12 being a first value; in the second direction, the distance between the control module 112 and the logic module 111 is a second value, such that there is a continuous region between the control module 112, the logic module 111, and the data buffer module 12; wherein, the first direction and the second direction are perpendicular.

[0075] It should be noted that the control module 112 and the data buffer module 12 can use the same sink potential or different sink potentials.

[0076] It should be noted that, Figure 5A Therefore Figure 3 Based on the detailed structure, Figure 5B Therefore Figure 4 A detailed structure based on this. The following is based on... Figure 5A Let's take an example to illustrate. Figure 5B The situations shown or other circumstances can be understood by referring to the examples.

[0077] like Figure 5A As shown, the control module 112 is divided into a first control module and a second control module. The first and second control modules are of the same size and are symmetrically located on the left and right sides of the logic module 111. In the second direction, the distance between the first control module and the logic module 111 is a second value, and the distance between the second control module and the logic module 111 is a second value. In the first direction, the top of the data buffer module 12 is directly adjacent to the bottom of the first control module and the bottom of the second control module, and the bottom of the logic module 111 is higher than the top of the data buffer module 12, thus forming a continuous region among the first control module, the second control module, the logic module 111, and the data buffer module 12.

[0078] In addition, in some other embodiments, the first control module and the second control module can also be asymmetrically arranged, that is, the "distance between the first control module and the logic module 111" and the "distance between the second control module and the logic module 111" can be unequal.

[0079] like Figure 5BAs shown, the control module 112 may also include only one control module 112. In this case, a continuous region can also be formed in the control module 112, the logic module 111 and the data buffer module 12.

[0080] It should be noted that the shape of the continuous region can be varied and can be designed according to the actual situation. However, the continuous region needs to be placed between the control module, logic module, and data buffer module to facilitate sharing of the capacitor region in subsequent applications.

[0081] In some embodiments, Figure 5A On the basis of, such as Figure 6 As shown, the data processing structure 10 also includes multiple capacitor modules; wherein, the multiple capacitor modules are all located in a continuous area between the control module 112, the logic module 111 and the data buffer module 12; wherein, the data sampling module and the data buffer module 12 share the multiple capacitor modules to implement the power supply noise reduction function.

[0082] It should be noted that, ideally, a semiconductor device has a stable power supply voltage. However, during the operation of a semiconductor device, other components may couple to the power supply, generating interference signals and noise. Capacitor modules (or decoupling capacitors) can meet the changing current requirements of the circuit while preventing mutual coupling between different components. In other words, a decoupling capacitor is a capacitor installed at the power supply terminal of a component in the circuit. This capacitor can provide a more stable power supply and reduce noise coupled to the power supply terminal, indirectly reducing the impact of this noise on other components.

[0083] Please refer to Figure 2 The logic module and the control module are not separate, and there is no continuous area between them to accommodate the capacitor module. Therefore, there is no capacitor module between them. In this embodiment, since the well regions of the control module 112 and the logic module 111 are separate, the resulting continuous area can be used to accommodate the capacitor module. This reduces the substrate noise generated by the control module 112, improves the interference of the control module 112 to the logic module 111, and enhances the performance of the data sampling module 11. At the same time, since the continuous area is formed between the control module 112, the logic module 111, and the data buffer module 12, the capacitor module in the continuous area can be shared by the control module 112, the logic module 111, and the data buffer module 12, improving the space utilization of the layout, reducing the layout area occupied by the data buffer module, and thus reducing the chip cost.

[0084] Furthermore, the specific number and distribution of capacitor modules need to be selected based on the size of the continuous area. Generally, layout design software provides some capacitor modules of fixed size, and designers can insert appropriate capacitor modules according to the size of the continuous area. Figure 6 As shown, five capacitor modules are placed in a continuous area, but this does not constitute a specific limitation.

[0085] In some embodiments, the power supply terminal of the capacitor module is connected to the power signal terminal through a metal layer (MO) and a contact structure, and the ground terminal of the capacitor module is connected to the ground signal terminal through a metal layer and a contact structure; wherein, the power signal terminal supplies power to the data sampling module 11 and the data buffer module 12.

[0086] Here, the power signal terminal serves as the global power supply for the entire device. Since the capacitor module is packaged between the power signal terminal and the ground signal terminal, it enables noise reduction and decoupling of the global power supply.

[0087] In some embodiments, each capacitor module includes a plurality of capacitor structures arranged in parallel, the first end of each capacitor structure being connected to the power supply terminal of its respective capacitor module, and the second end of each capacitor structure being connected to the ground terminal of its respective capacitor module.

[0088] In other words, each capacitor module is formed by multiple capacitor structures connected in parallel, and these capacitor structures can be columnar capacitors. For each capacitor module, the first end of all capacitor structures is connected to the power supply terminal of that module, and then the power supply terminal is connected to the power signal terminal through a metal layer (M0) and a contact structure. Simultaneously, the second end of all capacitor structures is connected to the ground terminal of that module, and then the ground terminal is connected to the ground signal terminal through a metal layer (M0) and a contact structure. As mentioned above, the power signal terminal is the global power supply for the data sampling module and the data buffer module 12. Thus, during the operation of the data sampling module 11 and the data buffer module 12, the capacitor modules in the continuous area can perform power coupling and noise reduction, improving the working performance of the data sampling module 11 and the data buffer module 12.

[0089] In other embodiments, the capacitor structure may also be a parallel-plate capacitor. Alternatively, both parallel-plate capacitors and cylindrical capacitors can be used simultaneously in the same semiconductor device to achieve power supply noise reduction.

[0090] As can be seen from the above, for the data processing structure 10, the well potentials of the logic module 111 and the control module 112 in the data sampling module 11 are separated, and there is a continuous region between the logic module 111, the control module 112 and the data buffer module 12. This continuous region is filled with multiple capacitor modules, so that the logic module 111, the control module 112 and the data buffer module 12 can share the region capacitor to achieve noise reduction coupling of the power supply, improve the space utilization of the layout, reduce the layout area occupied by the data buffer module, and thus reduce the chip cost.

[0091] In some implementations, such as Figure 7A and Figure 7B As shown, the continuous region has a first opening and a second opening in the second direction, and the first opening and the second opening are symmetrically distributed along the logic module 111.

[0092] When there are multiple data processing structures 10, the multiple data processing structures 10 are arranged sequentially along the second direction; wherein, the first opening of the continuous region in the data sampling module 11 is connected to the second opening of the continuous region in the adjacent data sampling module 11, so that the continuous regions of all data sampling modules 11 are connected.

[0093] It should be noted that, for Figure 7A The structure, Figure 8 Schematic diagrams of multiple data processing structures 10 are provided. For example... Figure 8 As shown, the continuous regions in multiple data processing structures 10 are interconnected, allowing designers to have more capacitive filling methods.

[0094] As mentioned above, Figure 9 As shown, in some embodiments, the control module 112 includes a first control module and a second control module; in a second direction, the first control module and the second control module are symmetrically located on both sides of the logic module 111.

[0095] like Figure 9 As shown, in the first direction, the length of the first control module and the length of the second control module are both third values, the length of the logic module 111 is a fourth value, and the sum of the fourth value and the first value is greater than the third value.

[0096] In this way, the highest point of the first control module / second control module in the first direction is lower than the highest point of the logic module 111, thus forming the first opening and the second opening.

[0097] In some embodiments, in a second direction, a first control module in one data processing structure 10 is adjacent to a second control module in another data processing structure 10; in a plurality of capacitor modules, one of the capacitor modules provides power supply noise reduction function for both the first control module and the adjacent second control module.

[0098] For example, such as Figure 10 As shown, some capacitor modules are set in a continuous area formed by two data processing structures. In this case, the capacitor module is used simultaneously by the second control module of the first data processing structure and the first control module of the second data processing structure.

[0099] In some embodiments, the first side of the first control module is aligned with the first side of the data buffer module 12, and the second side of the first control module is aligned with the second side of the data buffer module 12; wherein the first side and the second side are opposite to each other along the second direction.

[0100] In summary, the embodiments of this disclosure provide a data processing structure. On the one hand, this data processing structure separates the well potentials of the control module and the logic module to reduce substrate noise generated by the control module and improve the performance of the data processing structure when sampling signals. On the other hand, after the well potentials of the control module and the logic module are separated, the control module is connected to a power supply with a lower voltage, which can save the power consumption of the control module. Furthermore, after the well potentials are separated, there is a continuous region between the control module and the logic module. This continuous region is used for capacitor filling, so that the data sampling module and the surrounding data buffer module can share the region capacitance, which can improve the space utilization of the layout, reduce the overall layout area, and thus reduce the chip cost.

[0101] In another embodiment of this disclosure, see Figure 11 This illustrates a schematic diagram of a semiconductor structure 20 provided in an embodiment of this disclosure. For example... Figure 11 As shown, the semiconductor structure 20 includes a plurality of data processing structures 10, the structure of which is as described above.

[0102] It should be noted that, please refer to Figure 3 or Figure 4The data processing structure includes a data sampling module 11, which includes a logic module 111 and a control module 112. The control module 112 is located around the logic module 111. The logic module 111 includes a first well region, and the control module 112 includes a second well region. There is a gap between the first well region and the second well region, so that the control module 112 and the logic module 111 are separately configured. The control module 112 is used to generate an enable control signal. The logic module 111 is used to receive a first data signal, a clock signal, and the enable control signal. When the enable control signal is valid, the first data signal is sampled using the clock signal to output a second data signal.

[0103] In this way, since the control module 112 and the logic module 11 are completely separated, the interference problem caused by the control module 112 to the logic module 11 can be improved, the data sampling effect of the logic module 11 can be improved, and the substrate noise can be reduced.

[0104] In some embodiments, the first well region is connected to a first power source, the second well region is connected to a second power source, and the potential of the first power source is higher than the potential of the second power source.

[0105] In some embodiments, the data processing structure 10 further includes a data buffer module 12, which is used to output the first data signal or receive the second data signal; the data buffer module 12 and the data sampling module 11 are adjacent to each other, and the data sampling module 11 and the data buffer module 12 are arranged along a first direction.

[0106] In some embodiments, in a first direction, the projection of the control module 112 overlaps with the projection of the logic module 11.

[0107] In some embodiments, in the first direction, the control module 112 and the logic module 11 are both located on the same side of the data buffer module 12, and the control module 112 is in contact with the data buffer module 12, with the distance between the logic module 11 and the data buffer module 12 being a first value; in the second direction, the distance between the control module 112 and the logic module 11 is a second value, such that there is a continuous region between the control module 112, the logic module 11, and the data buffer module 12; wherein, the second direction is perpendicular to the first direction.

[0108] In some embodiments, the data processing structure 10 further includes a plurality of capacitor modules; wherein the plurality of capacitor modules are located in a continuous region between the control module 112, the logic module 11 and the data buffer module 12; wherein the data sampling module 11 and the data buffer module 12 share the plurality of capacitor modules to implement power supply noise reduction function.

[0109] In some embodiments, the power supply terminal of the capacitor module is connected to the power signal terminal through a metal layer and a contact structure, and the ground terminal of the capacitor module is connected to the ground signal terminal through a metal layer and a contact structure; wherein, the power signal terminal supplies power to the data sampling module 11 and the data buffer module 12.

[0110] In some embodiments, each capacitor module includes a plurality of capacitor structures arranged in parallel, the first end of each capacitor structure being connected to the power supply terminal of its respective capacitor module, and the second end of each capacitor structure being connected to the ground terminal of its respective capacitor module.

[0111] In some embodiments, the capacitor structure is a columnar capacitor structure.

[0112] In some embodiments, the continuous region has a first opening and a second opening in the second direction, and the first opening and the second opening are symmetrically distributed along the logic module 11; when there are multiple data processing structures 10, the multiple data processing structures 10 are arranged sequentially along the second direction; wherein, the first opening of the continuous region in the data sampling module 11 is connected to the second opening of the continuous region in the adjacent data sampling module 11, so that the continuous regions of all data sampling modules 11 are connected.

[0113] In some embodiments, the control module 112 includes a first control module and a second control module; in a second direction, the first control module and the second control module are symmetrically located on both sides of the logic module 11; in a first direction, the length of the first control module and the length of the second control module are both a third value, the length of the logic module 11 is a fourth value, and the sum of the fourth value and the first value is greater than the third value.

[0114] In some embodiments, in a second direction, a first control module in one data processing structure 10 is adjacent to a second control module in another data processing structure 10; in a plurality of capacitor modules, one of the capacitor modules provides power supply noise reduction function for both the first control module and the adjacent second control module.

[0115] In some embodiments, the data sampling module 11 is at least a parallel-to-serial conversion module, and the first well region and the second well region are deep N-wells.

[0116] This disclosure provides a semiconductor structure that implements signal sampling processing through multiple data processing structures. On one hand, the data processing structures separate the well potentials of the control module and the logic module to reduce substrate noise generated by the control module and improve the noise reduction of the data processing structure during signal sampling. On the other hand, after the well potentials of the control module and the logic module are separated, the control module is connected to a power supply with a lower voltage, which can save the power consumption of the control module. Furthermore, after the well potentials are separated, there is a continuous region between the control module and the logic module. This continuous region is used for capacitor filling, so that the data sampling module and the surrounding data buffer module can share the region capacitance, which can improve the space utilization of the layout, reduce the overall layout area, and thus reduce the chip cost.

[0117] In yet another embodiment of this disclosure, see [link to relevant documentation]. Figure 12 This illustrates a schematic diagram of the structure of a memory 30 provided in an embodiment of this disclosure. For example... Figure 12 As shown, the memory 30 includes the aforementioned semiconductor structure 20.

[0118] This disclosure provides a memory in which the semiconductor structure implements signal sampling processing through multiple data processing structures as described above. On the one hand, the data processing structure separates the well potentials of the control module and the logic module to reduce substrate noise generated by the control module and improve the noise reduction of the data processing structure during signal sampling. On the other hand, after the well potentials of the control module and the logic module are separated, the control module is connected to a power supply with a lower voltage, which can save the power consumption of the control module. Furthermore, after the well potentials are separated, there is a continuous region between the control module and the logic module. This continuous region is used for capacitor filling, so that the data sampling module and the surrounding data buffer module can share the region capacitance, which can improve the space utilization of the layout, reduce the overall layout area, and thus reduce the chip cost.

[0119] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure.

[0120] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0121] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0122] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0123] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0124] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0125] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A data processing structure, characterized in that, The data processing structure includes a data sampling module, which further includes a logic module and a control module. The control module is located around the logic module. The logic module includes a first well region, and the control module includes a second well region. A gap exists between the first well region and the second well region, allowing the control module and the logic module to be separately configured. The control module is used to generate an enable control signal; The logic module is used to receive a first data signal, a clock signal, and an enable control signal; when the enable control signal is valid, it uses the clock signal to sample and process the first data signal and outputs a second data signal.

2. The data processing structure according to claim 1, characterized in that, The first well region is connected to a first power source, the second well region is connected to a second power source, and the potential of the first power source is higher than the potential of the second power source.

3. The data processing structure according to any one of claims 1-2, characterized in that, The data processing structure further includes a data buffer module, which is used to output the first data signal or receive the second data signal; The data buffer module and the data sampling module are adjacent to each other, and the data sampling module and the data buffer module are arranged along a first direction.

4. The data processing structure according to claim 3, characterized in that, In the first direction, the projection of the control module overlaps with the projection of the logic module.

5. The data processing structure according to claim 4, characterized in that, In the first direction, the control module and the logic module are both located on the same side of the data buffer module, and the control module is in contact with the data buffer module. The distance between the logic module and the data buffer module is a first value. In the second direction, the distance between the control module and the logic module is a second value, such that there is a continuous region between the control module, the logic module, and the data buffer module. The second direction is perpendicular to the first direction.

6. The data processing structure according to claim 5, characterized in that, The data processing structure also includes multiple capacitor modules; wherein... Multiple capacitor modules are located in a continuous area between the control module, the logic module, and the data buffer module; wherein the data sampling module and the data buffer module share multiple capacitor modules to implement power supply noise reduction function.

7. The data processing structure according to claim 6, characterized in that, The power supply terminal of the capacitor module is connected to the power signal terminal through a metal layer and a contact structure, and the ground terminal of the capacitor module is connected to the ground signal terminal through a metal layer and a contact structure. The power signal terminal supplies power to the data sampling module and the data buffer module.

8. The data processing structure according to claim 6, characterized in that, Each capacitor module includes multiple capacitor structures connected in parallel. The first end of each capacitor structure is connected to the power supply terminal of its respective capacitor module, and the second end of each capacitor structure is connected to the ground terminal of its respective capacitor module.

9. The data processing structure according to claim 8, characterized in that, The capacitor structure is a columnar capacitor structure.

10. The data processing structure according to claim 6, characterized in that, The continuous region has a first opening and a second opening in the second direction, and the first opening and the second opening are symmetrically distributed along the logic module; When there are multiple data processing structures, the multiple data processing structures are arranged sequentially along the second direction; wherein, the first opening of the continuous region in the data sampling module is connected to the second opening of the continuous region in the adjacent data sampling module, so that the continuous regions of all data sampling modules are connected.

11. The data processing structure according to claim 10, characterized in that, The control module includes a first control module and a second control module; in a second direction, the first control module and the second control module are symmetrically located on both sides of the logic module. In the first direction, the lengths of the first control module and the second control module are both third values, the length of the logic module is a fourth value, and the sum of the fourth value and the first value is greater than the third value.

12. The data processing structure according to claim 10, characterized in that, In the second direction, the first control module in the data processing structure is adjacent to the second control module in another data processing structure; among the plurality of capacitor modules, one of the capacitor modules provides power supply noise reduction function for the first control module and the adjacent second control module.

13. The data processing structure according to claim 2, characterized in that, The data sampling module is at least a parallel-to-serial conversion module, and the first well region and the second well region are deep N-wells.

14. A semiconductor structure, characterized in that, The semiconductor structure includes a plurality of data processing structures as described in any one of claims 1-13.

15. A memory, characterized in that, The memory includes the semiconductor structure as described in claim 14.

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