A credit backpressure-based network-on-chip verification method and device

Abstract

This invention provides an on-chip network verification method and device based on credit backpressure, belonging to the field of chip verification technology. This invention avoids the setup time violation risk of traditional rising-edge sampling by synchronously sampling the credit signal and the valid data signal on the falling edge of the clock, and can stably capture the signal state within the same clock cycle, solving the sampling deviation problem in scenarios where data transmission and credit return occur simultaneously. By combining the states of the two signals to determine the counter update method, it fully covers all signal combination scenarios, ensuring that the credit update logic completely matches the actual hardware behavior. Through credit overflow and underflow boundary checks before the update, it intercepts the risk of counting anomalies in advance. Simultaneously, it configures an independent credit counter for each virtual channel to avoid inter-channel interference, and performs flow control verification based on accurate credit counters, solving the problems of unreliable verification results and low scenario coverage caused by inaccurate counting.

Description

Technical Field

[0001] This invention relates to the field of chip verification technology, and in particular to an on-chip network verification method and device based on credit backpressure. Background Technology

[0002] Network on chip (NoC), as the core interconnect architecture between multi-core processors and system on chip (SoC) chips, widely adopts a credit-based backpressure flow control mechanism to avoid data loss and buffer overflow. Under this mechanism, the sending end maintains a credit counter to reflect the available space in the receiving end's buffer. Data can only be sent when the credit value is greater than zero. After consuming data, the receiving end returns the credit value to the sending end to update the counter.

[0003] To improve link utilization and avoid deadlock, on-chip networks (BTC) commonly introduce virtual channel mechanisms. During BTC verification, the update accuracy of the credit counter directly determines the accuracy and reliability of flow control verification.

[0004] In existing on-chip network verification methods, credit signals and valid data signals are usually sampled synchronously on the rising edge of the clock. This sampling method is prone to setup time violations and cannot accurately identify the combined state of data transmission and credit return occurring simultaneously within the same clock cycle. This leads to inconsistencies between the credit counter update logic and the actual hardware behavior, resulting in credit counting errors.

[0005] Insufficient accuracy in credit counting errors makes it impossible to accurately reproduce the credit backpressure timing and state transitions during actual on-chip network operation. This results in inaccurate on-chip network flow control verification, low verification scenario coverage, and ultimately unreliable verification results, making it difficult to effectively detect flow control defects in hardware design. Summary of the Invention

[0006] This invention provides an on-chip network verification method and device based on credit backpressure, which solves the problem of insufficient credit counting accuracy in the on-chip network verification process.

[0007] In a first aspect, the present invention provides an on-chip network verification method based on credit backpressure, applied to a verification unit, the verification unit comprising multiple virtual channels, each virtual channel corresponding to a credit counter, the method comprising: synchronously sampling a credit signal and a data valid signal on the falling edge of a clock for any target virtual channel among the multiple virtual channels; performing a combined state judgment based on the credit signal and the data valid signal to determine the update method of the credit counter corresponding to the target virtual channel; performing credit overflow and underflow boundary checks on the update method to obtain a check result; updating the credit counter corresponding to the target virtual channel based on the check result and the update method; and performing on-chip network flow control verification based on the updated credit counter.

[0008] Secondly, embodiments of the present invention provide an on-chip network verification device based on credit backpressure. The verification device includes a verification unit, which includes multiple virtual channels, each virtual channel corresponding to a credit counter. The verification device stores a computer program, and the verification device calls and runs the computer program to execute the method described in the first aspect above.

[0009] Thirdly, embodiments of the present invention provide a computer-readable storage medium storing a computer program, characterized in that, when the computer program is executed by a processor, it implements the steps of the method as described in the first aspect and any possible implementation thereof.

[0010] This invention provides an on-chip network verification method and device based on credit backpressure. By synchronously sampling the credit signal and the valid data signal on the falling edge of the clock, this invention avoids the setup time violation risk inherent in traditional rising edge sampling, and can stably capture the signal state within the same clock cycle, solving the sampling deviation problem in scenarios where data transmission and credit return occur simultaneously. By combining the states of the two signals to determine the counter update method, it fully covers all signal combination scenarios, ensuring that the credit update logic perfectly matches the actual hardware behavior. Through credit overflow and underflow boundary checks before the update, it proactively intercepts the risk of counting anomalies. Simultaneously, it configures an independent credit counter for each virtual channel to avoid inter-channel interference, and performs flow control verification based on accurate credit counters, solving the problems of unreliable verification results and low scenario coverage caused by inaccurate counting. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of the structure of a reusable on-chip network verification unit based on UVM provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of an on-chip network verification method based on credit backpressure provided in an embodiment of the present invention; Figure 3 This is a flowchart illustrating a precise credit management algorithm based on falling edge sampling provided in an embodiment of the present invention; Figure 4 This is a flowchart illustrating an intelligent arbitration mechanism supporting multiple virtual channels provided in an embodiment of the present invention; Figure 5 This is a flowchart illustrating a buffer backpressure mechanism based on a global transaction pool provided in an embodiment of the present invention; Figure 6 This is a schematic flowchart of a credit return mechanism that simulates the behavior of a real receiver, provided by an embodiment of the present invention. Figure 7 This is a flowchart illustrating an automatic response mechanism based on a global transaction pool provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of an extensible transaction type hierarchy provided by an embodiment of the present invention; Figure 9 This is a flowchart illustrating a multi-level integrity check mechanism provided in an embodiment of the present invention. Detailed Implementation

[0013] To make the objectives, technical solutions, and advantages of the present invention clearer, the following description will be provided in conjunction with the accompanying drawings and specific embodiments.

[0014] As described in the background section, Network on-Chip (NoC) is a key interconnect architecture in modern multi-core processors and SoC chips, used to connect multiple processing cores, memory units, and peripherals. NoC employs packet switching technology, encapsulating data into packets or even smaller flow control units (flits) for transmission. To prevent data loss and buffer overflows, NoC commonly uses a credit-based flow control mechanism. That is: The sending end maintains a credit counter, which indicates the available buffer space at the receiving end; After consuming the data, the receiving end returns credit to the sending end. The sender can only send data when the credit score is greater than 0.

[0015] Meanwhile, to improve link utilization and avoid deadlock, NoC introduces a Virtual Channel (VC) mechanism: physical links reuse multiple virtual channels; each VC has an independent buffer and flow control; different priorities or types of data streams use different VCs.

[0016] Verification of NoC credit backpressure mechanisms faces the following challenges: High timing accuracy requirements: The sampling timing of credit signals and data signals must precisely match hardware behavior. High scenario complexity: It needs to cover complex scenarios such as multi-VC competition, credit depletion, and backpressure propagation. Verification component reusability requirements: Different NoC architectures have different credit mechanisms, requiring highly parameterized verification components. Automation requirements: Large-scale NoC systems contain hundreds of communication channels, making manually writing verification sequences inefficient.

[0017] Currently, the following solutions exist for NoC credit management: Option A: A simple credit verification component based on the Universal Verification Methodology (UVM). The driver and monitor are built using the UVM framework; basic credit sending and receiving functions are implemented; the credit counter is maintained internally by the driver; a single virtual channel is supported; and credit signals and valid data signals are sampled simultaneously on the rising edge of the clock.

[0018] Option B: Dedicated NoC verification IP. Commercial verification IP, for specific NoC protocols (such as AXI-Stream, TileLink); fixed credit management strategy; limited parameterization capabilities; high licensing fees; source code is not visible and difficult to customize.

[0019] Option C: Manually written verification environment. Custom-developed for a specific project; credit management logic is scattered across multiple modules; lacks a unified interface and configuration mechanism; difficult to port to other projects; requires manually writing response sequences for each communication scenario.

[0020] The above solution has the following drawbacks.

[0021] Disadvantage 1: Insufficient credit management accuracy. Existing solutions typically sample both the credit signal and the data validity signal simultaneously on the rising edge of the clock, failing to properly handle situations where data is sent and credits are returned concurrently. For example, when the sender both sends data (consuming 1 credit) and receives a credit return (increasing 1 credit) in the same clock cycle, theoretically the total credit count should remain unchanged. However, due to sampling timing issues, only one event may be detected, leading to an error in the credit counter. This error can result in credit overflow (exceeding the maximum value) or underflow (less than 0), potentially causing data loss or deadlock.

[0022] Disadvantage 2: Incomplete virtual channel support. Most solutions only support a single virtual channel, making it impossible to verify multi-VC scenarios; even if multiple VCs are supported, independent credit management is lacking, with all VCs sharing a single credit pool; independent sending queues are missing, making it impossible to isolate data streams from different VCs; and an arbitration mechanism is lacking when multiple VCs are ready simultaneously, making it impossible to verify VC contention scenarios. Therefore, it is impossible to verify key scenarios in real-world NoCs such as VC contention, priority scheduling, and deadlock avoidance, resulting in low verification coverage.

[0023] To address the aforementioned shortcomings, this invention provides an on-chip network verification method based on credit backpressure. It offers several advantages: 1. Precise credit management mechanism: By improving sampling timing, it correctly handles various combinations of credit and data transmission, ensuring 100% accuracy of the credit counter. 2. Full support for virtual channels: It provides an independent credit counter, sending queue, and arbitration mechanism for each VC, supporting 1-N virtual channels. 3. High parameterization and reusability: It supports flexible configuration of key parameters such as transmission width, number of VCs, and maximum credit value, allowing a single component to adapt to multiple NoC protocols. 4. Modeling realistic verification scenarios: It supports configurable credit return latency and data sending latency, simulating real NoC behavior and improving verification coverage. 5. Increased verification automation: It provides an automatic response mechanism and a global transaction pool, reducing manual coding workload by more than 60%. 6. Ensuring verification integrity: It provides a multi-layered integrity check mechanism to detect problems early.

[0024] like Figure 1 As shown, this invention provides a reusable on-chip network verification unit based on UVM. The verification unit includes a proxy module, a driver, a monitor, a sequencer, an interface, and a global transaction pool.

[0025] The Verification Agent module is the top-level container, containing a driver, monitor, and sequencer. The driver is responsible for credit management and data transmission / reception. The monitor samples bus signals and collects coverage data. The sequencer is responsible for transaction scheduling. The Verification Interface is a parameterized verification interface that connects the verification environment and the Device Under Test (DUT). The Global Transaction Pool (GTP) stores transactions across agents and supports automatic responses.

[0026] based on Figure 1 The verification unit shown is as follows: Figure 2As shown, this invention provides an on-chip network verification method based on credit backpressure. The verification unit includes multiple virtual channels, each corresponding to a credit counter. The method includes steps S101-S104.

[0027] S101. For any target virtual channel among multiple virtual channels, synchronously sample the credit signal and data valid signal on the falling edge of the clock.

[0028] S102. Based on the credit signal and the valid data signal, perform a combined state judgment to determine the update method of the credit counter corresponding to the target virtual channel.

[0029] As one possible implementation, step S102 can be specifically implemented as steps S1021-S1024.

[0030] S1021. If the credit signal is valid and the data valid signal is invalid, then the update method is determined to be the credit counter incremented by 1.

[0031] S1022. If the credit signal is invalid and the data valid signal is valid, then the update method is determined to be decrementing the credit counter by 1.

[0032] S1023. If the credit signal is valid and the data valid signal is valid, then the update method is determined to be that the credit counter remains unchanged.

[0033] S1024. If the credit signal is invalid and the data valid signal is invalid, then the update method is determined to be that the credit counter remains unchanged.

[0034] This invention provides a precise credit management algorithm based on falling edge sampling. Algorithm principle: Sampling timing: Sampling the credit signal (credit) and the data validity signal (trans_valid) at the falling edge of the clock. Four case handling: Updating the credit counter according to four cases based on the combination of the two signals. Boundary checking: Checking boundary conditions before each update to prevent overflow and underflow. The credit update rule table is shown in Table 1.

[0035] Table 1

[0036] like Figure 3 The flowchart shown is a process for the precise credit management algorithm based on falling edge sampling provided by the present invention.

[0037] This invention employs falling-edge sampling to avoid setup time violations and ensure stable sampling values. It fully covers four scenarios, handling all possible signal combinations, especially simultaneous transmission and response. Boundary checks prevent credit overflow (exceeding max_credit) and underflow (less than 0). Independent VC management ensures each VC has its own independent credit management task without interference. Existing solutions using rising-edge sampling have a credit error rate of 5-10%. This invention, using falling-edge sampling, achieves a credit error rate of 0%.

[0038] For example, embodiments of the present invention can sample the credit signal and the data valid signal (trans_valid) on the falling edge of the clock; and update the credit counter in four cases based on the combination of the two signals.

[0039] Case 1: When credit=1 and trans_valid=0, the credit counter is incremented by 1.

[0040] Case 2: When credit=0 and trans_valid=1, the credit counter is decremented by 1.

[0041] Case 3: When credit=1 and trans_valid=1, the credit counter remains unchanged.

[0042] Case 4: When credit=0 and trans_valid=0, the credit counter remains unchanged.

[0043] Before each update, check the boundary conditions. If the boundary check fails, report the error and specify the virtual channel number.

[0044] S103. Perform credit overflow and underflow boundary checks on the update method to obtain the check results.

[0045] S104. Based on the inspection results and the update method, update the credit counter corresponding to the target virtual channel.

[0046] S105. Based on the updated credit counter, perform on-chip network flow control verification.

[0047] This invention provides an on-chip network verification method based on credit backpressure. By synchronously sampling the credit signal and the valid data signal on the falling edge of the clock, it avoids the setup time violation risk of traditional rising edge sampling, and can stably capture the signal state within the same clock cycle, solving the sampling deviation problem in scenarios where data transmission and credit return occur simultaneously. By combining the states of the two signals to determine the counter update method, it fully covers all signal combination scenarios, ensuring that the credit update logic and the actual hardware behavior are completely matched. By checking the credit overflow and underflow boundaries before the update, it intercepts the risk of counting anomalies in advance. At the same time, it configures an independent credit counter for each virtual channel to avoid interference between channels. Based on the accurate credit counter, it performs flow control verification, solving the problems of unreliable verification results and low scenario coverage caused by inaccurate counting.

[0048] Optionally, the on-chip network verification method based on credit backpressure provided in this embodiment of the invention further includes steps S201-S204 before step S101.

[0049] S201. Obtain the configuration parameters of the verification unit, including the data transmission width, the total number of virtual channels, the maximum credit value per channel, and the configuration quantities of the global transaction pool.

[0050] S202. Based on the total number of virtual channels, set up multiple virtual channels and assign an independent credit counter to each virtual channel.

[0051] S203. Instantiate the parameterized verification interface based on the data transmission width and the total number of virtual channels.

[0052] As exemplified in Table 2, this invention defines a parameterized verification interface that supports flexible configuration. The parameterized design supports different data widths and the number of VCs without requiring code modification. Each VC is provided with an independent credit signal and a credit_cnt counter, achieving complete isolation. Rising-edge driving and falling-edge sampling are distinguished to ensure timing correctness.

[0053] Table 2

[0054] S204. Based on the configuration parameters, automatically adapt to different on-chip network protocols and hardware architectures to realize the initial configuration and reuse settings of the verification unit.

[0055] For example, the interface definition in this invention includes a transmission width parameter (TRANS_WIDTH) and a virtual channel number parameter (CRDT_CHENNEL). Credit signals are defined as an array credit[CRDT_CHENNEL-1:0], with one signal per VC. The credit counter is defined as a two-dimensional array credit_cnt[CRDT_CHENNEL-1:0][31:0]. Through parameterized instantiation, a single component can adapt to different NoC protocols and configurations.

[0056] Thus, this invention defines the parameterized pre-configuration process of the verification unit, which can flexibly configure core indicators such as data bit width, number of virtual channels, and global transaction pool parameters, realize automatic instantiation and cross-architecture adaptation of the verification interface, greatly improve the reusability of the verification environment, and reduce the verification setup cost of different on-chip network projects.

[0057] Optionally, the on-chip network verification method based on credit backpressure provided in this embodiment of the invention further includes steps S301-S304.

[0058] S301. Configure an independent, mutually isolated data transmission queue for each virtual channel.

[0059] S302. For each virtual channel, independently perform credit signal sampling, credit counter update and boundary check operations.

[0060] S303. Independently monitor the credit margin, queue depth, and transmission readiness status of each virtual channel to obtain the independent monitoring status of each virtual channel.

[0061] S304. Based on the independent monitoring status of each virtual channel, perform independent flow control on each virtual channel to achieve complete isolation between virtual channels.

[0062] For example, embodiments of the present invention can maintain an independent credit counter array credit_cnt[VcNum] for each virtual channel; maintain an independent sending queue drv_que[VcNum] for each virtual channel; initiate an independent credit management task for each virtual channel without interference; and employ a random arbitration algorithm when multiple virtual channels are ready simultaneously. This achieves independent credit management and arbitration mechanisms for multiple virtual channels, fully supports VC-level flow control and fair scheduling, supports 1 to N virtual channels, and maintains 100% isolation between VCs.

[0063] Thus, the present invention defines an independent isolation management mechanism for multiple virtual channels, configuring an independent transmission queue for each virtual channel, and independently executing credit management, status monitoring and flow control, achieving complete isolation between channels, avoiding signal interference and counting crosstalk between multiple channels, and further ensuring the accuracy of credit counting and control independence of a single channel.

[0064] Optionally, the on-chip network verification method based on credit backpressure provided in this embodiment of the invention further includes steps S401-S404.

[0065] S401. Traverse each virtual channel and select the currently ready virtual channels with credit balance greater than 0 and sending queue not empty.

[0066] S402. Determine if the number of currently ready virtual channels is greater than 1.

[0067] S403. If the number of currently ready virtual channels is 1, then select the currently ready virtual channel as the current sending channel.

[0068] S404. If the number of currently ready virtual channels is greater than 1, a random arbitration strategy is used to select the current transmission channel from the currently ready virtual channels.

[0069] For example, step S404 can be specifically implemented as steps S4041-S4044.

[0070] S4041, for the currently ready virtual channel, allocate a continuous and non-overlapping arbitration sequence number range according to preset rules.

[0071] For example, the preset rule is to assign a continuous arbitration sequence number interval of equal width to each ready virtual channel in ascending order of the ready virtual channel number; for example, for two ready virtual channels, the intervals [0,49] and [50,99] are assigned respectively, and the total range of the interval is consistent with the range of random number values.

[0072] For example, step S4041 can be implemented as follows: Step 1: Obtain the IDs of all currently ready virtual channels, sort them in ascending order, and obtain the ready channel list VC_ready_list={VC0,VC1,VC2,...,VCn}, where n is the current number of ready channels – 1.

[0073] Step 2: Assign each ready virtual channel a continuous arbitration sequence number interval of equal width. The total width of the interval is fixed at 100, and the width of a single channel interval is 100 / (n+1) and rounded down. For example, when there are 2 ready channels, VC0 is assigned the interval [0,49] and VC1 is assigned the interval [50,99]. When there are 4 ready channels, each channel is assigned a continuous interval of 25 width.

[0074] Step 3: Generate uniformly distributed random numbers in the range of 0-99 using the SystemVerilog system function $urandom_range(), match the interval to which the random numbers belong, and determine the corresponding virtual channel as the current transmission channel.

[0075] Step 4: Record this transmission event and update the historical transmission statistics of each channel to prevent a single channel from being starved for a long time and to ensure scheduling fairness.

[0076] S4042. Generate uniformly distributed random numbers whose value range covers the entire arbitration sequence number interval.

[0077] S4043. Match the target interval to which the uniformly distributed random number belongs, and determine the ready virtual channel corresponding to the target interval as the current sending channel.

[0078] S4044. Record the transmission events of the selected virtual channel and update the historical transmission statistics of each ready virtual channel.

[0079] S405. Perform data transmission and credit consumption operations based on the current transmission channel to complete on-chip network transmission verification.

[0080] For example, such as Figure 4 As shown, this invention provides an intelligent arbitration mechanism supporting multiple virtual channels. The conditions for a VC to send data are: Condition 1: The VC's sending queue is not empty (data is waiting to be sent); Condition 2: The VC's credit counter > 0 (the receiver has space) or credit checking is disabled. Arbitration strategy: Single VC ready: Directly select the VC without arbitration; Multiple VC ready: Randomly select from ready VCs to achieve fair scheduling; Support for expansion: Priority scheduling can be supported by modifying the arbitration logic.

[0081] Thus, this invention defines an arbitration scheduling mechanism for multiple virtual channels, which can accurately select ready channels with sufficient credit and non-empty queues. When multiple channels are ready at the same time, random arbitration is used to select the sending channel, fully covering the multi-virtual channel competition scenario, improving the verification scenario coverage, and ensuring the consistency between verification behavior and the actual hardware scheduling logic.

[0082] Optionally, the on-chip network verification method based on credit backpressure provided in this embodiment of the invention further includes steps S501-S505.

[0083] S501: Real-time monitoring of the queue depth of the global transaction pool and the queue depth of each virtual channel.

[0084] The global transaction pool is pre-configured, and the configuration parameters of the global transaction pool include maximum depth, maximum depth of a single virtual channel queue, hysteresis trigger threshold, and hysteresis release threshold. S502. If the queue depth of the global transaction pool is detected to be greater than or equal to the first hysteresis trigger threshold, then the global backpressure blocking mechanism is started.

[0085] For example, when the global backpressure blocking mechanism is activated, the sequencers of all sending agents in the verification environment are blocked, and the issuance of new verification transactions is stopped.

[0086] S503. If the queue depth of any virtual channel is detected to be greater than or equal to the second hysteresis trigger threshold, the VC-level backpressure blocking mechanism corresponding to that virtual channel is activated.

[0087] For example, in an embodiment of the present invention, when the VC-level backpressure blocking mechanism is activated, only the sending permission of the corresponding virtual channel is blocked, while the other virtual channels that have not triggered backpressure remain in normal sending state.

[0088] For example, the hysteresis trigger threshold corresponding to the global transaction pool is the first hysteresis trigger threshold, and the hysteresis trigger threshold corresponding to the single virtual channel queue is the second hysteresis trigger threshold.

[0089] S504. If the depth of the queue that triggers backpressure is less than the hysteresis release threshold, the backpressure blocking mechanism at the corresponding level of the queue will be automatically released.

[0090] S505. During the activation of the backpressure blocking mechanism, the transaction cycle dependency relationship of the entire link is monitored in real time. If the duration of the backpressure blocking mechanism is greater than the preset deadlock detection timeout threshold, a deadlock alarm is triggered and diagnostic information is output.

[0091] For example, such as Figure 5 As shown, this invention provides a buffer backpressure mechanism based on a global transaction pool for cross-agent flow control and deadlock avoidance. Mechanism principle: The global transaction pool acts as a shared buffer in the verification environment, storing transactions sent by the sending agent but not yet processed by the receiving agent. When the transaction pool reaches its capacity limit, the backpressure mechanism is triggered, preventing the sending agent from sending new transactions, thereby achieving end-to-end flow control. The backpressure triggering conditions are shown in Table 3.

[0092] Table 3

[0093] The backpressure mechanism includes: a tiered system: global level (controlling the total capacity of the entire transaction pool); VC level (controlling the queue depth of each virtual channel); and Agent level (controlling the sending rate of a single Agent). Hysteresis features include: backpressure trigger threshold: 80%-100% capacity; backpressure release threshold: 50%-75% capacity, preventing jitter caused by frequent triggering / release. Priority support allows high-priority transactions to overcome some backpressure limits; low-priority transactions are preferentially blocked during backpressure, preventing low-priority traffic from starving high-priority traffic. Deadlock detection includes: detecting circular dependencies (A waiting for B, B waiting for C, C waiting for A); a timeout mechanism (alerting when backpressure duration exceeds a threshold); and providing deadlock diagnostic information (displaying blocked links and waiting relationships).

[0094] The configuration parameters are shown in Table 4.

[0095] Table 4

[0096] This invention employs cross-Agent backpressure: unlike traditional point-to-point credit backpressure, this invention achieves global traffic control across multiple agents. Hierarchical control: a three-tiered backpressure mechanism (global, VC, Agent) allows for fine-grained control of traffic at different granularities. Hysteresis design: avoids backpressure jitter, improving system stability. Deadlock prevention: proactively detects and prevents deadlocks in the verification environment. Observability: provides detailed backpressure status and statistical information, facilitating debugging and performance optimization.

[0097] Thus, this invention defines a hierarchical backpressure control and deadlock detection mechanism. It sets hysteresis thresholds to trigger hierarchical backpressure for the global transaction pool and single virtual channels respectively, avoiding frequent backpressure jitter. At the same time, deadlock detection is achieved through circular dependency monitoring and timeout alarms, which can cover extreme traffic scenarios and greatly improve the scenario coverage and fault tolerance of the verification.

[0098] Optionally, the on-chip network verification method based on credit backpressure provided in this embodiment of the invention further includes steps S601-S607.

[0099] S601. Based on the pre-configured global transaction pool, establish a transaction interaction channel between the sending agent and the receiving agent.

[0100] S602. Write the verification transaction generated by the sending agent into the global transaction pool, and synchronously update the queue depth statistics of the global transaction pool.

[0101] S603. Control the receiving agent to automatically read unprocessed verification transactions from the global transaction pool, generate corresponding response transactions based on the type of verification transactions, and complete the return of response transactions.

[0102] S604. During the entire life cycle of the verification transaction, record in real time the credit count data of each virtual channel, the status information of the data sending queue, and the transaction forwarding records of the entire link.

[0103] S605. After the verification process ends, based on the recorded credit count data, traverse each virtual channel and check whether the credit counter corresponding to each virtual channel has been restored to the initial maximum value.

[0104] S606. Based on the recorded status information of the data sending queue and the transaction forwarding records of the entire link, check whether the data sending queue of each virtual channel is empty and whether each verification transaction and the corresponding response transaction form a closed loop.

[0105] S607. If there is a situation where the credit counter has not been restored to the initial maximum value, the data sending queue is not empty, or the verification transaction and the corresponding response transaction do not form a closed loop, it is determined that there is an abnormal state and an error message is output.

[0106] In some embodiments, the error message includes the virtual channel number with an abnormal state and the type of fault.

[0107] As Figure 6 shown, the embodiment of the present invention provides a credit return mechanism that simulates the behavior of a real receiver. Credit return conditions: non-reset state; credit未满 (credit_cnt < max_credit); queue non-empty (there is data to receive). Delay control: off mode: delay = 0, immediately return credit; random mode: use the random delay in the transaction (such as 0 - 63 cycles); fixed mode: use the configured fixed delay (such as 5 cycles).

[0108] As Figure 7 shown, the present invention provides an automatic response mechanism based on a global transaction pool, which greatly reduces manual coding. As shown in Table 5, the present invention provides a type definition table for a proxy module.

[0109] Table 5

[0110] As Figure 8 shown, the present invention provides an extensible transaction type hierarchy. Among them, the delay distribution constraints are shown in Table 6.

[0111] Table 6

[0112] Exemplarily, as Figure 9As shown, this invention provides a multi-layered integrity check mechanism. The checks include: credit counter check: whether the credit counter of each VC has been restored to its initial value (max_credit); sending queue check: whether the sending queue of each VC is empty; and runtime boundary check: credit overflow / underflow detection.

[0113] For example, this invention sets the maximum depth of the global transaction pool (max_pool_depth) and the maximum depth of a single VC queue (max_vc_depth). When the global transaction pool depth reaches the backpressure trigger threshold (e.g., 80% capacity), the sending sequencer is blocked; when the depth of a single VC queue reaches the VC-level backpressure threshold, the sending of that VC is blocked. This invention employs a hysteresis mechanism. The backpressure trigger threshold is higher than the backpressure release threshold; this avoids jitter caused by frequent triggering / release. This invention provides a deadlock detection mechanism: detecting circular dependencies, a timeout alarm mechanism, and providing deadlock diagnostic information. Priority differentiation is supported: high-priority transactions can break through some backpressure limits, while low-priority transactions are blocked first.

[0114] This invention offers significant advantages over existing technologies in terms of credit management accuracy. Existing technologies (Solution A) typically sample the credit signal and data validity signal at the rising edge of the clock. This approach carries the risk of setup time violations, especially when data is sent and credit is returned simultaneously, easily leading to incorrect credit counting. In contrast, this invention employs a clock falling edge sampling strategy, effectively avoiding setup time violations and ensuring stable signal values ​​are sampled.

[0115] When dealing with scenarios where credits are sent and returned simultaneously, existing technologies often only detect one of the events, leading to inaccuracies in the credit counter. This invention, through falling-edge sampling and an algorithm design that fully covers four scenarios, can correctly handle all signal combinations, including credit-only returns, data-only transmission, simultaneous transmission and return, and no operation, achieving 100% accuracy.

[0116] Furthermore, this invention introduces a robust boundary check mechanism. Before each credit counter update, it checks for overflow (exceeding max_credit) or underflow (below 0). If an anomaly is detected, it immediately reports the error and specifies the virtual channel number. Existing technologies typically lack this protection mechanism. Real-world testing data shows that in 100,000 random tests, existing technologies exhibited 523 credit counting errors (an error rate of approximately 5-10%), while this invention had 0 errors, resulting in a 100% improvement in credit management accuracy.

[0117] This invention represents a significant leap forward in virtual channel support. Existing technologies (Solution A) typically support only a single virtual channel and employ fixed configurations, failing to meet the verification requirements of multi-VC scenarios. Even when some solutions claim to support multiple VCs, they often involve all VCs sharing a single credit pool, lacking true independence and unable to verify the competition and isolation characteristics between VCs.

[0118] This invention, through parametric design, supports flexible configuration of 1 to N virtual channels, increasing flexibility N times. More importantly, this invention provides each VC with a completely independent credit counter and sending queue, achieving 100% isolation. Each VC's credit management task runs independently without interference, realistically simulating the behavior of VCs in hardware.

[0119] In multi-VC arbitration, existing technologies typically do not support or only provide simple polling mechanisms. This invention implements an intelligent arbitration algorithm: when only one VC is ready, that VC is directly selected; when multiple VCs are ready simultaneously, random fair arbitration is employed to ensure that each VC has an equal opportunity to send. This design not only covers VC competition scenarios but also reserves an interface for subsequent expansion of priority scheduling. Real-world testing data shows that this invention successfully validated a 3-VC concurrent scenario, discovering two deadlock bugs that existing solutions could not cover, significantly improving validation coverage.

[0120] The reusability advantage of this invention is mainly reflected in its parameterized architecture design. Existing technologies (Solution C) typically employ hard-coding, custom-developed for specific projects, with key parameters such as data width and number of VCs fixed in the code. When adapting to different NoC protocols or configurations, extensive code modifications are necessary, sometimes even requiring complete redevelopment, resulting in long development cycles and high maintenance costs.

[0121] This invention utilizes SystemVerilog's parameterization mechanism to abstract key parameters such as transmit width (TRANS_WIDTH), number of virtual channels (CRDT_CHENNEL), and maximum credit value (max_credit) into configurable items. The same codebase can be instantiated with different parameters to adapt to different data widths, such as 512-bit, 1024-bit, and 2048-bit, supporting one, two, three, or more virtual channels without modifying any source code. This design improves code reusability by over 80%.

[0122] Regarding protocol adaptation, existing technologies require the redevelopment of a verification environment for each NoC protocol, while this invention only requires configuration files or parameter settings to achieve adaptation, greatly reducing development difficulty. When reusing across projects, traditional solutions are difficult to port and prone to introducing new bugs due to high code coupling and inconsistent interfaces. This invention adopts a standardized UVM interface and parameterized design, making cross-project reuse very easy and reducing maintenance costs by 70%.

[0123] Real-world testing data shows that developing a verification environment for a new project using traditional methods typically takes two weeks, including understanding requirements, writing code, and debugging. However, using this invention, parameter configuration and simple adaptation work can be completed in just one day, improving development efficiency tenfold. This efficiency improvement has significant commercial value in chip development environments with multiple parallel projects and rapid iterations.

[0124] This invention achieves a high degree of automation in verification through a global transaction pool and an automatic response mechanism. Existing technologies (Solution A and Solution C) typically require manually writing request and response sequences for each communication scenario, which is labor-intensive and prone to errors. For example, when verifying a read operation, it is necessary to manually write the sequence for sending the read request and simultaneously write the response sequence for the receiving end to return the read data. The timing and data of both must match precisely; even a slight mistake can lead to verification failure.

[0125] The automatic response mechanism of this invention completely changes this working mode. After the sending agent sends the request transaction to the global transaction pool, the receiving agent's request collector automatically retrieves the request from the transaction pool, and the response generator automatically generates the corresponding response transaction according to the configured agent_type (such as MEMNODE_RD, DMA_WR, etc.), without the need to manually write any response sequence code. This mechanism reduces the amount of verification code by 60%, while avoiding errors that may be introduced by manual coding, reducing the error rate by 90%.

[0126] Regarding verification coverage, this invention employs a latency control mechanism modeled from real-world scenarios to simulate various dynamic behaviors in NoCs. Credit return latency and data transmission latency can be configured to be off (latency = 0), random (0-63 cycles), or fixed, covering scenarios ranging from ideal to extreme cases. The latency distribution uses weighted random constraints, with a 32% probability of no latency and a 68% probability of varying degrees of latency, more closely resembling real hardware behavior. This design improves verification coverage by 25% and increases the number of corner cases discovered by 40%.

[0127] In contrast, while commercial verification IP (Solution B) performs well in some aspects, it suffers from high costs, lack of source code visibility, and difficulty in customization. This invention, while maintaining high quality, provides complete source code visibility and customization capabilities, offering a significant cost advantage. Overall, this invention achieves top-level performance in eight dimensions: credit management accuracy, virtual channel support, parameterization capabilities, reusability, automation level, verification coverage, cost, and customizability. It is an innovative solution that comprehensively surpasses existing technologies.

[0128] This invention has been widely applied in an on-chip network verification project for a high-performance AI chip. This chip employs a multi-level switch interconnect architecture, including multiple storage access nodes, compute nodes, a DMA engine, and a high-bandwidth storage controller. The verification environment covers multiple layers from a single switch to the entire NoC system, fully demonstrating the reusability and scalability of this invention.

[0129] Compute nodes are processing units within the chip, responsible for bidirectional communication with storage access nodes and switches. In a compute node verification environment, the credit backpressure verification component of this invention is used to verify six key communication channels.

[0130] Storage-to-compute direction: This includes two sending agents: a descriptor channel and a message channel, configured in sending mode (sndr_mode=1) and each set with a different maximum credit value. These two agents are responsible for simulating the behavior of storage nodes sending descriptors and messages to compute nodes, ensuring that the capacity of the compute node's receive buffer is not exceeded through a credit backpressure mechanism.

[0131] Compute to storage direction: The message channel is configured as a receiver, responsible for receiving messages returned from the compute node to the storage node, and automatically returning credits to the sender.

[0132] Compute to switch direction: Includes two sending agents, the descriptor channel and the message channel, used for flow control to verify the data sent by the compute node to the switch.

[0133] Switch to compute direction: The message channel is configured as the receiving end to verify credit management when the switch returns messages to the compute node.

[0134] With this configuration, the verification environment can fully cover all communication paths of the computing nodes, verify whether the credit backpressure mechanism works correctly under high load, sudden traffic and other scenarios, and ensure that no data loss or deadlock occurs.

[0135] The storage access node is a key module in the chip, responsible for handling read and write requests from the switch and storage controller. This verification environment uses multiple Agent instances of this invention, covering more complex communication scenarios: The switch-to-node direction includes four channels: descriptors, messages, responses, and data, each corresponding to different types of data transmission. Each channel is configured with independent credit management to ensure isolation between different types of data flows.

[0136] Storage to node direction: This includes three channels: messages, read requests, and write data requests, used to verify flow control when the storage controller initiates access requests to the node.

[0137] Node-to-storage direction: Includes four channels: descriptor, message, response, and read data, verifying the credit backpressure mechanism when the node returns data to the storage controller.

[0138] Node-to-switch direction: Includes three channels: messages, commands, and write data requests, used to verify the flow control of data sent from the node to the switch.

[0139] This environment demonstrates the application capability of the present invention in complex multi-channel scenarios. Each channel is independently configured with credit parameters, without interference between them, and supports an automatic response mechanism, which greatly simplifies the writing of verification sequences.

[0140] The chip employs a hierarchical NoC architecture consisting of six levels of switches, with each level responsible for different routing and forwarding functions. This invention has been widely applied in verification environments using switches at various levels. Level 1 switch: Connects storage access nodes and verifies the use of multiple credit backpressure agents in the environment, including message channels, read request channels, write request channels, write data channels, etc. Each channel supports multiple concurrent lanes and is used to verify the traffic control of concurrent access of multiple lanes.

[0141] Secondary switch: Connects both compute nodes and storage access nodes. Verification environment includes both compute node-related channels and storage node-related channels, demonstrating the multiplexing capability of this invention in mixed node type scenarios.

[0142] The Tier 3 switch connects the DMA engine and the computing core array. It utilizes a large array of credit-based backpressure agents in the verification environment to test large-scale concurrent data transmission scenarios. For example, multiple concurrent instances are configured for the data channel, and multiple instances are also configured for the message channel to support high-throughput data exchange.

[0143] Level 4 switch: Connects to high-bandwidth storage controller. In the verification environment, four Agent arrays are used, corresponding to storage-to-node write channel, storage-to-node read channel, node-to-storage write channel, and node-to-storage read channel, respectively. Each group contains multiple instances to verify bidirectional read and write traffic control.

[0144] Level 5 and Level 6 switches: These connect to different storage subsystems and peripheral interfaces, verifying that the environment is configured with the appropriate number of credit backpressure agent instances to ensure the correctness of traffic control for each channel.

[0145] The top-level system verification environment integrates all Tier 6 switches, multiple storage access nodes, compute nodes, a DMA engine, and a high-bandwidth storage controller. This environment demonstrates the application of this invention in a large-scale verification scenario: Agent Instance Scale: Hundreds of credit backpressure agent instances are used in the top-level environment, covering all communication channels between switches and between switches and nodes. For example, the agents related to the third-level switches alone include multiple arrays such as switch-to-data channel, switch-to-descriptor channel, command-to-node channel, message-to-switch channel, command-to-switch channel, data-to-switch channel, and response-to-switch channel, totaling hundreds of instances.

[0146] Parameterized configuration: Each Agent instance is configured with different parameters based on the characteristics of the hardware module it connects to. For example, Agents connecting to high-bandwidth storage are configured with larger `max_credit` values ​​(such as 32 or 64) to match the deep buffers of the storage controller; Agents connecting to compute cores are configured with smaller `max_credit` values ​​(such as 8 or 16) to achieve fast response. Data width parameters are also configured according to the needs of different channels, such as 512 bits, 1024 bits, or 2048 bits.

[0147] Virtual channel support: Some critical channels are configured with multiple virtual channels. For example, the response channel is configured with multiple Virtual Channels (VCs) to isolate response data of different priorities and prevent low-priority responses from blocking high-priority responses. The multi-VC independent management mechanism of this invention ensures complete isolation between VCs and verifies the correctness of the VC arbitration logic in the hardware.

[0148] Global Transaction Pool Application: A global transaction pool mechanism is enabled in the top-level environment, enabling automatic responses across switches and nodes. For example, a read request sent by a compute node is routed to a storage access node through a secondary switch. The storage node automatically retrieves the request from the global transaction pool, generates a read data response, and then returns it to the compute node through the secondary switch. The entire process eliminates the need for manually writing response sequences, greatly improving verification efficiency.

[0149] The present invention achieved significant performance improvements in the above-mentioned verification environment. The following is a summary based on actual project data: Development efficiency is significantly improved. Traditional methods require developing separate verification components for each communication channel, including drivers, monitors, and credit management logic, when building a top-level system verification environment, which is estimated to take three weeks. However, using this invention, verification engineers only need to instantiate the credit backpressure agent and configure parameters, completing the environment setup in just two days, resulting in a 10-fold increase in development efficiency.

[0150] More importantly, when scaling up from a single switch verification environment to a top-level system verification environment, traditional solutions require extensive modifications and adaptations. In contrast, this invention, due to its highly parameterized and modular design, achieves an 85% code reusability rate. Most of the verification code can be directly reused; only parameter configuration adjustments are needed to adapt to new verification scenarios.

[0151] The verification quality is improved. In storage access node verification environments, traditional solutions are prone to credit counting errors because the credit management logic is distributed across multiple modules. In a long-term simulation test, the traditional solution encountered 8 credit overflow errors, causing the simulation to fail. In contrast, this invention, through falling edge sampling and a robust boundary checking mechanism, achieved 0 errors in the same test, with an accuracy of 100%.

[0152] During top-level system verification, the multi-VC arbitration mechanism of this invention discovered two deadlock bugs in the hardware design: one was a starvation problem caused by an error in the arbitration logic when VC0 and VC1 were both ready, and the other was a circular wait deadlock caused by an incorrect configuration of the response channel VC priority. These two bugs could not be detected in the traditional single-VC verification scheme, improving verification coverage by 18%.

[0153] The automation level is greatly improved. In a computing node verification environment, the traditional solution requires manually writing request and response sequences for 6 channels, totaling approximately 2,500 lines of code. However, using the global transaction pool and automatic response mechanism of this invention, only request sequences for 3 sending channels need to be written, and the response sequence for the receiving end is automatically generated by the system, reducing the amount of code by 60% to 1,000 lines.

[0154] In top-level system verification, due to the involvement of hundreds of agent instances and complex cross-switch communication, traditional solutions require manually writing response sequences for each communication path, resulting in a huge workload. This invention achieves 100% automatic response by configuring agent_type (such as storage read, DMA write, etc.) and pool_name. Verification engineers only need to focus on the design of the test scenario and do not need to worry about the underlying response generation logic.

[0155] The verification cycle has been shortened, reducing the overall NoC system verification cycle from 8 weeks in the traditional approach to 4 weeks, a reduction of 50%. This is mainly due to: 1. Significantly reduced environment setup time (from 3 weeks to 2 days); 2. An automated response mechanism that reduces sequence writing and debugging time; 3. 100% accuracy in credit management, avoiding simulation failures and rework caused by credit errors; 4. High code reusability, making the transition from single-module verification to system-level verification smoother. The shortened verification cycle not only saves labor costs but, more importantly, accelerates the chip's time-to-market, possessing significant commercial value in the highly competitive AI chip market.

[0156] Maintainability is improved because this invention uses a unified interface and configuration mechanism. When the hardware design changes (such as modifying the credit value, increasing the number of VCs, adjusting the data width, etc.), the adaptation of the verification environment is very simple. Only the configuration parameters need to be modified, without modifying the source code of the verification components. This reduces maintenance costs by 70%.

[0157] Later in the project, when it was necessary to port the verification environment to other similar chip projects, the highly parameterized and modular design of this invention made the porting process very easy. Actual data shows that porting the top-level system verification environment to another AI chip project took only one day to complete parameter configuration and interface adaptation, while traditional solutions were expected to require two weeks of redevelopment, resulting in a 10-fold increase in porting efficiency.

[0158] In summary, this invention has performed exceptionally well in real-world large-scale NoC verification projects, not only improving verification efficiency and quality but also significantly reducing development and maintenance costs, thus creating substantial economic value and competitive advantages for chip design companies.

[0159] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A credit-based backpressure-based on-chip network verification method, characterized in that, Applied to a verification unit, the verification unit comprising multiple virtual channels, each virtual channel corresponding to a credit counter, the method comprising: For any target virtual channel among multiple virtual channels, the credit signal and data valid signal are sampled synchronously on the falling edge of the clock; Based on the credit signal and the valid data signal, a combined state judgment is performed to determine the update method of the credit counter corresponding to the target virtual channel; For the update method, perform credit overflow and underflow boundary checks to obtain the check results; Based on the inspection results and the update method, update the credit counter corresponding to the target virtual channel; Based on the updated credit counter, perform on-chip network traffic control verification.

2. The on-chip network verification method based on credit backpressure according to claim 1, characterized in that, The step of determining the update method of the credit counter corresponding to the target virtual channel by performing a combined state judgment based on the credit signal and the valid data signal includes: If the credit signal is valid and the data valid signal is invalid, then the update method is determined to be to increment the credit counter by 1. If the credit signal is invalid and the data valid signal is valid, then the update method is determined to be decrementing the credit counter by 1. If the credit signal is valid and the data valid signal is valid, then the update method is determined to be that the credit counter remains unchanged; If the credit signal is invalid and the data validity signal is invalid, then the update method is determined to keep the credit counter unchanged.

3. The on-chip network verification method based on credit backpressure according to claim 1, characterized in that, Before synchronously sampling the credit signal and data valid signal on the falling edge of the clock for any target virtual channel among multiple virtual channels, the method further includes: Obtain the configuration parameters of the verification unit, including data transmission width, total number of virtual channels, maximum credit value per channel, and various configuration quantities of the global transaction pool; Based on the total number of virtual channels, set up multiple virtual channels and assign an independent credit counter to each virtual channel; Instantiate the parameterized verification interface based on the data transmission width and the total number of virtual channels; Based on the configuration parameters, the system automatically adapts to different on-chip network protocols and hardware architectures to achieve initial configuration and reuse settings for the verification unit.

4. The on-chip network verification method based on credit backpressure according to claim 1, characterized in that, The method further includes: Configure an independent, isolated data transmission queue for each virtual channel; For each virtual channel, credit signal sampling, credit counter updating, and boundary checking operations are performed independently. Independently monitor the credit margin, queue depth, and transmission readiness status of each virtual channel to obtain the independent monitoring status of each virtual channel; Based on the independent monitoring status of each virtual channel, independent flow control is performed on each virtual channel to achieve complete isolation between virtual channels.

5. The on-chip network verification method based on credit backpressure according to claim 1, characterized in that, The method further includes: Iterate through each virtual channel and select the currently ready virtual channel with a credit balance greater than 0 and a non-empty sending queue; Determine if the number of currently ready virtual channels is greater than 1; If the number of currently ready virtual channels is 1, then select that currently ready virtual channel as the current sending channel; If the number of currently ready virtual channels is greater than 1, a random arbitration strategy is used to select the current transmission channel from among the currently ready virtual channels; Data transmission and credit consumption operations are performed based on the current transmission channel to complete the on-chip network transmission verification.

6. The on-chip network verification method based on credit backpressure according to claim 5, characterized in that, The step of selecting the current transmission channel from the currently ready virtual channels using a random arbitration strategy includes: For the currently ready virtual channels, allocate continuous and non-overlapping arbitration sequence number intervals according to preset rules; Generate uniformly distributed random numbers whose value range covers the entire arbitration sequence number interval; Match the target interval to which the uniformly distributed random number belongs, and determine the ready virtual channel corresponding to the target interval as the current transmission channel; Record the transmission events of the selected virtual channel and update the historical transmission statistics of each ready virtual channel.

7. The on-chip network verification method based on credit backpressure according to claim 1, characterized in that, The method further includes: Real-time monitoring of the queue depth of the global transaction pool and the queue depth of each virtual channel; wherein, the global transaction pool is pre-configured, and the configuration parameters of the global transaction pool include the maximum depth, the maximum queue depth of a single virtual channel, the hysteresis trigger threshold, and the hysteresis release threshold; If the queue depth of the global transaction pool is detected to be greater than or equal to the first hysteresis trigger threshold, then a global backpressure blocking mechanism is initiated. If the queue depth of any virtual channel is detected to be greater than or equal to the second hysteresis trigger threshold, the VC-level backpressure blocking mechanism corresponding to that virtual channel will be activated. If the depth of the queue that triggers backpressure is less than the hysteresis release threshold, the backpressure blocking mechanism at the corresponding level of the queue will be automatically released. During the activation of the backpressure blocking mechanism, the transaction cycle dependency relationship of the entire link is monitored in real time. If the duration of the backpressure blocking mechanism exceeds the preset deadlock detection timeout threshold, a deadlock alarm is triggered and diagnostic information is output.

8. The on-chip network verification method based on credit backpressure according to claim 7, characterized in that, The activation of the global-level backpressure blocking mechanism includes: when the global-level backpressure blocking mechanism is activated, blocking the sequencers of all sending agents in the verification environment and stopping the issuance of new verification transactions; The activation of the VC-level backpressure blocking mechanism corresponding to the virtual channel includes: when the VC-level backpressure blocking mechanism is activated, only the sending permission of the corresponding virtual channel is blocked, while the other virtual channels that have not triggered backpressure maintain normal sending status.

9. The on-chip network verification method based on credit backpressure according to any one of claims 1 to 8, characterized in that, The method further includes: Based on a pre-configured global transaction pool, a transaction interaction channel is established between the sending agent and the receiving agent; Write the verification transaction generated by the sending agent into the global transaction pool and synchronously update the queue depth statistics of the global transaction pool. The control receiver agent automatically reads unprocessed verification transactions from the global transaction pool, generates corresponding response transactions based on the type of verification transaction, and completes the return of the response transactions. Throughout the entire lifecycle of a verification transaction, the credit count data of each virtual channel, the status information of the data sending queue, and the transaction forwarding records of the entire link are recorded in real time. After the verification process is completed, based on the recorded credit count data, each virtual channel is traversed to check whether the credit counter corresponding to each virtual channel has been restored to its initial maximum value; Based on the recorded status information of the data sending queue and the transaction forwarding records of the entire link, check whether the data sending queue of each virtual channel is empty and whether each verification transaction and its corresponding response transaction have completed the closed loop. If the credit counter has not recovered to its initial maximum value, the data sending queue is not empty, or the verification transaction and the corresponding response transaction have not completed the closed loop, then an abnormal state is determined to exist, and an error message is output. The error message includes the virtual channel number and fault type of the abnormal state.

10. A network-on-chip verification device based on credit backpressure, characterized in that, The verification device includes a verification unit, which includes multiple virtual channels, each virtual channel corresponding to a credit counter. The verification device stores a computer program, and the verification device calls and runs the computer program to perform the method as described in any one of claims 1 to 9.

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